Source driver and output circuit thereof, display device

Abstract

Provided are a source driver, an output circuit thereof, and a display device, and the technical field belongs to display technology. The output circuit comprises an output buffer unit, a first switch unit, and a second switch unit. The output buffer unit can buffer a pair of output signals with opposite polarities, and the first switch unit and the second switch unit can cooperate with each other to control the pair of output signals with opposite polarities to be transmitted to two output terminals coupled with different pixels. In this way, each unit in the output circuit can be designed to work in the same low-voltage driving environment (including a pull-up voltage, a pull-down voltage, and an intermediate voltage), i.e., a low-voltage transistor can be used to design each unit in the output circuit of the display driver. Further, the working power consumption of the display driver can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a source driver and its output circuit, and a display device. Background Technology

[0002] Liquid crystal display (LCD) products are among the most common display products today, offering advantages such as high brightness, wide viewing angle, and vibrant colors.

[0003] LCD products typically include a source driver and an LCD panel. The source driver transmits data signals to the LCD panel to drive the display. Furthermore, to ensure the LCD panel can reliably display a normal screen image, the source driver often transmits data signals with continuously reversed polarity to the LCD panel. For example, for two adjacent pixels in the same row, the source driver provides data signals with opposite polarities to those two pixels.

[0004] However, most source drivers for transmitting polarity-reversed data signals currently require high-voltage driving, which results in a large amount of power consumption. Summary of the Invention

[0005] This disclosure provides a source driver, its output circuit, and a display device, which can solve the problem of high power consumption in source drivers in related technologies. The technical solution is as follows:

[0006] On one hand, an output circuit for a source driver is provided, the output circuit comprising:

[0007] The output buffer unit is configured to buffer a pair of input signals with opposite polarities into a pair of output signals with opposite polarities based on the pull-up voltage provided by the pull-up power supply terminal, the intermediate voltage provided by the intermediate power supply terminal, and the pull-down voltage provided by the pull-down power supply terminal. The intermediate voltage is less than the pull-up voltage and greater than the pull-down voltage.

[0008] The first switching unit is configured to control the pair of output signals to be transmitted to the intermediate node on the corresponding path via a direct path and a cross path, respectively, and to control the intermediate voltage to be transmitted to the intermediate node, wherein the direct path and the cross path of each of the pair of output signals are different;

[0009] The second switching unit is configured to control the transmission of the signal of the intermediate node on the direct path and the signal of the intermediate node on the cross path to two output terminals, which are used to couple to different pixels in the display panel.

[0010] The second switching unit includes a plurality of N-type transistors and a plurality of P-type transistors; and the substrates of transistors of the same type that transmit signals of the same polarity are used to receive the same substrate voltage.

[0011] Optionally, both the P-type transistor and the N-type transistor include: a well region, and an active region and a source-drain conductive region located within the well region and arranged in an overlapping manner;

[0012] The plurality of P-type transistors, including different active regions and different source-drain conductive regions, are located in the same well region; the plurality of N-type transistors, including different active regions and different source-drain conductive regions, are located in the same well region.

[0013] Optionally, the output circuit further includes:

[0014] The third switching unit is configured to control the same substrate voltage transmitted to the substrate of the same type of transistor.

[0015] Optionally, the third switching unit includes:

[0016] Each of the plurality of P-type transistors has a first switching subunit that corresponds to one of them, and is configured to control the same first substrate voltage to be transmitted to the substrate of the plurality of P-type transistors.

[0017] The second switching sub-units, each corresponding to one of the plurality of N-type transistors, are configured to control the same second substrate voltage to be transmitted to the substrates of the plurality of N-type transistors.

[0018] Optionally, the second switching unit includes a plurality of N-type transistors and a plurality of P-type transistors in a one-to-one correspondence; the first substrate voltage includes the pull-up voltage or the intermediate voltage; the second substrate voltage includes the intermediate voltage or the pull-down voltage;

[0019] The first switch subunit includes two first single-pole single-throw switches connected in series. The input terminals of the two first single-pole single-throw switches are respectively coupled to the pull-up power supply terminal and the intermediate power supply terminal. The output terminals of the two first single-pole single-throw switches are both coupled to the substrate of the P-type transistor.

[0020] The second switching subunit includes two second single-pole single-throw switches connected in series. The input terminals of the two second single-pole single-throw switches are respectively coupled to the pull-down power supply terminal and the intermediate power supply terminal. The output terminals of the two second single-pole single-throw switches are both coupled to the substrate of the N-type transistor.

[0021] Optionally, the output buffer unit includes:

[0022] The first output buffer subunit is configured to buffer and output the positive input signal of the pair of opposite polarity input signals as a positive output signal based on the pull-up voltage and the intermediate voltage.

[0023] The second output buffer subunit is configured to buffer and output the negative input signal of the pair of opposite polarity input signals as a negative output signal based on the intermediate voltage and the pull-down voltage.

[0024] Optionally, the first switching unit includes:

[0025] The third switch subunit is configured to control the pair of output signals to be transmitted to the intermediate nodes on the corresponding paths via direct paths and cross paths, respectively.

[0026] The fourth switching subunit is configured to control the transmission of the intermediate voltage to the intermediate node.

[0027] Optionally, both the third switch subunit and the second switch unit include a direct path switch section for providing a direct path and a cross path switch section for providing a cross path.

[0028] The direct path switch unit in the third switch subunit is configured to control the pair of output signals to be transmitted to the intermediate node on the direct path via the corresponding direct path, and the direct path switch unit in the second switch unit is configured to control the signal of the intermediate node on the direct path to be transmitted to the two output terminals.

[0029] The cross-path switch in the third switch subunit is configured to control the pair of output signals to be transmitted to the intermediate node on the cross-path via the corresponding cross-path, and the cross-path switch in the second switch unit is configured to control the signal of the intermediate node on the cross-path to be transmitted to the two output terminals.

[0030] On the other hand, a source driver is provided, the source driver including: a driving circuit, and a plurality of output circuits as described in one aspect above;

[0031] The driving circuit is configured to transmit a pair of input signals with opposite polarities to the output circuit.

[0032] In another aspect, a display device is provided, the display device comprising: a display panel, and a source driver as described in the other aspect above;

[0033] The display panel includes multiple pixels, and the source driver is configured to transmit multiple pairs of output signals to the multiple pixels through multiple output circuits, with each pair of output signals having opposite polarities.

[0034] In summary, the beneficial effects of the technical solution provided in this disclosure can include at least the following:

[0035] A source driver, its output circuit, and a display device are provided. The output circuit includes an output buffer unit, a first switching unit, and a second switching unit. The output buffer unit buffers a pair of output signals with opposite polarities. The first and second switching units cooperate to control the transmission of the pair of output signals with opposite polarities to two output terminals coupled to different pixels. This allows each unit in the output circuit to operate under the same low-voltage driving environment (including pull-up voltage, pull-down voltage, and intermediate voltage), enabling the use of low-voltage transistors in the output circuit design of the display driver. Furthermore, this helps to reduce the power consumption of the display driver. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic block diagram of the output circuit of a source driver provided in an embodiment of this disclosure;

[0038] Figure 2 This is a schematic block diagram of a portion of the switching units in an output circuit provided in an embodiment of this disclosure;

[0039] Figure 3 This is a schematic block diagram of a portion of the switching units in an output circuit provided in an embodiment of this disclosure;

[0040] Figure 4 This is a circuit diagram of a portion of the switching units in a more specific exemplary output circuit provided in this disclosure embodiment;

[0041] Figure 5 This is a schematic block diagram of another source driver output circuit provided in an embodiment of this disclosure;

[0042] Figure 6 This is a schematic block diagram of another source driver output circuit provided in the embodiments of this disclosure;

[0043] Figure 7 This is a schematic block diagram of another source driver output circuit provided in an embodiment of this disclosure;

[0044] Figure 8This is a circuit diagram of a more specific exemplary source driver output circuit provided in an embodiment of this disclosure;

[0045] Figure 9 Is Figure 8 The diagram shows the working principle of a direct output stage output circuit based on the above.

[0046] Figure 10 Is Figure 8 The diagram shown is based on the working principle of a cross-output stage output circuit.

[0047] Figure 11 This is a circuit diagram of another more specific exemplary source driver output circuit provided in this disclosure embodiment;

[0048] Figure 12 Is Figure 11 The diagram shown is a structural layout of the second switching unit in an output circuit.

[0049] Figure 13 This is a structural layout of a second switching unit in an output circuit of a related technology;

[0050] Figure 14 This is a schematic block diagram of a source driver provided in an embodiment of this disclosure;

[0051] Figure 15 This is a schematic block diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0053] Figure 1 This is a schematic block diagram of the output circuit of a source driver provided in an embodiment of this disclosure. (See reference) Figure 1 As can be seen, the output circuit includes: output buffer unit 01, first switch unit 02, and second switch unit 03.

[0054] For example, output buffer unit 01 is configured based on the pull-up (T) power supply terminal V. T Provided pull-up voltage, middle (M) power supply terminal V M The provided intermediate voltage and the pull-down (B) power supply terminal V B The provided pull-down voltage buffers a pair of input signals with opposite polarities into a pair of output signals INP and INN with opposite polarities.

[0055] Therefore, for reference Figure 1It can be seen that the output buffer unit 01 can be connected to the pull-up power supply terminal V respectively. T Intermediate power supply terminal V M and pull-down power supply terminal V B The output buffer unit 01 is coupled to receive pull-up voltage, intermediate voltage and pull-down voltage respectively; the output buffer unit 01 may have a pair of input terminals IN(N) and IN(N+1) and receive a pair of input signals of opposite polarity provided from the pair of input terminals IN(N) and IN(N+1); the output buffer unit 01 may also have a pair of output terminals and output a pair of output signals INP and INN of opposite polarity through the buffer of the pair of output terminals.

[0056] Optionally, the pair of input signals here refers to the data signals converted by the front-end digital-to-analog converter. The output signal INP can be a positive (P) data signal, and the corresponding input terminal IN(N) receives a positive data signal; the output signal INN can be a negative (N) data signal, and the corresponding input terminal IN(N+1) receives a negative data signal.

[0057] The intermediate voltage is less than the pull-up voltage and greater than the pull-down voltage. For example, in some embodiments, the intermediate voltage can be the average of the sum of the pull-up and pull-down voltages. For instance, assuming the pull-up voltage is 9 volts (V) and the pull-down voltage is 0, the intermediate voltage can be 4.5V; assuming the pull-up voltage is 4.5V and the pull-down voltage is -4.5V, the intermediate voltage can be 0. Therefore, the output buffer unit 01 can be driven in a low-voltage environment. The output buffer unit 01 may include multiple low-voltage driven transistors.

[0058] For example, the first switching unit 02 is configured to control the output buffer unit 01 to buffer a pair of output signals INP and INN, which are transmitted to intermediate nodes on the corresponding paths (e.g., nodes n1 to n4 shown in the figure) via direct and cross paths, respectively, and to control the intermediate voltage V. M The signal is transmitted to an intermediate node. The direct path and the cross path traversed by this pair of output signals are both different.

[0059] For example, for a pair of output signals, the positive output signal INP can be controlled by the first switching unit 02 to transmit the positive output signal INP through a direct path to an intermediate node n1 on that direct path, and can also be controlled by the first switching unit 02 to transmit the positive output signal INP through a cross path to an intermediate node n2 on that cross path. For a pair of output signals, the negative output signal INN can be controlled by the first switching unit 02 to transmit the negative output signal INN through another direct path to an intermediate node n3 on that other direct path, and can also be controlled by the first switching unit 02 to transmit the negative output signal INN through another cross path to an intermediate node n4 on that other cross path. Correspondingly, as... Figure 1 As shown, there are a total of four intermediate nodes, including two intermediate nodes n1 and n3 located on the direct path, and two intermediate nodes n2 and n4 located on the intersecting path. The above is only an example, and the embodiments disclosed herein are not limited thereto.

[0060] Therefore, for reference Figure 1 It can be seen that the first switching unit 02 can be connected to the two output terminals of the output buffer unit 01 (the two output terminals output a pair of output signals INP and INN with opposite polarities), the four intermediate nodes n1, n2, n3 and n4, and the intermediate power supply terminal V. M Coupling. The first switching unit 02 can control the connection between the two output terminals of the output buffer unit 01 and the intermediate node. When the first switching unit 02 controls the two output terminals of the output buffer unit 01 to be connected to the intermediate node, the pair of output signals INP and INN buffered by the output buffer unit 01 through its two output terminals can be transmitted to the intermediate node. Furthermore, the first switching unit 02 can also control the intermediate power supply terminal V. M The connection and disconnection between the intermediate node and the intermediate power supply terminal V is controlled by the first switching unit 02. M When connected to the intermediate node, it can transmit data from the intermediate power supply terminal V to the intermediate node. M The intermediate voltage.

[0061] For example, the second switching unit 03 is configured to control the transmission of signals from intermediate nodes on the direct path and intermediate nodes on the cross path to two output terminals OUT, respectively. <n>and OUT<N+1> .

[0062] Among them, the two output terminals OUT <n>and OUT<N+1> It can be used to couple with different pixels in a display panel. Optionally, the two output terminals OUT... <n>and OUT<N+1> This can be used to couple two pixels in the same row but different columns to provide a pair of data signals of opposite polarity to the two pixels in the same row but different columns. Of course, display panels typically include multiple rows and columns of pixels, so the display driver can include multiple output circuits, each of which can be coupled to two different pixels to transmit a pair of data signals of opposite polarity to the coupled pixels. This disclosure embodiment illustrates the output circuit coupled to the Nth pixel and the (N+1)th pixel in a different row from adjacent columns, where N is an integer greater than 0. OUT <n>It can refer to the output terminal that couples to the even number of pixels, OUT.<N+1> It can refer to the output terminal that is coupled to the odd number of pixels.

[0063] Therefore, for reference Figure 1 It can be seen that the second switch unit 03 can be connected to the four intermediate nodes n1, n2, n3 and n4, and the two output terminals OUT, respectively. <n>and OUT<N+1> Coupling. The second switching unit 03 can control the intermediate node and the two output terminals OUT. <n>and OUT<N+1> The switching on and off is controlled by the second switching unit 03, which controls the connection between each intermediate node and the two output terminals OUT. <n>and OUT<N+1> When the circuit is turned on, the signal from the intermediate node can be transmitted to the two output terminals OUT. <n>and OUT<N+1> The signals at the intermediate node can include output signals INP and INN with opposite polarities, or they can include intermediate voltages. When the signals at the intermediate node are output signals INP and INN with opposite polarities, they are transmitted to the two output terminals OUT via the second switching unit 03. <n>and OUT<N+1> The signals are: a pair of output signals INP and INN with opposite polarities, which allows the pair of input signals with opposite polarities to be output through two output terminals OUT. <n>and OUT<N+1> The signal is transmitted to different pixels to avoid liquid crystal hysteresis and ensure reliable display of the LCD panel. When the signal at the intermediate node is an intermediate voltage, it is transmitted to the two output terminals OUT via the second switching unit 03. <n>and OUT<N+1> The signal is the intermediate voltage, which can be considered as the voltage applied to the two output terminals OUT. <n>and OUT<N+1> Perform charge sharing.

[0064] Based on the above embodiments, it can be seen that the output circuit has two output terminals OUT. <n>and OUT<N+1> Each input terminal can be individually associated with one of the two input terminals, IN(N) and IN(N+1). In other words, the output signal (e.g., INP) buffered from the input signal received at input terminal IN(N) can be directly transmitted to the corresponding output terminal OUT via a direct path. <n>And it can be transmitted to the output terminal OUT via a cross path. <n>Adjacent output terminals OUT<N+1> The output signal buffered from the input signal received at input terminal IN(N+1) can be directly transmitted to the corresponding output terminal OUT via a direct path.<N+1> And it can be transmitted to the output terminal OUT via a cross path.<N+1> Adjacent output terminals OUT <n>Correspondingly, a direct path can refer to the following: the output buffer unit 01 buffers a pair of output signals INP and INN with opposite polarities based on its two input terminals IN(N) and IN(N+1), which are then transmitted one-to-one to the two output terminals OUT. <n>and OUT<N+1> The path taken. A cross path can refer to: the output buffer unit 01 buffers a pair of output signals INP and INN with opposite polarities based on two input terminals IN(N) and IN(N+1), which are transmitted one-to-one to two output terminals OUT.<N+1> and OUT <n>The path taken.

[0065] It should be noted that each switching unit included in the output circuit of this embodiment can be driven within a voltage range between the pull-up voltage and the intermediate voltage, or between the intermediate voltage and the pull-down voltage, meaning it can operate under the same low-voltage driving environment as the output buffer unit 01. Correspondingly, each switching unit can include multiple transistors with low voltage withstand values. This satisfies the low-power requirement.

[0066] Optional, Figure 2 This is a schematic block diagram of a portion of the switching units in an output circuit provided in an embodiment of this disclosure. (Reference) Figure 2 As can be seen, the second switching unit 03 may include multiple N-type transistors and multiple P-type transistors (only one N-type transistor and one P-type transistor are shown in the figure). Furthermore, the substrates of transistors of the same type transmitting signals of the same polarity can be used to receive the same substrate voltage, meaning they can be under the control of the same body voltage. Consequently, transistors of the same type transmitting signals of the same polarity can share the same well, i.e., be located within the same well region. In this way, the area occupied by the second switching unit 03 can be minimized, thereby reducing the overall size of the output circuit.

[0067] Example, reference Figure 2 Both P-type and N-type transistors can be metal-oxide-semiconductor (MOS) field-effect transistors. Correspondingly, a P-type transistor can be... Figure 2 The PMOS transistor shown can be an N-type transistor. Figure 2 The NMOS transistor shown is an example. Furthermore, the substrate of a PMOS transistor transmitting a signal of the same polarity can receive the same first substrate voltage V1, and the substrate of an NMOS transistor transmitting a signal of the same polarity can receive the same second substrate voltage V2.

[0068] In summary, this disclosure provides an output circuit for a source driver. The output circuit includes an output buffer unit, a first switching unit, and a second switching unit. The output buffer unit buffers a pair of output signals with opposite polarities, and the first and second switching units cooperate to control the transmission of these opposite polarities to two output terminals coupled to different pixels. This allows each unit in the output circuit to operate under the same low-voltage driving environment (including pull-up voltage, pull-down voltage, and intermediate voltage), enabling the use of low-voltage transistors in the output circuit design of the display driver. Furthermore, this helps reduce the power consumption of the display driver.

[0069] Furthermore, since the substrates of transistors of the same type transmitting signals of the same polarity in the second switching unit directly coupled to the output terminal in the output circuit can receive the same substrate voltage, it can be known that these transistors of the same type transmitting signals of the same polarity can share a single well region. This also reduces the area occupied by the output circuit, thereby reducing the area of ​​the source driver.

[0070] Optional, continue to refer to Figure 2 As can be seen, in this embodiment of the present disclosure, the output circuit may further include: a third switching unit 04.

[0071] For example, the third switching unit 04 can be configured to control the same substrate voltage transmitted to the substrate of the same type of transistor. For instance, the third switching unit 04 can be configured to control the same first substrate voltage V1 transmitted to the PMOS transistor and control the same second substrate voltage V2 transmitted to the NMOS transistor.

[0072] Therefore, for reference Figure 2 It can also be seen that the third switching unit 04 can be coupled to the power supply terminal providing the substrate voltage (including two power supply terminals providing the first substrate voltage V1 and the second substrate voltage V2) and the substrate of the transistor, respectively, to control the switching on and off of the power supply terminal providing the substrate voltage and the substrate of the transistor. When the power supply terminal providing the substrate voltage and the substrate of the transistor are turned on, the substrate voltage provided by the power supply terminal can be transmitted to the substrate of the transistor.

[0073] Optional, Figure 3 This is a schematic block diagram of a portion of the switching units in an output circuit provided in an embodiment of this disclosure. (Reference) Figure 3 As can be seen, the third switching unit 04 described in this embodiment may include: a first switching subunit 041 corresponding to a plurality of P-type transistors (e.g., PMOS transistors) and a second switching subunit 042 corresponding to a plurality of N-type transistors (e.g., NMOS transistors).

[0074] For example, the first switching subunit 041 can be configured to control the same first substrate voltage V1 to be transmitted to the substrates of multiple P-type transistors. The second switching subunit 042 can be configured to control the same second substrate voltage V2 to be transmitted to the substrates of multiple N-type transistors. That is, different switching subunits can control the required substrate voltage to be transmitted to the substrates of different types of transistors.

[0075] Therefore, for reference Figure 3 As can be seen, the first switching subunit 041 can be coupled to the power supply terminal providing the first substrate voltage V1 and the substrate of the PMOS transistor, respectively, to control the on / off state of the power supply terminal providing the first substrate voltage V1 and the substrate of the PMOS transistor. When the power supply terminal providing the first substrate voltage V1 and the substrate of the PMOS transistor are turned on, the first substrate voltage V1 can be transmitted to the substrate of the PMOS transistor. The second switching subunit 042 can be coupled to the power supply terminal providing the second substrate voltage V2 and the substrate of the NMOS transistor, respectively, to control the on / off state of the power supply terminal providing the second substrate voltage V2 and the substrate of the NMOS transistor. When the power supply terminal providing the second substrate voltage V2 and the substrate of the NMOS transistor are turned on, the second substrate voltage V2 can be transmitted to the substrate of the NMOS transistor.

[0076] Optionally, in some embodiments, the second switching unit 03 may include: a plurality of N-type transistors and a plurality of P-type transistors in a one-to-one correspondence. The first substrate voltage V1 may include: a pull-up power supply terminal V T Provided pull-up voltage or intermediate power supply V M The provided intermediate voltage. The second substrate voltage V2 may include: an intermediate power supply terminal V. M Provided intermediate voltage or pull-down power supply terminal V B The provided pull-down voltage.

[0077] Optional, Figure 4 This is a circuit diagram of a portion of the switching units in a more specific exemplary output circuit provided in this disclosure. (See reference...) Figure 4 It can be seen that the first switch subunit 041 can be connected to the pull-up power supply terminal V respectively. T and intermediate power supply terminal V M Coupling; the second switch subunit 042 can be coupled to the pull-down power supply terminal V. B and intermediate power supply terminal V M Coupled.

[0078] For example, such as Figure 4 As shown, the first switch subunit 041 described in this embodiment may include two first single-pole single-throw switches K11 and K12 connected in series. The input terminals of the two first single-pole single-throw switches K11 and K12 can be respectively connected to the pull-up power supply terminal V. T and intermediate power supply terminal V M The outputs of the two first single-pole single-throw switches K11 and K12 can both be coupled to the substrate of the P-type transistor.

[0079] For example, such as Figure 4 As shown, the second switch subunit 042 may include two second single-pole single-throw switches K21 and K22 connected in series. The input terminals of the two second single-pole single-throw switches K21 and K22 can be respectively connected to the pull-down power supply terminal V. B and intermediate power supply terminal V M The outputs of the two second single-pole single-throw switches K21 and K22 can both be coupled to the substrate of the N-type transistor. Figure 4 Based on the structure, we can know that:

[0080] For P-type transistors: If, when controlling the two first single-pole single-throw (SPS) switches K11 and K12, SPS K11 is closed and SPS K12 is not closed, then the pull-up power supply terminal V will be... T and intermediate power supply terminal V M The pull-up power supply terminal V in T The substrate of the P-type transistor is turned on, and a pull-up voltage is transferred to the substrate of the P-type transistor as the first substrate voltage V1; if the first single-pole single-throw switch K12 is closed and the first single-pole single-throw switch K11 is not closed, then the pull-up power supply terminal V1 will be turned on. T and intermediate power supply terminal V M intermediate power supply terminal V M It is connected to the substrate of the P-type transistor and transmits an intermediate voltage to the substrate of the P-type transistor as the first substrate voltage V1.

[0081] For N-type transistors: If, when controlling two second single-pole single-throw switches K21 and K22, switch K21 is closed and switch K22 is not closed, then the pull-down power supply terminal V will be... B and intermediate power supply terminal V M intermediate power supply terminal V M The substrate of the N-type transistor is connected to the ground, and an intermediate voltage is transferred to the substrate of the N-type transistor as the second substrate voltage V2. If the second single-pole single-throw switch K22 is closed and the second single-pole single-throw switch K21 is not closed, then the pull-down power supply terminal V2 will be connected to the ground. B and intermediate power supply terminal V M The pull-down power supply terminal V in B It is connected to the substrate of the N-type transistor and a pull-down voltage is transmitted to the substrate of the N-type transistor as the second substrate voltage V2.

[0082] Optional, Figure 5 This is a schematic block diagram of another source driver output circuit provided in an embodiment of this disclosure. (See reference) Figure 5 As can be seen, the output buffer unit 01 described in this disclosure may include: a first output buffer subunit 011 and a second output buffer subunit 012.

[0083] For example, the first output buffer subunit 011 can be configured to buffer the positive input signal of a pair of input signals with opposite polarities and output it as a positive output signal INP based on the pull-up voltage and the intermediate voltage.

[0084] For example, the second output buffer subunit 012 can be configured to buffer the negative input signal of a pair of input signals with opposite polarities into a negative output signal INN based on the intermediate voltage and the pull-down voltage.

[0085] Therefore, for reference Figure 5 It can be seen that the first output buffer subunit 011 can be connected to the pull-up power supply terminal V respectively. T and intermediate power supply terminal V M Coupled, the first output buffer subunit 011 can have an input terminal IN(N) to receive a positive input signal. The output terminal of the first output buffer subunit 011 can buffer the positive input signal received at the input terminal IN(N) and output it as a positive output signal INP. The second output buffer subunit 012 can be connected to the intermediate power supply terminal V. M and pull-down power supply terminal V B Coupled, the second output buffer subunit 012 may have an input terminal IN(N+1) to receive a negative polarity input signal. The output terminal of the second output buffer subunit 012 can buffer the negative polarity input signal received by the input terminal IN(N+1) and output it as a negative polarity output signal INN.

[0086] Optional, Figure 6 This is a schematic block diagram of another source driver output circuit provided in an embodiment of this disclosure. (See reference) Figure 6 As can be seen, the first switch unit 02 described in the embodiments of this disclosure may include: a third switch subunit 021 and a fourth switch subunit 022.

[0087] For example, the third switch subunit 021 can be configured to control a pair of output signals INP and INN to be transmitted to intermediate nodes on the corresponding paths via direct and cross paths, respectively.

[0088] For example, the fourth switch subunit 022 can be configured to control the transmission of intermediate voltage to the intermediate node.

[0089] Therefore, for reference Figure 6 It can be seen that the third switch subunit 021 can be coupled to the two output terminals of the output buffer unit 01 (i.e., the output terminals of the first output buffer subunit 011 and the second output buffer subunit 012) and the four intermediate nodes n1, n2, n3 and n4 respectively, to control the on / off state of the two output terminals of the output buffer unit 01 and the four intermediate nodes n1, n2, n3 and n4. When the third switch subunit 021 controls the output terminals of the first output buffer subunit 011 and the second output buffer subunit 012 to be connected to the intermediate nodes, the output signals INP and INN can be transmitted to the intermediate nodes. The fourth switch subunit 022 can be coupled to the intermediate power supply terminal V respectively. M And four intermediate nodes n1, n2, n3 and n4 are coupled to control the intermediate power supply terminal V. M The connection and disconnection with the four intermediate nodes n1, n2, n3, and n4 are controlled by the fourth switch subunit 022, which controls the intermediate power supply terminal V. M When connected to the intermediate node, intermediate voltage can be transmitted to the intermediate node.

[0090] Optional, Figure 7 This is a schematic block diagram of another source driver output circuit provided in an embodiment of this disclosure. See also... Figure 7 It can be seen that both the third switch subunit 021 and the second switch unit 03 may include: a direct path switch section B1x for providing a direct path and a cross path switch section B2x for providing a cross path. For distinction, the direct path switch sections B1 of the third switch subunit 021 and the second switch unit 03 are respectively identified as B11 and B12, and the cross path switch sections B2 of the third switch subunit 021 and the second switch unit 03 are respectively identified as B21 and B22.

[0091] For example, the direct path switch section B11 in the third switch subunit 021 can be configured to control a pair of output signals INP and INN to be transmitted to intermediate nodes n1 and n3 on the direct path via corresponding direct paths, respectively. The direct path switch section B12 in the second switch unit 03 can be configured to control the signals (including output signals and intermediate voltages) of intermediate nodes n1 and n3 on the direct path to be transmitted to two output terminals OUT, respectively. <n>and OUT<N+1> .

[0092] For example, the cross-path switch section B21 in the third switch subunit 021 can be configured to control a pair of output signals INP and INN to be transmitted to intermediate nodes n2 and n4 on the cross-path via the corresponding cross-path, respectively. The cross-path switch section B22 in the second switch unit 03 can be configured to control the signals of intermediate nodes n2 and n4 on the cross-path to be transmitted to two output terminals OUT, respectively.<N+1> and OUT <n>.

[0093] Therefore, for reference Figure 7 It can be seen that the direct path switch B11 in the third switch subunit 021 can be coupled to the output terminals of the first output buffer subunit 011, the second output buffer subunit 012, and intermediate nodes n1 and n3, respectively. The direct path switch B11 in the third switch subunit 021 can control the connection between the output terminal of the first output buffer subunit 011 and the intermediate node n1. When the output terminal of the first output buffer subunit 011 is connected to the intermediate node n1, the output signal INP can be transmitted to the intermediate node n1 via the direct path. It can also control the connection between the output terminal of the second output buffer subunit 012 and the intermediate node n3. When the output terminal of the second output buffer subunit 012 is connected to the intermediate node n3, the output signal INN can be transmitted to the intermediate node n3 via the direct path. The cross path switch B21 in the third switch subunit 021 can be coupled to the output terminals of the first output buffer subunit 011, the second output buffer subunit 012, and intermediate nodes n2 and n4, respectively. The cross-path switch B21 in the third switch subunit 021 can control the connection and disconnection between the output terminal of the first output buffer subunit 011 and the intermediate node n2. When the output terminal of the first output buffer subunit 011 is connected to the intermediate node n2, the output signal INP can be transmitted to the intermediate node n2 via the cross-path. It can also control the connection and disconnection between the output terminal of the second output buffer subunit 012 and the intermediate node n4. When the output terminal of the second output buffer subunit 012 is connected to the intermediate node n4, the output signal INN can be transmitted to the intermediate node n4 via the cross-path.

[0094] For example, the direct path switch section B12 in the second switch unit 03 can be connected to intermediate nodes n1 and n3, as well as the two output terminals OUT. <n>and OUT<N+1> Coupling. In this embodiment of the present disclosure, the direct-path switch section B12 in the second switch unit 03 can control the intermediate node n1 and the output terminal OUT. <n>The on / off state, and the control intermediate node n1 and output terminal OUT <n>When the circuit is turned on, the signal at intermediate node n1 (including output signal INP or intermediate voltage) can be transmitted to the output terminal OUT. <n>; and can control intermediate node n3 and output terminal OUT<N+1> The on / off state, and the control intermediate node n3 and output terminal OUT<N+1> When the circuit is turned on, the signal at intermediate node n3 (including the output signal INN or intermediate voltage) can be transmitted to the output terminal OUT.<N+1> The cross-path switch section B22 in the second switch unit 03 can be connected to intermediate nodes n2 and n4, as well as the two output terminals OUT, respectively. <n>and OUT<N+1> Coupling. The cross-path switch B22 in the second switch unit 03 can control the intermediate node n2 and the output terminal OUT.<N+1> The on / off state, and the control intermediate node n2 and output terminal OUT<N+1> When the circuit is turned on, the signal at intermediate node n2 (including output signal INP or intermediate voltage) can be transmitted to the output terminal OUT.<N+1> ; and can control intermediate node n4 and output terminal OUT <n>The on / off state, and the control intermediate node n4 and output terminal OUT <n>When the circuit is turned on, the signal at intermediate node n4 (including the output signal INN or intermediate voltage) can be transmitted to the output terminal OUT. <n>.

[0095] Optional, Figure 8 This is a circuit diagram of a more specific exemplary source driver output circuit provided in an embodiment of this disclosure. (See reference...) Figure 8 It can be seen that the first output buffer subunit 011 and the second output buffer subunit 012 described in the embodiments of this disclosure may include an amplifier (AMP).

[0096] Among them, since the first output buffer subunit 011 buffers the positive output signal INP, the included amplifier AMP can also be called a positive amplifier (PAMP) that amplifies positive signals; the second output buffer subunit 012 buffers the negative output signal INN, so the included amplifier AMP can also be called a negative amplifier (NAMP) that amplifies negative signals.

[0097] For example, the direct path switch section B11 in the third switch subunit 021 may include two transistors SW1 and SW8; the cross path switch section B21 in the third switch subunit 021 may include two transistors SW2 and SW7.

[0098] like Figure 8 As shown, the input terminal of transistor SW1 can be coupled to the output terminal of PAMP to receive the positive output signal INP from PAMP; the output terminal of transistor SW1 can be coupled to intermediate node n1; the input terminal of transistor SW8 can be coupled to the output terminal of NAMP to receive the negative output signal INN from NAMP; the output terminal of transistor SW8 can be coupled to intermediate node n3; the input terminal of transistor SW2 can be coupled to the output terminal of PAMP to receive the positive output signal INP from PAMP; the output terminal of transistor SW2 can be coupled to intermediate node n2; the input terminal of transistor SW7 can be coupled to the output terminal of NAMP to receive the negative output signal INN from NAMP; the output terminal of transistor SW7 can be coupled to intermediate node n4.

[0099] For example, the direct path switch section B12 in the second switch unit 03 may include two transistors SW5 and SW12; the cross path switch section B22 in the second switch unit 03 may include two transistors SW6 and SW11.

[0100] like Figure 8 As shown, the input terminal of transistor SW5 can be coupled to the intermediate node n1, and the output terminal of transistor SW5 can be coupled to the output terminal OUT. <n>Coupling; the input terminal of transistor SW12 can be coupled to the intermediate node n3, and the output terminal of transistor SW12 can be coupled to the output terminal OUT.<N+1> Coupling; the input terminal of transistor SW6 can be coupled to the intermediate node n2, and the output terminal of transistor SW6 can be coupled to the output terminal OUT.<N+1> Coupling; the input terminal of transistor SW11 can be coupled to the intermediate node n4, and the output terminal of transistor SW11 can be coupled to the output terminal OUT. <n>Coupled.

[0101] For example, the fourth switch subunit 022 may include four transistors SW3, SW4, SW9, and SW10. The input terminals of transistors SW3, SW4, SW9, and SW10 can all be connected to the intermediate power supply terminal V. M The output of transistor SW3 can be coupled to intermediate node n1, the output of transistor SW4 can be coupled to intermediate node n2, the output of transistor SW9 can be coupled to intermediate node n4, and the output of transistor SW10 can be coupled to intermediate node n3.

[0102] Optional, see reference Figure 8 It can also be seen that transistors SW1, SW2, SW7, SW8, SW5, SW6, SW11, and SW12 can all include P-type and N-type transistors connected in parallel. Transistors SW1 and SW5 are connected in series, transistors SW2 and SW6 are connected in series, transistors SW7 and SW11 are connected in series, and transistors SW8 and SW12 are connected in series.

[0103] The output circuit described in this embodiment can operate in the following sequentially executed phases: direct output phase, charge sharing phase, cross-output phase, and charge sharing phase.

[0104] Optional, Figure 9 Is Figure 8 The diagram shows the working principle of a direct output stage output circuit. Figure 10 Is Figure 8 The diagram illustrates the working principle of a cross-output stage output circuit. Solid lines indicate enabled paths, while dashed lines indicate disabled paths.

[0105] refer to Figure 9 It can be seen that during the direct output stage, of the two first single-pole single-throw switches K11 and K12 connected to transistors SW5 and SW12, first single-pole single-throw switch K11 is closed, while first single-pole single-throw switch K12 is not closed. Correspondingly, this allows the pull-up power supply terminal V to... T The substrates of the PMOS transistors included in transistors SW5 and SW12 are connected to provide pull-up voltages. Two second single-pole single-throw (SPS) switches K21 and K22 are used; switch K21 is closed, and switch K22 is not closed. Accordingly, the intermediate power supply terminal V is made to... M Intermediate voltages are provided to the substrates of the NMOS transistors included in transistors SW5 and SW12. Additionally, of the two first single-pole single-throw switches K11 and K12 connected to transistors SW6 and SW11, first single-pole single-throw switch K11 is not closed, and first single-pole single-throw switch K12 is closed. Accordingly, the intermediate power supply terminal V can be... M Intermediate voltages are provided to the substrates of the PMOS transistors included in transistors SW6 and SW11. Two second single-pole single-throw (SPS) switches K21 and K22 are connected; switch K21 is open, and switch K22 is closed. Accordingly, this allows the pull-down power supply terminal V to be... B A pull-down voltage is provided to the substrates of the NMOS transistors included in transistors SW6 and SW11. Based on this, the direct path switching sections B1x of the third switching subunit 021 and the second switching unit 03 are both enabled, while the cross-path switching sections B2x are both disabled. That is, transistors SW1, SW5, SW8, and SW12 are all turned on, and the direct paths containing transistors SW1, SW5, SW8, and SW12 are enabled; transistors SW2, SW6, SW7, and SW11 are all turned off, and the cross-paths containing transistors SW2, SW6, SW7, and SW11 are disabled. Furthermore, the pair of output signals INP and INN, buffered by the output buffer unit 01, can be output as follows: Figure 9 The data is transmitted directly to the two output terminals OUT via a direct path. <n>and OUT<N+1> Specifically: the positive output signal INP can be transmitted to the output terminal OUT through the direct path provided by transistors SW1 and SW5. <n>The negative polarity output signal INN can be transmitted to the output terminal OUT through the direct path provided by transistors SW8 and SW12.<N+1> .

[0106] Furthermore, during the direct output phase, in the fourth switching subunit 022, transistors SW4 and SW9, coupled to intermediate nodes n2 and n4 on the deactivated cross-path, can both be turned on, while transistors SW3 and SW10, coupled to intermediate nodes n1 and n3 on the activated direct path, can both be turned off. Consequently, the fourth switching subunit 022 can transmit the intermediate voltage power supply terminal V to the intermediate nodes n2 and n4 on the deactivated cross-path. M The provided intermediate voltage is used to pre-charge intermediate nodes n2 and n4. During the charge-sharing phase following the direct output phase, transistors SW1, SW2, SW7, and SW8 of the third switching subunit 021 can all be turned off, and transistors SW5, SW6, SW11, and SW12 of the second switching subunit 03 can all be turned on, as can transistors SW3, SW4, SW9, and SW10 of the fourth switching subunit 022. Furthermore, the intermediate voltage power supply terminal V... M The provided intermediate voltage can be transmitted to the two output terminals OUT via the transistors activated in the second switching unit 03. <n>and OUT<N+1> In order to achieve charge sharing.

[0107] refer to Figure 10 It can be seen that during the cross-output phase, of the two first single-pole single-throw switches K11 and K12 connected to transistors SW5 and SW12, first single-pole single-throw switch K12 is closed, while first single-pole single-throw switch K11 is not closed. Correspondingly, this allows the intermediate power supply terminal V to... M Intermediate voltages are provided to the substrates of the PMOS transistors included in transistors SW5 and SW12. Two second single-pole single-throw (SPS) switches K21 and K22 are used; switch K22 is closed, and switch K21 is open. This allows the pull-down power supply terminal V to be... B A pull-down voltage is provided to the substrates of the NMOS transistors included in transistors SW5 and SW12. Additionally, of the two first single-pole single-throw switches K11 and K12 connected to transistors SW6 and SW11, first single-pole single-throw switch K11 is closed, and first single-pole single-throw switch K12 is not closed. Accordingly, the pull-up power supply terminal V can be... T The substrates of the PMOS transistors included in transistors SW6 and SW11 are connected to provide pull-up voltages. Two second single-pole single-throw (SPS) switches K21 and K22 are used; switch K21 is closed, and switch K22 is not closed. Accordingly, the intermediate power supply terminal V... M An intermediate voltage is provided to the substrates of the NMOS transistors included in transistors SW6 and SW11. Based on this, the cross-path switching sections B2x included in the third switching subunit 021 and the second switching unit 03 are both enabled, while the direct path switching sections B1x are both disabled. That is, transistors SW2, SW6, SW7, and SW11 are all turned on, and the cross-path containing transistors SW2, SW6, SW7, and SW11 is enabled; transistors SW1, SW5, SW8, and SW12 are all turned off, and the direct path containing transistors SW1, SW5, SW8, and SW12 is disabled. Furthermore, the pair of output signals INP and INN, buffered by the output buffer unit 01, can be output as follows: Figure 10 The data is transmitted to the two output terminals OUT via a cross path.<N+1> and OUT <n>Specifically: the positive output signal INP can be transmitted to the output terminal OUT through the cross path provided by transistors SW2 and SW6.<N+1> The negative polarity output signal INN can be transmitted to the output terminal OUT through the cross path provided by transistors SW7 and SW11. <n>.

[0108] Furthermore, during the cross-output phase, in the fourth switching subunit 022, transistors SW3 and SW10, coupled to intermediate nodes n1 and n3 on the disabled direct path, can both be turned on, while transistors SW4 and SW9, coupled to intermediate nodes n2 and n4 on the enabled cross-path, can both be turned off. Consequently, the fourth switching subunit 022 can transmit the intermediate voltage power supply terminal V to the intermediate nodes n1 and n3 on the disabled direct path. M The provided intermediate voltage is used to pre-charge intermediate nodes n1 and n3. During the charge-sharing phase following the cross-output phase, transistors SW1, SW2, SW7, and SW8 of the third switching subunit 021 can all be turned off, and transistors SW5, SW6, SW11, and SW12 of the second switching subunit 03 can all be turned on, as can transistors SW3, SW4, SW9, and SW10 of the fourth switching subunit 022. Furthermore, the intermediate voltage power supply terminal V... M The provided intermediate voltage can be transmitted to the two output terminals OUT via the transistors activated in the second switching unit 03. <n>and OUT<N+1> In order to achieve charge sharing.

[0109] Therefore, it can also be concluded that transistors SW1 and SW5 can generate a positive output signal INP that is transmitted to the output terminal OUT. <n>A direct path; transistors SW8 and SW12 can form a negative polarity output signal INN that is transmitted to the output terminal OUT.<N+1> A direct path; transistors SW2 and SW6 can form a positive output signal INP that is transmitted to the output terminal OUT.<N+1> The cross path; transistors SW7 and SW11 can form a negative polarity output signal INN to be transmitted to the output terminal OUT. <n>Crossing pathways.

[0110] It should be noted that the aforementioned transistors can be driven within the range between the pull-up voltage and the intermediate voltage, or between the intermediate voltage and the pull-down voltage, used to drive the output buffer unit 01. Therefore, low-voltage transistors can be used to implement each switching unit, instead of using switches driven in high-voltage environments or those with voltage ratings corresponding to high voltages, thus meeting the technical requirements of low power consumption and providing stable electrical characteristics.

[0111] Optional, Figure 11 This is a circuit diagram of another more specific exemplary source driver output circuit provided in this disclosure embodiment. (See reference...) Figure 11 As can be seen, it schematically illustrates four sets of output circuits, showing only the portion of each set used to output the same positive polarity output signal INP. These four sets of output circuits are connected to adjacent odd-numbered output terminals OUT. <1> OUT <3> OUT <5> and OUT <7> Coupled. In these four output circuits, the second switching unit 03 includes four P-type transistors (PMOS). <1> PMOS <2> PMOS <3> and PMOS <4> The substrates are all connected to the pull-up power supply terminal V via two first single-pole single-throw switches K11 and K12 respectively. T and intermediate power supply terminal V M The PMOS transistor is coupled to receive a pull-up voltage or intermediate voltage. In the diagram, the coupling node between the PMOS transistor's substrate and the two first single-pole single-throw switches K11 and K12 is labeled NA. The second switching unit 03 includes four N-type transistors (NMOS). <1> NMOS <2> NMOS <3> and NMOS <4> The substrates are all connected to the intermediate power supply terminal V via two second single-pole single-throw switches K21 and K22 respectively. M and pull-down power supply terminal V B The coupling is used to receive intermediate voltage or pull-down voltage. In the figure, the coupling node between the substrate of the NMOS transistor and the two second single-pole single-throw switches K21 and K22 is marked as NB.

[0112] Optional, Figure 12 Is Figure 11 The diagram shows a layout of the second switching unit in an output circuit. (Reference) Figure 12 It can be seen that, Figure 11 The four P-type transistors PMOS shown <1> PMOS <2> PMOS <3> and PMOS <4> They can share the same well (W); four N-type transistors (NMOS). <1> NMOS <2> NMOS <3> and NMOS <4> They can share the same pit region (PW).

[0113] For example, in embodiments of this disclosure, both P-type and N-type transistors may include a well region, and an active (ACT) region and a source-drain (SD) conductive region located within the well region and overlapping thereon. Specifically, the different active regions ACT and different source-drain conductive regions SD of multiple P-type transistors are located within the same well region NW. Similarly, the different active regions ACT and different source-drain conductive regions SD of multiple N-type transistors are located within the same well region PW.

[0114] Optional, Figure 13 This is a structural layout of a second switching unit in an output circuit in a related technology. The structural layout is a schematic diagram in which transistors of the same type that transmit signals of the same polarity are not located in the same well region.

[0115] contrast Figure 12 and Figure 13 It can be seen that, assuming the length of the source-drain conductive region SD in a P-type transistor is N_TR, the distance between the boundary of the source-drain conductive region SD and the well region PW is N_A, and the distance between the well regions PW of two adjacent P-type transistors is N_B, then in a structure where the four P-type transistors are not located in the same well region, the required length satisfies: N_TR*4+(N_A*6+N_B*3); the required length of the four P-type transistors refers to the farthest distance between the source-drain conductive layers SD of the two P-type transistors that are farthest apart. Since the four P-type transistors in this embodiment can share a single well region PW, it can be assumed that the distance between the well regions PW of two adjacent P-type transistors is N_C, which is generally less than N_B. The required length of the four P-type transistors satisfies: N_TR*4+(N_C*3). N_TR*4+(N_A*6+N_B*3)>>N_TR*4+(N_C*3).

[0116] Similarly, for an N-type transistor, assuming the length of the source / drain conductive region SD in the N-type transistor is P_TR, the distance between the boundary of the source / drain conductive region SD and the well region PW is P_A, and the distance between the well regions PW of two adjacent N-type transistors is P_B, then in a structure where four N-type transistors are not located in the same well region, the required length satisfies: P_TR*4+(P_A*6+P_B*3). Since in this embodiment, four N-type transistors can share a single well region P_WELL, it can be assumed that the distance between the well regions NW of two adjacent N-type transistors is P_C, which is generally less than P_B. The required length of the four N-type transistors then satisfies: P_TR*4+(P_C*3). P_TR*4+(P_A*6+P_B*3)>>P_TR*4+(P_C*3).

[0117] In summary, this disclosure provides an output circuit for a source driver. The output circuit includes an output buffer unit, a first switching unit, and a second switching unit. The output buffer unit buffers a pair of output signals with opposite polarities, and the first and second switching units cooperate to control the transmission of these opposite polarities to two output terminals coupled to different pixels. This allows each unit in the output circuit to operate under the same low-voltage driving environment (including pull-up voltage, pull-down voltage, and intermediate voltage), enabling the use of low-voltage transistors in the output circuit design of the display driver. Furthermore, this helps reduce the power consumption of the display driver.

[0118] Furthermore, since the substrates of transistors of the same type transmitting signals of the same polarity in the second switching unit directly coupled to the output terminal in the output circuit can receive the same substrate voltage, it can be known that these transistors of the same type transmitting signals of the same polarity can share a single well region. This also reduces the area occupied by the output circuit, thereby reducing the area of ​​the source driver.

[0119] Figure 14 This is a schematic block diagram of a source driver provided in an embodiment of this disclosure. (See reference...) Figure 14 As can be seen, the source driver described in this embodiment includes a driving circuit and a plurality of output circuits as described in the above embodiments.

[0120] The drive circuit is configured to transmit a pair of input signals of opposite polarity to the output circuit. Therefore, combined with... Figure 14 As can be seen from the above embodiments, the driving circuit can be coupled to the two input terminals IN(N) and IN(N+1) of the output buffer unit in each output circuit.

[0121] It should be noted that this refers to the driver circuit transmitting a pair of input signals with opposite polarities to an output circuit. For different output circuits, the driver circuit can transmit different input signals to them.

[0122] Since the source driver can have essentially the same technical effect as the output circuit described in the previous embodiments, for the sake of brevity, the technical effect of the source driver will not be described again here.

[0123] Figure 15 This is a schematic block diagram of a display device provided in an embodiment of this disclosure. (See reference) Figure 15 As can be seen, the display device described in the embodiments of this disclosure includes: a display panel, and as follows: Figure 14 The source driver is shown.

[0124] The display panel includes multiple pixels (not shown in the figure). The source driver is configured to transmit multiple pairs of output signals to the multiple pixels through multiple output circuits, with each pair of output signals having opposite polarities. Thus, combined with... Figure 15 As can be seen from the description in the above embodiments, the source driver can utilize its multiple pairs of output terminals (e.g., a pair of output terminals OUT). <n>and OUT<N+1> It can be coupled to the display panel, or more specifically, to multiple pixels in the display panel, so as to transmit multiple pairs of output signals to multiple pixels.

[0125] Since the display device can have essentially the same technical effects as the output circuit included in the source driver described in the previous embodiments, the technical effects of the display device will not be described again here for the sake of brevity.

[0126] It should be noted that the terminology used in the embodiments of this disclosure is for illustrative purposes only and is not intended to limit the scope of this disclosure. Unless otherwise defined, the technical or scientific terms used in the implementation of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains.

[0127] For example, the terms "first," "second," or "third," and similar terms used in this patent application specification and claims, do not indicate any order, quantity, or importance, but are merely used to distinguish different components. "Connection" or "coupled" refers to an electrical connection.

[0128] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0129] The word "includes" or similar terms means that the elements or objects preceding "includes" or "include" cover the elements or objects listed after "includes" or "includes" and their equivalents, but do not exclude other elements or objects.

[0130] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0131] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An output circuit for a source driver, characterized in that, The output circuit includes: The output buffer unit is configured to buffer a pair of input signals with opposite polarities into a pair of output signals with opposite polarities based on the pull-up voltage provided by the pull-up power supply terminal, the intermediate voltage provided by the intermediate power supply terminal, and the pull-down voltage provided by the pull-down power supply terminal. The intermediate voltage is less than the pull-up voltage and greater than the pull-down voltage. The first switching unit is configured to control the pair of output signals to be transmitted to the intermediate node on the corresponding path via a direct path and a cross path, respectively, and to control the intermediate voltage to be transmitted to the intermediate node, wherein the direct path and the cross path of each of the pair of output signals are different; The second switching unit is configured to control the transmission of signals from intermediate nodes on the direct path and intermediate nodes on the cross path to two output terminals, which are used to couple with different pixels in the display panel. The second switching unit includes a plurality of N-type transistors and a plurality of P-type transistors in a one-to-one correspondence. Each P-type transistor and each N-type transistor includes a well region and an active region and a source-drain conductive region located within the well region and arranged in an overlapping manner. A third switching unit is configured to control the same substrate voltage to be transmitted to the substrates of the same type of transistors transmitting the same polarity signal among the plurality of N-type transistors and the plurality of P-type transistors, so that the same type of transistors are under the control of the same body voltage, and the different active regions and different source-drain conductive regions of the same type of transistors are located in the same well region and share the same well; wherein, the third switching unit includes: a first switching subunit corresponding one-to-one with the plurality of P-type transistors, and a second switching subunit corresponding one-to-one with the plurality of N-type transistors, and the first substrate voltage transmitted to the substrates of the plurality of P-type transistors includes the pull-up voltage or the intermediate voltage. The second substrate voltage transmitted to the substrate of the plurality of N-type transistors includes the intermediate voltage or the pull-down voltage; the first switching subunit includes two first single-pole single-throw switches connected in series, the input terminals of the two first single-pole single-throw switches being coupled to the pull-up power supply terminal and the intermediate power supply terminal respectively, and the output terminals of the two first single-pole single-throw switches being coupled to the substrate of the P-type transistor; the second switching subunit includes two second single-pole single-throw switches connected in series, the input terminals of the two second single-pole single-throw switches being coupled to the pull-down power supply terminal and the intermediate power supply terminal respectively, and the output terminals of the two second single-pole single-throw switches being coupled to the substrate of the N-type transistor.

2. The output circuit according to claim 1, characterized in that, The output buffer unit includes: The first output buffer subunit is configured to buffer and output the positive input signal of the pair of opposite polarity input signals as a positive output signal based on the pull-up voltage and the intermediate voltage. The second output buffer subunit is configured to buffer and output the negative input signal of the pair of opposite polarity input signals as a negative output signal based on the intermediate voltage and the pull-down voltage.

3. The output circuit according to claim 1 or 2, characterized in that, The first switching unit includes: The third switch subunit is configured to control the pair of output signals to be transmitted to the intermediate nodes on the corresponding paths via direct paths and cross paths, respectively. The fourth switching subunit is configured to control the transmission of the intermediate voltage to the intermediate node.

4. The output circuit according to claim 3, characterized in that, Both the third switch subunit and the second switch unit include a direct path switch section for providing a direct path and a cross path switch section for providing a cross path; The direct path switch unit in the third switch subunit is configured to control the pair of output signals to be transmitted to the intermediate node on the direct path through the corresponding direct path, and the direct path switch unit in the second switch unit is configured to control the signal of the intermediate node on the direct path to be transmitted to the two output terminals. The cross-path switch in the third switch subunit is configured to control the pair of output signals to be transmitted to the intermediate node on the cross-path via the corresponding cross-path, and the cross-path switch in the second switch unit is configured to control the signal of the intermediate node on the cross-path to be transmitted to the two output terminals.

5. A source driver, characterized in that, The source driver includes: a driving circuit, and a plurality of output circuits as described in any one of claims 1 to 4; The driving circuit is configured to transmit a pair of input signals with opposite polarities to the output circuit.

6. A display device, characterized in that, The display device includes: a display panel, and a source driver as described in claim 5; The display panel includes multiple pixels, and the source driver is configured to transmit multiple pairs of output signals to the multiple pixels through multiple output circuits, with each pair of output signals having opposite polarities.

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