A corrugated gate-all-around SOI LDMOS device

Abstract

The present invention discloses a folded ring-gate SOI LDMOS device, which uses a ring surface gate, a buried gate and a trench gate to jointly form a folded ring-gate structure. Such a folded ring-gate structure significantly increases the effective length and width of the channel of the SOI LDMOS device, alleviates the contradiction between the breakdown voltage and the on-resistance of the device caused by the limitations of the channel length and width, effectively reduces the on-resistance of the device on the premise of ensuring the breakdown voltage, improves the overall on-state performance, and at the same time can increase the current flux and provide better heat conduction and heat dissipation capabilities, which is of great significance for improving the device performance. In addition, the folded ring-gate structure is compatible with the traditional power integrated circuit process, solves the process challenges of SOI LDMOS devices with a smaller channel width to a certain extent, and meets the development requirements of SOI intelligent power integrated circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a corrugated gate-all-around SOI LDMOS device. Background Art

[0002] SOI LDMOS devices are widely used in academic research due to their excellent integration capabilities. Due to the limitations of the channel length and width of SOI LDMOS devices, there is a constraint relationship between the breakdown voltage and the on-resistance of the device. Therefore, the research focus of SOI LDMOS devices is to improve the contradictory relationship between the breakdown voltage and the on-resistance to enhance the overall performance of the device. The gate-all-around SOI LDMOS device is an improved SOI LDMOS structure, and its main feature is the introduction of a circular gate in the LDMOS structure. The gate-all-around SOI LDMOS device provides a reliable and efficient solution for high-performance power applications through characteristics such as optimized electric field distribution control, reduced leakage current, increased breakdown voltage, decreased on-resistance, and improved switching speed. However, the longitudinal electrode region introduced by this structure occupies a large amount of chip area, resulting in a decline in device performance. Moreover, there are problems such as surface electric field concentration and severe non-uniformity of the body electric field distribution in the lateral breakdown voltage structure of power devices, which weaken the drift region charge depletion effect and the breakdown voltage capability, becoming a bottleneck restricting the development and application of three-dimensional power devices. Therefore, how to achieve three-dimensional breakdown voltage of the drift region using the lateral structure of the device and relieve the contradictory relationship between the breakdown voltage and the on-resistance by reconstructing the body electric field is a thorny problem worthy of in-depth exploration in the field of power device design. Summary of the Invention

[0003] The present invention aims to solve the problems of small channel width, low breakdown voltage, and difficult process existing in the existing gate-all-around SOI LDMOS, and provides a corrugated gate-all-around SOI LDMOS device.

[0004] To solve the above problems, the present invention is realized through the following technical solutions:

[0005] A folded-ring-gate SOI LDMOS device includes a substrate layer, a buried oxide layer, a channel region, a drift region, a drain region, a source region, a ring surface gate, a buried gate, a source, a drain, and a gate; the buried oxide layer is disposed above the substrate layer; the channel region and the drift region are disposed above the buried oxide layer, and the channel region and the drift region are adjacent to each other; the source region is in the channel region; the drain region is in the drift region; the buried gate is horizontally embedded in the buried oxide layer and is located directly below the channel region; the ring surface gate is disposed around the outer surface of the channel region, and an insulating medium is connected between the entire inner surface of the ring surface gate and the entire outer surface of the channel region; the buried gate and the ring surface gate are connected through an electrode wire; the source S is led out from the source region, the drain D is led out from the drain region, and the gate G is led out from the ring surface gate; the difference is that it further includes at least one trench gate; the trench gate is vertically embedded in the channel region, the upper surface of the trench gate is flush with the upper surface of the channel region, and the lower surface of the trench gate is higher than the lower surface of the channel region; the upper surface of the trench gate is directly connected and communicated with the ring surface gate.

[0006] In the above solution, the trench gate is vertically or obliquely embedded in the channel region.

[0007] In the above solution, all the trench gates have the same angle with the vertical direction.

[0008] In the above solution, the trench gate is made of the same material as the ring surface gate and the buried gate.

[0009] In the above solution, the ring surface gate, the buried gate, and the trench gate are made of polysilicon or aluminum.

[0010] In the above solution, insulating media are coated on all surfaces of the trench gate embedded in the channel region.

[0011] In the above solution, the insulating medium is silicon dioxide or silicon nitride.

[0012] In the above solution, the horizontal part of the ring surface gate, that is, the part located above the channel region and the trench gate, is integrally concave-convex.

[0013] In the above solution, all the trench gates are square-shaped.

[0014] Compared with the prior art, on the basis of the existing annular-gate SOI LDMOS device, the present invention adds a trench gate. The annular surface gate, buried gate and trench gate together form a corrugated annular-gate structure. Such a corrugated annular-gate structure significantly increases the effective length and width of the channel of the SOI LDMOS device, alleviates the contradiction between the breakdown voltage and on-resistance of the device caused by the limitations of the channel length and width. On the premise of ensuring the breakdown voltage, the on-resistance of the device is effectively reduced, the overall on-state performance is improved. At the same time, the current flux can be increased, and better heat conduction and heat dissipation capabilities can be provided, which is of great significance for improving the device performance. In addition, the corrugated annular-gate structure is compatible with the traditional power integrated circuit process, which solves the process challenges of the SOI LDMOS device with a small channel width to a certain extent and meets the development requirements of the SOI smart power integrated circuit. Brief Description of the Drawings

[0015] Figure 1 It is a schematic perspective view of the three-dimensional structure of a corrugated annular-gate SOI LDMOS device.

[0016] Figure 2 It is an internal perspective three-dimensional view of the corrugated annular-gate SOI LDMOS device with part of the annular surface gate removed.

[0017] Reference numerals in the figure: 1, substrate layer; 2, buried oxide layer; 3, channel region; 4, drift region; 5, drain region; 6, source region; 7, annular surface gate; 8, buried gate; 9, trench gate; 10, insulating medium; 11, electrode wire. Detailed Description of the Invention

[0018] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific examples and the accompanying drawings. It should be noted that the directional terms mentioned in the examples, such as "upper", "lower", "middle", "left", "right", "front", "rear", etc., are only the directions with reference to the accompanying drawings. Therefore, the directions used are only for illustration and not for limiting the protection scope of the present invention.

[0019] A corrugated annular-gate SOI LDMOS device, as Figure 1 and 2As shown, it includes a substrate layer 1, a buried oxide layer 2, a channel region 3, a drift region 4, a drain region 5, a source region 6, a surrounding surface gate 7, a buried gate 8, a trench gate 9, a source, a drain, and a gate. The buried oxide layer 2 is disposed above the substrate layer 1. The channel region 3 and the drift region 4 are disposed above the buried oxide layer 2, and the channel region 3 and the drift region 4 are adjacent to each other, where the channel region 3 is in the front and the drift region 4 is in the rear. The source region 6 is in the channel region 3 and is located at the upper front side of the channel region 3. The source S is led out from the source region 6. The drain region 5 is in the drift region 4 and is located at the upper rear side of the drift region 4. The drain D is led out from the drain region 5. The surrounding surface gate 7, the buried gate 8, and the trench gate 9 together form a gate region. The gate G is led out from the gate region, that is, the surrounding surface gate 7.

[0020] The surrounding surface gate 7 is in an n shape, that is, it includes 1 horizontal part and 2 vertical parts. The upper ends of the 2 vertical parts are connected to the two ends of the horizontal part, and the lower ends of the 2 vertical parts are suspended. The surrounding surface gate 7 surrounds the outer surface of the channel region 3, that is, the upper surface and the left and right side surfaces, and an insulating medium 10 is connected between the entire inner surface of the surrounding surface gate 7 and the entire outer surface of the channel region 3. That is: the horizontal part of the surrounding surface gate 7 covers the upper surface of the channel region 3, and an insulating medium 10 is provided between the inner surface of the horizontal part of the surrounding surface gate 7 and the upper surface of the channel region 3; the 2 vertical parts of the surrounding surface gate 7 respectively cover the left and right side surfaces of the channel region 3, and an insulating medium 10 is provided between the inner surfaces of the 2 vertical parts of the surrounding surface gate 7 and the left and right side surfaces of the channel region 3. The insulating medium 10 realizes electrical isolation between the surrounding surface gate 7 and the channel region 3.

[0021] The buried gate 8 is in a flat plate shape and is horizontally embedded into the buried oxide layer 2 from the front side of the buried oxide layer 2 and is located directly below the entire channel region 3. The front surface and the left and right side surfaces of the buried gate 8 are flush with the front surface and the left and right side surfaces of the buried oxide layer 2 respectively, and the rear surface of the buried gate 8 is flush with the rear surface of the channel region 3 in the longitudinal projection. The buried gate 8 is connected to the surrounding surface gate 7 through an electrode wire 11.

[0022] The number of trench gates 9 is one or more. In the present invention, the number of trench gates 9 is 2 to 10. These trench gates 9 are all square-shaped and are evenly distributed in the channel region 3 in the left-right direction, and each trench gate 9 is independent. The trench gates 9 are longitudinally embedded into the channel region 3 from the upper surface of the channel region 3, and the trench gates 9 have the same angle α with the vertical direction. In the present invention, the trench gates 9 can be vertically embedded into the channel region 3, and at this time the angle α between the trench gates 9 and the vertical direction is 0°; the trench gates 9 can also be inclined to the left or right and embedded into the channel region 3, and at this time the value range of the angle α is 0°, 30°]. The upper surface of the trench gate 9 is flush with the upper surface of the channel region 3, the lower surface of the trench gate 9 is higher than the lower surface of the channel region 3, the front surface of the trench gate 9 is flush with the front surface of the channel region 3, and the rear surface of the trench gate 9 is flush with the rear surface of the channel region 3. The upper surface of the trench gate 9 is directly connected and communicated with the inner surface of the lateral part of the ring surface gate 7. Each surface of the trench gate 9 embedded in the channel region 3, that is, the left and right surfaces, the front and rear surfaces, and the lower surface of the trench gate 9, is coated with an insulating medium 10 to achieve electrical isolation between the trench gate 9 and the channel region 3.

[0023] Since the lateral part of the ring surface gate 7 is connected to the upper surface of the channel region 3 through the insulating medium 10, and the lateral part of the ring surface gate 7 is directly connected to the upper surface of the trench gate 9, when the lateral part of the ring surface gate 7 has a uniform thickness, the lateral part of the ring surface gate 7 will present an uneven shape as a whole, that is, the upper and lower surfaces of the lateral part of the ring surface gate 7 are both non-planar surfaces. The ring surface gate 7, the buried gate 8, and the trench gate 9 are used as the gate regions of the SOI LDMOS device, and the materials used for the three are the same, and they can use the gate materials commonly used in SOI LDMOS devices, such as polysilicon or aluminum, etc. The insulating material is used to achieve electrical isolation between the gate region and the channel region 3, and it uses the insulating materials commonly used in SOI LDMOS devices, such as silicon dioxide or silicon nitride, etc.

[0024] Compared with the traditional ring-gate SOI LDMOS device, the gate region of the corrugated ring-gate SOI LDMOS device is composed of a surface gate, a trench gate 9, and a buried gate 8 to jointly form a corrugated ring-gate structure, and realizes three-dimensional complete wrapping of the gate to the channel region 3, forming a closed electron channel around. At this time, electrons are more easily guided and accelerated under the action of the gate, thereby improving the electron mobility and conductivity in the channel, and improving the constraint relationship between the LDMOS on-resistance and breakdown voltage. The embedded trench gate 9 can effectively increase the effective length and width of the channel region 3. The effective length of the channel region 3 is determined by the vertical height of the trench gate 9, and the effective width of the channel region 3 is determined by the horizontal distance between the trench gates 9, that is, the greater the vertical height of the trench gate 9 and the greater the horizontal distance between the trench gates 9, the better the corrugation effect, and the greater the improvement amplitude of the channel width and the effective length. The embedded trench gate 9 can also increase the current flux and provide better heat conduction and heat dissipation capabilities. Figure 1The direction indicated by the black dashed arrow shown in the figure is the heat flow direction, and the position where the arrow is located is the heat dissipation path; when conducting in the forward direction, the current in the newly added channel region 3 of the folded gate-all-around structure mainly flows through the bottom of the drift region 4. The thermal conductivity of the buried gate 8 metal electrode is higher than that of the buried oxide layer 2 dielectric, and more heat flows from the buried gate 8 to the substrate, alleviating the self-heating performance of the device. The embedded trench gate 9 also introduces new electric field peaks in the buried oxide layer 2, reconstructs the body electric field, and improves the breakdown voltage characteristics of the device. It can also disperse the electric field, reduce the electric field concentration, and lower the breakdown risk; it can also form a new double-layer channel region 3 under the trench gate 9. Figure 2 As shown by the white dashed box, the utilization rate of the device area is also improved. Thus, it can be seen that the present invention uses the ring surface gate 7, trench gate 9, and buried gate 8 to establish a folded gate-all-around structure, which solves the problems of small channel width and process difficulties to a certain extent, and alleviates the constraint relationship between the breakdown voltage and on-resistance of the device; the application of this technology can improve the device performance and provide a new idea for solving the challenges in device design.

[0025] It should be noted that although the embodiments described above of the present invention are illustrative, they are not limitations of the present invention. Therefore, the present invention is not limited to the above specific embodiments. Without departing from the principle of the present invention, any other embodiments obtained by those skilled in the art under the inspiration of the present invention are deemed to be within the protection scope of the present invention.

Claims

1. A folded-ring-gate SOI LDMOS device, comprising a substrate layer (1), a buried oxide layer (2), a channel region (3), a drift region (4), a drain region (5), a source region (6), a ring surface gate (7), a buried gate (8), a source electrode, a drain electrode and a gate electrode; the buried oxide layer (2) is disposed above the substrate layer (1); the channel region (3) and the drift region (4) are disposed above the buried oxide layer (2), and the channel region (3) is adjacent to the drift region (4); the source region (6) is located in the channel region (3); the drain region (5) is located in the drift region (4); the buried gate (8) is laterally embedded in the buried oxide layer (2) and is located directly below the channel region (3); the ring surface gate (7) is disposed around the outer surface of the channel region (3), and the entire inner surface of the ring surface gate (7) is connected to the entire outer surface of the channel region (3) through an insulating medium (10); the buried gate (8) is connected to the ring surface gate (7) through an electrode wire (11); the source electrode S is led out from the source region (6), the drain electrode D is led out from the drain region (5), and the gate electrode G is led out from the ring surface gate (7); Characterized in that, it further includes at least one trench gate (9); the trench gate (9) is vertically or obliquely embedded in the channel region (3); the upper surface of the trench gate (9) is directly connected and communicated with the ring surface gate (7).

2. A folded-ring-gate SOI LDMOS device according to claim 1, Characterized in that, all the trench gates (9) have the same angle with the vertical direction.

3. A folded-ring-gate SOI LDMOS device according to claim 1, Characterized in that, the trench gate (9) is made of the same material as the ring surface gate (7) and the buried gate (8).

4. A folded-ring-gate SOI LDMOS device according to claim 1 or 3, Characterized in that, the ring surface gate (7), the buried gate (8) and the trench gate (9) are made of polysilicon or aluminum.

5. A folded-ring-gate SOI LDMOS device according to claim 1, Characterized in that, each surface of the trench gate (9) embedded in the channel region (3) is coated with an insulating medium (10).

6. A folded-ring-gate SOI LDMOS device according to claim 1 or 5, Characterized in that, the insulating medium (10) is silicon dioxide or silicon nitride.

7. A folded-ring-gate SOI LDMOS device according to claim 1, Characterized in that, the lateral part of the ring surface gate (7), i.e., the part located above the channel region (3) and the trench gate (9), is integrally concave-convex.

8. A folded-ring-gate SOI LDMOS device according to claim 1, Characterized in that, all the trench gates (9) are square-shaped.

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