Pixel circuit, driving method thereof, display panel and display device

Abstract

A pixel circuit and a driving method thereof, a display panel and a display device. The pixel circuit comprises a data writing circuit, a driving circuit and a compensation circuit; the driving circuit comprises a control end, a first end and a second end, and the compensation circuit is connected to the control end, the first end and the second end of the driving circuit and is configured to write a compensation voltage based on a first reset voltage into the control end of the driving circuit under the control of a compensation control signal; the data writing circuit is connected to the control end of the driving circuit and is configured to write a coupling voltage based on a data voltage into the control end of the driving circuit under the control of a scanning signal; and the driving circuit is configured to control a driving current for driving a light emitting element to emit light under the control of a voltage applied to the control end of the driving circuit.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a pixel circuit and its driving method, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels possess characteristics such as self-illumination, high contrast, low power consumption, wide viewing angle, fast response speed, applicability to flexible panels, wide operating temperature range, and simple manufacturing, making them promising for future development. As a next-generation display technology, OLED display panels can be widely used in devices with display functions, such as mobile phones, monitors, laptops, digital cameras, and instruments. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a pixel circuit, including: a data writing circuit, a driving circuit, and a compensation circuit; wherein, the driving circuit includes a control terminal, a first terminal, and a second terminal; the compensation circuit is connected to the control terminal, the first terminal, and the second terminal of the driving circuit, and is configured to write a compensation voltage based on a first reset voltage to the control terminal of the driving circuit under the control of a compensation control signal; the data writing circuit is connected to the control terminal of the driving circuit and is configured to write a coupling voltage based on a data voltage to the control terminal of the driving circuit under the control of a scan signal; the driving circuit is configured to control the driving current for driving a light-emitting element to emit light under the control of a voltage applied to the control terminal of the driving circuit.

[0004] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the data writing circuit includes a first data writing sub-circuit and a second data writing sub-circuit, the scan signal includes a first scan sub-signal and a second scan sub-signal, the first data writing sub-circuit is connected to a data writing node and configured to write the data voltage to the data writing node under the control of the first scan sub-signal; the second data writing sub-circuit is connected to the data writing node and the control terminal of the driving circuit and configured to write the coupling voltage based on the voltage of the data writing node to the control terminal of the driving circuit under the control of the second scan sub-signal.

[0005] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the first data writing sub-circuit includes a first data writing transistor, the second data writing sub-circuit includes a second data writing transistor and a first capacitor, the first terminal of the first data writing transistor is configured to receive the data voltage, the second terminal of the first data writing transistor is connected to the data writing node, the gate of the first data writing transistor is configured to receive the first scan sub-signal, the first terminal of the first capacitor is connected to the data writing node, the second terminal of the first capacitor is connected to the first terminal of the second data writing transistor, the second terminal of the second data writing transistor is connected to the control terminal of the driving circuit, and the gate of the second data writing transistor is configured to receive the second scan sub-signal.

[0006] For example, at least one embodiment of the pixel circuit provided in this disclosure further includes: a first reset circuit, wherein the first reset circuit is connected to the data writing node and is configured to write a second reset voltage into the data writing node under the control of a first reset control signal to reset the data writing node.

[0007] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the first reset circuit includes a first reset transistor, a first terminal of the first reset transistor is configured to receive a second reset voltage, a second terminal of the first reset transistor is connected to the data writing node, and a gate of the first reset transistor is configured to receive the first reset control signal.

[0008] For example, in the pixel circuit provided in at least one embodiment of this disclosure, the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit, and the compensation control signal includes a first compensation control sub-signal and a second compensation control sub-signal. The first compensation sub-circuit is connected to the second terminal of the driving circuit and is configured to write the first reset voltage to the second terminal of the driving circuit under the control of the first compensation control sub-signal. The second compensation sub-circuit is connected to the first terminal of the driving circuit and the control terminal of the driving voltage and is configured to write the compensation voltage to the control terminal of the driving circuit under the control of the second compensation control sub-signal.

[0009] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the first compensation sub-circuit includes a first compensation transistor, the second compensation sub-circuit includes a second compensation transistor, the first terminal of the first compensation transistor is configured to receive the first reset voltage, the second terminal of the first compensation transistor is connected to the second terminal of the driving circuit, and the gate of the first compensation transistor is configured to receive the first compensation control sub-signal; the first terminal of the second compensation transistor is connected to the first terminal of the driving circuit, the second terminal of the second compensation transistor is connected to the control terminal of the driving circuit, and the gate of the second compensation transistor is configured to receive the second compensation control sub-signal.

[0010] For example, at least one embodiment of the pixel circuit provided in this disclosure further includes a storage circuit, wherein the storage circuit is connected to the control terminal of the driving circuit and the first terminal of the light-emitting element, and is configured to store the voltage of the control terminal of the driving circuit.

[0011] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the storage circuit includes a second capacitor, the first terminal of the second capacitor is connected to the control terminal of the driving circuit, and the second terminal of the second capacitor is connected to the first terminal of the light-emitting element.

[0012] For example, at least one embodiment of the pixel circuit provided in this disclosure further includes an isolation circuit, wherein the isolation circuit is connected between the control terminal of the driving circuit and the storage circuit, and is configured to disconnect the connection between the control terminal of the driving circuit and the storage circuit when the data writing circuit writes the coupling voltage based on the data voltage to the control terminal of the driving circuit under the control of an isolation control signal.

[0013] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the isolation circuit includes an isolation transistor, a first terminal of which is connected to the control terminal of the driving circuit, a second terminal of which is connected to the storage circuit, and the gate of which is configured to receive the isolation control signal.

[0014] For example, in the pixel circuit provided in at least one embodiment of this disclosure, the phase of the isolation control signal is opposite to the phase of the second scan sub-signal.

[0015] For example, at least one embodiment of the pixel circuit provided in this disclosure further includes: a second reset circuit, wherein the second reset circuit is connected to a first terminal of the light-emitting element and is configured to write a third reset voltage to the first terminal of the light-emitting element under the control of a second reset control signal to reset the first terminal of the light-emitting element.

[0016] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the second reset circuit includes a second reset transistor, the first terminal of the second reset transistor is connected to the first terminal of the light-emitting element, the second terminal of the second reset transistor is configured to receive the third reset voltage, and the gate of the second reset transistor is configured to receive the second reset control signal.

[0017] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the first reset voltage and the third reset voltage are the same.

[0018] For example, at least one embodiment of the pixel circuit provided in this disclosure further includes a first light-emitting control circuit, wherein the first light-emitting control circuit is connected to a first end of the light-emitting element and a second end of the driving circuit, and is configured to control the connection between the first end of the light-emitting element and the second end of the driving circuit to be disconnected or connected under the control of a first light-emitting control signal.

[0019] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the first light-emitting control circuit includes a first light-emitting control transistor, the gate of the first light-emitting control transistor is configured to receive the first light-emitting control signal, the first terminal of the first light-emitting control transistor is connected to the second terminal of the driving circuit, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the light-emitting element.

[0020] For example, at least one embodiment of the pixel circuit provided in this disclosure further includes a second light-emitting control circuit, wherein the second light-emitting control circuit is connected to the first power line and the first end of the driving circuit, and is configured to control the connection between the first end of the driving circuit and the first power line to be disconnected or connected under the control of the second light-emitting control signal.

[0021] For example, in the pixel circuit provided in at least one embodiment of this disclosure, the second light-emitting control circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is configured to receive the second light-emitting control signal, the first terminal of the second light-emitting control transistor is connected to the first power line, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the driving circuit.

[0022] For example, in a pixel circuit provided in at least one embodiment of this disclosure, the driving circuit includes a driving transistor, the control terminal of the driving circuit includes the control electrode of the driving transistor, the first terminal of the driving circuit includes the first electrode of the driving transistor, and the second terminal of the driving circuit includes the second electrode of the driving transistor.

[0023] At least one embodiment of this disclosure also provides a pixel circuit, including: a data writing circuit, a driving circuit, a compensation circuit, a storage circuit, a first reset circuit, a second reset circuit, a first light emission control circuit, and a second light emission control circuit; wherein, the driving circuit includes a driving transistor, the data writing circuit includes a first data writing sub-circuit and a second data writing sub-circuit, the first data writing sub-circuit includes a first data writing transistor, the second data writing sub-circuit includes a second data writing transistor and a first capacitor, a first terminal of the first data writing transistor is configured to receive the data voltage, a second terminal of the first data writing transistor is connected to the data writing node, a gate of the first data writing transistor is configured to receive a first scan sub-signal, a first terminal of the first capacitor is connected to the data writing node, a second terminal of the first capacitor is connected to the first terminal of the second data writing transistor, a second terminal of the second data writing transistor is connected to the gate of the driving transistor, and the gate of the second data writing transistor is configured to receive a second scan sub-signal; the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit, the first compensation sub-circuit includes a first compensation transistor, the second compensation sub-circuit includes a second compensation transistor, a first terminal of the first compensation transistor is configured to receive a first reset voltage, and a second terminal of the first compensation transistor is connected to the driving transistor. The second electrode, the gate of the first compensation transistor is configured to receive a first compensation control sub-signal; the first electrode of the second compensation transistor is connected to the first electrode of the driving transistor, the second electrode of the second compensation transistor is connected to the gate of the driving transistor, and the gate of the second compensation transistor is configured to receive a second compensation control sub-signal; the first reset circuit includes a first reset transistor, the first electrode of the first reset transistor is configured to receive a second reset voltage, the second electrode of the first reset transistor is connected to the data write node, and the gate of the first reset transistor is configured to receive a first reset control signal; the storage circuit includes a second capacitor, the first electrode of the second capacitor is connected to the gate of the driving transistor, and the second electrode of the second capacitor is connected to the first terminal of the light-emitting element; the second reset circuit includes a second reset transistor, the first electrode of the second reset transistor is connected to the first terminal of the light-emitting element, the second electrode of the second reset transistor is configured to receive a third reset voltage, and the gate of the second reset transistor is configured to receive a second reset control signal; the first light-emitting control circuit includes a first light-emitting control transistor, the gate of the first light-emitting control transistor is configured to receive a first light-emitting control signal, the first electrode of the first light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is connected to the first terminal of the light-emitting element;The second light-emitting control circuit includes a second light-emitting control transistor, the gate of which is configured to receive a second light-emitting control signal. The first terminal of the second light-emitting control transistor is connected to a first power supply line, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the driving transistor.

[0024] For example, at least one embodiment of the pixel circuit provided in this disclosure further includes an isolation circuit, wherein the isolation circuit includes an isolation transistor, the second capacitor is connected to the gate of the driving transistor through the isolation transistor, the first terminal of the isolation transistor is connected to the gate of the driving transistor, the second terminal of the isolation transistor is connected to the first terminal of the second capacitor, and the gate of the isolation transistor is configured to receive an isolation control signal.

[0025] At least one embodiment of this disclosure also provides a driving method applied to a pixel circuit according to any embodiment of this disclosure, comprising: in a compensation phase, writing a compensation voltage based on a first reset voltage to a control terminal of the driving circuit; in a data writing phase, writing a coupling voltage based on the data voltage to a control terminal of the driving circuit; and in a light emission phase, driving the light-emitting element to emit light based on the voltage of the control terminal of the driving circuit.

[0026] For example, in a driving method provided in at least one embodiment of this disclosure, when the data writing circuit includes a first data writing sub-circuit and a second data writing sub-circuit, the first data writing sub-circuit is connected to a data writing node, and the second data writing sub-circuit is connected to the data writing node and the control terminal of the driving circuit, the driving method includes: during the compensation phase, writing a second reset voltage to the data writing node to reset the data writing node.

[0027] For example, the driving method provided in at least one embodiment of this disclosure further includes: resetting the first end of the light-emitting element during a reset phase.

[0028] At least one embodiment of this disclosure also provides a display panel including pixel circuitry according to any embodiment of this disclosure.

[0029] At least one embodiment of this disclosure also provides a display device, including a display panel according to any embodiment of this disclosure. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0031] Figure 1This is a schematic diagram of a pixel circuit structure;

[0032] Figure 2A A schematic diagram of a pixel circuit provided for at least one embodiment of this disclosure;

[0033] Figure 2B A schematic diagram of another pixel circuit provided for at least one embodiment of this disclosure;

[0034] Figure 3A This is a schematic diagram of the structure of a pixel circuit provided in at least one embodiment of the present disclosure;

[0035] Figure 3B A schematic diagram of another pixel circuit provided in at least one embodiment of the present disclosure;

[0036] Figure 4 A schematic flowchart illustrating a method for driving a pixel circuit according to at least one embodiment of this disclosure;

[0037] Figure 5A A circuit timing diagram of a pixel circuit provided for at least one embodiment of this disclosure;

[0038] Figure 5B A circuit timing diagram of another pixel circuit provided for at least one embodiment of this disclosure;

[0039] Figure 6 A schematic block diagram of a display panel provided for at least one embodiment of this disclosure;

[0040] Figure 7 A schematic block diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0043] Figure 1 This is a schematic diagram of a pixel circuit.

[0044] like Figure 1 As shown, the pixel circuit 100 has a 7T1C (i.e., 7 transistors and 1 capacitor) structure. The pixel circuit 100 includes first transistors M1 to seventh transistors M7 and a storage capacitor Ct. The first transistor M1 is a driving transistor and is configured to generate a driving current for driving the light-emitting element 110 to emit light. For example, the gate of the first transistor M1 is coupled to node A1, the first terminal of the first transistor M1 is coupled to node A2, the second terminal of the first transistor M1 is coupled to node A3, the gate of the second transistor M2 is configured to receive a control signal Rt1, the first terminal of the second transistor M2 is configured to receive a reset voltage Vre, the second terminal of the second transistor M2 is coupled to node A1, the gate of the third transistor M3 is configured to receive a control signal Rt2, the first terminal of the third transistor M3 is configured to receive an initial voltage Vin, the second terminal of the third transistor M3 is coupled to node A4, the gates of the fourth transistor M4 and the fifth transistor M5 are configured to receive a control signal Sa, and the first terminal of the fourth transistor M4 is coupled to node A3. The second terminal of the fourth transistor M4 is coupled to node A1. The first terminal of the fifth transistor M5 is configured to receive the data signal Da. The second terminal of the fifth transistor M5 is coupled to node A2. The first terminal of the sixth transistor M6 is coupled to the power supply line Vd. The second terminal of the sixth transistor M6 is coupled to node A2. The gates of the sixth transistor M6 and the seventh transistor M7 are configured to receive the control signal ES. The first terminal of the seventh transistor M7 is coupled to node A3. The second terminal of the seventh transistor M7 is coupled to node A4. The anode of the light-emitting element 110 is coupled to node A4. The cathode of the light-emitting element 110 is coupled to the power supply line Vs. The first terminal of the storage capacitor Ct is coupled to node A1. The second terminal of the storage capacitor Ct is coupled to the power supply line Vd.

[0045] like Figure 1 As shown, the first terminal of the first transistor M1, the second terminal of the fifth transistor M5, and the second terminal of the sixth transistor M6 are all coupled to node A2, that is, the first terminals of the first transistor M1, the second terminals of the fifth transistor M5, and the second terminals of the sixth transistor M6 are electrically connected to each other; the second terminals of the first transistor M1, the first terminals of the fourth transistor M4, and the first terminals of the seventh transistor M7 are all coupled to node A3, that is, the second terminals of the first transistor M1, the first terminals of the fourth transistor M4, and the first terminals of the seventh transistor M7 are electrically connected to each other; the second terminals of the third transistor M3, the second terminals of the seventh transistor M7, and the anode of the light-emitting element 110 are all coupled to node A4, that is, the second terminals of the third transistor M3, the second terminals of the seventh transistor M7, and the anode of the light-emitting element 110 are electrically connected to each other; the gate of the first transistor M1, the second terminal of the second transistor M2, the second terminal of the fourth transistor M4, and the first terminal of the storage capacitor Ct are all coupled to node A1, that is, the gate of the first transistor M1, the second terminal of the second transistor M2, the second terminal of the fourth transistor M4, and the first terminal of the storage capacitor Ct are electrically connected to each other.

[0046] For example, pixel circuit 100 is a circuit based on LTPO (Low Temperature Polycrystalline Oxide) technology, that is, pixel circuit 100 includes oxide thin-film transistors and low temperature polycrystalline silicon thin-film transistors. For example, pixel circuit 100 includes two oxide (e.g., indium gallium zinc oxide, IGZO) thin-film transistors and five low temperature polycrystalline silicon (LTPS) thin-film transistors. For example, the second transistor M2 and the fourth transistor M4 are IGZO thin-film transistors, and the first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are LTPS thin-film transistors.

[0047] For example, Figure 1 The driving process of the pixel circuit 100 shown includes a reset stage, a data writing compensation stage, and a light emission stage.

[0048] During the reset phase, under the control of control signal Rt1, the second transistor M2 is turned on, and the reset voltage Vre is provided to node A1, i.e., the gate of the first transistor M1, via the second transistor M2, thereby resetting the gate of the first transistor M1. Under the control of control signal Rt2, the third transistor M3 is turned on, and the initial voltage Vin is provided to node A4, i.e., the anode of the light-emitting element 110, via the third transistor M3, thereby resetting the anode of the light-emitting element 110. During the reset phase, the remaining transistors M1 and M4 to M7 in the pixel circuit 100 are all turned off. During the reset phase, the voltage at node A1 is the reset voltage Vre, and the voltage at node A4 is the initial voltage Vin.

[0049] During the data write compensation phase, under the control of the control signal Sa, both the fourth transistor M4 and the fifth transistor M5 are turned on. Because the fourth transistor M4 is on, the gate and second electrode of the first transistor M1 are electrically connected, thus the first transistor M1 is in a diode-connected state and is in saturation. The data signal Da can sequentially charge the storage capacitor Ct via the fifth transistor M5, the first transistor M1, and the fourth transistor M4 until the voltage at node A1 is Da + Vth, where Vth represents the threshold voltage of the first transistor M1, thereby achieving threshold compensation for the first transistor M1. During the data write compensation phase, the remaining transistors M2-M3 and M6-M7 in the pixel circuit 100 are all turned off. During the data write compensation phase, the voltage at node A1 changes from the reset voltage Vin to the voltage Da + Vth.

[0050] During the light-emitting stage, under the control of the control signal ES, both the sixth transistor M6 and the seventh transistor M7 are turned on, and the current path from the power line Vd to the power line Vs is opened. The driving current generated by the first transistor M1 can be transmitted to the light-emitting element 110 through the turned-on first transistor T1, the turned-on sixth transistor M6 and the turned-on seventh transistor M7 to drive the light-emitting element 110 to emit light.

[0051] exist Figure 1 In the pixel circuit 100 shown, data writing and threshold compensation are performed simultaneously. For high-frequency drive display mode, this will result in insufficient compensation time for the pixel circuit, leading to uneven brightness of the display panel and thus affecting the display effect of the display panel.

[0052] Currently, changes in the mobility (Mob) of oxide transistors (OPTs) result in significant variations in their drive current, which is relatively small. This means that fluctuations in the Mob of OPTs have a substantial impact on luminous brightness. In contrast, changes in the Mob of low-temperature polycrystalline silicon (LTPS) transistors (LSPs) result in smaller variations in their drive current, thus having a smaller impact on charging. The lower Mob of OPTs leads to a slower threshold voltage compensation phase. This characteristic necessitates circuit optimization by extending the threshold compensation time to compensate for the lower mobility.

[0053] At least one embodiment of this disclosure provides a pixel circuit, which includes a data writing circuit, a driving circuit, and a compensation circuit. The driving circuit includes a control terminal, a first terminal, and a second terminal. The compensation circuit is connected to the control terminal, the first terminal, and the second terminal of the driving circuit and is configured to write a compensation voltage based on a first reset voltage to the control terminal of the driving circuit under the control of a compensation control signal. The data writing circuit is connected to the control terminal of the driving circuit and is configured to write a coupling voltage based on a data voltage to the control terminal of the driving circuit under the control of a scan signal. The driving circuit is configured to control the driving current for driving a light-emitting element to emit light under the control of a voltage applied to the control terminal of the driving circuit.

[0054] In the pixel circuit provided in the embodiments of this disclosure, the threshold compensation period and the data writing period are separated by the data writing circuit and the compensation circuit, thereby extending the threshold compensation time, improving the threshold compensation effect, achieving the purpose of full compensation, making the compensation time independent of the refresh rate and resolution of the display panel, improving the image quality impact caused by the process, improving the uniformity of display brightness of the display panel, and improving the display effect.

[0055] At least one embodiment of this disclosure also provides a driving method for driving the aforementioned pixel circuit, as well as a display panel and display device including the aforementioned pixel circuit.

[0056] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings; however, this disclosure is not limited to these specific embodiments. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. When any component of an embodiment of the invention appears in more than one drawing, the component is indicated by the same reference numerals in each drawing.

[0057] Figure 2A This is a schematic diagram of a pixel circuit provided for at least one embodiment of the present disclosure. Figure 2B This is a schematic diagram of another pixel circuit provided in at least one embodiment of the present disclosure. Figure 3AThis is a schematic diagram of the structure of a pixel circuit provided in at least one embodiment of the present disclosure. Figure 3B This is a schematic diagram of another pixel circuit structure provided for at least one embodiment of the present disclosure. For example, Figure 3A for Figure 2A The diagram shows an example of the structure of a pixel circuit. Figure 3B for Figure 2B The diagram shows a schematic of an example pixel circuit.

[0058] For example, such as Figure 2A and Figure 2B As shown, the pixel circuit 200 includes a data writing circuit 210, a driving circuit 220, and a compensation circuit 230. For example, the pixel circuit 200 is configured to drive the light-emitting element EL to emit light.

[0059] For example, the pixel circuit 200 provided in this embodiment can be applied to a display panel, such as an OLED display panel (e.g., an AMOLED display panel).

[0060] For example, such as Figure 2A and Figure 2B As shown, the drive circuit 220 includes a control terminal, a first terminal, and a second terminal. For example, the control terminal of the drive circuit 220 is electrically connected to the first node N1, the first terminal of the drive circuit 220 is electrically connected to the second node N2, and the second terminal of the drive circuit 220 is electrically connected to the third node N3.

[0061] For example, the compensation circuit 230 is connected to the control terminal, the first terminal, and the second terminal of the driving circuit 210, i.e., connected to the first node N1, the second node N2, and the third node N3, and is configured to write a compensation voltage based on the first reset voltage to the control terminal of the driving circuit 210 under the control of the compensation control signal; the data writing circuit 210 is connected to the control terminal of the driving circuit 220, i.e. connected to the first node N1, and is configured to write a coupling voltage based on the data voltage to the control terminal of the driving circuit 220 under the control of the scan signal; the driving circuit 220 is configured to control the driving current for the light-emitting element EL to emit light under the control of the voltage applied to the control terminal of the driving circuit 220.

[0062] For example, the voltage at the control terminal of the drive circuit 220 is related to the compensation voltage and the coupling voltage.

[0063] It should be noted that in the embodiments of this disclosure, "connection" refers to electrical connection.

[0064] For example, the light-emitting element (EL) can be a light-emitting diode (LED). The LED can be a micro LED, an organic light-emitting diode (OLED), or a quantum dot LED (QLED). The EL is configured to receive a light emission signal (e.g., a driving current as described above) during operation and emit light of an intensity corresponding to that signal. The EL can, for example, use different light-emitting materials to emit different colors of light, thus achieving colored light emission.

[0065] For example, a light-emitting element (EL) may include a first electrode, a second electrode, and a light-emitting layer disposed between the first and second electrodes. The first electrode of the EL may be an anode, and the second electrode of the light-emitting diode may be a cathode. It should be noted that, in the embodiments of this disclosure, the light-emitting layer of the EL may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer, etc. Generally, a EL has a light-emitting threshold voltage; it emits light when the voltage between the first and second electrodes of the EL is greater than or equal to the light-emitting threshold voltage. In practical applications, the specific structure of the EL can be designed and determined according to the actual application scenario, and is not limited here.

[0066] For example, such as Figure 3A and Figure 3B As shown, the first electrode of the light-emitting element EL is connected to the fourth node N4, and the second electrode of the light-emitting element EL is connected to the second power line Vss.

[0067] For example, such as Figure 3A and Figure 3B As shown, the driving circuit 220 may include a driving transistor T1. The gate of the driving transistor T1 is the control terminal of the driving circuit 220. The first terminal of the driving transistor T1 is the first terminal of the driving circuit 220, and the second terminal of the driving transistor T1 is the second terminal of the driving circuit 220. That is, the gate of the driving transistor T1 is connected to the first node N1, the first terminal of the driving transistor T1 is connected to the second node N2, and the second terminal of the driving transistor T1 is connected to the third node N3.

[0068] For example, in some embodiments, such as Figure 2A and Figure 2BAs shown, the data writing circuit 210 may include a first data writing sub-circuit 2101 and a second data writing sub-circuit 2102. The scan signal includes a first scan sub-signal and a second scan sub-signal. The first data writing sub-circuit 2101 is connected to the data writing node N5 and configured to write a data voltage to the data writing node N5 under the control of the first scan sub-signal. The second data writing sub-circuit 2102 is connected to the data writing node N5 and the control terminal (i.e., the first node N1) of the driving circuit 220 and configured to write a coupled voltage based on the voltage of the data writing node N5 to the control terminal of the driving circuit 220 under the control of the second scan sub-signal. For example, the voltage of the data writing node N5 is obtained based on the data voltage and may include the data voltage.

[0069] For example, in some embodiments, such as Figure 3A and Figure 3B As shown, the first data writing sub-circuit 2101 includes a first data writing transistor T2, and the second data writing sub-circuit 2102 includes a second data writing transistor T3 and a first capacitor C1.

[0070] For example, the first terminal of the first data writing transistor T2 is configured to receive the data voltage Vdata. For example, the first terminal of the first data writing transistor T2 can be connected to the data line Vdata to receive the data voltage Vdata. The second terminal of the first data writing transistor T2 is connected to the data writing node N5. The gate of the first data writing transistor T2 is configured to receive the first scan sub-signal SG1. For example, the gate of the first data writing transistor T2 can be connected to the first scan signal line SG1 to receive the first scan sub-signal SG1.

[0071] For example, the first terminal of the first capacitor C1 is connected to the data writing node N5, the second terminal of the first capacitor C1 is connected to the first terminal of the second data writing transistor T3, the second terminal of the second data writing transistor T3 is connected to the control terminal of the driving circuit 220, i.e. the first node N1, and the gate of the second data writing transistor T3 is configured to receive the second scan sub-signal SG2. For example, the gate of the second data writing transistor T3 can be connected to the second scan signal line SG2 to receive the second scan sub-signal SG2.

[0072] For example, the first scan sub-signal SG1 and the second scan sub-signal SG2 are the same. In some examples, the gate of the first data writing transistor T2 and the gate of the second data writing transistor T3 can be connected to the same signal line (i.e., the first scan signal line SG1 and the second scan signal line SG2 are the same signal line) to receive the same scan signal (i.e., the first scan sub-signal SG1 or the second scan sub-signal SG2), thereby saving the number of signal lines, simplifying the circuit structure, optimizing the circuit layout space, and saving costs. However, this disclosure is not limited to this. The gate of the first data writing transistor T2 and the gate of the second data writing transistor T3 can also be connected to different signal lines (i.e., the first scan signal line SG1 and the second scan signal line SG2 are two different signal lines), so that the first data writing transistor T2 and the second data writing transistor T3 can be controlled separately. For example, the different signal lines output the same signal.

[0073] It should be noted that the first scan sub-signal SG1 received by the gate of the first data writing transistor T2 and the second scan sub-signal SG2 received by the gate of the second data writing transistor T3 may also be different, depending on the type of the first data writing transistor T2 and the second data writing transistor T3 and the driving timing of the pixel circuit 200. This disclosure does not impose any specific restrictions on this.

[0074] For example, in some embodiments, such as Figure 2A and Figure 2B As shown, the compensation circuit 230 is connected to the first node N1, the second node N2, and the third node N3. For example, as... Figure 3A and Figure 3B As shown, the compensation circuit 230 includes a first compensation sub-circuit 2301 and a second compensation sub-circuit 2301, and the compensation control signal includes a first compensation control sub-signal CG1 and a second compensation control sub-signal CG2.

[0075] For example, the first compensation sub-circuit 2301 is connected to the second terminal (i.e., the third node N3) of the drive circuit 220 and is configured to write the first reset voltage Vinit1 to the second terminal of the drive circuit 220 under the control of the first compensation control sub-signal CG1. The second compensation sub-circuit 2302 is connected to the first terminal (i.e., the second node N2) of the drive circuit 220 and the control terminal (i.e., the first node N1) of the drive voltage 220 and is configured to write the compensation voltage to the control terminal of the drive circuit 220 under the control of the second compensation control sub-signal CG2. For example, the second compensation sub-circuit 2302 controls the connection between the first terminal of the drive circuit 220 and the control terminal of the drive voltage 220 to be turned on or off under the control of the second compensation control sub-signal CG2.

[0076] For example, in some embodiments, such as Figure 3A and Figure 3B As shown, the first compensation sub-circuit 2301 includes a first compensation transistor T4, and the second compensation sub-circuit 2302 includes a second compensation transistor T5. The first terminal of the first compensation transistor T4 is configured to receive a first reset voltage Vinit1. For example, the first terminal of the first compensation transistor T4 is connected to the first reset voltage line Vinit1 to receive the first reset voltage Vinit1. That is, the first reset voltage line Vinit1 is used to transmit the first reset voltage Vinit1 to the first terminal of the first compensation transistor T4. The second terminal of the first compensation transistor T4 is connected to the second terminal of the driving circuit 220, i.e., the third node N3. The gate of the first compensation transistor T4 is configured to receive a first compensation control sub-signal CG1. For example, the gate of the first compensation transistor T4 is connected to the first compensation control signal line CG1 to receive the first compensation control sub-signal CG1.

[0077] In the embodiments of this disclosure, the data voltage is written by the data writing circuit 210, and threshold compensation is implemented by the compensation circuit 230. For example, during the data writing phase, the data writing circuit 210 writes a coupling voltage based on the data voltage to the control terminal of the driving circuit 200. During the compensation phase, which is different from the data writing phase, the compensation circuit 230 writes a compensation voltage based on the first reset voltage to the control terminal of the driving circuit 200. Threshold compensation and data writing are implemented separately in two independent phases by two different circuits, without affecting each other, thus avoiding the limitation of the threshold compensation time by the data writing time. For example, the effective time of the first compensation control sub-signal CG1 can determine the compensation time. By controlling the effective time of the first compensation control sub-signal CG1, the length of the threshold compensation time can be controlled, thereby extending the threshold compensation time, improving the threshold compensation effect, and mitigating the image quality impact caused by the process.

[0078] For example, in some embodiments, such as Figure 3A and Figure 3B As shown, the first terminal of the second compensation transistor T5 is connected to the first terminal of the driving circuit 220, i.e., the second node N2, and the second terminal of the second compensation transistor T5 is connected to the control terminal of the driving circuit 220, i.e., the first node N1. The gate of the second compensation transistor T5 is configured to receive the second compensation control sub-signal CG2. For example, the gate of the second compensation transistor T5 is connected to the second compensation control signal line CG2 to receive the second compensation control sub-signal CG2.

[0079] For example, the first compensation control sub-signal CG1 and the second compensation control sub-signal CG2 are different, and the first compensation control signal line CG1 and the second compensation control signal line CG2 are two different signal lines.

[0080] For example, such as Figure 2A and Figure 2B As shown, the pixel circuit 200 also includes a first reset circuit 240, which is connected to the data writing node N5 and configured to write a second reset voltage to the data writing node N5 under the control of a first reset control signal to reset the data writing node N5. The first reset circuit 240 is used to reset the data writing node N5 to prevent the data voltage written to the data writing node N5 in the previous frame from affecting the display of the current frame and to avoid display errors.

[0081] For example, in some embodiments, such as Figure 3A and Figure 3B As shown, the first reset circuit 240 includes a first reset transistor T6. The first terminal of the first reset transistor T6 is configured to receive a second reset voltage Vinit2. For example, the first terminal of the first reset transistor T6 is connected to the second reset voltage line Vinit2 to receive the second reset voltage Vinit2. That is, the second reset voltage line Vinit2 is used to transmit the second reset voltage Vinit2 to the first terminal of the first reset transistor T6. The second terminal of the first reset transistor T6 is connected to the data write node N5. The gate of the first reset transistor T6 is configured to receive a first reset control signal RG1. For example, the gate of the first reset transistor T6 is connected to the first reset control signal line RG1 to receive the first reset control signal RG1.

[0082] For example, in some embodiments, the first reset voltage Vinit1 and the second reset voltage Vinit2 can be the same. In this case, the first reset voltage line Vinit1 and the second reset voltage line Vinit2 can be the same signal line, thereby saving the number of signal lines, reducing circuit complexity, and saving costs. However, this disclosure is not limited to this. The first reset voltage line Vinit1 and the second reset voltage line Vinit2 can also be different signal lines. In this case, the first reset voltage Vinit1 and the second reset voltage Vinit2 can be the same or different.

[0083] For example, such as Figure 2A and Figure 2B As shown, in some embodiments, the pixel circuit 200 may further include a storage circuit 250. For example, the storage circuit 250 is connected to the control terminal of the driving circuit 220 and the first terminal of the light-emitting element EL (i.e., the first electrode of the light-emitting element EL, i.e., the fourth node N4), and is configured to store the voltage of the control terminal of the driving circuit 220.

[0084] For example, in some embodiments, such as Figure 3A and Figure 3BAs shown, the storage circuit 250 may include a second capacitor C2. The first terminal of the second capacitor C2 is connected to the control terminal of the driving circuit 220, i.e., the first node N1, and the second terminal of the second capacitor C2 is connected to the first terminal of the light-emitting element EL, i.e., the fourth node N4. Figure 3A As shown, in some examples, the first terminal of the second capacitor C2 is directly connected to the first node N1.

[0085] For example, in some embodiments, such as Figure 2B As shown, the pixel circuit 200 also includes an isolation circuit 260. The isolation circuit 260 is connected between the control terminal of the driving circuit 220 and the storage circuit 250, and is configured to disconnect the connection between the control terminal of the driving circuit 220 and the storage circuit 250 when the data writing circuit 210 writes a coupled voltage based on the data voltage to the control terminal of the driving circuit 220 under the control of the isolation control signal.

[0086] For example, isolation circuit 260 can isolate the control terminal of driving circuit 220 and storage circuit 250, thereby preventing the coupling effect of the second capacitor C2 in storage circuit 250 from affecting the voltage at the first node N1 when the coupled voltage is written to the control terminal of driving circuit 220, preventing the second capacitor C2 in storage circuit 250 from affecting the coupled voltage written to the control terminal of driving circuit 220, and preventing the first capacitor and the second capacitor from affecting the data range. The data range represents the difference between the data voltage in the white state and the data voltage in the black state, which can determine the overall brightness of the display panel controlled by the driver chip (IC).

[0087] For example, in some embodiments, such as Figure 3B As shown, the isolation circuit 260 includes an isolation transistor T7. The first terminal of the isolation transistor T7 is connected to the control terminal of the driving circuit 220, i.e., the first node N1. The second terminal of the isolation transistor T7 is connected to the storage circuit 250, for example, to the first terminal of the second capacitor C2. The gate of the isolation transistor T7 is configured to receive the isolation control signal IG. For example, the gate of the isolation transistor T7 can be connected to the isolation control signal line IG to receive the isolation control signal IG.

[0088] For example, in some embodiments, the isolation transistor T7 is of the same type as the second data writing transistor T3. In this case, the phase of the isolation control signal IG is opposite to the phase of the second scan sub-signal SG2, so that when the second data writing transistor T3 is turned on, the isolation transistor T7 is turned off.

[0089] For example, in some other embodiments, the type of isolation transistor T7 is different from the type of the second data writing transistor T3. For example, isolation transistor T7 is a P-type transistor and second data writing transistor T3 is an N-type transistor. In this case, the phase of the isolation control signal IG and the phase of the second scan sub-signal SG2 can also be the same, or the isolation control signal IG and the second scan sub-signal SG2 can be the same signal. In this case, the isolation control signal line and the second scan signal line can be the same signal line, thereby saving the number of signal lines.

[0090] It should be noted that this disclosure does not impose specific restrictions on the isolation control signal IG and the second scan sub-signal SG2, as long as the isolation circuit 260 can disconnect the connection between the control terminal of the drive circuit 220 and the storage circuit 250 when the data writing circuit 210 writes the coupling voltage based on the data voltage to the control terminal of the drive circuit 220.

[0091] For example, such as Figure 2A and Figure 2B As shown, the pixel circuit 200 may further include a second reset circuit 270. The second reset circuit 270 is connected to the first terminal of the light-emitting element EL, i.e., the fourth node N4, and is configured to write a third reset voltage to the first terminal of the light-emitting element EL under the control of a second reset control signal to reset the first terminal of the light-emitting element EL.

[0092] For example, in some embodiments, such as Figure 3A and Figure 3B As shown, the second reset circuit 270 includes a second reset transistor T8. The first terminal of the second reset transistor T8 is connected to the first terminal of the light-emitting element EL. The second terminal of the second reset transistor T8 is configured to receive a third reset voltage Vinit3. For example, the second terminal of the second reset transistor T8 can be connected to the third reset voltage line Vinit3 to receive the third reset voltage Vinit3. That is, the third reset voltage line Vinit3 is used to transmit the third reset voltage Vinit3 to the second terminal of the second reset transistor T8. The gate of the second reset transistor T8 is configured to receive a second reset control signal RG2. For example, the gate of the second reset transistor T8 can be connected to the second reset control signal line RG2 to receive the second reset control signal RG2.

[0093] For example, in some embodiments, the first reset voltage Vinit1, the second reset voltage Vinit2, and the third reset voltage Vinit3 are the same. In this case, the first reset voltage line Vinit1, the second reset voltage line Vinit2, and the third reset voltage line Vinit3 can be the same signal line, thereby saving the number of signal lines, reducing circuit complexity, and saving costs. However, this disclosure is not limited to this. At least two of the first reset voltage lines Vinit1, the second reset voltage line Vinit2, and the third reset voltage line Vinit3 can also be different signal lines. In this case, the first reset voltage Vinit1, the second reset voltage Vinit2, and the third reset voltage Vinit3 can be the same or different.

[0094] For example, in some embodiments, the second reset control signal RG2 and the second compensation control sub-signal CG2 are the same. In this case, the second reset control signal line RG2 and the second compensation control signal line CG2 can be the same signal line, thereby saving the number of signal lines, reducing circuit complexity, and saving costs. However, this disclosure is not limited to this. The second reset control signal line RG2 and the second compensation control signal line CG2 can also be different signal lines, so that the second reset transistor T8 and the second compensation transistor T5 can be controlled separately, increasing control flexibility. In this case, the second reset control signal RG2 and the second compensation control sub-signal CG2 can be the same or different.

[0095] For example, in some embodiments, the first reset control signal RG1 and the first compensation control sub-signal CG1 can be the same. In this case, the first reset control signal line RG1 and the first compensation control signal line CG1 can be the same signal line, thereby saving the number of signal lines, reducing circuit complexity, and saving costs. At this time, when both the first compensation transistor T4 and the second compensation transistor T5 are turned on and write the compensation voltage based on the first reset voltage to the gate of the driving transistor T1, the first reset transistor T6 also turns on under the control of the first reset control signal RG1 and writes the second reset voltage Vinit2 to the data writing node N5 to reset the data writing node N5. However, this disclosure is not limited to this. The first reset control signal line RG1 and the first compensation control signal line CG1 can also be different signal lines, so that the first reset transistor T6 and the first compensation transistor T4 can be controlled separately, increasing control flexibility. In this case, the first reset control signal RG1 and the first compensation control sub-signal CG1 can be the same or different.

[0096] For example, in some embodiments, the first reset control signal RG1 and the second reset control signal RG2 can be the same. In this case, the first reset control signal line RG1 and the second reset control signal line RG2 can be the same signal line, thereby saving the number of signal lines. When the second reset transistor T8 is turned on under the control of the second reset control signal RG2 and writes the third reset voltage Vinit3 to the first terminal of the light-emitting element EL (i.e., the fourth node N4) to reset the first terminal of the light-emitting element EL, the first reset transistor T6 is also turned on under the control of the first reset control signal RG1 and writes the second reset voltage Vinit2 to the data writing node N5 to reset the data writing node N5. That is, the reset of the data writing node N5 and the reset of the fourth node N4 are achieved simultaneously. However, this disclosure is not limited to this; the first reset control signal line RG1 and the second reset control signal line RG2 can also be different signal lines. In this case, the first reset control signal RG1 and the second reset control signal RG2 can be the same or different.

[0097] For example, such as Figure 2A and Figure 2B As shown, the pixel circuit 200 may further include a first light-emitting control circuit 280, which is connected to the first end (i.e., the fourth node N4) of the light-emitting element EL and the second end (i.e., the third node N3) of the driving circuit 220, and is configured to control the connection between the first end of the light-emitting element EL and the second end of the driving circuit 220 to be disconnected or connected under the control of the first light-emitting control signal.

[0098] For example, in some embodiments, such as Figure 3A and Figure 3B As shown, the first light-emitting control circuit 280 includes a first light-emitting control transistor T9. The gate of the first light-emitting control transistor T9 is configured to receive a first light-emitting control signal EM1. For example, the gate of the first light-emitting control transistor T9 is connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal EM1. The first terminal of the first light-emitting control transistor T9 is connected to the second terminal of the driving circuit 220, and the second terminal of the first light-emitting control transistor T9 is connected to the first terminal of the light-emitting element EL.

[0099] For example, such as Figure 2A and Figure 2B As shown, the pixel circuit 200 may further include a second light-emitting control circuit 290, which is connected to the first power line Vdd and the first end (i.e., the second node N2) of the driving circuit 220, and is configured to control the connection between the first end of the driving circuit 220 and the first power line Vdd to be disconnected or connected under the control of the second light-emitting control signal.

[0100] For example, in some embodiments, such as Figure 3A and Figure 3B As shown, the second light-emitting control circuit 290 includes a second light-emitting control transistor T10. The gate of the second light-emitting control transistor T10 is configured to receive a second light-emitting control signal EM2. For example, the gate of the second light-emitting control transistor T10 is connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal EM2. The first terminal of the second light-emitting control transistor T10 is connected to the first power supply line Vdd, and the second terminal of the second light-emitting control transistor T10 is connected to the first terminal of the driving circuit 220, namely the second node N2.

[0101] For example, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are different signal lines. The first light-emitting control signal EM1 and the second light-emitting control signal EM2 are not the same.

[0102] For example, in some embodiments, the display panel includes multiple pixel circuits arranged in an array. In this case, the first light-emitting control signal line EM1 is a signal line connected to the pixel circuit in the row where the pixel circuit 200 is located, and the second light-emitting control signal line EM2 is a signal line connected to the pixel circuit in the row above the row where the pixel circuit 200 is located. By multiplexing the light-emitting control signal lines, the control of the first light-emitting control transistor T9 and the second light-emitting control transistor T10 in the pixel circuit 200 can be realized, saving the number of signal lines in the display panel. For example, if the row where the pixel circuit 200 is located is the second row, then the row above the row where the pixel circuit 200 is located is the first row. In this case, the first light-emitting control signal line EM1 is a signal line connected to the pixel circuit located in the first row, and the second light-emitting control signal line EM2 is a signal line connected to the pixel circuit located in the second row. In this case, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be generated by the same gate driving circuit.

[0103] For example, in embodiments of this disclosure, all transistors T1 to T10 can be of the same type, such as N-type transistors, thereby reducing the complexity of the transistor fabrication process. For example, all transistors T1 to T10 can be oxide transistors, which can effectively reduce transistor size and prevent leakage current, reducing layout space and facilitating high PPI (Pixels Per Inch) layouts.

[0104] For example, the pixel circuit provided in this disclosure can be applied to a display panel. In this case, the switching frequency of the content displayed on the display panel can be 50Hz, 60Hz, etc. In this case, the pixel circuit in the display panel is in a high-frequency display mode, that is, the switching frequency is high.

[0105] It should be noted that in the embodiments of the present disclosure, each node (the first node N1, the second node N2, the third node N3, the fourth node N4, and the data writing node N5) is set for better describing the circuit structure and does not represent an actually existing component. A node represents the convergence point of relevant circuit connections in the circuit structure, that is, the components / circuits connected with the same node identifier are electrically connected to each other.

[0106] For example, one of the voltages output by the first power supply line Vdd and the second power supply line Vss is a high voltage, and the other is a low voltage. For example, in the embodiments as Figure 3A and Figure 3B shown, the voltage output by the first power supply line Vdd is a constant first voltage, and the first voltage is a positive voltage; while the voltage output by the second power supply line Vss is a constant second voltage, and the second voltage is a negative voltage, etc. For example, in some examples, the second power supply line Vss can be grounded.

[0107] For example, in specific implementation, in the embodiments of the present disclosure, the third reset voltage Vinit3 and the second voltage Vss output by the second power supply line Vss can satisfy the following formula: Vinit3 - Vss < VEL, so as to avoid the light-emitting element EL from emitting light in the non-light-emitting stage (for example, the reset stage, the compensation stage, and the data writing stage to be described below). VEL represents the light-emitting threshold voltage of the light-emitting element EL.

[0108] It should be noted that the transistors adopted in the embodiments of the present disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The thin-film transistors can include polycrystalline silicon thin-film transistors, amorphous silicon thin-film transistors, oxide thin-film transistors (for example, indium gallium zinc oxide (IGZO) thin-film transistors), or organic thin-film transistors, etc. In the embodiments of the present disclosure, the thin-film transistors are taken as examples for illustration. The source and drain of the transistor can be symmetric in structure, so there is no difference between its source and drain in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole, and the other is the second pole. The first and second poles of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0109] For example, according to their characteristics, transistors can be divided into N-type transistors and P-type transistors. For clarity, the embodiments of this disclosure use an N-type transistor (e.g., an N-type MOS transistor) as an example to illustrate the technical solution of this disclosure in detail. In this case, the first terminal of the transistor is the drain, and the second terminal is the source. It should be noted that the transistors in the embodiments of this disclosure are not limited to N-type transistors. For example, depending on actual needs, one or more transistors in the pixel circuit provided in the embodiments of this disclosure can also be P-type transistors. In this case, the first terminal of the transistor is the source, and the second terminal is the drain. It is only necessary to connect the terminals of the selected type of transistor according to the terminals of the corresponding transistors in the embodiments of this disclosure. When using an N-type transistor, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin-film transistor. Compared with using low-temperature polycrystalline silicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin-film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented. Of course, low-temperature polycrystalline silicon or amorphous silicon can also be used as the active layer of the thin-film transistor.

[0110] It should be noted that in the embodiments of this disclosure, the reference numerals SG1, SG2, CG1, CG2, RG1, RG2, EM1, EM2, Vinit1, Vinit2, Vinit3, Vdata, Vdd, and Vss represent both signal lines or terminals and signals on signal lines.

[0111] It is worth noting that, depending on the actual application requirements, the pixel circuit 200 may also have other structures. In addition, the specific structure and implementation of each circuit in the pixel circuit 200 can be set according to the actual application requirements, and the embodiments disclosed herein do not impose specific limitations on this.

[0112] At least one embodiment of this disclosure also provides a driving method, for example, which can be used to drive the pixel circuit described in any of the above embodiments, such as... Figure 2A and Figure 2B The pixel circuit shown.

[0113] Figure 4 This is a schematic flowchart illustrating a method for driving a pixel circuit according to at least one embodiment of the present disclosure.

[0114] For example, such as Figure 4 As shown, in some embodiments, the driving method includes the following steps S110 to S130.

[0115] In step S110: During the compensation phase, the compensation voltage based on the first reset voltage is written to the control terminal of the drive circuit.

[0116] In step S120: During the data writing stage, the coupling voltage based on the data voltage is written to the control terminal of the drive circuit.

[0117] In step S130: During the light-emitting stage, the light-emitting element is driven to emit light based on the voltage at the control terminal of the driving circuit.

[0118] For example, the data writing phase and the compensation phase are different; in some examples, the data writing phase and the compensation phase do not overlap in time.

[0119] In the driving method provided in this embodiment, during the data writing stage, a coupling voltage based on the data voltage is written to the control terminal of the driving circuit to achieve data writing. During the compensation stage, a compensation voltage based on the first reset voltage is written to the control terminal of the driving circuit to achieve threshold compensation. By separating the data writing and threshold compensation, the threshold compensation time can be extended to achieve sufficient compensation, improve the compensation effect, and make the threshold compensation time independent of the refresh rate and resolution of the display panel, thereby improving the uniformity of the display brightness of the display panel and enhancing the display effect.

[0120] For example, in some embodiments, the driving method further includes step S100. For example, as... Figure 4 As shown, in step S100, during the reset phase, the first terminal of the light-emitting element is reset. For example, during the reset phase, a third reset voltage is written to the first terminal of the light-emitting element to reset the first terminal of the light-emitting element.

[0121] For example, in some embodiments, where the data writing circuit includes a first data writing sub-circuit and a second data writing sub-circuit, the first data writing sub-circuit being connected to the data writing node and the second data writing sub-circuit being connected to the control terminal of the data writing node and the driving circuit, the driving method may further include resetting the data writing node. For example, the process of resetting the data writing node needs to be performed before the data writing phase.

[0122] For example, in some embodiments, the first reset control signal RG1 and the first compensation control sub-signal CG1 may be the same. In this case, step S110 further includes: during the compensation phase, writing a second reset voltage to the data writing node to reset the data writing node. That is, the process of resetting the data writing node is implemented during the compensation phase. At this time, during the data writing phase, the second reset control signal RG2 may be at an inactive level or at an active level.

[0123] For example, in some other embodiments, the first reset control signal RG1 and the second reset control signal RG2 may be the same. In this case, step S100 further includes: during the reset phase, writing a second reset voltage to the data writing node to reset the data writing node. That is, the process of resetting the data writing node is implemented during the reset phase. At this time, during the data writing phase, both the first reset control signal RG1 and the second reset control signal RG2 are at an inactive level.

[0124] It should be noted that in the embodiments of this disclosure, when the signal is at an active level, it indicates that the signal can control the corresponding transistor to turn on, while when the signal is at an inactive level, it indicates that the signal can control the corresponding transistor to turn off. For example, when the transistor is an N-type transistor, the active level can be high, and the inactive level can be low.

[0125] Figure 5A A timing diagram of a pixel circuit provided for at least one embodiment of this disclosure. Figure 5A The circuit timing diagram shown corresponds to Figure 3A The pixel circuit shown.

[0126] The following is combined Figure 5A describe Figure 3A The working process of the pixel circuit is shown. Figure 5A As shown, the following description is based on the example of the first reset control signal RG1 and the first compensation control sub-signal CG1 being the same signal, the second reset control signal RG2 and the second compensation control sub-signal CG2 being the same signal, and the first scan sub-signal SG1 and the second scan sub-signal SG2 being the same signal.

[0127] For example, the operation of a pixel circuit in a display frame may include: reset phase P1, compensation phase P2, data writing phase P3, and light emission phase P4.

[0128] For example, such as Figure 5AAs shown, during the reset phase P1, the second reset control signal RG2, the second compensation control sub-signal CG2, and the second light emission control signal EM2 are at high levels, while the first reset control signal RG1, the first compensation control sub-signal CG1, the first light emission control signal EM1, the first scan sub-signal SG1, and the second scan sub-signal SG2 are at low levels. Consequently, the second compensation transistor T5 is turned on under the control of the high level of the second compensation control sub-signal CG2, and the second light emission control transistor T10 is turned on under the control of the high level of the second light emission control signal EM2. This allows the first voltage Vdd output from the first power line Vdd to be provided to the gate and second terminal of the driving transistor T1, i.e., the first node N1 and the second node N2, through the turned-on second light emission control transistor T10 and the second compensation transistor T5. This ensures that the voltages at the gate and the second terminal of the driving transistor T1 are both the first voltage Vdd, thus resetting the gate and the second terminal of the driving transistor T1. Simultaneously, the second reset transistor T8 is turned on under the control of the high level of the second reset control signal RG2. This allows the third reset voltage Vinit3 output from the third reset voltage line Vinit3 to be supplied to the first electrode (i.e., the fourth node N4) of the light-emitting element EL through the turned-on second reset transistor T8, thereby resetting the first electrode of the light-emitting element EL. At this time, the first data write transistor T2, the second data write transistor T3, the first compensation transistor T4, the first reset transistor T6, and the first light-emitting control transistor T9 are all turned off.

[0129] Therefore, during the reset phase P1, the voltage of the first node N1 and the voltage of the second node N2 are both the first voltage Vdd, and the voltage of the fourth node N4 is the third reset voltage Vinit3.

[0130] For example, such as Figure 5AAs shown, during the compensation phase P2, the first reset control signal RG1, the first compensation control sub-signal CG1, the second reset control signal RG2, and the second compensation control sub-signal CG2 are at high levels, while the first light emission control signal EM1, the second light emission control signal EM2, the first scan sub-signal SG1, and the second scan sub-signal SG2 are at low levels. Consequently, the first compensation transistor T4 is turned on under the control of the high level of the first compensation control sub-signal CG1, so as to provide the first reset voltage Vinit1 on the first reset voltage line Vinit1 to the second terminal of the driving transistor T1, i.e., the third node N3, so that the voltage of the second terminal of the driving transistor T1 is the first reset voltage Vinit1. At this time, during the reset phase P1, the first voltage Vdd is written to the gate of the driving transistor T1, thus turning on the driving transistor T1. Furthermore, the second compensation transistor T5 also turns on under the control of the high level of the second compensation control sub-signal CG2, allowing the driving transistor T1 to form a diode connection. Thus, the first reset voltage Vinit1 charges the gate of the driving transistor T1 via the turned-on driving transistor T1 and the second compensation transistor T5 until the gate voltage of the driving transistor T1 is Vinit1 + Vth. The gate voltage Vinit1 + Vth of the driving transistor T1 is stored through the second capacitor C2, where Vth represents the threshold voltage of the driving transistor T1. The first reset transistor T6 turns on under the control of the high level of the first reset control signal RG1, thus providing the second reset voltage Vinit2 on the second reset voltage line Vinit2 to the data writing node N5, thereby resetting the voltage of the data writing node N5 to the second reset voltage Vinit2. Simultaneously, the second reset transistor T8 is turned on under the control of the high level of the second reset control signal RG2. This allows the third reset voltage Vinit3 output from the third reset voltage line Vinit3 to be supplied to the first electrode (i.e., the fourth node N4) of the light-emitting element EL through the turned-on second reset transistor T8, thereby maintaining the voltage of the first electrode (i.e., the fourth node N4) of the light-emitting element EL at the third reset voltage Vinit3. At this time, the first data write transistor T2, the second data write transistor T3, the first light-emitting control transistor T9, and the second light-emitting control transistor T10 are all turned off.

[0131] Therefore, during the compensation phase P2, the voltages of the first node N1 and the second node N2 are both Vinit1 + Vth, the voltage of the third node N3 is the first reset voltage Vinit1, the voltage of the fourth node N4 is the third reset voltage Vinit3, and the voltage of the data writing node N5 is the second reset voltage Vinit2.

[0132] For example, the compensation voltage is the voltage written to the first node N1 during the compensation phase, i.e., Vinit1 + Vth. When the second compensation transistor T5 is turned on, the compensation voltage can be written to the gate of the driving transistor T1. This compensation voltage is obtained based on the first reset voltage Vinit1, and the threshold voltage of the driving transistor T1 is compensated based on this compensation voltage.

[0133] For example, in the compensation stage P2, the threshold compensation time can be controlled by controlling the duration of the first compensation control sub-signal CG1 and the second compensation control sub-signal CG2 being at a high level. Since the compensation stage P2 only involves threshold compensation and no data is written, the threshold compensation time can be adjusted according to actual needs. For example, the duration of the first compensation control sub-signal CG1 and the second compensation control sub-signal CG2 being at a high level can be appropriately extended, thereby extending the threshold compensation time. This makes the threshold compensation process more flexible, improves the threshold compensation effect, and mitigates the image quality impact caused by the process.

[0134] For example, such as Figure 5AAs shown, during the data writing phase P3, the first scan sub-signal SG1 and the second scan sub-signal SG2 are at high levels, while the first reset control signal RG1, the first compensation control sub-signal CG1, the second reset control signal RG2, the second compensation control sub-signal CG2, the first light emission control signal EM1, and the second light emission control signal EM2 are at low levels. Consequently, the first data writing transistor T2 is turned on under the control of the high level of the first scan sub-signal SG1, and the second data writing transistor T3 is turned on under the control of the high level of the second scan sub-signal SG2. Thus, the data voltage Vdata on the data line Vdata is provided to the data writing node N5 through the turned-on first data writing transistor T2, causing the voltage of the data writing node N5 to jump from the second reset voltage Vinit2 to the data voltage Vdata. That is, the voltage change of the data writing node N5 is Vdata - Vinit2. Then, due to the voltage division caused by the coupling of the first capacitor C1 and the second capacitor C2, the voltage change of the first node N1 is (C11 / (C11+C12))*(Vdata-Vinit2), where C11 is the capacitance value of the first capacitor C1 and C12 is the capacitance value of the second capacitor C2. Thus, the voltage of the first node N1 becomes Vinit1+Vth+(C11 / (C11+C12))*(Vdata-Vinit2). At this time, the second light-emitting control transistor T10 is turned off under the control of the low level of the second light-emitting control signal EM2, and the second compensation transistor T5 is turned off under the control of the low level of the second compensation control sub-signal CG2, so the second node N2 is floating. At this time, the voltage of the second node N2 is maintained at Vinit1 + Vth; the first compensation transistor T4 is turned off under the control of the low level of the first compensation control sub-signal CG1, and the first light-emitting control transistor T9 is turned off under the control of the low level of the first light-emitting control signal EM1, so the third node N3 is floating. At this time, the voltage of the third node N3 is maintained at the first reset voltage Vinit1; the second reset transistor T8 is turned off under the control of the low level of the second reset control signal RG2, so the fourth node N4 is floating. At this time, the voltage of the fourth node N4 is maintained at the third reset voltage Vinit3.

[0135] Therefore, during the data writing phase P3, the voltage of the first node N1 is Vinit1 + Vth + (C11 / (C11 + C12)) * (Vdata - Vinit2), the voltage of the second node N2 is Vinit1 + Vth, the voltage of the third node N3 is the first reset voltage Vinit1, the voltage of the fourth node N4 is the third reset voltage Vinit3, and the voltage of the data writing node N5 is the data voltage Vdata.

[0136] For example, the coupling voltage is the voltage change of the first node N1 during the data writing phase, i.e. (C11 / (C11+C12))*(Vdata-Vinit2). This coupling voltage is obtained based on the data voltage Vdata and the second reset voltage Vinit2. In addition, this coupling voltage is also related to the capacitance value C11 of the first capacitor C1 and the capacitance value C12 of the second capacitor C2.

[0137] For example, during the data writing phase P3, the gate voltage of the driving transistor T1 is Vinit1+Vth+(C11 / (C11+C12))*(Vdata-Vinit2), which means that the gate voltage of the driving transistor T1 at this time is the sum of the compensation voltage and the coupling voltage.

[0138] For example, in some embodiments, during the data writing phase P3, the second reset control signal RG2 and the second compensation control sub-signal CG2 can also be at a high level. At this time, the second reset transistor T8 is turned on under the control of the high level of the second reset control signal RG2, so that the third reset voltage Vinit3 output by the third reset voltage line Vinit3 can be provided to the fourth node N4 through the turned-on second reset transistor T8, and the voltage of the fourth node N4 remains at the third reset voltage Vinit3. The second compensation transistor T5 is turned on under the control of the high level of the second compensation control sub-signal CG2, so that the first node N1 and the second node N2 are turned on, and the voltage of the second node N2 is the same as the voltage of the first node N1, that is, the voltage of the second node N2 is also Vinit1+Vth+(C11 / (C11+C12))*(Vdata-Vinit2). It should be noted that when the second reset control signal RG2 and the second compensation control sub-signal CG2 are not the same signal, during the data writing stage P3, the second reset control signal RG2 can be at a high level, while the second compensation control sub-signal CG2 can be at a low level. Of course, it can also be at a high level, depending on the actual needs.

[0139] For example, such as Figure 5AAs shown, during the light-emitting stage P4, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at high levels, while the first reset control signal RG1, the first compensation control sub-signal CG1, the second reset control signal RG2, the second compensation control sub-signal CG2, the first scan sub-signal SG1, and the second scan sub-signal SG2 are at low levels. Thus, the first light-emitting control transistor T9 is turned on under the control of the high level of the first light-emitting control signal EM1. At this time, the voltage of the fourth node N4 jumps from the third reset voltage Vinit3 to Voled+Vss. Voled represents the voltage between the first electrode and the second electrode of the light-emitting element EL during the light-emitting stage. Therefore, the voltage change of the fourth node N4 is (Voled+Vss)-Vinit3. The second data writing transistor T3 is turned off under the control of the low level of the second scan sub-signal SG1. The first node N1 is only coupled by the second capacitor C2. Due to the coupling effect of the second capacitor C2, the voltage change of the first node N1 is the same as the voltage change of the fourth node N4, that is, the voltage change of the first node N1 is also (Voled+Vss)-Vinit3. Therefore, the voltage of the first node N1 changes from Vinit1+Vth+(C11 / (C11+C12))*(Vdata-Vinit2) to Vinit1+Vth+(C11 / (C11+C12))*(Vdata-Vinit2)+(Voled+Vss)-Vinit3. The second light-emitting control transistor T10 is turned on under the control of the high level of the second light-emitting control signal EM2. Therefore, the voltage of the third node N3 is the same as the voltage of the fourth node N4, that is, the voltage of the third node N3 is Voled+Vss. For example, the second terminal of driving transistor T1 is the source. At this time, the gate voltage of driving transistor T1 is the voltage of the first node N1, and the source voltage of driving transistor T1 is the voltage of the third node N3. Therefore, the gate-source voltage of driving transistor T1 (i.e., the voltage difference between the gate and source of driving transistor T1) is:

[0140] Vgs=Vinit1+Vth+(C11 / (C11+C12))*(Vdata-Vinit2)+(Voled+Vss)-Vinit3-(Voled+Vss)=Vinit1+Vth+(C11 / (C11+C12))*(Vdata-Vinit2)-Vinit3

[0141] For example, in some embodiments, the first reset voltage Vinit1 and the third reset voltage Vinit3 can be the same, thus Vgs = Vth + (C11 / (C11+C12))*(Vdata-Vinit2). At this time, the driving transistor T1 is in saturation, thereby causing the driving transistor T1 to generate a driving current I. OLED:

[0142] I OLED = (1 / 2)*K*(Vgs-Vth) 2 =(1 / 2)*K*((C11 / (C11+C12))*(Vdata-Vinit2)) 2 ,

[0143] K is a structural constant related to the process and design. As can be seen from the above equation, the drive current I... OLED The threshold voltage Vth of the driving transistor T1 and the first voltage Vdd of the first power line Vdd are no longer affected; only the second reset voltage Vinit2 and the data voltage Vdata are relevant. The data voltage Vdata is directly transmitted via the data line and is independent of the threshold voltage Vth of the driving transistor T1. This solves the problem of threshold voltage drift caused by the manufacturing process and prolonged operation of the driving transistor T1. The second reset voltage Vinit2 is provided by the second reset voltage line and is independent of the power supply voltage drop (IR drop) of the first power line Vdd, thus solving the IR drop problem of the display panel. In summary, the pixel circuit can guarantee the driving current I... OLED The accuracy of eliminating the threshold voltage and IR drop of the driving transistor T1 on the driving current I OLED This ensures the normal operation of the light-emitting element (EL), improves the uniformity of the displayed image, and enhances the display effect.

[0144] For example, K can be represented as:

[0145] K = μ n C ox (W / L)

[0146] Where, μ n To drive the electron mobility of transistor T1, C ox W is the gate capacitance of the driving transistor T1, W is the channel width of the driving transistor T1, and L is the channel length of the driving transistor T1.

[0147] For example, according to the formula for the driving current mentioned above, the driving current is also related to the capacitance value C11 of the first capacitor C1 and the capacitance value C12 of the second capacitor C2. The ratio of C11 / C12 will affect the data range. Figure 3B The pixel circuit shown can avoid the influence of C11 / C12 on the data range.

[0148] Figure 5B A circuit timing diagram of another pixel circuit provided for at least one embodiment of this disclosure. Figure 5B The circuit timing diagram shown corresponds to Figure 3BThe pixel circuit shown.

[0149] The following is combined Figure 5B describe Figure 3B The working process of the pixel circuit is shown. Figure 5B As shown, the following description is based on the example of the first reset control signal RG1 and the first compensation control sub-signal CG1 being the same signal, the second reset control signal RG2 and the second compensation control sub-signal CG2 being the same signal, and the first scan sub-signal SG1 and the second scan sub-signal SG2 being the same signal.

[0150] For example, the operation of a pixel circuit in a display frame may include: reset phase P1, compensation phase P2, data writing phase P3, and light emission phase P4.

[0151] It should be noted that, with Figure 5A Compared to the circuit timing diagram shown, Figure 5B The circuit timing diagram shown includes the isolation control signal IG. The timing of the other signals remains unchanged. Only the differences are described below, and the same parts will not be repeated.

[0152] For example, such as Figure 5B As shown, during the reset phase P1, the isolation control signal IG is at a high level, and the isolation transistor T7 is turned on, thereby connecting the second capacitor C2 to the first node N1. At this time, the first voltage Vdd written to the first node N1 can be stored through the second capacitor C2. Based on the above description, it can be seen that during the reset phase P1, the voltage of the first node N1 and the voltage of the second node N2 are both the first voltage Vdd, and the voltage of the fourth node N4 is the third reset voltage Vinit3.

[0153] For example, such as Figure 5B As shown, during the compensation phase P2, the isolation control signal IG is at a high level, and the isolation transistor T7 is turned on, thereby connecting the second capacitor C2 to the first node N1. At this time, the voltage Vinit1+Vth written to the first node N1 can be stored through the second capacitor C2. Based on the above description, it can be seen that during the compensation phase P2, the voltages of the first node N1 and the second node N2 are both Vinit1+Vth, the voltage of the third node N3 is the first reset voltage Vinit1, the voltage of the fourth node N4 is the third reset voltage Vinit3, and the voltage of the data-written node N5 is the second reset voltage Vinit2. For example, the compensation voltage is the voltage written to the first node N1 during the compensation phase, i.e., Vinit1+Vth.

[0154] For example, such as Figure 5BAs shown, during the data writing phase P3, the isolation control signal IG is at a low level, and the isolation transistor T7 is turned off, thus disconnecting the connection between the second capacitor C2 and the first node N1. At this time, the first node N1 is only coupled by the first capacitor C1, making the voltage change of the first node N1 the same as the voltage change of the data writing node N5. The voltage change of the data writing node N5 is Vdata - Vinit2, and therefore, the voltage change of the first node N1 is also Vdata - Vinit2. Thus, the voltage of the first node N1 becomes Vinit1 + Vth + (Vdata - Vinit2). Based on the above description, it can be seen that during the data writing phase P3, the voltage of the second node N2 is Vinit1 + Vth, the voltage of the third node N3 is the first reset voltage Vinit1, and the voltage of the fourth node N4 is the third reset voltage Vinit3. For example, the coupling voltage is the voltage change of the first node N1 during the data writing phase, i.e. (Vdata-Vinit2). This coupling voltage is obtained based on the data voltage Vdata and the second reset voltage Vinit2, and is independent of the capacitance values ​​of the first capacitor C1 and the second capacitor C2.

[0155] For example, such as Figure 5B As shown, during the light-emitting stage P4, the voltage of the fourth node N4 jumps from the third reset voltage Vinit3 to Voled+Vss. Voled represents the voltage between the first and second electrodes of the light-emitting element EL during the light-emitting stage. Therefore, the voltage change of the fourth node N4 is (Voled+Vss)-Vinit3. During the light-emitting stage P4, the isolation control signal IG is at a high level, and the isolation transistor T7 is turned on, thereby connecting the second capacitor C2 to the first node N1. At this time, based on the coupling effect of the second capacitor C2, the first node N1 changes with the fourth node N4. The voltage change of the first node N1 is the same as the voltage change of the fourth node N4, that is, the voltage change of the first node N1 is also (Voled+Vss)-Vinit3. Thus, the voltage of the first node N1 changes from Vinit1+Vth+(Vdata-Vinit2) to Vinit1+Vth+(Vdata-Vinit2)+(Voled+Vss)-Vinit3. At this time, the gate-source voltage of driving transistor T1 (i.e., the voltage difference between the gate and source of driving transistor T1) is:

[0156] Vgs=Vinit1+Vth+(Vdata-Vinit2)+(Voled+Vss)-Vinit3-(Voled+Vss)

[0157] =Vinit1+Vth+(Vdata-Vinit2)-Vinit3

[0158] For example, in some embodiments, the first reset voltage Vinit1 and the third reset voltage Vinit3 can be the same, thus Vgs = Vth + (Vdata - Vinit2). At this time, the driving transistor T1 is in saturation, thereby causing the driving transistor T1 to generate a driving current I. OLED :

[0159] I OLED = (1 / 2)*K*(Vgs-Vth) 2 = (1 / 2)*K*(Vdata-Vinit2) 2 .

[0160] As can be seen from the above formula, the driving current I OLED It is no longer affected by the capacitance value C11 of the first capacitor C1 and the capacitance value C12 of the second capacitor C2, thus avoiding the influence of the capacitance value C11 of the first capacitor C1 and the capacitance value C12 of the second capacitor C2 on the data range.

[0161] For example, such as Figure 5A and Figure 5B As shown, in terms of time, the compensation phase P2 is located before the data writing phase P3, so the reset of the data writing node N5 can be achieved in the reset phase P1 and / or the compensation phase P2. In terms of time, the compensation phase P2 and the data writing phase P3 do not overlap with each other, so that the threshold compensation process and the data writing process are separated, avoiding the limitation of the threshold compensation time by the data writing time. This allows for the extension of the threshold compensation time, improving the threshold compensation effect, achieving the purpose of full compensation, and improving the image quality impact caused by the process.

[0162] It should be noted that the embodiments provided in this disclosure... Figure 5A and Figure 5B The circuit timing diagram shown is merely illustrative; the specific timing of the pixel circuit can be set according to the actual application scenario, and this disclosure does not impose specific limitations on it. The gate control signals differ for different types of transistors. For example, for an N-type transistor, the transistor is in the ON state when the control signal is high, and in the OFF state when the control signal is low. For a P-type transistor, the transistor is in the ON state when the control signal is low, and in the OFF state when the control signal is high. The control signals in the embodiments of this disclosure can vary accordingly based on the type of transistor.

[0163] At least one embodiment of this disclosure also provides a display panel. Figure 6 A schematic block diagram of a display panel provided for at least one embodiment of the present disclosure.

[0164] like Figure 6 As shown, the display panel 600 includes a plurality of pixel units 610, which can be arranged in an array. Each pixel unit 610 may include a pixel circuit 611 and a light-emitting element 612. For example, the pixel circuit 611 may be the pixel circuit 200 described in any of the above embodiments, and the light-emitting element 612 may be the light-emitting element EL described in any of the above embodiments.

[0165] In this display panel, the threshold compensation period and the data writing period are separated by the data writing period in the pixel circuit, thereby improving the threshold compensation effect and achieving full compensation. The compensation time is independent of the refresh rate and resolution of the display panel, which improves the image quality caused by the process, improves the uniformity of the display brightness, and enhances the display effect.

[0166] For example, the multiple pixel units 610 may include multiple red pixel units, multiple blue pixel units, and multiple green pixel units.

[0167] For example, the display panel 800 can be a liquid crystal display panel or an organic light-emitting diode (OLED) display panel, etc.

[0168] For example, the display panel 600 can be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel. In addition, the display panel 600 can be not only a flat panel, but also a curved panel, or even a spherical panel.

[0169] For example, the display panel 600 can also have a touch function, that is, the display panel 600 can be a touch display panel.

[0170] For example, the display panel 600 can be applied to any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0171] For example, the display panel 600 can be a flexible display panel, thereby meeting various practical application needs. For instance, the display panel 600 can be applied to curved screens, etc.

[0172] It should be noted that the display panel 600 may also include other components, and the embodiments of this disclosure do not limit this. For clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the display panel 600. To achieve the basic functions of the display panel 600, those skilled in the art can provide and set other structures (not shown) according to specific needs, and the embodiments of this disclosure do not limit this.

[0173] At least one embodiment of this disclosure also provides a display device. Figure 7A schematic block diagram of a display device provided for at least one embodiment of the present disclosure.

[0174] like Figure 7 As shown, the display device 700 may include a display panel 710 for displaying images. The display panel 710 may be any of the display panels provided in any embodiment of this disclosure, for example, Figure 6 The display panel 600 shown is shown.

[0175] For example, such as Figure 7 As shown, the display device 700 may include a gate driver 720, which is disposed on the display panel 710 and in the peripheral area of ​​the display panel 710.

[0176] For example, such as Figure 7 As shown, the display device 700 also includes a data driver 730 and a timing controller 740. For example, the data driver 730 and the timing controller 740 may also be disposed in the peripheral area of ​​the display panel 710. However, this disclosure is not limited thereto. The data driver 730 and the timing controller 740 may also be disposed outside the display panel 710 and connected to the display panel 710 via a flexible circuit board.

[0177] For example, the display device 700 includes multiple gate lines GL, multiple data lines DL, and multiple pixel units P. The multiple pixel units P are defined by the intersection of the multiple gate lines GL and the multiple data lines DL. The multiple gate lines GL, the multiple data lines DL, and the multiple pixel units P are all disposed in the display area of ​​the display panel 710. The gate driver 720 can be electrically connected to the data writing circuit in the pixel circuit of the pixel unit through the multiple gate lines GL (i.e., the aforementioned first scan signal line and second scan signal line) to provide scan signals to the data writing circuit. The data driver 730 can be electrically connected to the data writing circuit in the pixel circuit of the pixel unit through the multiple data lines DL to provide data voltage to the data writing circuit.

[0178] For example, the timing controller 740 processes externally input digital image data DRGB to match the size and resolution of the display device 700, and then provides the processed image data RGB to the data driver 730. The timing controller 740 uses a synchronization signal SYNC (e.g., dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from outside the display device 700 to generate a gate control signal GCS and a data control signal DCS. The timing controller 740 also provides the gate control signal GCS to the gate driver 720 and the data control signal DCS to the data driver 730 to control the gate driver 720 and the data driver 730.

[0179] For example, the outputs of multiple shift register units in the gate driver 720 are connected to multiple gate lines GL. The multiple gate lines GL are connected to multiple rows of pixel units. The outputs of the multiple shift register units in the gate driver circuit 720 sequentially output multiple signals (e.g., the scan signals described above) to the multiple gate lines GL, so that the multiple rows of pixel units in the display device 700 can be scanned line by line.

[0180] For example, the data driver 730 uses a reference gamma voltage to convert the processed image data RGB input from the timing controller 740 into a data voltage based on multiple data control signals DCS originating from the timing controller 740. The data driver 730 provides the converted data voltage to multiple data lines DL.

[0181] For example, the gate driver 720 and the data driver 730 can be implemented by their respective application-specific integrated circuit chips (e.g., semiconductor chips), or they can be directly fabricated on the display panel 710 by semiconductor fabrication processes. For example, the gate driver 720 can be integrated into the display device 700 to form a GOA (gate driver on array) circuit.

[0182] For example, such as Figure 7 As shown, the gate control signal GCS provided by the timing controller 740 can be transmitted to the gate driver 720 as a trigger signal via the trigger signal line NGSTV.

[0183] The technical effects of the display device 700 are the same as those of the display panel described in the embodiments of this disclosure, and will not be repeated here.

[0184] For example, the display device 700 can be any product or component with display function, such as an LCD panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc., and the embodiments disclosed herein are not limited thereto.

[0185] It should be noted that other components of the display device 700 (such as voltage conversion circuits, image data encoding / decoding circuits, clock circuits, etc.) are all present in the art and should not be described in detail here, nor should they be construed as limiting the present disclosure.

[0186] The following points should be noted regarding this disclosure:

[0187] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0188] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0189] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0190] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A pixel circuit, comprising: Data writing circuit, driving circuit, and compensation circuit; The driving circuit includes a control terminal, a first terminal, and a second terminal. The compensation circuit is connected to the control terminal, the first terminal and the second terminal of the drive circuit, and is configured to write a compensation voltage based on the first reset voltage into the control terminal of the drive circuit under the control of the compensation control signal. The data writing circuit is connected to the control terminal of the driving circuit and is configured to write a coupling voltage based on the data voltage into the control terminal of the driving circuit under the control of the scanning signal. The driving circuit is configured to control the driving current that drives the light-emitting element to emit light under the control of the voltage applied to the control terminal of the driving circuit. The data writing circuit includes a first data writing sub-circuit and a second data writing sub-circuit, and the scanning signal includes a first scanning sub-signal and a second scanning sub-signal. The first data writing sub-circuit is connected to the data writing node and is configured to write the data voltage to the data writing node under the control of the first scan sub-signal; The second data writing sub-circuit is connected to the control terminal of the data writing node and the driving circuit, and is configured to write the coupling voltage based on the voltage of the data writing node to the control terminal of the driving circuit under the control of the second scan sub-signal.

2. The pixel circuit according to claim 1, wherein, The first data writing sub-circuit includes a first data writing transistor, and the second data writing sub-circuit includes a second data writing transistor and a first capacitor. The first terminal of the first data write transistor is configured to receive the data voltage, the second terminal of the first data write transistor is connected to the data write node, and the gate of the first data write transistor is configured to receive the first scan sub-signal. The first terminal of the first capacitor is connected to the data write node, and the second terminal of the first capacitor is connected to the first terminal of the second data write transistor. The second terminal of the second data write transistor is connected to the control terminal of the driving circuit, and the gate of the second data write transistor is configured to receive the second scan sub-signal.

3. The pixel circuit according to claim 1, further comprising: First reset circuit, The first reset circuit is connected to the data writing node and is configured to write a second reset voltage into the data writing node under the control of a first reset control signal to reset the data writing node.

4. The pixel circuit according to claim 3, wherein, The first reset circuit includes a first reset transistor. The first terminal of the first reset transistor is configured to receive the second reset voltage, the second terminal of the first reset transistor is connected to the data write node, and the gate of the first reset transistor is configured to receive the first reset control signal.

5. The pixel circuit according to any one of claims 1 to 4, wherein, The compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit, and the compensation control signal includes a first compensation control sub-signal and a second compensation control sub-signal. The first compensation sub-circuit is connected to the second terminal of the drive circuit and is configured to write the first reset voltage to the second terminal of the drive circuit under the control of the first compensation control sub-signal. The second compensation sub-circuit is connected to the first terminal of the drive circuit and the control terminal of the drive circuit, and is configured to write the compensation voltage into the control terminal of the drive circuit under the control of the second compensation control sub-signal.

6. The pixel circuit according to claim 5, wherein, The first compensation sub-circuit includes a first compensation transistor, and the second compensation sub-circuit includes a second compensation transistor. The first terminal of the first compensation transistor is configured to receive the first reset voltage, the second terminal of the first compensation transistor is connected to the second terminal of the driving circuit, and the gate of the first compensation transistor is configured to receive the first compensation control sub-signal. The first terminal of the second compensation transistor is connected to the first terminal of the driving circuit, the second terminal of the second compensation transistor is connected to the control terminal of the driving circuit, and the gate of the second compensation transistor is configured to receive the second compensation control sub-signal.

7. The pixel circuit according to any one of claims 1 to 4, further comprising: Storage circuit, The storage circuit is connected to the control terminal of the driving circuit and the first terminal of the light-emitting element, and is configured to store the voltage of the control terminal of the driving circuit.

8. The pixel circuit according to claim 7, wherein, The storage circuit includes a second capacitor, the first terminal of which is connected to the control terminal of the driving circuit, and the second terminal of which is connected to the first terminal of the light-emitting element.

9. The pixel circuit according to claim 7 further includes an isolation circuit. in, The isolation circuit is connected between the control terminal of the drive circuit and the storage circuit, and is configured to disconnect the connection between the control terminal of the drive circuit and the storage circuit when the data writing circuit writes the coupling voltage based on the data voltage to the control terminal of the drive circuit under the control of the isolation control signal.

10. The pixel circuit according to claim 9, wherein, The isolation circuit includes an isolation transistor. The first terminal of the isolation transistor is connected to the control terminal of the driving circuit, the second terminal of the isolation transistor is connected to the storage circuit, and the gate of the isolation transistor is configured to receive the isolation control signal.

11. The pixel circuit according to claim 9, wherein, The phase of the isolation control signal is opposite to the phase of the second scan sub-signal.

12. The pixel circuit according to any one of claims 1 to 4, further comprising: Second reset circuit, The second reset circuit is connected to the first end of the light-emitting element and is configured to write a third reset voltage to the first end of the light-emitting element under the control of a second reset control signal to reset the first end of the light-emitting element.

13. The pixel circuit according to claim 12, wherein, The second reset circuit includes a second reset transistor. The first terminal of the second reset transistor is connected to the first terminal of the light-emitting element, the second terminal of the second reset transistor is configured to receive the third reset voltage, and the gate of the second reset transistor is configured to receive the second reset control signal.

14. The pixel circuit according to claim 12, wherein, The first reset voltage and the third reset voltage are the same.

15. The pixel circuit according to any one of claims 1 to 4, further comprising a first light-emitting control circuit. in, The first light-emitting control circuit is connected to the first end of the light-emitting element and the second end of the driving circuit, and is configured to control the connection between the first end of the light-emitting element and the second end of the driving circuit to be disconnected or connected under the control of the first light-emitting control signal.

16. The pixel circuit according to claim 15, wherein, The first light-emitting control circuit includes a first light-emitting control transistor. The gate of the first light-emitting control transistor is configured to receive the first light-emitting control signal, the first terminal of the first light-emitting control transistor is connected to the second terminal of the driving circuit, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the light-emitting element.

17. The pixel circuit according to any one of claims 1 to 4, further comprising a second light-emitting control circuit. in, The second light-emitting control circuit is connected to the first power line and the first end of the driving circuit, and is configured to control the connection between the first end of the driving circuit and the first power line to be disconnected or connected under the control of the second light-emitting control signal.

18. The pixel circuit according to claim 17, wherein, The second light-emitting control circuit includes a second light-emitting control transistor, the gate of which is configured to receive the second light-emitting control signal, the first terminal of which is connected to the first power line, and the second terminal of which is connected to the first terminal of the driving circuit.

19. The pixel circuit according to any one of claims 1 to 4, wherein, The driving circuit includes a driving transistor. The control terminal of the driving circuit includes the control electrode of the driving transistor, the first terminal of the driving circuit includes the first electrode of the driving transistor, and the second terminal of the driving circuit includes the second electrode of the driving transistor.

20. A pixel circuit, comprising: Data writing circuit, driving circuit, compensation circuit, storage circuit, first reset circuit, second reset circuit, first light-emitting control circuit and second light-emitting control circuit; The driving circuit includes a driving transistor. The data writing circuit includes a first data writing sub-circuit and a second data writing sub-circuit. The first data writing sub-circuit includes a first data writing transistor, and the second data writing sub-circuit includes a second data writing transistor and a first capacitor. The first terminal of the first data write transistor is configured to receive a data voltage, the second terminal of the first data write transistor is connected to a data write node, the gate of the first data write transistor is configured to receive a first scan sub-signal, the first terminal of the first capacitor is connected to the data write node, the second terminal of the first capacitor is connected to the first terminal of the second data write transistor, the second terminal of the second data write transistor is connected to the gate of the driving transistor, and the gate of the second data write transistor is configured to receive a second scan sub-signal. The compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit. The first compensation sub-circuit includes a first compensation transistor, and the second compensation sub-circuit includes a second compensation transistor. The first terminal of the first compensation transistor is configured to receive a first reset voltage, the second terminal of the first compensation transistor is connected to the second terminal of the driving transistor, and the gate of the first compensation transistor is configured to receive a first compensation control sub-signal; the first terminal of the second compensation transistor is connected to the first terminal of the driving transistor, the second terminal of the second compensation transistor is connected to the gate of the driving transistor, and the gate of the second compensation transistor is configured to receive a second compensation control sub-signal. The first reset circuit includes a first reset transistor, the first terminal of which is configured to receive a second reset voltage, the second terminal of which is connected to the data write node, and the gate of which is configured to receive a first reset control signal. The storage circuit includes a second capacitor, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to the first terminal of the light-emitting element. The second reset circuit includes a second reset transistor, the first terminal of the second reset transistor is connected to the first terminal of the light-emitting element, the second terminal of the second reset transistor is configured to receive a third reset voltage, and the gate of the second reset transistor is configured to receive a second reset control signal. The first light-emitting control circuit includes a first light-emitting control transistor, the gate of the first light-emitting control transistor is configured to receive a first light-emitting control signal, the first terminal of the first light-emitting control transistor is connected to the second terminal of the driving transistor, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the light-emitting element. The second light-emitting control circuit includes a second light-emitting control transistor, the gate of which is configured to receive a second light-emitting control signal, the first terminal of which is connected to a first power supply line, and the second terminal of which is connected to the first terminal of the driving transistor.

21. The pixel circuit according to claim 20, further comprising an isolation circuit. in, The isolation circuit includes an isolation transistor, and the second capacitor is connected to the gate of the driving transistor through the isolation transistor. The first terminal of the isolation transistor is connected to the gate of the driving transistor, the second terminal of the isolation transistor is connected to the first terminal of the second capacitor, and the gate of the isolation transistor is configured to receive an isolation control signal.

22. A driving method applied to a pixel circuit according to any one of claims 1 to 21, comprising: During the compensation phase, a compensation voltage based on the first reset voltage is written to the control terminal of the drive circuit; During the data writing phase, the coupling voltage based on the data voltage is written to the control terminal of the drive circuit; During the light-emitting phase, the light-emitting element is driven to emit light based on the voltage at the control terminal of the driving circuit.

23. The driving method according to claim 22, wherein, In the case where the data writing circuit includes a first data writing sub-circuit and a second data writing sub-circuit, the first data writing sub-circuit is connected to the data writing node, and the second data writing sub-circuit is connected to the data writing node and the control terminal of the driving circuit. The driving method includes: During the compensation phase, a second reset voltage is written to the data writing node to reset the data writing node.

24. The driving method according to claim 22 or 23, further comprising: During the reset phase, the first end of the light-emitting element is reset.

25. A display panel comprising a pixel circuit according to any one of claims 1 to 21.

26. A display device comprising a display panel according to claim 25.

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