Image sensor with improved pixel gated diode leakage and method of manufacture

Abstract

The application provides an image sensor with improved pixel field effect transistor GIDL and a preparation method. The image sensor comprises a pixel field effect transistor and a peripheral logic field effect transistor. The pixel field effect transistor comprises a charge transport gate and a floating diffusion active region. A gate edge region near one end of the floating diffusion active region in the charge transport gate has a different structure from a gate edge region of the peripheral logic field effect transistor. The electric field intensity of the gate edge region near one end of the floating diffusion active region in the charge transport gate is lower than that of a gate center region of the charge transport gate. The GIDL phenomenon of the pixel field effect transistor is improved, and the image quality of the CIS is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of sensors, in particular to an image sensor with improved pixel field effect transistor GIDL and a preparation method. BACKGROUND

[0002] An image sensor is a functional device that converts a light image on a photosensitive surface into an electrical signal in a corresponding proportional relationship by using the photoelectric conversion function of a photoelectric device. Among them, the image sensor includes two types of CMOS (Complementary Metal Oxide Semiconductor) image sensor and CCD (Charged Coupled Device) image sensor, which can be widely applied to digital cameras, mobile phones, medical devices, automobiles and other application occasions.

[0003] In a CMOS image sensor (CIS), a photosensitive pixel array and a peripheral logic circuit system are provided, the photosensitive pixel array is used to collect photoelectric signal information of an image, and external light irradiated on the pixel array will cause photoelectric effect to generate corresponding charges in the pixel unit to collect image signals. Figure 1 The photosensitive pixel array generally includes a photodiode 101, a charge transfer gate 102, a reset transistor 103, a source follower transistor 104 and a floating diffusion active region FD, and the peripheral logic circuit system includes a peripheral logic field effect transistor to realize the control and readout of the photosensitive pixel array.

[0004] CIS has been everywhere in our daily life, and with the advent of the Internet of Things era, it has become a trend for CIS development to promote the reduction of pixel pitch to smaller sizes and realize greater integration through pixel-level interconnection. However, with the miniaturization trend of production process, the gate dielectric layer of the charge transfer gate in the CIS is getting thinner and thinner, the floating diffusion active region is getting shallower and shallower, and the doping amount is getting higher and higher, and as Figure 2 During exposure, in order to prevent electrons from flowing into the photodiode 101 under lightless conditions, the charge transfer gate 102 takes N type as an example, the gate bias is negative, so that the gate of the charge transfer gate 102 and the floating diffusion active region FD at the drain end thereof form a high potential difference, resulting in the formation of a depletion region on the surface of the overlapping area of the gate and the drain of the charge transfer gate 102, and the positive and negative carriers will flow to the drain and the substrate under the action of a strong electric field, thereby causing a leakage current between the drain and the gate, triggering the gate-induced drain leakage (GIDL) phenomenon, and the GIDL phenomenon will cause the problem of white pixel bad pixels of the CIS image, thereby reducing the image quality of the CIS.

[0005] Therefore, it is necessary to provide an image sensor and a manufacturing method for improving pixel field effect transistor GIDL. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide an image sensor and a manufacturing method for improving pixel field effect transistor GIDL, which are used to solve the problem of pixel field effect transistor GIDL of the image sensor in the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides an image sensor for improving pixel field effect transistor GIDL, which comprises a pixel field effect transistor and a peripheral logic field effect transistor, the pixel field effect transistor comprises a charge transport gate and a floating diffusion active region, the gate edge region of the charge transport gate near one end of the floating diffusion active region has a different structure from the corresponding gate edge region of the peripheral logic field effect transistor, and the electric field intensity of the gate edge region of the charge transport gate near one end of the floating diffusion active region is lower than that of the central region of the charge transport gate.

[0008] Optionally, the thickness of the gate dielectric layer of the charge transport gate near the edge region of one end of the floating diffusion active region is greater than that of the central region of the gate dielectric layer.

[0009] Optionally, the dielectric constant of the gate dielectric layer near the edge region of one end of the floating diffusion active region is less than that of the central region of the gate dielectric layer.

[0010] Optionally, the gate dielectric layer of the central region of the charge transport gate has the same material and thickness as the gate dielectric layer of the peripheral logic field effect transistor.

[0011] Optionally, the surface of the charge transport gate is covered with a positive charge film, which changes the work function of the gate edge region near one end of the floating diffusion active region to reduce the electric field intensity.

[0012] Optionally, the positive charge film comprises one or a combination of hafnium oxide layer, aluminum oxide layer, tantalum oxide layer and silicon oxynitride layer.

[0013] Optionally, the gate polysilicon layer of the charge transport gate near one end of the floating diffusion active region has a different doping type from the gate polysilicon layer of the charge transport gate near one end of the photosensitive region, so as to change the work function of the gate edge region near one end of the floating diffusion active region and reduce the electric field intensity.

[0014] Optionally, the width of the gate polysilicon layer of different doping type near one end of the floating diffusion active region is between 40nm and 50nm.

[0015] Optionally, the floating diffusion active region and the drain region of the peripheral logic field effect transistor each include a shallowly doped drain region and a drain body region in sequence, and the depth of the shallowly doped drain region of the floating diffusion active region is greater than the depth of the corresponding shallowly doped drain region of the peripheral logic field effect transistor drain region.

[0016] Optionally, the doping concentration of the shallowly doped drain region of the floating diffusion active region is less than the doping concentration of the corresponding shallowly doped drain region of the peripheral logic field effect transistor drain region.

[0017] In addition, the application also provides a preparation method of the image sensor for improving the pixel field effect transistor GIDL, including the following steps:

[0018] providing a substrate, and preparing the pixel field effect transistor and the peripheral logic field effect transistor in the substrate based on different mask plates, so that the gate edge region of the charge transport gate near one end of the floating diffusion active region has a different structure from the corresponding gate edge region of the peripheral logic field effect transistor, and the electric field intensity of the gate edge region of the charge transport gate near one end of the floating diffusion active region is lower than the electric field intensity of the central region of the charge transport gate.

[0019] Optionally, the step of forming the charge transport gate of the pixel field effect transistor includes:

[0020] forming a stacked gate dielectric material layer and a gate polysilicon material layer on the substrate;

[0021] forming a patterned photoresist, using the photoresist as a mask to etch the gate polysilicon material layer and the gate dielectric material layer, and removing the photoresist;

[0022] performing an oxidation treatment based on at least the exposed gate dielectric material layer to form the charge transport gate with a treated gate dielectric layer and a gate polysilicon layer, wherein the thickness of the edge region of the gate dielectric layer near one end of the floating diffusion active region is greater than the thickness of the central region of the gate dielectric layer, and / or the dielectric constant of the edge region of the gate dielectric layer near one end of the floating diffusion active region is less than the dielectric constant of the central region of the gate dielectric layer.

[0023] Optionally, the step of forming the charge transport gate of different doping type includes:

[0024] forming a layer of gate dielectric material and a layer of gate polysilicon material of a first doping type on the substrate in a stack;

[0025] performing ion implantation on edge regions of the layer of gate polysilicon material of the first doping type to form a layer of gate polysilicon material of a second doping type correspondingly;

[0026] forming a patterned photoresist, etching the layer of gate polysilicon material and the layer of gate dielectric material after ion implantation with the photoresist as a mask, and removing the photoresist to form the charge transport gate including a gate dielectric layer, a layer of gate polysilicon of the first doping type, and a layer of gate polysilicon of the second doping type, and the layer of gate polysilicon of the second doping type is located at an end of the charge transport gate close to the floating diffusion active region.

[0027] Optionally, after forming the charge transport gate with different doping types, the method further includes the following steps:

[0028] performing ion implantation on the substrate to form a shallow doped drain region of N-type doping, wherein the depth of the shallow doped drain region is greater than the depth of a corresponding shallow doped drain region of the peripheral logic field effect transistor, and / or the doping concentration of the shallow doped drain region is less than the doping concentration of the corresponding shallow doped drain region of the peripheral logic field effect transistor;

[0029] forming a gate sidewall;

[0030] forming the drain body region based on the gate sidewall to obtain the floating diffusion active region.

[0031] As described above, the image sensor with improved pixel field effect transistor GIDL and the manufacturing method thereof of the present application, the image sensor includes a pixel field effect transistor and a peripheral logic field effect transistor, the pixel field effect transistor includes a charge transport gate and a floating diffusion active region, and the edge region of the charge transport gate corresponding to an end close to the floating diffusion active region has a different structure from the edge region of the peripheral logic field effect transistor, including one or a combination of making the edge thickness of the gate dielectric layer at the end close to the floating diffusion active region greater than the center thickness of the gate dielectric layer, reducing the edge dielectric constant of the gate dielectric layer, covering a positive charge film on the surface of the charge transport gate, doping the edge of the gate polysilicon layer corresponding to the end close to the floating diffusion active region with a different conductive type, increasing the depth of the shallow doped drain region of the floating diffusion active region, and reducing the doping concentration of the shallow doped drain region of the floating diffusion active region, so that the electric field intensity of the edge region of the charge transport gate corresponding to the end close to the floating diffusion active region is lower than the electric field intensity of the center region of the charge transport gate, to improve the pixel field effect transistor GIDL phenomenon and improve the image quality of the CIS. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A circuit schematic diagram of an image sensor in the prior art is shown.

[0033] Figure 2 A circuit schematic diagram of an image sensor in the prior art is shown. Figure 1 A device cross-sectional structure schematic diagram of the area of dashed box A.

[0034] Figure 3 Figure 7 Figure 8 Three different structure schematic diagrams of an image sensor in the embodiment of the present application to improve the pixel field effect transistor GIDL are shown.

[0035] Figures 4-6 A device cross-sectional structure schematic diagram of the area of dashed box A. Figure 3 A schematic diagram of each step in the preparation of an image sensor in the corresponding embodiment is shown.

[0036] Figures 9-12 A device cross-sectional structure schematic diagram of the area of dashed box A. Figure 8 A schematic diagram of each step in the preparation of an image sensor in the corresponding embodiment is shown.

[0037] Figures 13-15 A device cross-sectional structure schematic diagram of the area of dashed box A. Figures 9-12 A schematic diagram of forming a shallow doped drain and a drain main region based on the embodiment shown. DETAILED DESCRIPTION

[0038] The embodiments of the present application will be described in detail by specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. The present application can also be implemented or applied by other different specific embodiments, and each detail in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0039] As in the detailed description of the embodiments of the present application, the cross-sectional diagrams of the device structure will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual fabrication.

[0040] ​​For ease of description, spatial relation terms such as "below," "below," "lower than," "below," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more layers in between. Wherein, when an element is referred to as being "fixed to" or "set on" another element, it may be directly on or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to or indirectly connected to the other element.

[0041] The text may use expressions such as "between..." to indicate that both endpoints are included, and may also use expressions such as "multiple" to indicate two or more, unless otherwise explicitly specified. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] like Figures 3-15 As shown, this embodiment provides an image sensor with improved pixel field-effect transistor (GIDL). The image sensor includes a pixel field-effect transistor and a peripheral logic field-effect transistor. The pixel field-effect transistor includes a charge transport gate 102 and a floating diffuse active region FD. The gate edge region of the charge transport gate 102 near one end of the floating diffuse active region FD has a different structure from the gate edge region corresponding to the peripheral logic field-effect transistor. Furthermore, the electric field strength of the gate edge region B near one end of the floating diffuse active region FD in the charge transport gate 102 is lower than the electric field strength of the gate center region C of the charge transport gate 102, thereby improving the GIDL phenomenon of the pixel field-effect transistor and enhancing the image quality of the image sensor.

[0044] Specifically, the edge region of the gate electrode 102 near the one end of the floating diffusion active region FD and the edge region of the gate electrode corresponding to the peripheral logic field effect transistor have different structures, which include one or a combination of the following: the edge thickness of the gate dielectric layer 112 near the one end of the floating diffusion active region FD is greater than the center thickness of the gate dielectric layer; the dielectric constant of the edge region of the gate dielectric layer 112 near the one end of the floating diffusion active region FD is reduced; a positive charge film 200 is coated on the surface of the gate structure of the charge transport gate 102; the edge of the gate polysilicon layer 122 near the one end of the floating diffusion active region FD is doped with a different conductivity type; the depth of the shallow doped drain region 401 in the floating diffusion active region FD is increased; and the doping concentration of the shallow doped drain region 401 in the floating diffusion active region FD is reduced.

[0045] As an example, the charge transport gate 102 can include an N-type charge transport gate or a P-type charge transport gate.

[0046] Specifically, in order to make the image sensor have high mobility, the charge transport gate 102 of the image sensor in the embodiment adopts an N-type charge transport gate, that is, the charge transport transistor in the pixel region is selected as an N-type transistor; during exposure, the gate bias of the charge transport gate 102 is negative, so as to completely prevent any electron from flowing into the photodiode 101 under lightless conditions, but not limited to this, and the charge transport gate 102 can also adopt a P-type charge transport gate according to needs. In addition, it should be noted that in the embodiment, the peripheral logic region can adopt the design of the peripheral logic region of the image sensor in the prior art, and adopt the existing circuit and the corresponding field effect transistor, for example, the peripheral logic region can include a circuit for forming a charge transport transistor (TX) gate control signal. In an optional example, the pixel region includes a charge transport transistor (including the charge transport gate), a reset transistor, a source follower transistor, and a pixel selection transistor, and optionally, the above-mentioned transistors all adopt NMOS tubes; in addition, the peripheral logic region includes NMOS tubes and PMOS tubes which can be used to form the corresponding required circuit, and both can be set according to actual needs.

[0047] The following will be described in combination with Figures 3-15 The structures and preparation methods of the image sensor for improving the pixel field effect transistor GIDL in the embodiment will be introduced.

[0048] In the manufacturing of the image sensor, the pixel field effect transistor and the peripheral logic field effect transistor can be manufactured based on different mask plates on a provided substrate, so that the charge transport gate has different structures near the gate edge region of one end of the floating diffusion active region FD and the gate edge region corresponding to the peripheral logic field effect transistor, and the electric field intensity of the charge transport gate near the gate edge region corresponding to the one end of the floating diffusion active region FD is lower than the electric field intensity of the central region of the charge transport gate.

[0049] As shown in Figures 3-6 , the thickness of the edge region B of the gate dielectric layer 112 near the one end of the floating diffusion active region FD in the charge transport gate 102 is greater than the thickness of the central region C of the gate dielectric layer 112.

[0050] Specifically, in this structure, when the image sensor is exposed during exposure, the gate edge of the charge transport gate 102 and its drain end, i.e. the floating diffusion active region FD, form a high potential difference, as shown in the B region in Figure 3 . By setting the edge thickness of the gate dielectric layer 112 near the one end of the floating diffusion active region FD in the charge transport gate 102 to be greater than the central thickness of the gate dielectric layer 112, the electric field intensity of the floating diffusion active region FD near the channel side of the charge transport gate 102 can be effectively reduced, thereby improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white pixel bad pixel of the CIS image, and further improving the image quality of the CIS.

[0051] As an example, the gate dielectric layer 112 of the charge transport gate 102 can include one or a combination of a silicon dioxide layer, a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer. Specifically, in the present embodiment, the gate dielectric layer 112 is selected to be a silicon dioxide layer, but is not limited thereto.

[0052] In an example, as shown in Figures 4-6 , the manufacturing of the charge transport gate in the pixel field effect transistor can include the following steps:

[0053] S1-1: providing a substrate structure 500, wherein the substrate structure 500 can have the photodiode;

[0054] S1-2: forming a stacked gate dielectric material layer 501 and a gate polysilicon material layer 502 on the gate dielectric material layer 501 on the substrate structure 500;

[0055] S1-3: forming a patterned photoresist 503 on the surface of the gate polysilicon material layer 502, as shown in Figure 4 .

[0056] S1-4: etching the gate poly-silicon material layer 502 and the gate dielectric material layer 501 with the photoresist 503 as a mask, and removing the photoresist 503, to obtain an initial gate dielectric layer 505 and a gate electrode layer 504, as shown in Figure 5

[0057] S1-5: at least the exposed gate dielectric material layer is subjected to an oxidation process, such as the exposed sidewall of the initial gate dielectric layer 505, to obtain the gate dielectric layer 112 with an edge thickness greater than a center thickness, to prepare the charge transport gate 102 with the gate dielectric layer 112 and the gate poly-silicon layer 122. In one embodiment, a high-temperature oxidation process, such as 900°C, can be used to form an oxide layer on the obtained initial gate structure and the surrounding active area surface, such as a 2nm-thick oxide layer, to obtain an intermediate thin-edge-thick gate dielectric layer based on the process, i.e., a gate dielectric layer with an edge region 507 and a center region 506. Figure 6

[0058] The preparation method of the charge transport gate 102 is not limited to this, and can be adapted as needed, and the gate dielectric layer 112 is not limited to a silicon dioxide layer, and other insulating dielectric layers can also be used, which are not limited here. The edge thickness of the gate dielectric layer 112 corresponding to the floating diffusion active area FD end of the charge transport gate can include 1nm-10nm, such as 1nm, 5nm, 10nm, etc., which can be selected as needed.

[0059] As an example, the gate dielectric layer 112 of the charge transport gate 102 is composed of material layers of different materials, and the edge dielectric constant of the gate dielectric layer 112 corresponding to the floating diffusion active area FD end is less than the center dielectric constant of the gate dielectric layer 112. For example, the center region is a High-k thin film, such as a SiN, HfO2, Al2O3 layer, etc.; the edge region is a Low-k thin film, such as a SiO2 layer, to alleviate GIDL. The structure of the gate dielectric layer of this example can be obtained based on the above process, and other process methods in the art can also be used.

[0060] As an example, the gate dielectric layer 112 corresponding to the center region of the charge transport gate 102 has the same material and thickness as the gate dielectric layer corresponding to the peripheral logic field effect transistor.

[0061] ​​Specifically, by increasing the thickness of the gate dielectric layer 112 corresponding to the one end of the floating diffusion active region FD or / and reducing the dielectric constant of the gate dielectric layer 112 of the charge transport gate 102 corresponding to the one end of the floating diffusion active region FD, the electric field intensity of the floating diffusion active region FD corresponding to the one end of the charge transport gate 102 can be effectively reduced, thereby improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white point bad pixel of the CIS image, and further improving the image quality of the CIS.

[0062] As shown in FIG. 1, the surface of the gate structure of the charge transport gate 102 can be covered with a positive charge film 200 to change the work function of the gate edge region corresponding to the one end of the floating diffusion active region FD through the positive charge film 200, thereby reducing the electric field intensity of the floating diffusion active region FD corresponding to the one end of the charge transport gate 102, improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white point bad pixel of the CIS image, and further improving the image quality of the CIS. Figure 7 As shown in FIG. 1, the surface of the gate structure of the charge transport gate 102 can be covered with a positive charge film 200 to change the work function of the gate edge region corresponding to the one end of the floating diffusion active region FD through the positive charge film 200, thereby reducing the electric field intensity of the floating diffusion active region FD corresponding to the one end of the charge transport gate 102, improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white point bad pixel of the CIS image, and further improving the image quality of the CIS.

[0063] As an example, the positive charge film 200 can include one or a combination of a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer.

[0064] Specifically, the positive charge film 200 can be a high dielectric constant material layer, which can be formed by using one or a combination of a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer. The method for forming the positive charge film 200 can be a deposition method such as CVD, so as to cover the charge transport gate 102 corresponding to the one end of the floating diffusion active region FD, to change the work function of the gate edge region corresponding to the one end of the floating diffusion active region FD through the positive charge film 200, reduce the electric field intensity of the gate edge region corresponding to the one end of the floating diffusion active region FD, improve the GIDL leakage problem of the pixel field effect transistor, improve the defect of the white point bad pixel of the CIS image, and further improve the image quality of the CIS.

[0065] As shown in FIG. 1, the surface of the gate structure of the charge transport gate 102 can be covered with a positive charge film 200 to change the work function of the gate edge region corresponding to the one end of the floating diffusion active region FD through the positive charge film 200, thereby reducing the electric field intensity of the floating diffusion active region FD corresponding to the one end of the charge transport gate 102, improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white point bad pixel of the CIS image, and further improving the image quality of the CIS. Figure 8 As shown in FIG. 1, the surface of the gate structure of the charge transport gate 102 can be covered with a positive charge film 200 to change the work function of the gate edge region corresponding to the one end of the floating diffusion active region FD through the positive charge film 200, thereby reducing the electric field intensity of the floating diffusion active region FD corresponding to the one end of the charge transport gate 102, improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white point bad pixel of the CIS image, and further improving the image quality of the CIS.

[0066] Specifically, in the embodiment, the gate polysilicon layer 122 of the charge transport gate 102 is an N-type doped polysilicon layer, and a P-type gate polysilicon layer 132 is formed at the edge of the gate polysilicon layer 122 close to one end of the floating diffusion active area FD, so that the work function of the edge region of the corresponding gate close to one end of the floating diffusion active area FD can be changed through the P-type gate polysilicon layer 132, thereby effectively reducing the electric field intensity of the floating diffusion active area FD region close to one side of the channel of the charge transport gate 102, improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white pixel bad pixel of the CIS image, and further improving the image quality of the CIS.

[0067] In an example, referring to Figures 9-12 , forming the charge transport gate with different doping types can include the following steps:

[0068] S2-1: providing a substrate structure 600, which can have the photodiode therein;

[0069] S2-2: forming a stacked gate dielectric material layer 601 and an N-type gate polysilicon material layer 602 on the substrate structure 600, as shown in Figure 9 ;

[0070] S2-3: ion implantation is performed on the edge region of the N-type gate polysilicon material layer 602 to form a P-type gate polysilicon material layer 603, as shown in Figure 10 ;

[0071] S2-4: forming a patterned photoresist 604, as shown in Figure 11 , etching the N-type gate polysilicon material layer 602 and the gate dielectric material layer 601 using the photoresist 604 as a mask to form the charge transport gate 605 including the gate dielectric layer 606, the N-type gate polysilicon layer, and the P-type gate polysilicon layer 605a, and the P-type gate polysilicon layer 605a is located at the edge of the N-type gate polysilicon layer close to one end of the floating diffusion active area FD, as shown in Figure 12 .

[0072] The preparation method of the charge transport gate 102 is not limited to this and can be adapted as needed, which is not limited here. The width of the P-type gate polysilicon layer 132 corresponding to one end of the floating diffusion active area FD can be 40-50 nm, such as 40 nm, 45 nm, 50 nm, etc., which can be selected as needed.

[0073] Further, the charge transport gate 102 can further include a gate sidewall 300, the floating diffusion active region FD can include a shallow doped drain region 401 and a drain bulk region 402, the shallow doped drain region 401 is located above the drain bulk region 402, and the doping concentration of the shallow doped drain region 401 is less than that of the drain bulk region 402, so that a doped region with different doping amount can be prepared in the floating diffusion active region FD through the gate sidewall 300. The present application can reduce the electric field intensity of the floating diffusion active region FD region near the side of the channel of the charge transport gate 102, thereby improving the GIDL leakage problem of the pixel field effect transistor 102, improving the defect of the white pixel bad pixel of the CIS image, and further improving the image quality of the CIS.

[0074] In an example, referring to Figures 13-14 The step of forming the shallow doped drain region and the drain bulk region can include:

[0075] The above steps S2-1 to S2-4 are executed, but are not limited thereto, and steps S1-1 to S1-5 can also be executed. In the present embodiment, steps S2-1 to S2-4 are executed as an example, which can be seen from Figures 9-12 The following steps are then executed:

[0076] S2-5: ion implantation is performed to form an N-type lightly doped shallow doped drain region 607, as shown in Figure 13 ;

[0077] S2-6: the gate sidewall 608 is formed, as shown in Figure 14 The material of the gate sidewall 608 is not limited here;

[0078] S2-7: the drain bulk region 609 is formed based on the gate sidewall 608, as shown in Figure 15 .

[0079] As an example, the floating diffusion active region FD and the drain region of the peripheral logic field effect transistor each include a shallow doped drain region and a drain bulk region in turn, the depth of the shallow doped drain region 401 corresponding to the floating diffusion active region FD is greater than the depth of the shallow doped drain region corresponding to the peripheral logic field effect transistor; and / or the doping concentration of the shallow doped drain region 401 corresponding to the floating diffusion active region FD is less than the doping concentration of the shallow doped drain region corresponding to the peripheral logic field effect transistor.

[0080] Specifically, in forming the floating diffusion active region FD, a high-energy and low-dose doping method can be used to form the shallow-doped drain region 401 with a large depth in the pixel field effect transistor, so as to effectively reduce the electric field intensity of the floating diffusion active region FD near the channel side of the charge transport gate 102, thereby improving the GIDL leakage problem of the pixel field effect transistor, improving the defect of the white pixel bad pixel of the CIS image, and further improving the image quality of the CIS. In addition, the low doping dose can further reduce the electric field intensity of the corresponding position and improve the GIDL.

[0081] In summary, the image sensor for improving the GIDL of the pixel field effect transistor and the preparation method thereof, the image sensor includes a pixel field effect transistor and a peripheral logic field effect transistor, the pixel field effect transistor includes a charge transport gate and a floating diffusion active region, and the corresponding gate edge region of the charge transport gate near one end of the floating diffusion active region has a different structure from the corresponding gate edge region of the peripheral logic field effect transistor, including one or a combination of making the edge thickness of the gate dielectric layer near one end of the floating diffusion active region greater than the center thickness of the gate dielectric layer, reducing the edge dielectric constant of the gate dielectric layer, covering a positive charge film on the surface of the charge transport gate, doping the gate polysilicon layer edge corresponding to one end of the floating diffusion active region with a different conductivity type, increasing the depth of the shallow-doped drain region of the floating diffusion active region, and reducing the doping concentration of the shallow-doped drain region of the floating diffusion active region, so that the electric field intensity of the gate edge region of the charge transport gate near one end of the floating diffusion active region is lower than the electric field intensity of the gate center region of the charge transport gate, to improve the GIDL phenomenon of the pixel field effect transistor and improve the image quality of the CIS.

[0082] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. An image sensor that improves pixel gate-induced drain leakage (GIDL), characterized by, The image sensor includes a pixel field effect transistor and a peripheral logic field effect transistor, the pixel field effect transistor includes a charge transfer gate and a floating diffusion active region, a gate edge region near one end of the floating diffusion active region of the charge transfer gate has a different structure from a corresponding gate edge region of the peripheral logic field effect transistor, the different structure includes one or a combination of making the thickness of a gate dielectric layer near one end of the floating diffusion active region larger than the thickness of a central region of the gate dielectric layer, reducing the dielectric constant of the edge region of the gate dielectric layer near one end of the floating diffusion active region, covering a positive charge film on the surface of the gate structure of the charge transfer gate, doping a gate polysilicon layer near one end of the floating diffusion active region with a different conductivity type, increasing the depth of a shallowly doped drain region in the floating diffusion active region, and reducing the doping concentration of the shallowly doped drain region in the floating diffusion active region, and the electric field intensity of the gate edge region near one end of the floating diffusion active region of the charge transfer gate is lower than the electric field intensity of the central region of the charge transfer gate.

2. The image sensor of claim 1, wherein: The thickness of the gate dielectric layer near one end of the floating diffusion active region of the charge transfer gate is larger than the thickness of the central region of the gate dielectric layer.

3. The image sensor of claim 2, wherein: The dielectric constant of the edge region of the gate dielectric layer near one end of the floating diffusion active region is smaller than the dielectric constant of the central region of the gate dielectric layer.

4. The image sensor of claim 2, wherein: The gate dielectric layer of the central region of the charge transfer gate has the same material and thickness as the gate dielectric layer of the peripheral logic field effect transistor.

5. The image sensor of claim 1, wherein: The surface of the charge transfer gate is covered with a positive charge film, which changes the work function of the gate edge region near one end of the floating diffusion active region to reduce the electric field intensity.

6. The image sensor of claim 5, wherein: The positive charge film includes one or a combination of a hafnium oxide layer, an aluminum oxide layer, a tantalum oxide layer, and a silicon oxynitride layer.

7. The image sensor of claim 1, wherein: The gate polysilicon layer near one end of the floating diffusion active region of the charge transfer gate has a different doping type from the gate polysilicon layer near one end of the photosensitive region of the charge transfer gate, which changes the work function of the gate edge region near one end of the floating diffusion active region to reduce the electric field intensity.

8. The image sensor of claim 7, wherein: The width of the gate polysilicon layer with a different doping type near one end of the floating diffusion active region is between 40 nm and 50 nm.

9. The image sensor of any of claims 1-8, wherein: The floating diffusion active region and the drain region of the peripheral logic field effect transistor each include a shallowly doped drain region and a drain main region in sequence, and the depth of the shallowly doped drain region of the floating diffusion active region is greater than the depth of the corresponding shallowly doped drain region of the drain region of the peripheral logic field effect transistor.

10. The image sensor of claim 9, wherein: The doping concentration of the shallowly doped drain region of the floating diffusion active region is smaller than the doping concentration of the corresponding shallowly doped drain region of the drain region of the peripheral logic field effect transistor.

11. A method of manufacturing an image sensor that improves pixel GIDL as claimed in any one of claims 1 to 10, characterized by The method includes the following steps: A substrate is provided, in which the pixel field effect transistor and the peripheral logic field effect transistor are prepared based on different mask plates, so that the charge transport gate has different structures at a gate edge region near one end of the floating diffusion active region and a gate edge region corresponding to the peripheral logic field effect transistor, and the electric field strength of the charge transport gate at the gate edge region near one end of the floating diffusion active region is lower than the electric field strength of the center region of the charge transport gate.

12. The method of fabricating an image sensor according to claim 11, wherein The step of forming the charge transport gate of the pixel field effect transistor includes: forming a stacked gate dielectric material layer and a gate polysilicon material layer on the substrate; forming a patterned photoresist, using the photoresist as a mask to etch the gate polysilicon material layer and the gate dielectric material layer, and removing the photoresist; performing an oxidation treatment based on at least the exposed gate dielectric material layer to form the charge transport gate with a treated gate dielectric layer and a gate polysilicon layer, wherein the thickness of the edge region of the gate dielectric layer near one end of the floating diffusion active region is greater than the thickness of the center region of the gate dielectric layer, and / or the dielectric constant of the edge region of the gate dielectric layer near one end of the floating diffusion active region is less than the dielectric constant of the center region of the gate dielectric layer.

13. The method of claim 11, wherein: The step of forming the charge transport gate with different doping types includes: forming a stacked gate dielectric material layer and a first-doping-type gate polysilicon material layer on the substrate; performing ion implantation on the edge region of the first-doping-type gate polysilicon material layer to correspondingly form a second-doping-type gate polysilicon material layer; forming a patterned photoresist, using the photoresist as a mask to etch the ion-implanted gate polysilicon material layer and the gate dielectric material layer, and removing the photoresist to form the charge transport gate including a gate dielectric layer, a first-doping-type gate polysilicon layer, and a second-doping-type gate polysilicon layer, and the second-doping-type gate polysilicon layer is located at one end of the charge transport gate near the floating diffusion active region.

14. The method of fabricating an image sensor according to claim 13, wherein After forming the charge transport gate with different doping types, the method further includes the steps of: performing ion implantation on the substrate to form an N-type doped shallow doped drain region, wherein the depth of the shallow doped drain region is greater than the depth of a corresponding shallow doped drain region of the drain region of the peripheral logic field effect transistor, and / or the doping concentration of the shallow doped drain region is less than the doping concentration of a corresponding shallow doped drain region of the drain region of the peripheral logic field effect transistor; forming a gate sidewall; forming a drain body region based on the gate sidewall to obtain the floating diffusion active region.

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