Array substrate, display panel and display device

Abstract

An array substrate (100), a display panel and a display device; the array substrate (100) comprises a first substrate (1), a switching layer group (2), an insulating layer group (3) and a reflective layer (5) which are sequentially stacked; the switching layer group (2) comprises a plurality of switching units (23) and a plurality of first light shielding layers (21), the plurality of first light shielding layers (21) are arranged at intervals, and the first light shielding layer (21) is arranged in the same layer and the same material with one of the switching units (23); the insulating layer group (3) is provided with a plurality of first protrusions (34) on the side away from the first substrate (1); the reflective layer (5) is provided with a plurality of second protrusions (51) on the side away from the first substrate (1), the orthographic projection of the first protrusion (34) on the first substrate (1) is located within the orthographic projection of the second protrusion (51) on the first substrate (1), and the orthographic projection of the first light shielding layer (21) on the first substrate (1) is located within the orthographic projection of the reflective layer (5) on the first substrate (1).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate, a display panel, and a display device. Background Technology

[0002] Reflection type liquid crystal display (RLCD) is widely used in products such as e-books and outdoor advertising due to its advantages such as being thin, light, energy-saving, and eye-friendly.

[0003] However, current reflective liquid crystal displays have narrow viewing angles and uneven display.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate, a display panel, and a display device.

[0006] According to one aspect of this disclosure, an array substrate is provided, comprising:

[0007] First substrate;

[0008] A switching layer assembly is disposed on one side of the first substrate. The switching layer assembly includes multiple switching units and multiple first light-shielding layers. The multiple first light-shielding layers are spaced apart, and the first light-shielding layers are disposed in the same layer and made of the same material as one of the switching units.

[0009] An insulating layer group is disposed on the side of the switching layer group away from the first substrate. The side of the insulating layer group away from the first substrate has a plurality of first protrusions. A first connecting portion is connected between adjacent first protrusions. The height of the first protrusions in a third direction is higher than the height of the first connecting portion in the third direction. The orthographic projection of the first protrusions and the first connecting portion on the first substrate is located within the orthographic projection of the first light-shielding layer on the first substrate. The third direction is perpendicular to the side of the first substrate close to the switching layer group.

[0010] A reflective layer is disposed on the side of the insulating layer group facing away from the first substrate. The side of the reflective layer facing away from the first substrate has a plurality of second protrusions. The orthographic projection of the first protrusion on the first substrate is located within the orthographic projection of the second protrusion on the first substrate. The reflective layer includes a plurality of reflective portions. The orthographic projection of the first light-shielding layer on the first substrate is located within the orthographic projection of the reflective portion on the first substrate.

[0011] In one exemplary embodiment of this disclosure, the area of ​​the orthographic projection of the first light-shielding layer on the first substrate accounts for 80% to 100% of the area of ​​the orthographic projection of the reflective portion on the first substrate.

[0012] In one exemplary embodiment of this disclosure, the orthographic projection of the first light-shielding layer on the first substrate continuously covers the orthographic projection of at least two first protrusions and the first connecting portion therebetween on the first substrate.

[0013] In one exemplary embodiment of this disclosure, the area of ​​the orthographic projection of the first protrusion onto the first substrate accounts for more than 80% of the area of ​​the orthographic projection of the first light-shielding layer onto the first substrate.

[0014] In one exemplary embodiment of this disclosure, the switch layer group includes:

[0015] The source and drain layers are provided with the same material as the first light-shielding layer.

[0016] In one exemplary embodiment of this disclosure, the switch layer group further includes:

[0017] A gate layer is disposed on one side of the first substrate.

[0018] A gate insulating layer is disposed on the side of the gate layer away from the first substrate.

[0019] An active layer is disposed on the side of the gate insulating layer away from the first substrate.

[0020] The source and drain layers are disposed on the side of the active layer away from the first substrate.

[0021] In one exemplary embodiment of this disclosure, the gate layer includes:

[0022] Multiple gate lines extend along a first direction, which is parallel to the side of the first substrate near the switch layer group.

[0023] Multiple sub-second electrodes are arranged in an array, and the sub-second electrodes are configured in a frame shape;

[0024] Multiple connecting portions are provided, which connect between two adjacent sub-second electrodes arranged along the first direction.

[0025] In one exemplary embodiment of this disclosure, the orthographic projections of the plurality of second protrusions on the first substrate overlap with the orthographic projections of the gate lines on the first substrate.

[0026] In one exemplary embodiment of this disclosure, the active layer includes:

[0027] The channel portion is located on the side of the gate line away from the first substrate.

[0028] The first filling portion is spaced apart from the channel portion and is located on the side of the connecting portion away from the first substrate, and covers at least a portion of the sidewall of the connecting portion;

[0029] The second filling portion is spaced apart from the channel portion and is located on the side of the gate line away from the first substrate, and covers at least a portion of the sidewall of the gate line.

[0030] In one exemplary embodiment of this disclosure, the source-drain layer includes:

[0031] A data line extends along a second direction, which intersects with the first direction, and a first portion of the data line is located on the side of the first filling portion away from the connecting portion, and a second portion of the data line is located on the side of a portion of the second filling portion away from the gate line;

[0032] A first light-shielding layer is disposed on one side of the data line in a first direction, and the orthographic projection of the first light-shielding layer on the first substrate is located within the orthographic projection of the sub-second electrode on the first substrate.

[0033] The source, one end of which is connected to the data line;

[0034] The drain electrode has one end connected to the first light-shielding layer;

[0035] The second electrode connection portion is connected between two adjacent sub-second electrodes in the second direction, and a portion of the second electrode connection portion is located on the side of the other portion of the second filling portion away from the grid line.

[0036] In one exemplary embodiment of this disclosure, the source-drain layer further includes:

[0037] A maintenance block is connected to the side of the first light-shielding layer near the gate line, and the orthographic projection of the maintenance block on the first substrate overlaps with the orthographic projection of the gate line on the first substrate.

[0038] In one exemplary embodiment of this disclosure, a first via is provided on the insulating layer group, and the array substrate further includes:

[0039] A first electrode layer is disposed between the insulating layer group and the reflective layer. The first electrode layer includes a plurality of first electrodes, and the first electrodes are connected to the first light-shielding layer through the first via.

[0040] In one exemplary embodiment of this disclosure, the orthographic projection of the first electrode on the first substrate overlaps with the orthographic projection of the gate line on the first substrate; the orthographic projection of the reflective portion on the first substrate overlaps with the orthographic projection of the gate line on the first substrate.

[0041] In one exemplary embodiment of this disclosure, the orthographic projection of the first electrode on the first substrate is located within the orthographic projection of the reflective portion on the first substrate.

[0042] In one exemplary embodiment of this disclosure, the shape of the orthographic projection of the first electrode on the first substrate is the same as the shape of the orthographic projection of the reflective portion on the first substrate.

[0043] In one exemplary embodiment of this disclosure, the insulating layer group includes:

[0044] A first protective layer is disposed on the side of the source / drain layer away from the first substrate, and a first sub-via is provided on the first protective layer;

[0045] An insulating layer is disposed on the side of the first protective layer away from the first substrate, and a second sub-via is provided on the insulating layer;

[0046] A second protective layer is disposed on the side of the insulating layer away from the first substrate, and a portion of the second protective layer covers the hole wall of the second sub-via. A third sub-via is disposed on the second protective layer, and the first sub-via, the second sub-via, and the third sub-via communicate to form the first via.

[0047] Wherein, the orthographic projection of the first sub-via on the first substrate is located within the orthographic projection of the second sub-via on the first substrate, and the orthographic projection of the third sub-via on the first substrate is located within the orthographic projection of the second sub-via on the first substrate.

[0048] In one exemplary embodiment of this disclosure, the array substrate has a bonding area disposed on one side of the display area, and the array substrate further includes:

[0049] Multiple first bonding pins are disposed in the bonding region, and the first bonding pins are disposed in the same layer and material as the gate layer or the source-drain layer;

[0050] Multiple second bonding pins are disposed in the bonding area and are located on the side of the first bonding pin away from the first substrate. The second bonding pins are disposed in the same layer and material as the first electrode. The orthographic projection of the second bonding pin on the first substrate is located within the orthographic projection of the first bonding pin on the first substrate. A gap is provided between the edge of the orthographic projection of the second bonding pin on the first substrate away from the display area and the edge of the orthographic projection of the first bonding pin on the first substrate away from the display area.

[0051] In one exemplary embodiment of this disclosure, a groove penetrating the first protective layer and the second protective layer is provided in the bonding area, and the groove is located on the side of the first bonding pin away from the display area.

[0052] In one exemplary embodiment of this disclosure, the side of the insulating layer group facing away from the first substrate includes a first plane, and the orthographic projection of the first plane on the first substrate overlaps with the orthographic projection of the channel portion on the first substrate.

[0053] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0054] A spacer is disposed on the side of the first plane away from the first substrate.

[0055] In one exemplary embodiment of this disclosure, the side of the insulating layer group facing away from the first substrate includes a second plane, and the orthographic projection of the second plane on the first substrate is located within the orthographic projection of the space between two adjacent first electrodes on the first substrate.

[0056] In one exemplary embodiment of this disclosure, the switch layer group further includes:

[0057] The gate layer and a plurality of second light-shielding layers are arranged at intervals. The second light-shielding layers are disposed in the same layer and made of the same material as the gate layer. The orthogonal projection of the second light-shielding layer on the first substrate is located within the orthogonal projection of the reflective portion on the first substrate.

[0058] In one exemplary embodiment of this disclosure, the switch layer group includes:

[0059] A gate layer is disposed on one side of the first substrate, and the first light-shielding layer is disposed in the same layer and made of the same material as the gate layer.

[0060] In one exemplary embodiment of this disclosure, the gate layer includes:

[0061] Multiple gate lines extend along a first direction, which is parallel to the side of the first substrate near the switch layer group.

[0062] Multiple sub-second electrodes are arranged in an array, and the sub-second electrodes are configured in a frame shape, with the first light-shielding layer disposed within the frame shape.

[0063] In one exemplary embodiment of this disclosure, the first light-shielding layer and the second electrode are integrally connected; or a second gap is provided between the first light-shielding layer and the second electrode.

[0064] In one exemplary embodiment of this disclosure, the height of the sidewall of the second protrusion in a third direction decreases as the distance from the middle of the second protrusion to the first surface increases, the first surface being parallel to the side of the first substrate near the switch layer group, and the third direction being perpendicular to the first surface.

[0065] In one exemplary embodiment of this disclosure, the angle between the sidewall of the second protrusion and the first surface is greater than or equal to 6° and less than or equal to 13°.

[0066] In one exemplary embodiment of this disclosure, the sidewall of the second protrusion includes a first portion, a second portion, and a third portion that are smoothly connected in sequence. The first portion is closer to the first substrate than the third portion. The first portion and the third portion are configured as arc surfaces, and the second portion is configured as a slope surface.

[0067] In one exemplary embodiment of this disclosure, the first portions of the plurality of second protrusions are smoothly connected.

[0068] According to another aspect of this disclosure, a display panel is provided, comprising:

[0069] The array substrate is any one of the array substrates described above;

[0070] A color filter substrate is disposed on the side of the array substrate near the reflective layer;

[0071] A frame is disposed between the array substrate and the color filter substrate;

[0072] A liquid crystal layer is disposed between the array substrate and the color filter substrate, and is located within the frame.

[0073] In one exemplary embodiment of this disclosure, the orthographic projection of the adhesive frame on the first substrate does not overlap with the orthographic projection of the insulating layer in the insulating layer group on the first substrate.

[0074] According to another aspect of this disclosure, a display device is provided, comprising: a display panel as described in any one of the preceding claims.

[0075] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0076] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0077] Figure 1 This is a schematic diagram of the structure of a display panel with a scattering film.

[0078] Figure 2 A schematic diagram of the process structure for forming the first protrusion.

[0079] Figure 3 This is a schematic diagram of the structure of a first example embodiment of the array substrate disclosed herein.

[0080] Figure 4 This is a schematic diagram of the structure of an example embodiment of the display panel of this disclosure.

[0081] Figure 5 for Figure 3 A schematic diagram of the middle gate layer.

[0082] Figure 6 In order to be in Figure 5 This is a schematic diagram of the structure after the active layer is formed based on the above.

[0083] Figure 7 In order to be in Figure 6 This is a schematic diagram of the structure after the source and drain layers are formed on the basis of the above.

[0084] Figure 8 In accordance with Figure 7 A cross-sectional view of the section after cutting through AA or BB.

[0085] Figure 9 In order to be in Figure 7 This is a schematic diagram of the structure after the first electrode is formed.

[0086] Figure 10 This is a schematic diagram of the structure after a reflective layer is formed on the first electrode.

[0087] Figure 11 Figure 3A partially enlarged schematic diagram of the two second protrusions in the middle.

[0088] Figure 12 In accordance with Figure 9 A schematic diagram of the cross-section after CC sectioning.

[0089] Figure 13 In accordance with Figure 9 A cross-sectional view of DD after it has been cut.

[0090] Figure 14 This is a top view of the array substrate disclosed herein.

[0091] Figure 15 This is a cross-sectional view of the non-display area of ​​the display panel disclosed herein.

[0092] Figure 16 This is a schematic diagram of the structure of the second exemplary embodiment of this disclosure.

[0093] Figure 17 for Figure 16 A schematic diagram of an example embodiment of the gate layer.

[0094] Figure 18 for Figure 16 A schematic diagram of another example implementation of the gate layer in the diagram.

[0095] Figure 19 This is a schematic diagram of the structure of the third exemplary embodiment of this disclosure.

[0096] Explanation of reference numerals in the attached figures:

[0097] 100. Array substrate; 200. Color filter substrate;

[0098] 1. First substrate;

[0099] 2. Switching layer group; 21. First light-shielding layer; 22. Second light-shielding layer; 23. Switching unit; 24. Gate layer; 241. Gate line; 242. Second electrode; 2421. Sub-second electrode; 2422. Connecting part; 243. Second gap; 25. Gate insulating layer; 26. Active layer; 261. First filling part; 262. Second filling part; 263. Channel part; 27. Source-drain layer; 271. Data line; 272. Source; 273. Drain; 274. Second electrode connecting part; 275. Repair block;

[0100] 3. Insulating layer group; 31. First protective layer; 311. First sub-via; 32. Insulating layer; 321. Second sub-via; 33. Second protective layer; 331. Third sub-via; 34. First protrusion; 35. First via; 36. First plane; 37. Second plane; 38. First connecting part;

[0101] 4. First electrode layer; 41. First electrode;

[0102] 5. Reflective layer; 51. Second protrusion; 511. First part; 512. Second part; 513. Third part; 52. First gap; 53. Reflective part;

[0103] 61. First bonding pin; 62. Second bonding pin;

[0104] 7. Groove;

[0105] 8. Spacer; 91. First alignment membrane; 92. Second alignment membrane;

[0106] 201. Second substrate; 202. Light-transmitting portion; 203. Light-shielding portion;

[0107] 301. Frame; 302. Liquid crystal layer; 303. Scattering film;

[0108] 401. Support column; 402. Equipment platform;

[0109] 501, Cutting line;

[0110] X, first direction; Y, second direction; Z, third direction;

[0111] AA, display area; BOD, binding area. Detailed Implementation

[0112] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0113] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0114] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0115] Reference Figure 1 As shown, some RLCD products require the use of a diffuse reflection film 303 (POL) to achieve diffuse reflection. However, diffuse reflection films are expensive, and the material of the half-wave plate in the diffuse reflection film is brittle and prone to breakage due to thermal expansion during reliability testing, thus affecting the reliability test. A method to diffusely reflect light can be used by forming a textured structure (second protrusion 51) on the reflective layer 5, instead of the diffuse reflection film 303.

[0116] The inventors discovered that the main reason for the uneven display on the display panel is the unevenness of the uneven texture (second protrusion 51) formed on the reflective layer 5, which leads to uneven diffuse reflection light. (Refer to...) Figure 2 As shown, the main problem with the unevenness of the formed convex-concave structure (second protrusion 51) is that the support pillar 401 for picking up and placing the first substrate 1 is provided on the exposure equipment platform, and the material of the support pillar 401 is different from that of the equipment platform 402. When the insulating layer 32 is exposed and etched to form the first protrusion 34, because the material of the support pillar 401 is different from that of the equipment platform 402, the energy of the light reflected from the equipment platform 402 and the support pillar 401 to the array substrate 100 is different after the light shines on the equipment platform 402 and the support pillar 401. This results in different exposure energy for the insulating layer 32, and ultimately, the angle of the first protrusion 34 formed at the support pillar 401 and the equipment platform 402 is different. This leads to different reflectivity of the display panel at the support pillar 401 and the equipment platform 402, and uneven reflected light, which ultimately affects the display effect.

[0117] This disclosure provides an array substrate 100 according to an exemplary embodiment, with reference to... Figures 3-19As shown, the array substrate 100 may include a display area AA and a bonding area BOD. The array substrate 100 may include a first substrate 1, a switching layer group 2, an insulating layer group 3, and a reflective layer 5. The switching layer group 2 is disposed on one side of the first substrate 1. The switching layer group 2 includes a plurality of switching units 23 and a plurality of first light-shielding layers 21. The plurality of first light-shielding layers 21 are spaced apart, and the first light-shielding layers 21 are disposed in the same layer and of the same material as one of the switching units 23. The insulating layer group 3 is disposed on the side of the switching layer group 2 away from the first substrate 1. A plurality of first protrusions 34 are provided on the side of the insulating layer group 3 away from the first substrate 1; a reflective layer 5 is provided on the side of the reflective layer 5 away from the first substrate 1, and a plurality of second protrusions 51 are provided on the side of the reflective layer 5 away from the first substrate 1. The orthographic projection of the first protrusion 34 on the first substrate 1 is located within the orthographic projection of the second protrusion 51 on the first substrate 1. The reflective layer 5 includes a plurality of reflective portions 53, and the orthographic projection of the first light-shielding layer 21 on the first substrate 1 is located within the orthographic projection of the reflective portion 53 on the first substrate 1.

[0118] The array substrate 100 disclosed herein has, on one hand, a plurality of second protrusions 51 provided on the side of the reflective layer 5 facing away from the first substrate 1. These second protrusions 51 reflect ambient light incident on the array substrate 100 to form diffuse reflection, replacing the scattering film 303. This not only reduces costs but also, according to... Figure 1 and Figure 4 As shown, Figure 1 This is a schematic diagram of the structure of a display panel with a scattering film. Figure 4 This is a schematic diagram of the structure of the display panel disclosed herein. From the diagram, we can see that the viewing angle α in step 1 is less than... Figure 4 The uniformity of the viewing angle β in the image can be improved by using multiple second protrusions 51.

[0119] On the other hand, the orthographic projection of the first light-shielding layer 21 on the first substrate 1 is located within the orthographic projection of the reflective portion 53 on the first substrate 1, and the distance between the edge of the first light-shielding layer 21 and the edge of the reflective portion 53 is less than or equal to 30 micrometers; the area of ​​the first light-shielding layer 21 is made as large as possible so that when the insulating layer group 3 is etched to form the first protrusion 34, as much reflected light from the equipment platform 402 and the support column 401 can be blocked as much as possible, preventing the reflected light from hitting the insulating layer group 3, thereby avoiding the unevenness of the first protrusion 34 due to the different intensities of reflected light caused by the different materials of the equipment platform 402 and the support column 401, and thus avoiding the unevenness of the second protrusion 51; so that the morphology of the multiple second protrusions 51 is basically the same and they are evenly distributed in all places, thereby making the display of the display panel uniform in all places.

[0120] On the other hand, the first light-shielding layer 21 and one of the switching units 23 are made of the same material and are formed by the same patterning process. Therefore, setting the first light-shielding layer 21 will not increase the manufacturing process steps or cost of the array substrate 100, nor will it increase the thickness of the array substrate 100.

[0121] In this example embodiment, the first substrate 1 may be a glass substrate; of course, in some other example embodiments of this disclosure, the first substrate 1 may also be quartz, etc.; the first substrate 1 may also include an insulating material layer, which may be disposed on one side of the glass substrate, and the insulating material layer may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate.

[0122] In this example implementation, refer to Figure 3 and Figure 5 As shown, a gate layer 24 can be disposed on one side of the first substrate 1. The gate layer 24 may include multiple gate lines 241, multiple sub-second electrodes 2421, and multiple connecting portions 2422. The sub-second electrodes 2421 can be configured as a frame shape, for example, a rectangular frame. This configuration avoids the following: the overlapping area between the subsequently formed first light-shielding layer 21 and the sub-second electrodes 2421 is too large, resulting in an excessively large storage capacitance, leading to an excessively long charging time and inability to fully charge; or the area of ​​the sub-second electrodes 2421 is too small, resulting in an excessively small storage capacitance and causing crosstalk.

[0123] A gate line 241 extends along a first direction X, which is parallel to the side of the first substrate 1 closest to the switching layer group 2. A portion of the gate line 241 can serve as a gate electrode. Multiple sub-second electrodes 2421 are arranged in an array, with the sub-second electrodes 2421 arranged along the first direction X forming a row. A gate line 241 is disposed between two adjacent rows of sub-second electrodes 2421, meaning the gate line 241 is disposed on one side of the sub-second electrode 2421 along the second direction Y. A connecting portion 2422 connects two adjacent sub-second electrodes 2421 arranged along the first direction X; that is, multiple sub-second electrodes 2421 located in the same row are interconnected via the connecting portion 2422. The sub-second electrode 2421 can be a sub-common electrode, which is disposed across the entire layer, while the sub-second electrodes 2421 need to be connected as a single unit.

[0124] In this example implementation, refer to Figure 3 and Figure 6As shown, a gate insulating layer 25 is disposed on the side of the gate layer 24 away from the first substrate 1. An active layer 26 is disposed on the side of the gate insulating layer 25 away from the first substrate 1. The active layer 26 may include a channel portion 263, a conductor portion, a first fill portion 261, and a second fill portion 262. The channel portion 263 is disposed on the side of the gate line 241 away from the first substrate 1, and a portion of the gate line 241 opposite to the channel portion 263 serves as the gate. Two conductor portions are connected one-to-one at both ends of the channel portion 263. The first fill portion 261 is disposed on the side of the connection portion 2422 away from the first substrate 1 and covers at least a portion of the sidewall of the connection portion 2422, thereby reducing the slope of the sidewall of the connection portion 2422. The second fill portion 262 is disposed on the side of the gate line 241 away from the first substrate 1 and covers at least a portion of the sidewall of the gate line 241, thereby reducing the slope of the sidewall of the gate line 241.

[0125] In this example implementation, refer to Figure 3 , Figure 7 and Figure 8 As shown, a source-drain layer 27 is disposed on the side of the active layer 26 away from the first substrate 1. The source-drain layer 27 may include a source electrode 272, a drain electrode 273, a data line 271, a first light-shielding layer 21, and a second electrode connection portion 274. The data line 271 extends along a second direction Y, which intersects with the first direction X. For example, the second direction Y may be perpendicular to the first direction X. Therefore, the data line 271 and the gate line 241 will inevitably intersect. However, due to the steep slope of the side of the gate line 241 and the thin thickness of the gate insulation layer 25, the flattening effect on the gate line 241 is weak. As a result, the data line 271 is prone to breakage at the intersection with the gate line 241, leading to an open circuit. By placing a portion of the second filling portion 262 at the intersection of the gate line 241 and the data line 271, a portion of the data line 271 is located on the side of the second filling portion 262 away from the gate line 241. The second filling portion 262 can further flatten the slope of the side of the gate line 241. The data line 271 placed on the second filling portion 262 is less likely to break and will not be open circuit.

[0126] Furthermore, the data line 271 and the second electrode connection portion 274 will inevitably intersect. However, since the second electrode connection portion 274 and the gate line 241 are formed through the same patterning process, the slope of the side of the second electrode connection portion 274 is relatively steep, and the thickness of the gate insulation layer 25 is relatively thin, resulting in a weaker planarization effect on the second electrode connection portion 274. Therefore, the data line 271 is prone to breakage at the intersection with the second electrode connection portion 274, leading to an open circuit. By setting the first filling portion 261 at the intersection of the second electrode connection portion 274 and the data line 271, even if a part of the data line 271 is located on the side of the first filling portion 261 away from the second electrode connection portion 274, the first filling portion 261 can further planarize the slope of the side of the second electrode connection portion 274. The data line 271 set on the first filling portion 261 is not easy to break and will not be open circuit.

[0127] Please continue to refer to Figure 7 As shown, the first light-shielding layer 21 is disposed on one side of the data line 271 in the first direction X. The orthographic projection of the first light-shielding layer 21 on the first substrate 1 is located within the orthographic projection of the sub-second electrode 2421 on the first substrate 1. For example, the orthographic projection of the first light-shielding layer 21 on the first substrate 1 may coincide with the orthographic projection of the sub-second electrode 2421 on the first substrate 1; alternatively, the edge of the orthographic projection of the first light-shielding layer 21 on the first substrate 1 may be located inside the outermost edge of the orthographic projection of the sub-second electrode 2421 on the first substrate 1, and the distance between the edge of the orthographic projection of the first light-shielding layer 21 on the first substrate 1 and the outermost edge of the orthographic projection of the sub-second electrode 2421 on the first substrate 1 is greater than or equal to 0 μm and less than or equal to 10 μm. The overlapping portion of the first light-shielding layer 21 and the sub-second electrode 2421 forms a storage capacitor. The size of the overlapping portion of the first light-shielding layer 21 and the sub-second electrode 2421 is designed to match the required size of the storage capacitor.

[0128] One end of the source 272 is connected to the data line 271, and the other end is connected to a conductor portion; one end of the drain 273 is connected to the first light-shielding layer 21, and the other end is connected to another conductor portion. The gate, the channel portion 263, the source 272, the drain 273, and the two conductor portions form a switching unit 23, which is a thin-film transistor.

[0129] It should be noted that the thin-film transistor described in this specification is a bottom-gate thin-film transistor. In other exemplary embodiments of this disclosure, the thin-film transistor may also be a top-gate or dual-gate type, and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0130] Please continue to refer to Figure 7 As shown, the sub-second electrode 2421 can be a sub-common electrode. The common electrode is disposed throughout the entire layer. The sub-second electrodes 2421 need to be connected as a whole. Two adjacent sub-second electrodes 2421 in the first direction X are connected as a whole through the connecting part 2422. The second electrode connecting part 274 is connected between two adjacent sub-second electrodes 2421 in the second direction Y, and a part of the second electrode connecting part 274 is located on the side of the second filling part 262 away from the gate line 241. The second electrode connection 274 and the gate line 241 will inevitably intersect. However, due to the steep slope of the side of the gate line 241 and the thin thickness of the gate insulation layer 25, the flattening effect on the gate line 241 is weak. Therefore, the second electrode connection 274 is prone to breakage at the intersection with the gate line 241, resulting in an open circuit. By setting another part of the second filling part 262 at the intersection of the gate line 241 and the second electrode connection 274, a part of the second electrode connection 274 is located on the side of the second filling part 262 away from the gate line 241. The second filling part 262 can further flatten the slope of the side of the gate line 241. The second electrode connection 274 set on the second filling part 262 is not easy to break and will not cause an open circuit.

[0131] The spacing between the first light-shielding layer 21 and the two gate lines 241 on both sides is different, or the spacing between the same gate line 241 and the two first light-shielding layers 21 on both sides is different. Specifically, the spacing W1 between the gate line 241 and the first light-shielding layer 21 belonging to the same pixel is greater than the spacing W2 between the gate line 241 and the first light-shielding layer 21 not belonging to the same pixel.

[0132] Furthermore, the second protrusion 51 and the first protrusion 34 may not be provided in the gap between the first light-shielding layer 21 and the gate line 241. That is, the orthographic projections of the plurality of first protrusions 34 and the plurality of second protrusions 51 on the first substrate 1 do not overlap with the orthographic projection of the gap on the first substrate 1; however, the orthographic projections of the plurality of first protrusions 34 and the plurality of second protrusions 51 on the first substrate 1 partially overlap with the orthographic projection of the gate line 241 on the first substrate 1. This arrangement can increase the area of ​​the reflective layer 5 and improve the display effect.

[0133] In this example embodiment, the source-drain layer 27 may further include a maintenance block 275, which is connected to the side of the first light-shielding layer 21 near the gate line 241. Specifically, the maintenance block 275 may be located on the side of the first light-shielding layer 21 away from the switching unit 23. Of course, the maintenance block 275 may also be located on the side of the first light-shielding layer 21 near the switching unit 23.

[0134] The orthographic projection of the repair block 275 on the first substrate 1 overlaps with the orthographic projection of the gate line 241 on the first substrate 1. In the event of a damaged thin-film transistor (switching unit 23), the corresponding sub-pixel cannot be displayed. The source 272 connected to the data line 271 can be disconnected, and the repair block 275 can be connected to the gate line 241 via a via. An electrical signal is then supplied to the first light-shielding layer 21 through the gate line 241. The first light-shielding layer 21 transmits this electrical signal to the pixel electrode (first electrode 4), thus enabling the pixel to be displayed. Alternatively, in some other exemplary embodiments of this disclosure, the drain 273 connected to the first light-shielding layer 21 can be disconnected.

[0135] In this example implementation, refer to Figure 3 As shown, an insulating layer group 3 is disposed on the side of the source / drain layer 27 away from the first substrate 1. The insulating layer group 3 may include a first protective layer 31, an insulating layer 32, and a second protective layer 33. The first protective layer 31 is disposed on the side of the source / drain layer 27 away from the first substrate 1, and a first sub-via 311 is disposed on the first protective layer 31, which connects to the first light-shielding layer 21. The material of the first protective layer 31 may be an inorganic material, such as silicon nitride, silicon oxide, etc. The thickness of the first protective layer 31 is greater than or equal to 100 nm and less than or equal to 500 nm.

[0136] An insulating layer 32 is disposed on the side of the first protective layer 31 away from the first substrate 1. A second sub-via 321 is provided on the insulating layer 32, which communicates with the first sub-via 311, thereby connecting the second sub-via 321 to the first light-shielding layer 21. The material of the insulating layer 32 can be an organic material, such as polyimide, polycarbonate, polyacrylate, etc. The thickness of the insulating layer 32 is greater than or equal to 0.5 μm and less than or equal to 5 μm. Due to the relatively thick thickness of the insulating layer 32, etching the insulating layer 32 to form the third protrusion will naturally form the first protrusion 34 in the second protective layer 33 subsequently formed on the side of the insulating layer 32 away from the substrate. Moreover, the insulating layer 32 can be made of photoresist. When forming the third protrusion and the second sub-via 321 on the insulating layer 32, only exposure and development are required, saving process steps. However, when forming the third protrusion on other film layers, after exposure and development, etching of other film layers using photoresist as a mask is required.

[0137] The insulating layer 32 has a plurality of third protrusions on the side away from the first substrate 1. The height of the sidewall of the third protrusion in the third direction Z decreases as the distance from the center of the third protrusion to the first surface increases. The first surface is parallel to the side of the first substrate 1 near the switch layer group 2, that is, the first surface is a plane formed by the first direction X and the second direction Y, and the third direction Z is perpendicular to the first surface. For example, the sidewall of the third protrusion can be set as an arc surface, which can be a circular arc surface, an elliptical arc surface, etc. Specifically, the third protrusion can be set as a spherical cap structure, an ellipsoidal cap structure, etc. The sidewall of the third protrusion can also be set as an inclined surface. Specifically, in order to ensure that the second protrusion formed later has a sufficient reflective surface, the third protrusion may not have a top surface, that is, the third protrusion can be set as various pyramidal structures.

[0138] The second protective layer 33 is disposed on the side of the insulating layer 32 away from the first substrate 1, and a portion of the second protective layer 33 also covers the hole wall of the second sub-via 321. A third sub-via 331 is disposed on the second protective layer 33, and the third sub-via 331 communicates with the second sub-via 321 and the first sub-via 311, so that the third sub-via 331 communicates to the first light-shielding layer 21. The first sub-via 311, the second sub-via 321, and the third sub-via 331 form a first via 35, which communicates to the first light-shielding layer 21. The material of the second protective layer 33 can be an inorganic material, and the material of the second protective layer 33 can be the same as that of the first protective layer 31, for example, it can be silicon nitride, silicon oxide, etc. The first protective layer 31 and the second protective layer 33 can protect the insulating layer 32. The thickness of the second protective layer 33 is greater than or equal to 50 nm and less than or equal to 350 nm.

[0139] Because the second protective layer 33 is relatively thin, a plurality of first protrusions 34 are formed on the side of the second protective layer 33 away from the first substrate 1. The first protrusions 34 are disposed opposite to the aforementioned third protrusions, that is, the first protrusions 34 are located on the side of the third protrusion away from the first substrate 1. The height of the sidewall of the first protrusion 34 in the third direction Z also decreases as the distance from the center of the first protrusion 34 to the first surface increases. For example, the side of the first protrusion 34 away from the first substrate 1 can be set as an arc surface. When the sidewall of the third protrusion is a circular arc surface, an elliptical arc surface, etc., the sidewall of the first protrusion 34 is correspondingly set as a circular arc surface, an elliptical arc surface, etc. When the third protrusion is set as a spherical cap structure, an ellipsoidal cap structure, etc., the first protrusion 34 is correspondingly set as a spherical cap structure, an ellipsoidal cap structure, etc. The side of the first protrusion 34 away from the first substrate 1 can also be set as an inclined surface. When the third protrusion is set as various pyramidal structures, the first protrusion 34 is correspondingly set as various pyramidal structures.

[0140] In other exemplary embodiments of this disclosure, the insulating layer group 3 may include only the insulating layer 32 and the second protective layer 33, or it may include more insulating material layers, such as passivation layers, buffer layers, etc. Furthermore, the protrusion can be disposed in any layer with a relatively thick thickness.

[0141] A first connecting portion 38 is connected between adjacent first protrusions 34. The height of the first protrusions 34 in the third direction Z is higher than the height of the first connecting portion 38 in the third direction Z. The orthographic projections of the first protrusions 34 and the first connecting portion 38 on the first substrate 1 are located within the orthographic projection of the first light-shielding layer 21 on the first substrate 1. The first connecting portion 38 is disposed opposite to the first portion 511.

[0142] For example, the orthographic projection of the first light-shielding layer 21 on the first substrate 1 can continuously cover the orthographic projections of the two first protrusions 34 and the first connecting portion 38 between them on the first substrate 1. Of course, the orthographic projection of the first light-shielding layer 21 on the first substrate 1 can continuously cover the orthographic projections of three or more first protrusions 34 and the first connecting portion 38 between them on the first substrate 1.

[0143] The area of ​​the orthographic projection of the first protrusion 34 on the first substrate 1 accounts for more than 80% of the area of ​​the orthographic projection of the first light-shielding layer 21 on the first substrate 1. For example, the area of ​​the orthographic projection of the first protrusion 34 on the first substrate 1 accounts for 85%, 90%, 95%, etc., or even 100%.

[0144] The specific fabrication process of the insulating layer group 3 is as follows: a first protective layer 31 and an insulating layer 32 are formed on the side of the source / drain layer 27 away from the first substrate 1. Then, the insulating layer 32 is patterned to form a second sub-via 321, and a plurality of third protrusions are formed on the side of the insulating layer 32 away from the first substrate 1. A second protective layer 33 is formed on the side of the insulating layer 32 away from the first substrate 1. Since the second sub-via 321 has already been formed on the insulating layer 32, a portion of the second protective layer 33 will cover the hole of the second sub-via 321. The bottom wall and the sidewall of the hole are formed. Finally, the first protective layer 31 and the second protective layer 33 are patterned to form the first sub-via 311 and the third sub-via 331. The first protective layer 31 and the second protective layer 33 within the second sub-via 321 are also patterned. Therefore, the orthographic projection of the first sub-via 311 on the first substrate 1 is located within the orthographic projection of the second sub-via 321 on the first substrate 1, and the orthographic projection of the third sub-via 331 on the first substrate 1 is located within the orthographic projection of the second sub-via 321 on the first substrate 1. Of course, in other exemplary embodiments of this disclosure, the first protective layer 31 and the second protective layer 33 can also be patterned in two separate steps. That is, after forming the second sub-via 321, the first protective layer 31 is patterned to form the first sub-via 311, then the second protective layer 33 is formed, and finally the second protective layer 33 is patterned to form the third sub-via 331.

[0145] When forming the first sub-via 311, the second sub-via 321, and the third sub-via 331 through the same patterning process of the first protective layer 31, the insulating layer 32, and the second protective layer 33, the material of the first protective layer 31 is relatively soft, and the thickness of the insulating layer 32 is relatively thick, resulting in a long etching time. Furthermore, the first protective layer 31 is located at the bottom layer, making it prone to undercutting, which significantly increases the process difficulty. Therefore, the insulating layer 32 is first patterned to form the second sub-via 321. Then, the first protective layer 31 and the second protective layer 33 are patterned at the second sub-via 321 to form the first sub-via 311 and the third sub-via 331. After removing the insulating layer 32, the thickness of both the first protective layer 31 and the second protective layer 33 is thinner, the etching time is shorter, and undercutting is less likely to occur, reducing the process difficulty. Moreover, the insulating layer 32 can be made of photoresist. When forming the third protrusion and the second sub-via 321 on the insulating layer 32, only exposure and development are required, and etching is not necessary.

[0146] Please continue to refer to Figure 3As shown, the side of the insulating layer group 3 facing away from the first substrate 1 includes a first plane 36. The orthographic projection of the first plane 36 on the first substrate 1 overlaps with the orthographic projection of the channel portion 263 on the first substrate 1. For example, the orthographic projection of the first plane 36 on the first substrate 1 may coincide with the orthographic projection of the channel portion 263 on the first substrate 1. Alternatively, the edge of the orthographic projection of the first plane 36 on the first substrate 1 may be located inside the edge of the orthographic projection of the channel portion 263 on the first substrate 1. Or, a portion of the orthographic projection of the first plane 36 on the first substrate 1 may overlap with a portion of the orthographic projection of the channel portion 263 on the first substrate 1.

[0147] Specifically, the side of the insulating layer 32 facing away from the first substrate 1 may include a third plane. The orthographic projection of the third plane onto the first substrate 1 overlaps with the orthographic projection of the channel portion 263 onto the first substrate 1. For example, the orthographic projection of the third plane onto the first substrate 1 may coincide with the orthographic projection of the channel portion 263 onto the first substrate 1. Alternatively, the edge of the orthographic projection of the third plane onto the first substrate 1 may be located inside the edge of the orthographic projection of the channel portion 263 onto the first substrate 1. Or, a portion of the orthographic projection of the third plane onto the first substrate 1 may overlap with a portion of the orthographic projection of the channel portion 263 onto the first substrate 1. The second protective layer 33 is disposed on the side of the insulating layer 32 away from the first substrate 1. Therefore, the first plane 36 is formed on the side of the second protective layer 33 away from the first substrate 1. Moreover, since the third protrusion on the insulating layer 32 is formed by etching the insulating layer 32, the third plane can be formed without etching at the third plane. Therefore, the third plane protrudes relative to the surrounding area. The second protective layer 33 formed subsequently has a certain planarization effect on the side of the insulating layer 32 that is away from the first substrate 1. Therefore, when the second protective layer 33 is thin, the orthographic projection of the first plane 36 on the first substrate 1 basically coincides with the orthographic projection of the third plane on the first substrate 1; when the second protective layer 33 is thick, the orthographic projection of the first plane 36 on the first substrate 1 is located inside the orthographic projection of the third plane on the first substrate 1.

[0148] In other words, the portion of the insulating layer group 3 facing away from the first substrate 1 and opposite to the channel portion 263 is a first plane 36. Specifically, the portion of the insulating layer 32 facing away from the first substrate 1 and opposite to the channel portion 263 is a plane, so the portion of the second protective layer 33 subsequently formed facing away from the first substrate 1 and opposite to the channel portion 263 is also a plane.

[0149] The array substrate 100 may further include spacers 8, which are disposed on the side of the first plane 36 away from the first substrate 1. Because the spacers 8 are used to support the color filter substrate 200, a relatively flat support plane is required. Therefore, a relatively flat base plane is needed for the spacers 8. The third protrusion would cause the base plane where the spacers 8 are disposed to be uneven. The first plane 36 provides a relatively flat base plane for the spacers 8. Therefore, when the spacers 8 are disposed in other positions, the first plane 36 can also be disposed in other positions.

[0150] In this example implementation, please continue to refer to Figure 3 and Figure 9 As shown, a first electrode layer 4 is disposed on the side of the insulating layer group 3 away from the first substrate 1, such that the first electrode layer 4 is located between the insulating layer group 3 and the reflective layer 5; the first electrode layer 4 includes a plurality of first electrodes 41, and the first electrodes 4 are connected to the first light-shielding layer 21 through a first via 35. The first electrode 4 can be a pixel electrode, and the first light-shielding layer 21 and the sub-second electrode directly form a Cst capacitor, thereby not increasing parasitic capacitance.

[0151] The material of the first electrode layer 4 can be ITO (Indium Tin Oxide). Alternatively, it can be other transparent conductive oxides such as IZO (Indium Zinc Oxide). The thickness of the first electrode layer 4 is greater than or equal to 30 nm and less than or equal to 100 nm. Because the first electrode layer 4 is relatively thin, multiple fourth protrusions are formed on the side of the second protective layer 33 facing away from the first substrate 1. These fourth protrusions are positioned opposite to the first protrusions 34, i.e., the fourth protrusions are located on the side of the first protrusions 34 away from the first substrate 1. The height of the sidewall of the fourth protrusion in the third direction Z also decreases as the distance from the center of the fourth protrusion to the first surface increases. For example, the side of the fourth protrusion away from the first substrate 1 can be an arc surface. If the sidewall of the first protrusion 34 is a circular arc surface, an elliptical arc surface, etc., then the corresponding sidewall of the fourth protrusion is also a circular arc surface, an elliptical arc surface, etc. If the first protrusion 34 is a spherical cap structure, an ellipsoidal cap structure, etc., then the corresponding fourth protrusion is also a spherical cap structure, an ellipsoidal cap structure, etc. The side of the fourth protrusion away from the first substrate 1 can also be configured as an inclined surface. When the first protrusion 34 is configured as various pyramidal structures, the fourth protrusion is also configured as various pyramidal structures accordingly.

[0152] Please refer to Figure 3 and Figure 10As shown, a reflective layer 5 is provided on the side of the first electrode layer 4 away from the first substrate 1. The reflective layer 5 can be made of metal. The thickness of the reflective layer 5 is greater than or equal to 50 nm and less than or equal to 300 nm. Since the reflective layer 5 is relatively thin, a plurality of second protrusions 51 are formed on the side of the reflective layer 5 away from the first substrate 1. The second protrusions 51 are disposed opposite to the fourth protrusion, that is, the second protrusions 51 are located on the side of the fourth protrusion away from the first substrate 1. The height of the sidewall of the second protrusion 51 in the third direction Z also decreases as the distance from the center of the second protrusion 51 to the first surface increases. For example, the side of the second protrusion 51 away from the first substrate 1 can be set as an arc surface. When the sidewall of the fourth protrusion is a circular arc surface, an elliptical arc surface, etc., the sidewall of the second protrusion 51 is correspondingly a circular arc surface, an elliptical arc surface, etc. When the fourth protrusion is set as a spherical cap structure, an ellipsoidal cap structure, etc., the second protrusion 51 is correspondingly set as a spherical cap structure, an ellipsoidal cap structure, etc. The side of the second protrusion 51 away from the first substrate 1 can also be configured as an inclined surface. When the fourth protrusion is configured as various pyramidal structures, the second protrusion 51 is also configured as various pyramidal structures accordingly.

[0153] Specifically, refer to Figure 11 As shown, the sidewall of the second protrusion 51 may include a first portion 511, a second portion 512, and a third portion 513 that are smoothly connected in sequence. The first portion 511 is closer to the first substrate than the third portion 513. The first portion 511 and the third portion 513 are curved surfaces. The radius of curvature of the first portion 511 may be smaller than the radius of curvature of the third portion 513. The first portion 511 may be recessed, and the third portion 513 may be protruding. The second portion 512 is a sloped surface. Specifically, the portion of the sidewall of the second protrusion 51 that is close to the first substrate may be a curved surface, the middle portion of the sidewall of the second protrusion 51 may be a sloped surface, and the portion of the sidewall of the second protrusion 51 that is away from the first substrate may be a curved surface.

[0154] The first portions 511 of the multiple second protrusions 51 are smoothly connected. Specifically, the first portions 511 of the multiple second protrusions 51 are smoothly connected at the bottom of the second protrusion 51; and the third portions 513 of the same second protrusion 51 are smoothly connected at the top of the second protrusion 51. This makes each part of the second protrusion 51 form a diffuse reflective surface, improving the reflective efficiency of the reflective layer 5 and ensuring the display effect.

[0155] The area of ​​the first light-shielding layer 21 projected onto the first substrate 1 accounts for 60% to 100% of the area of ​​the reflective portion 53 projected onto the first substrate 1. For example, the area of ​​the first light-shielding layer 21 projected onto the first substrate 1 accounts for 85% to 95% of the area of ​​the reflective portion 53 projected onto the first substrate 1, specifically, it can be 86%, 88%, 90%, 91%, 93.5%, etc.

[0156] The angle between the sidewall of the second protrusion 51 and the first surface is greater than or equal to 6° and less than or equal to 13°. For example, the angle between the sidewall of the second protrusion 51 and the first surface can be 7.5°, 9°, 9.5°, 10°, 10.5°, 12°, etc. Within this range, the reflectivity of the reflective layer 5 is the highest.

[0157] Reference Figure 11 As shown, when the side of the second protrusion 51 away from the first substrate 1 is set as an arc surface, the angle between the sidewall of the second protrusion 51 and the first surface refers to the angle λ between the tangent of the end of the first protrusion 34 near the first substrate and the first surface.

[0158] Reference Figure 10 As shown, the shape of the first electrode 41 can be the same as the shape of the reflective portion 53, that is, the shape of the orthographic projection of the first electrode 41 on the first substrate 1 can be the same as the shape of the orthographic projection of the reflective portion 53 on the first substrate 1. The orthographic projection of the first electrode 41 on the first substrate 1 is located within the orthographic projection of the reflective portion 53 on the first substrate 1. For example, the orthographic projection of the first electrode 41 on the first substrate 1 can overlap with the orthographic projection of the reflective portion 53 on the first substrate 1; alternatively, the edge of the orthographic projection of the first electrode 41 on the first substrate 1 can be located within the edge of the orthographic projection of the reflective portion 53 on the first substrate 1, and a gap is provided between the edge of the orthographic projection of the first electrode 41 on the first substrate 1 and the edge of the orthographic projection of the reflective portion 53 on the first substrate 1. The width of the gap is greater than or equal to 1 micrometer and less than or equal to 5 micrometers. For example, the width of the gap can be 2 micrometers, 3 micrometers, 4.5 micrometers, etc. This arrangement can avoid errors in the fabrication process of the first electrode 4 and the reflective portion 53, which could result in the reflective portion 53 not covering the first electrode 4.

[0159] In addition, in some other exemplary embodiments of this disclosure, the orthographic projection of the reflective portion 53 on the first substrate 1 may also be located within the orthographic projection of the first electrode 41 on the first substrate 1, that is, the edge of the first electrode 41 is not covered by the reflective portion 53. Since the material of the first electrode 41 is ITO, the first electrode 41 is prone to crystallization when the temperature rises during the deposition process. After etching the first electrode 41, some residue will also form sand residue. If the reflective portion 53 covers the etched position of the first electrode 41, due to the presence of sand residue, the reflective layer 5 is prone to bulging at the sand residue, resulting in abnormal reflectivity and abnormal display. If the edge of the first electrode 41 is not covered by the reflective portion 53, then the reflective portion 53 will not cover the sand residue, and there will be no bulging or abnormal reflectivity due to the sand residue, so that the display panel displays normally.

[0160] The orthographic projection of the first electrode 5 on the first substrate 1 overlaps with the orthographic projection of the gate line 241 on the first substrate 1; that is, the first electrode 5 not only covers the first light-shielding layer 21, but also protrudes towards the gate line 241 and partially overlaps with it. Similarly, the orthographic projection of the reflective portion 53 on the first substrate 1 overlaps with the orthographic projection of the gate line 241 on the first substrate 1; that is, the reflective portion 53 not only covers the first light-shielding layer 21, but also protrudes towards the gate line 241 and partially overlaps with it. By making the area of ​​the reflective portion 53 as large as possible, the reflective area is increased, thereby increasing the reflectivity and thus improving the display effect.

[0161] Reference Figure 12 and Figure 13 As shown, the side of the insulating layer group 3 facing away from the first substrate 1 may also include a second plane 37, the orthographic projection of the second plane 37 on the first substrate 1 being located within the orthographic projection of the space between two adjacent first electrodes 4 on the first substrate 1.

[0162] The second plane 37 may include a plurality of first sub-planes extending along the first direction X and a plurality of second sub-planes extending along the second direction Y. The width of the first sub-plane perpendicular to the first direction X is greater than or equal to 1 micrometer and less than or equal to 12 micrometers, for example, it may be 5 micrometers, 6 micrometers, 8 micrometers, etc.; the width of the second sub-plane perpendicular to the second direction Y is greater than or equal to 4 micrometers and less than or equal to 8 micrometers, for example, it may be 6 micrometers; the plurality of first sub-planes and the plurality of second sub-planes intersect to form a grid, and a plurality of first protrusions 34 are provided in each grid.

[0163] Specifically, the side of the insulating layer 32 facing away from the first substrate 1 may include a fourth plane. The orthographic projection of the fourth plane on the first substrate 1 lies within the orthographic projection of the space between two adjacent first electrodes 4 on the first substrate 1. The orthographic projection of the fourth plane on the first substrate 1 may coincide with the orthographic projection of the space between two adjacent first electrodes 4 on the first substrate 1, or it may lie inside the orthographic projection of the space between two adjacent first electrodes 4 on the first substrate 1. The second protective layer 33 is disposed on the side of the insulating layer 32 away from the first substrate 1; therefore, the second plane 37 is formed on the side of the second protective layer 33 away from the first substrate 1. Furthermore, since the third protrusion on the insulating layer 32 is formed by etching the insulating layer 32, the fourth plane can be formed without etching at the fourth plane; therefore, the fourth plane protrudes relative to its surroundings. The subsequently formed second protective layer 33 has a certain planarization effect on the side of the insulating layer 32 facing away from the first substrate 1. Therefore, when the second protective layer 33 is thin, the orthographic projection of the fourth plane on the first substrate 1 basically coincides with the orthographic projection of the second plane 37 on the first substrate 1; when the second protective layer 33 is thick, the orthographic projection of the fourth plane on the first substrate 1 is located inside the orthographic projection of the second plane 37 on the first substrate 1. Of course, as Figure 12 and Figure 13 As shown, the second plane 37 can also be formed by etching.

[0164] Since the reflective layer 5 is directly disposed on the side of the first electrode 4 away from the first substrate 1, and the material of the reflective layer 5 is Ag (silver), which is conductive, the reflective layer 5 will inevitably be energized when the first electrode 4 is energized. If the first protrusion 34 is also disposed in the space between two adjacent pixel areas, the surface of the reflective material layer formed in the space will be uneven. When the reflective material layer is etched to form different reflective parts 53 of different pixels, the photoresist in the recess of the space is not easy to remove, which makes it impossible to etch the reflective material layer. As a result, the pixel electrodes of two adjacent sub-pixels are connected to each other, resulting in poor bright spots.

[0165] After setting the second plane 37, the surface of the reflective material layer formed in the second plane 37 is relatively flat. When the reflective material layer is etched to form different reflective parts 53 of different pixels, the photoresist in the second plane 37 is easy to remove, and the reflective material layer will also be etched away, so that there is a gap between two adjacent reflective parts 53, so that the pixel electrodes of two adjacent sub-pixels will not connect with each other and will not cause bright spot defects.

[0166] It should be noted that the first plane 36 and the second plane 37 described above are not absolutely flat and also have a certain degree of roughness; the limitation of being flat is mainly relative to the other positions of the insulating layer group 3 where the first protrusion 34 is provided. The first protrusion 34 is not provided at the first plane 36 and the second plane 37, making the first plane 36 and the second plane 37 more flat.

[0167] In other example embodiments of this disclosure, a first protrusion 34 and a reflective layer 5 may also be provided between two adjacent pixels, and a second protrusion 51 may be provided on the reflective layer 5. The first protrusion 34 and the reflective layer 5 may not be provided only in the area opposite the thin-film transistor and the first via 35; therefore, the second protrusion 51 will not be formed. This arrangement increases the area of ​​the reflective layer 5, thereby improving the display effect.

[0168] The structure of the display area AA has been described in detail above. Please refer to... Figure 14 and Figure 15 As shown, in the bonding region BOD, the array substrate 100 may further include multiple first bonding pins 61 and multiple second bonding pins 62; the first bonding pins 61 are disposed in the same layer and material as the gate layer 24 or the source / drain layer 27; the multiple second bonding pins 62 are located one-to-one on the side of the multiple first bonding pins 61 away from the first substrate 1, the second bonding pins 62 are disposed in the same layer and material as the first electrode 4, the orthographic projection of the second bonding pins 62 on the first substrate 1 is located within the orthographic projection of the first bonding pins 61 on the first substrate 1, and a gap is provided between the edge of the orthographic projection of the second bonding pins 62 on the first substrate 1 away from the display area AA and the edge of the orthographic projection of the first bonding pins 61 on the first substrate 1 away from the display area AA; that is, the second bonding pins 62 are recessed inward towards the display area AA, and the distance m between the end face of the second bonding pins 62 away from the display area AA and the end face of the first bonding pins 61 away from the display area AA is the gap, the width of the gap is greater than or equal to 1.5 micrometers and less than or equal to 3.5 micrometers, for example, it can be 2 micrometers, 2.5 micrometers, 3 micrometers, etc. This setting can prevent the second bonding pin 62 from sticking up.

[0169] A groove 7 is provided in the bonding area BOD, penetrating the first protective layer 31 and the second protective layer 33. The groove 7 is located on the side of the first bonding pin 61 away from the display area AA, that is, the groove 7 is located on the side of the first bonding pin 61 close to the cutting line 501. Since cracks will be generated in the first protective layer 31 and the second protective layer 33 when the array substrate 100 is cut, the groove 7 can prevent the cracks from extending to the first bonding pin 61, thereby avoiding cracking of the first bonding pin 61 and ensuring the electrical performance of the first bonding pin 61.

[0170] The array substrate 100 may also include test traces. The distance between the test traces and the dicing lines of the array substrate 100 is greater than or equal to 0.2 mm and less than or equal to 0.3 mm. Increasing the distance between the test traces and the dicing lines can prevent the test traces from being scratched during dicing.

[0171] In another exemplary embodiment of this disclosure, reference is made to Figure 16 and Figure 17 As shown, the first light-shielding layer 21 and the gate layer 24 can be disposed on the same layer and with the same material. The gate layer 24 may include multiple gate lines 241, multiple sub-second electrodes 2421, and multiple connecting portions 2422. The sub-second electrodes 2421 can be configured as a frame shape, for example, the sub-second electrode 2421 can be configured as a rectangular frame. The gate lines 241 extend along a first direction X, which is parallel to the side of the first substrate 1 near the switching layer group 2, wherein a portion of the gate lines 241 can serve as gates. The multiple sub-second electrodes 2421 are arranged in an array, and the multiple sub-second electrodes 2421 arranged along the first direction X form a row, with a gate line 241 disposed between two adjacent rows of sub-second electrodes 2421, that is, the gate line 241 is disposed on one side of the sub-second electrode 2421 in the second direction Y. The connecting portions 2422 connect between two adjacent sub-second electrodes 2421 arranged along the first direction X, that is, multiple sub-second electrodes 2421 located in the same row are interconnected through the connecting portions 2422.

[0172] The first light-shielding layer 21 is disposed within the frame shape. The first light-shielding layer 21 can be configured as a rectangular sheet. The outer edge of the first light-shielding layer 21 can be connected to the inner edge of the second electrode 242 as a single unit, so that the first light-shielding layer 21 and the second electrode 242 form a rectangular sheet. This results in a larger area of ​​the sub-second electrode 2421, increasing the storage capacitance formed by the sub-second electrode 2421 and the source-drain layer, leading to excessively long charging time or failure to fully charge.

[0173] Of course, in some other exemplary embodiments of this disclosure, reference is made to Figure 18 As shown, a second gap 243 is provided between the first light-shielding layer 21 and the second electrode 242, which insulates the first light-shielding layer 21 from the second electrode 242. When the second electrode 242 is energized, the first light-shielding layer 21 will not be energized, thus preventing the first light-shielding layer 21 from affecting the capacitance of the array substrate 100. Moreover, given the available process conditions, the width of the second gap 243 can be made as narrow as possible, so that the area of ​​the first light-shielding layer 21 is as large as possible, blocking as much light as possible.

[0174] In this case, the source-drain layer 27 may include a source 272, a drain 273, a data line 271, and a second electrode connection portion 274. In the above embodiment, the area of ​​the portion configured as the first light-shielding layer 21 can be set relatively small, as long as it can be connected to the first electrode 4.

[0175] In another exemplary embodiment of this disclosure, reference is made to Figure 19 As shown, two light-shielding layers can be provided, namely a first light-shielding layer 21 and a second light-shielding layer 22. The first light-shielding layer 21 can be provided with the same copper material as the source and drain layers 27. The specific structure of the first light-shielding layer 21 has been described in detail above, so it will not be repeated here.

[0176] The second light-shielding layer 22 can be disposed on the same layer and made of the same material as the gate layer 24. That is, the gate layer 24 may include multiple second light-shielding layers 22, multiple gate lines 241, multiple sub-second electrodes 2421, and multiple connecting portions 2422. The sub-second electrodes 2421 can be configured as a frame shape, for example, the sub-second electrodes 2421 can be configured as a rectangular frame.

[0177] The second light-shielding layer 22 is disposed within the frame. The second light-shielding layer 22 can be configured as a rectangular sheet. The outer edge of the second light-shielding layer 22 can be connected to the inner edge of the second electrode 242 as a whole, so that the second light-shielding layer 22 and the second electrode 242 form a rectangular sheet.

[0178] Of course, in some other exemplary embodiments of this disclosure, a second gap 243 is provided between the second light-shielding layer 22 and the second electrode 242, so that the second light-shielding layer 22 and the second electrode 242 are insulated from each other. When the second electrode 242 is energized, the second light-shielding layer 22 will not be energized, thus preventing the second light-shielding layer 22 from affecting the capacitance of the array substrate 100. Moreover, when the process conditions are met, the width of the second gap 243 can be made as narrow as possible, so that the area of ​​the second light-shielding layer 22 is as large as possible, and the amount of light blocked is as much as possible.

[0179] Based on the same inventive concept, this disclosure provides an example embodiment of a display panel, which may include an array substrate 100, a color filter substrate 200, a frame 301, and a liquid crystal layer 302; the array substrate 100 is any of the array substrates described above; the color filter substrate 200 is disposed on the side of the array substrate 100 near the reflective layer 5; the frame 301 is disposed between the array substrate 100 and the color filter substrate 200; the liquid crystal layer 302 is disposed between the array substrate 100 and the color filter substrate 200, and is located within the frame 301.

[0180] The specific structure of the array substrate 100 has been described in detail above, so it will not be repeated here.

[0181] In this example implementation, refer to Figure 14 As shown, the orthographic projection of the frame 301 on the first substrate 1 does not overlap with the orthographic projection of the insulating layer 32 on the first substrate 1, i.e., a groove is cut into the insulating layer 32, and the second protective layer 33 covers the sidewall of the groove. This design is compatible with monochrome displays. The width K of the frame 301 is approximately 1 mm. On the side where the bonding area BOD is not provided, the distance K1 between the outer side of the frame 301 and the cutting line 501 is approximately 0.2 mm, and the distance K2 between the inner side of the frame 301 and the second protective layer 33 is approximately 0.2 mm.

[0182] Reference Figure 15 As shown, a first alignment film 91 is provided on the side of the array substrate 100 near the color filter substrate 200, and a second alignment film 92 is provided on the side of the color filter substrate 200 near the array substrate 100.

[0183] In this example embodiment, the color filter substrate 200 may include a second substrate 201, a light-transmitting portion 202, and a light-shielding portion 203. The light-transmitting portion 202 is disposed on the side of the second substrate 201 near the array substrate 100, and the light-transmitting portion 202 is disposed opposite to the pixel area. The light-shielding portion 203 is disposed on the side of the second substrate 201 near the array substrate 100, and the gap between the light-shielding portion 203 and the pixel area is disposed opposite to each other. The orthographic projection of the light-shielding portion 203 on the second substrate 201 is located inside the second substrate, that is, the edge of the light-shielding portion 203 is not flush with the edge of the second substrate 201, but is recessed relative to the edge of the second substrate 201.

[0184] Specifically, refer to Figure 12 As shown, on a cross section perpendicular to the second direction Y, i.e., on a cross section perpendicular to the data line 271; the width e of the light-shielding part 203 is approximately 11 micrometers, the width a of the data line 271 is approximately 4 micrometers, the gap d between two adjacent reflective parts 53 is approximately 6 micrometers, the overlap width f / g between the light-shielding part 203 and the reflective part 53 is approximately 2.5 micrometers, the distance b / c between the side of the data line 271 near the reflective part 53 and the side of the reflective part 53 near the data line 271 is approximately 1 micrometer, and the distance h / i between the side of the data line 271 near the second electrode 242 and the side of the second electrode 242 near the data line 271 is approximately 5.5 micrometers. In some other exemplary embodiments of this disclosure, the width a of the data line 271 is approximately 3.5 micrometers, the distance b / c between the side of the data line 271 near the reflector 53 and the side of the reflector 53 near the data line 271 is approximately 0.75 micrometers, and the distance h / i between the side of the data line 271 near the second electrode 242 and the side of the second electrode 242 near the data line 271 is approximately 7 micrometers.

[0185] Specifically, refer to Figure 13 As shown, in a cross-section perpendicular to the first direction X, i.e., a cross-section perpendicular to the gate line 241; the width e of the light-shielding portion 203 is approximately 13 micrometers, the width a of the gate line 241 is approximately 21.2 micrometers, the gap d between two adjacent reflective portions 53 is approximately 6 micrometers, the overlap width f / g between the light-shielding portion 203 and the reflective portion 53 is approximately 3.5 micrometers, and the distance b between the gate line 241 and the reflective portion 53 of the adjacent pixel area is approximately 10.5 micrometers. In some other exemplary embodiments of this disclosure, the width a of the gate line 241 is approximately 22.2 micrometers, 3.5 micrometers, etc., and the distance b between the gate line 241 and the reflective portion 53 of the adjacent pixel area is approximately 0.75 micrometers, etc.

[0186] Based on the same inventive concept, the present disclosure provides a display device that may include the display panel described in any of the above-mentioned embodiments. The specific structure of the display panel has been described in detail above, and therefore will not be repeated here.

[0187] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated here.

[0188] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts. Taking the monitor as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0189] Compared with the prior art, the beneficial effects of the display device provided by the example embodiments of the present invention are the same as the beneficial effects of the array substrate 100 provided by the example embodiments described above, and will not be repeated here.

[0190] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, include: First substrate; A switching layer assembly is disposed on one side of the first substrate. The switching layer assembly includes multiple switching units and multiple first light-shielding layers. The multiple first light-shielding layers are spaced apart, and the first light-shielding layers are disposed in the same layer and made of the same material as one of the switching units. An insulating layer assembly is disposed on the side of the switching layer assembly facing away from the first substrate. The side of the insulating layer assembly facing away from the first substrate has a plurality of first protrusions. A first connecting portion is connected between adjacent first protrusions. The height of the first protrusions in a third direction is higher than the height of the first connecting portion in the third direction. The orthographic projection of the first protrusions and the first connecting portion on the first substrate is located within the orthographic projection of the first light-shielding layer on the first substrate. The third direction is perpendicular to the side of the first substrate close to the switching layer assembly. A first via is disposed on the insulating layer assembly. A reflective layer is disposed on the side of the insulating layer group away from the first substrate. The side of the reflective layer away from the first substrate has a plurality of second protrusions. The orthographic projection of the first protrusion on the first substrate is located within the orthographic projection of the second protrusion on the first substrate. The reflective layer includes a plurality of reflective portions. The orthographic projection of the first light-shielding layer on the first substrate is located within the orthographic projection of the reflective portion on the first substrate. A first electrode layer is disposed between the insulating layer group and the reflective layer. The first electrode layer includes a plurality of first electrodes, and the first electrodes are connected to the first light-shielding layer through the first via.

2. The array substrate according to claim 1, wherein, The area of ​​the first light-shielding layer projected onto the first substrate accounts for 80% to 100% of the area of ​​the reflective portion projected onto the first substrate.

3. The array substrate according to claim 1, wherein, The first light-shielding layer continuously covers the orthographic projection of at least two of the first protrusions and the first connecting portion therebetween onto the first substrate.

4. The array substrate according to claim 1, wherein, The area of ​​the first protrusion projected onto the first substrate is more than 80% of the area of ​​the first light-shielding layer projected onto the first substrate.

5. The array substrate according to any one of claims 1 to 4, wherein, The switching layer group includes: The source and drain layers are provided with the same material as the first light-shielding layer.

6. The array substrate according to claim 5, wherein, The switch layer group also includes: A gate layer is disposed on one side of the first substrate. A gate insulating layer is disposed on the side of the gate layer away from the first substrate. An active layer is disposed on the side of the gate insulating layer away from the first substrate. The source and drain layers are disposed on the side of the active layer away from the first substrate.

7. The array substrate according to claim 6, wherein, The gate layer includes: Multiple gate lines extend along a first direction, which is parallel to the side of the first substrate near the switch layer group. Multiple sub-second electrodes are arranged in an array, and the sub-second electrodes are configured in a frame shape; Multiple connecting portions are provided, which connect between two adjacent sub-second electrodes arranged along the first direction.

8. The array substrate according to claim 7, wherein, The orthographic projections of the plurality of second protrusions on the first substrate overlap with the orthographic projections of the gate lines on the first substrate.

9. The array substrate according to claim 7, wherein, The active layer includes: The channel portion is located on the side of the gate line away from the first substrate. The first filling portion is spaced apart from the channel portion and is located on the side of the connecting portion away from the first substrate, and covers at least a portion of the sidewall of the connecting portion; The second filling portion is spaced apart from the channel portion and is located on the side of the gate line away from the first substrate, and covers at least a portion of the sidewall of the gate line.

10. The array substrate according to claim 9, wherein, The source / drain layer includes: A data line extends along a second direction, which intersects with the first direction, and a first portion of the data line is located on the side of the first filling portion away from the connecting portion, and a second portion of the data line is located on the side of a portion of the second filling portion away from the gate line; A first light-shielding layer is disposed on one side of the data line in a first direction, and the orthographic projection of the first light-shielding layer on the first substrate is located within the orthographic projection of the sub-second electrode on the first substrate. The source, one end of which is connected to the data line; The drain electrode has one end connected to the first light-shielding layer; The second electrode connection portion is connected between two adjacent sub-second electrodes in the second direction, and a portion of the second electrode connection portion is located on the side of the other portion of the second filling portion away from the grid line.

11. The array substrate according to claim 10, wherein, The source and drain layers further include: A maintenance block is connected to the side of the first light-shielding layer near the gate line, and the orthographic projection of the maintenance block on the first substrate overlaps with the orthographic projection of the gate line on the first substrate.

12. The array substrate according to claim 11, wherein, The orthographic projection of the first electrode on the first substrate overlaps with the orthographic projection of the gate line on the first substrate; the orthographic projection of the reflective portion on the first substrate overlaps with the orthographic projection of the gate line on the first substrate.

13. The array substrate according to claim 11, wherein, The orthographic projection of the first electrode on the first substrate is located within the orthographic projection of the reflective portion on the first substrate.

14. The array substrate according to claim 13, wherein, The shape of the orthographic projection of the first electrode on the first substrate is the same as the shape of the orthographic projection of the reflective portion on the first substrate.

15. The array substrate according to claim 11, wherein, The insulating layer assembly includes: A first protective layer is disposed on the side of the source / drain layer away from the first substrate, and a first sub-via is provided on the first protective layer; An insulating layer is disposed on the side of the first protective layer away from the first substrate, and a second sub-via is provided on the insulating layer; A second protective layer is disposed on the side of the insulating layer away from the first substrate, and a portion of the second protective layer covers the hole wall of the second sub-via. A third sub-via is disposed on the second protective layer, and the first sub-via, the second sub-via, and the third sub-via communicate to form the first via. Wherein, the orthographic projection of the first sub-via on the first substrate is located within the orthographic projection of the second sub-via on the first substrate, and the orthographic projection of the third sub-via on the first substrate is located within the orthographic projection of the second sub-via on the first substrate.

16. The array substrate according to claim 15, wherein, The array substrate has a bonding area disposed on one side of the display area, and the array substrate further includes: Multiple first bonding pins are disposed in the bonding region, and the first bonding pins are disposed in the same layer and material as the gate layer or the source-drain layer; Multiple second bonding pins are disposed in the bonding area and are located on the side of the first bonding pin away from the first substrate. The second bonding pins are disposed in the same layer and material as the first electrode. The orthographic projection of the second bonding pin on the first substrate is located within the orthographic projection of the first bonding pin on the first substrate. A gap is provided between the edge of the orthographic projection of the second bonding pin on the first substrate away from the display area and the edge of the orthographic projection of the first bonding pin on the first substrate away from the display area.

17. The array substrate according to claim 16, wherein, A groove is provided in the bonding area, penetrating the first protective layer and the second protective layer, and the groove is located on the side of the first bonding pin away from the display area.

18. The array substrate according to claim 11, wherein, The side of the insulating layer group facing away from the first substrate includes a first plane, and the orthographic projection of the first plane on the first substrate overlaps with the orthographic projection of the channel portion on the first substrate.

19. The array substrate according to claim 18, wherein, The array substrate further includes: A spacer is disposed on the side of the first plane away from the first substrate.

20. The array substrate according to claim 18, wherein, The side of the insulating layer group facing away from the first substrate includes a second plane, the orthographic projection of the second plane on the first substrate being located within the orthographic projection of the space between two adjacent first electrodes on the first substrate.

21. The array substrate according to claim 5, wherein, The switch layer group also includes: The gate layer and a plurality of second light-shielding layers are arranged at intervals. The second light-shielding layers are disposed in the same layer and made of the same material as the gate layer. The orthogonal projection of the second light-shielding layer on the first substrate is located within the orthogonal projection of the reflective portion on the first substrate.

22. The array substrate according to any one of claims 1 to 4, wherein, The switching layer group includes: A gate layer is disposed on one side of the first substrate, and the first light-shielding layer is disposed in the same layer and made of the same material as the gate layer.

23. The array substrate according to claim 22, wherein, The gate layer includes: Multiple gate lines extend along a first direction, which is parallel to the side of the first substrate near the switch layer group. Multiple sub-second electrodes are arranged in an array, and the sub-second electrodes are configured in a frame shape, with the first light-shielding layer disposed within the frame shape.

24. The array substrate according to claim 23, wherein, The first light-shielding layer is integrated with the second electrode; or a second gap is provided between the first light-shielding layer and the second electrode.

25. The array substrate according to claim 1, wherein, The height of the sidewall of the second protrusion in the third direction decreases as the distance from the middle of the second protrusion to the first surface increases, and the first surface is parallel to the side of the first substrate that is close to the switch layer group.

26. The array substrate according to claim 25, wherein, The angle between the sidewall of the second protrusion and the first surface is greater than or equal to 6° and less than or equal to 13°.

27. The array substrate according to claim 25, wherein, The sidewall of the second protrusion includes a first part, a second part, and a third part that are smoothly connected in sequence. The first part is closer to the first substrate than the third part. The first part and the third part are set as arc surfaces, and the second part is set as a slope surface.

28. The array substrate according to claim 27, wherein, The first portions of the multiple second protrusions are smoothly connected.

29. A display panel, wherein, include: The array substrate is the array substrate according to any one of claims 1 to 28; A color filter substrate is disposed on the side of the array substrate near the reflective layer; A frame is disposed between the array substrate and the color filter substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate, and is located within the frame.

30. The display panel according to claim 29, wherein, The orthographic projection of the frame on the first substrate does not overlap with the orthographic projection of the insulating layer in the insulating layer group on the first substrate.

31. A display device, wherein, include: The display panel according to any one of claims 29 to 30.

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