Driving method and display apparatus

Abstract

The application relates to a driving method, relating to the technical field of display. The driving method is used for driving a pixel array, comprising operations (S210) to (S220): in operation (S210), the timing of a gate driving signal (Gate) is set according to the effective time difference between a data signal (Vdata) and an effective signal of the gate driving signal (Gate); in operation (S220), the pixel array is driven by the gate driving signal (Gate). A display device (600) is also provided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a driving method and display device. BACKGROUND

[0002] A display device (e.g., an OLED display) can include a display panel, a gate driver, a data driver, and a timing controller. The display panel includes a pixel array composed of a plurality of pixels, a gate driving signal generated by the gate driver is provided to a pixel row, and the data driver provides a data voltage to the pixel.

[0003] However, a change in the data signal can cause a fluctuation in the power supply voltage, thereby causing a crosstalk phenomenon in the display panel when displaying a picture, and affecting the display effect of the display panel. SUMMARY

[0004] The present disclosure provides a driving method and display device.

[0005] According to a first aspect, the present disclosure provides a driving method, setting a timing of a gate driving signal according to an effective time difference between a data signal and an effective signal of the gate driving signal; and driving a pixel array by the gate driving signal.

[0006] For example, the effective time difference includes a first time difference between an application time of the data signal and a start time of an effective level of the gate driving signal; and setting the timing of the gate driving signal according to the effective time difference includes: setting the timing of the gate driving signal such that the first time difference between the application time of the data signal and the start time of the effective level of the gate driving signal is greater than 0.5 times of the effective time difference and less than the effective time difference, while keeping the effective duration of the data signal and the effective level of the gate driving signal unchanged.

[0007] For example, a ratio of the effective time difference to a scanning period of the gate driving signal is in a range of 35% to 45%.

[0008] For example, the ratio of the effective time difference to the scanning period of the gate driving signal is 39%.

[0009] For example, a ratio of the first time difference to the scanning period of the gate driving signal is in a range of 22% to 37%.

[0010] For example, the scanning period of the gate driving signal is 8.7μs, and the first time difference is in a range of 1.9μs to 3.2μs.

[0011] For example, the first time difference is greater than a jump time of the power supply voltage.

[0012] For example, the driving method further comprises setting a duration of the latch-in input period according to the effective time difference, so that a time difference between an ending moment of the latch-in input period and a starting moment of the effective level of the gate driving signal in the next scan period is greater than 0.5 times of the effective time difference and less than the effective time difference.

[0013] For example, the method according to the embodiments of the present disclosure further comprises: a first driving mode, the first time difference is A1; and a second driving mode, the first time difference is A2, A1 is greater than A2.

[0014] According to a second aspect, the present disclosure provides a display device, comprising: a pixel array; a timing controller; a source driver configured to generate a data signal under the control of the timing controller; and a gate driver configured to generate a gate driving signal under the control of the timing controller, wherein the timing controller is configured to set a timing of the gate driving signal according to an effective time difference between an effective signal of the data signal and the gate driving signal, so as to drive the pixel array by the gate driving signal.

[0015] For example, the effective time difference comprises a first time difference between an application moment of the data signal and a starting moment of the effective level of the gate driving signal; and the timing controller is further configured to set the timing of the gate driving signal so that the first time difference between the application moment of the data signal and the starting moment of the effective level of the gate driving signal is greater than 0.5 times of the effective time difference and less than the effective time difference, while keeping the effective level duration of the data signal and the gate driving signal unchanged.

[0016] For example, a ratio of the effective time difference to a scan period of the gate driving signal ranges from 35% to 45%.

[0017] For example, the ratio of the effective time difference to the scan period of the gate driving signal is 39%.

[0018] For example, a ratio of the first time difference to the scan period of the gate driving signal ranges from 22% to 37%.

[0019] For example, the scan period of the gate driving signal is 8.7 μs, and the first time difference ranges from 1.9 μs to 3.2 μs.

[0020] For example, the first time difference is greater than a transition time of a power supply voltage.

[0021] For example, the timing controller is further configured to set a duration of the latch-in input period according to the effective time difference, so that a time difference between an ending moment of the latch-in input period and a starting moment of the effective level of the gate driving signal in the next scan period is greater than 0.5 times of the effective time difference and less than the effective time difference.

[0022] For example, the display device of the embodiments of the present disclosure further comprises an external power supply arranged between the voltage source of the source driver and the pixel array.

[0023] For example, the display device of the embodiments of the present disclosure further comprises a resistor arranged between the voltage source of the source driver and the pixel array.

[0024] For example, the timing controller is further configured to set: a first driving mode, the first time difference being A1; and a second driving mode, the first time difference being A2, the A1 being greater than the A2. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1A is a signal timing diagram for driving a display panel according to an example;

[0026] Figure 1B is an abnormal display screen of a display device under the signal timing diagram driving; Figure 1A is a schematic diagram of an abnormal display screen under the signal timing diagram driving;

[0027] Figure 2 is a flow chart of a driving method according to an embodiment of the present disclosure;

[0028] Figure 3 is a signal timing diagram according to an embodiment of the present disclosure;

[0029] Figure 4 is a signal timing diagram according to another embodiment of the present disclosure;

[0030] Figure 5A is a structural schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0031] Figure 5B is a signal timing diagram of a pixel circuit in Figure 5A

[0032] Figure 6 is a block diagram of a display device according to an embodiment of the present disclosure; and

[0033] Figure 7 is a block diagram of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] ​In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be used in conjunction with the accompanying drawings of the embodiments of the present disclosure to clearly and completely describe the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are used only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it is possible to cause confusion to the understanding of the present disclosure, the conventional structure or configuration will be omitted. It should be noted that the shape and size of the components in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by a person of ordinary skill in the art. The "first", "second" and similar words used in the embodiments of the present disclosure do not represent any order, number or importance, but are only used to distinguish different components.

[0036] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" can mean that two components are directly connected, or that two components are connected via one or more other components. In addition, the two components can be connected or coupled by wired or wireless means.

[0037] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vdata can represent both a data signal and a level of the data signal. Similarly, the symbol Gate can represent both a gate drive signal and a level of the gate drive signal, the symbol VINT can represent both a predetermined initial voltage terminal and a voltage of the initial signal, and the symbol ELVDD can represent both a power supply and a power supply voltage provided by the power supply. The following embodiments are the same as this, and will not be described again.

[0038] Figure 1A is a signal timing diagram for driving a display panel according to an example. Figure 1B is a schematic diagram of an abnormal display screen of a display device under the driving of the signal timing diagram. Figure 1A is a schematic diagram of an abnormal display screen of a display device under the driving of the signal timing diagram.

[0039] As shown in FIG. 1, a display panel 100 includes a plurality of pixels 110, a plurality of gate lines 120, and a plurality of data lines 130. Figure 1AAs shown, when the data signal Vdata is applied, the change of the reference voltage AVDD of the data signal Vdata will cause the jump of the power voltage VDD. The time period a can be a time period in which the start time of the active level of the gate driving signal Gate is delayed from the application time of the data signal Vdata, and the time period b can be a time period in which the end time of the active level of the gate driving signal Gate is advanced from the end application time of the data signal Vdata. If the noise caused by the jump of the power voltage VDD is not eliminated at the start time of the active level of the gate driving signal Gate, that is, in the time period a, the crosstalk phenomenon will appear on the display panel, affecting the display effect of the display panel.

[0040] As shown in FIG. 1, a display panel includes pixel units 110, 120 and 130. In the display process, the gate driving signal Gate scans the pixel units row by row. The applied data signal Vdata makes the pixel unit 110 display a black image, and makes the pixel unit 120 and the pixel unit 130 display white images. Due to the noise caused by the jump of the power voltage VDD, the pixel unit 120 and the pixel unit 130 are affected by the crosstalk of the pixel unit 110, and the pixel unit 120 and the pixel unit 130 actually display gray images, thereby affecting the display effect of the display panel. Figure 1B As shown in FIG. 1, a display panel includes pixel units 110, 120 and 130. In the display process, the gate driving signal Gate scans the pixel units row by row. The applied data signal Vdata makes the pixel unit 110 display a black image, and makes the pixel unit 120 and the pixel unit 130 display white images. Due to the noise caused by the jump of the power voltage VDD, the pixel unit 120 and the pixel unit 130 are affected by the crosstalk of the pixel unit 110, and the pixel unit 120 and the pixel unit 130 actually display gray images, thereby affecting the display effect of the display panel.

[0041] The present disclosure provides a driving method for driving a pixel array, including setting a timing of a gate driving signal according to an active time difference between an active signal of a data signal and the gate driving signal; and driving the pixel array by the gate driving signal.

[0042] Figure 2 FIG. 2 is a flowchart of the driving method according to an embodiment of the present disclosure.

[0043] As shown in FIG. 1, a display panel includes pixel units 110, 120 and 130. In the display process, the gate driving signal Gate scans the pixel units row by row. The applied data signal Vdata makes the pixel unit 110 display a black image, and makes the pixel unit 120 and the pixel unit 130 display white images. Due to the noise caused by the jump of the power voltage VDD, the pixel unit 120 and the pixel unit 130 are affected by the crosstalk of the pixel unit 110, and the pixel unit 120 and the pixel unit 130 actually display gray images, thereby affecting the display effect of the display panel. Figure 2 As shown in FIG. 2, the driving method can include operation S210 to operation S220.

[0044] In operation S210, the timing of the gate driving signal is set according to the active time difference between the active signal of the data signal and the gate driving signal.

[0045] For example, the data signal is longer than the duration of the active level of the gate driving signal, which can avoid the driving transistor being turned on without writing the data signal. In one scanning period, the application time of the data signal is before the start time of the active level of the gate driving signal, and the end application time of the data signal is after the end time of the active level of the gate driving signal. The ratio of the active time difference to the scanning period of the gate driving signal is 35-45%. See Figure 1AThe effective time difference between the data signal and the active signal of the gate drive signal includes time period a and time period b. The scanning period of the gate drive signal is 1H, for example: the scanning period of the gate drive signal is the time required to scan one row of the pixel array.

[0046] For example, for any pixel array, the effective time difference can be fixed. According to the effective time difference, the timing of the gate drive signal is set, which can completely eliminate the noise generated due to the jump of the power supply voltage VDD before the starting time of the active level of the gate drive signal, thereby alleviating the crosstalk phenomenon on the display panel.

[0047] In operation 220, the pixel array is driven by the gate drive signal.

[0048] For example, the display panel includes a pixel array, and by setting the timing of the gate drive signal according to the disclosed embodiments, the pixel array is driven by the gate drive signal, which can alleviate the crosstalk phenomenon on the display panel.

[0049] According to the embodiments of the present disclosure, the noise generated due to the jump of the power supply voltage VDD can be completely eliminated before the starting time of the active level of the gate drive signal, thereby alleviating the crosstalk phenomenon on the display panel.

[0050] The present disclosure provides an embodiment of setting the timing of the gate drive signal. The effective time difference includes a first time difference between the application time of the data signal and the starting time of the active level of the gate drive signal.

[0051] Operation S210, according to the effective time difference between the data signal and the active signal of the gate drive signal, the step of setting the timing of the gate drive signal includes setting the timing of the gate drive signal, so that in the case of keeping the active duration of the data signal and the gate drive signal unchanged, the first time difference is greater than 0.5 times of the effective time difference and less than the effective time difference. The range of the ratio of the first time difference to the scanning period of the gate drive signal is 22-37%.

[0052] Figure 3 is a signal timing diagram according to an embodiment of the present disclosure. As Figure 3 shown, the low level of the gate drive signal is the active level. Figure 3 In the example of, Gate(N) represents the gate signal of the Nth row of pixels, and Gate(N+1) represents the gate signal of the N+1th row of pixels, where N is an integer greater than or equal to 1. The first time difference is time period a, and the first time difference is greater than 0.5 times of the effective time difference and less than the effective time difference. The effective time difference also includes a second time difference between the ending time of the active level of the gate drive signal and the ending application time of the data signal. The second time difference is time period b. The second time difference b is less than 0.5 times of the effective time difference and greater than 0.

[0053] For example, for a common timing of the gate driving signal, the first time difference and the second time difference can both equal to 0.5 times of the effective time difference. For example, for a default timing of the gate driving signal, when the duration of the gate driving signal active level and the effective time difference of the data signal is 3.4 μs, the first time difference and the second time difference are both 1.7 μs. At this time, the default value of the first time difference and the second time difference can be considered as 0.5 times of the effective time difference, for example, 1.7 μs. In the case of keeping the duration of the gate driving signal active level unchanged, the first time difference can be increased by delaying the starting time of the gate driving signal active level, so that the first time difference is greater than 0.5 times of the effective time difference and less than the effective time difference.

[0054] The first time can be greater than the duration of the power voltage jump. In the case that the first time difference is large enough, the noise generated by the power voltage VDD jump can be completely eliminated before the starting time of the gate driving signal active level, thereby alleviating the crosstalk phenomenon on the display panel.

[0055] Optionally, the first time difference is 1.2 times-2.4 times of the power voltage VDD jump time, so that the noise generated by the power voltage VDD jump can be better guaranteed to be completely eliminated before the starting time of the gate driving signal active level. For example, the first time difference is 2.4-3.2 μs, which is greater than the duration of the power voltage jump 2.0 μs.

[0056] Since the duration of the data signal and the gate driving signal active level is unchanged, the effective time difference (period a and period b) can be considered as unchanged. In the case that the first time difference (period a) is increased relative to the default value (the first time difference is 0.5 times of the effective time difference), the second time difference (period b) will be correspondingly reduced. In addition, the first time difference also needs to be less than the effective time difference. If the first time difference is increased without limit, the second time difference will not exist, that is, the end time of the data signal is before the end time of the gate driving signal active level, thereby causing that there is no data signal to be written in the case that the driving transistor is turned on.

[0057] The present disclosure provides a driving method of another embodiment. The driving method further includes, on the basis of operations S210 to S220, setting the duration of the latch input period according to the effective time difference, so that the time difference between the end time of the latch input period and the starting time of the gate driving signal active level of the next scan period is greater than 0.5 times of the effective time difference and less than the effective time difference.

[0058] The interval between two adjacent data signals is the latch input period. Changing the latch input period will result in a change in the frequency of the data signal, which will change the time at which the data signal is applied in the next scan cycle. For example, reducing the latch input period will result in the time at which the data signal is applied in the next scan cycle being advanced. At the same time, changing the latch input period will also result in a change in the data signal reference voltage AVDD, which will in turn change the time at which the power voltage signal VDD jumps.

[0059] Figure 4 is a signal timing diagram according to another embodiment of the present disclosure. Figure 4 In the example of FIG. 6, Gate(N) represents the gate signal of the Nth row of pixels, Gate(N+1) represents the gate signal of the N+1th row of pixels, and Gate(N+2) represents the gate signal of the N+2th row of pixels. As shown in FIG. 6, the duration of the first latch input period of the normal timing of the data signal is Latch input 1. For example, the duration of the first latch input period of the normal timing of the data signal is Latch input 1. Figure 4 Figure 4 The signal timing diagram shown in FIG. 6 can be obtained by first setting the timing of the gate drive signal and then setting the duration of the latch input period, while keeping the duration of the active level of the gate drive signal unchanged. First, the timing of the gate drive signal is set such that the first time difference (period a) is greater than 0.5 times the active time difference and less than the active time difference. Then, the duration of the second latch input period is set to Latch input 2, which is shorter than the duration of the first latch input period Latch input 1, so that the first time difference (period a') between the start time of the application of the data signal to the N+1th row of pixels and the start time of the active level of the next row of gate drive signals Gate(N+1) is greater than the first time difference (period a) between the start time of the application of the data signal to the Nth row of pixels and the start time of the active level of the Nth row of gate drive signals Gate(N). The second time difference a' is also greater than 0.5 times the active time difference and less than the active time difference.

[0060] It should be noted that, Figure 4 only to show that changing the duration of the latch input period Latch input will result in a change in the first time difference. Alternatively, in actual driving applications, the duration of the latch input period remains unchanged after the duration of the latch input period is set. For example, in the embodiment of the present disclosure, the duration of the latch input period in the timing of the data signal is set to Latch input 2.

[0061] ​For example, the driving method can also be to set the duration of the latch input period without changing the default timing of the gate drive signal, so that the time difference between the end of the latch input period and the start of the effective level of the gate drive signal in the next scan cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

[0062] For example, in the above-described normal timing of the data signal, the duration of the latch input period can be 1.5 μs. While keeping the duration of the data signal application and the normal timing of the gate drive signal unchanged, the duration of the latch input period can be reduced to increase the first time difference, making the first time difference greater than 0.5 times the effective time difference but less than the effective time difference. The duration of the latch input period can be set from 1.2 μs to 0.3 μs.

[0063] Optionally, the duration of the latched input period can be set to 0.4 μs.

[0064] Optionally, the overlap length between the data signal application duration and the gate drive signal activation duration can be kept fixed. This ensures that when the gate drive signal is output to each row, the effective data signal duration is substantially consistent.

[0065] Figure 5A This is a schematic diagram of the structure of a pixel circuit according to an embodiment of the present disclosure. Figure 5B for Figure 5A Signal timing diagram of the mid-pixel circuit.

[0066] Figure 5A and 5B As shown, in Figure 5A In the example, transistors T1 to T7 can be P-type transistors. During the initialization phase, the low level of the reset signal Reste1 is the active level.

[0067] Under the control of the reset signal Reste1, transistor T1 is turned on. The initialization signal VINT initializes the gate of the driving transistor T3, thereby initializing the gate voltage of the driving transistor T3 to VINT, and simultaneously charging the storage capacitor CST.

[0068] In the data writing stage, the low level of the gate drive signal Gate and the low level of the reset signal Reste2 are active levels. Under the control of the gate drive signal Gate, the transistors T2 and T4 are turned on. The driving transistor T3 is turned on under the driving of the voltage signal stored in the storage capacitor CST. The data signal Vdata is written to the node N1 along the path from the data signal terminal to the node N1 via the transistors T4, T3 and T2. Under the control of the reset signal Reste2, the transistor T7 is turned on, and the initialization signal VINT is written to the anode of the light emitting element EL along the initialization path from the predetermined initialization voltage terminal to the light emitting element EL, so as to initialize the anode voltage of the light emitting element EL to VINT.

[0069] It can be understood that the voltage difference (VINT-ELVSS) between the initialization signal terminal VINT and the second power terminal ELVSS should be less than the threshold voltage Voled of the light emitting element EL. ELVSS is the voltage of the second terminal of the light emitting element OLED, and Voled is the light emitting threshold voltage of the light emitting element EL. In this way, it can be ensured that the light emitting element EL does not emit light in the data writing stage.

[0070] In the light emitting stage, the low level of the light emitting control signal EM is an active level. Under the control of the light emitting control signal EM, the transistors T5 and T6 are turned on. The driving transistor T3 is turned on under the driving of the voltage signal stored in the storage capacitor CST. The transistors T5 and T6 are turned on, and the driving current is applied to the light emitting element EL along the light emitting path from the power supply to the light emitting element EL via the transistors T5, the driving transistor T3 and the transistors T6, so as to make the light emitting element EL emit light.

[0071] Of course, it can also be applicable to other pixel circuits. For example: the transistors T1-T2 are N-type transistors, and T3-T7 can be P-type transistors.

[0072] For example, the display panel comprising the pixel circuit as shown in Figure 5A The display panel comprising the pixel circuit as shown in the drawings is subjected to crosstalk test. In an example, the display scanning frame frequency is 60 Hz, and the resolution of the display panel is 1915 rows, so that the scanning period 1H of the gate drive signal Gate is 8.7 μs, the effective time difference a+b is 3.4 μs, and the default values of the first time difference a and the second time difference b are 1.7 μs. At this time, the ratio of the effective time difference to the scanning period of the gate drive signal is 39%.

[0073] Optionally, the scanning period H of the gate driving signal Gate can be determined by the scanning frame frequency and the resolution row number of the display panel. For example, the scanning frame frequency is 60 Hz, and the resolution row number of the display panel is 1915. It should be noted that the resolution row number of the display panel can include real rows and virtual rows. For example, the real rows are 1888, and the virtual rows are 27. The gate driving signal scans the virtual rows first and then scans the real rows. The scanning period 1H of the gate driving signal Gate is 1 / F* resolution row number = 1 / (60*1915) = 8.7 μs, where F = driving frequency * resolution row number.

[0074] Of course, other driving frequencies or resolutions are applicable in some embodiments. Optionally, the display panel can also have other resolutions, such as 10-30 Hz, or 90 Hz-120 Hz, and can also have other resolutions, such as a resolution row number of 2360.

[0075] Optionally, the values of the first time difference a and the second time difference b are changed by setting the timing of the gate driving signal and / or setting the duration of the latch input period. For example, the first time difference a is about 22-37% of 1 / F, where F = driving frequency * resolution row number. The present disclosure changes the ratio of the first time difference a to the second time difference b by setting the timing of the gate driving signal and / or setting the duration of the latch input period. In order to test the crosstalk phenomenon under different ratios a / b, a display panel including the pixel circuit shown in FIG. 1 is tested for crosstalk using the driving method according to the present disclosure. Figure 5A The display panel including the pixel circuit shown in FIG. 1 is tested for crosstalk using the driving method according to the present disclosure. The test results are shown in Table 1. The ratio a / b of the first time difference to the second time difference ranges from 0.0625 to 16 during the test. The lower the crosstalk level, the more serious the crosstalk phenomenon.

[0076] Table 1

[0077] a 3.2 3.0 2.5 2.0 1.7 1.4 0.9 0.4 0.2 b 0.2 0.4 0.9 1.4 1.7 2.0 2.5 3.0 3.2 Crosstalk level 4 3 2 4 0 -1 -2 -3 -4

[0078] As shown in Table 1, starting from the default value a = b = 1.7 μs, as the ratio a / b increases, the crosstalk phenomenon gradually decreases. When a / b = 16 and a = 3.2 μs, the crosstalk level reaches the highest. As the ratio a / b decreases, the crosstalk level decreases, and the crosstalk phenomenon gradually becomes more serious. When a / b = 0.0625 and a = 0.2 μs, the crosstalk level reaches the highest.

[0079] When the scanning period H of the gate driving signal is 8.7 μs, in order to ensure that the crosstalk phenomenon is alleviated, the ratio a / b of the first time difference to the second time difference can range from 1.27 to 16, and the range of the first time difference can be set to 1.9 μs-3.2 μs.

[0080] For example, when the display panel includes the pixel circuit shown in FIG. 1, the scanning period H of the gate driving signal Gate is 8.7 μs, the resolution row number of the display panel is 1915, and the driving frequency is 60 Hz, the first time difference a and the second time difference b can be set as follows. Figure 5AThe display panel of the pixel circuit shown is selected with any four test points in a display area, and the crosstalk test values of the test points are tested. The crosstalk test values of each test point in the horizontal direction and the vertical direction are tested by setting the timing of the gate drive signal and the duration of the latch input period. For the same display panel, under the same test conditions, in one comparison scheme, the crosstalk test values of the four test points are shown in Table 2, and the crosstalk test values of the four test points using the technical solution according to the embodiment of the present disclosure are shown in Table 3. In the above comparison scheme, the duration of the latch input period is 1.5 μs, and the ratio a / b of the first time difference to the second time difference ranges from 1, for example, the first time difference and the second time difference can be set to the default value 1.7 μs. According to the technical solution of the embodiment of the present disclosure, the duration of the latch input period is 0.4 μs, the ratio a / b of the first time difference to the second time difference ranges from 1.27 to 16, and the ratio of the first time difference to the duration of the latch input period ranges from 4.75 to 8, for example, the first time difference is 3.2, the second time difference is 0.2, and the ratio of the first time difference to the duration of the latch input period is 8.

[0081] Table 2

[0082]

[0083] Table 3

[0084]

[0085] As shown in Table 2, using the above comparison scheme, the crosstalk test value of test point 2 in the horizontal direction H is 2.35%, indicating that test point 2 has a serious crosstalk phenomenon in the horizontal direction. As shown in Table 3, according to the technical solution of the embodiment of the present disclosure, the crosstalk test values of the four test points in the horizontal direction and the vertical direction are all less than 2.00%, indicating that almost all the test points according to the technical solution of the embodiment of the present disclosure do not have a crosstalk phenomenon. Among them, the crosstalk test value of test point 2 in the horizontal direction H is 0.95%, indicating that test point 2 almost does not have a crosstalk phenomenon in the horizontal direction. Thus, it can be verified that the method of setting the timing of the gate drive signal and the duration of the latch input period improves the crosstalk phenomenon, and the crosstalk phenomenon of the display panel is alleviated after increasing the ratio a / b of the first time difference to the second time difference.

[0086] The display panel is also tested and improved in various working modes. For example, the working modes include high frequency driving and low frequency driving. For example, in a first driving mode, the first time difference is A1, for example, A1=2.6μs-3μs; in a second driving mode, the first time difference is A2, A1=2.0μs-2.4μs, wherein the first time difference A1 is greater than A2. Optionally, the first driving mode is high frequency driving (for example: 60HZ-240HZ), and the second driving mode is low frequency driving (for example: 10HZ-50HZ); of course, the second driving mode can also be high frequency driving (for example: 60HZ-240HZ), and the first driving mode is low frequency driving (for example: 10HZ-50HZ). In an embodiment, in order to alleviate the crosstalk phenomenon of the display panel, the first time difference in the high frequency driving mode (120HZ) is less than the first time difference in the low frequency driving mode (30HZ).

[0087] According to the embodiments of the present disclosure, the timing of the gate drive signal and / or the duration of the latch input period are set so that the first time difference and the second time difference have a ratio greater than 1. In the case where the first time difference is greater than 0.5 times the effective time difference, the power supply voltage ELVDD jumps away from the effective level of the gate drive signal, and the noise generated by the jump of the power supply voltage ELVDD can be eliminated before the start time of the effective level of the gate drive signal. When the start time of the effective level of the gate drive signal Gate is reached, the jumping power supply voltage ELVDD has basically recovered to the normal power supply voltage ELVDD, avoiding noise interference from being written into the storage capacitor CST, and improving the crosstalk phenomenon.

[0088] In the embodiments of the present disclosure, the timing of the light emitting control signal EM can also be set according to the timing of the gate drive signal. Since the start time of the effective level of the gate drive signal is delayed relative to the start time of the effective level in the normal timing, the reset signal Reste1 can be set so that the start time of the effective level of the reset signal Reste1 is delayed by the same amplitude as the start time of the effective level of the gate drive signal, while keeping the duration of the effective level of the reset signal Reste1 unchanged. In this way, the duration of the effective level of the light emitting control signal in the previous scan period can be extended relative to the default duration of the effective level of the light emitting control signal by setting the timing of the light emitting control signal. By extending the duration of the effective level of the light emitting control signal, the average current density can be reduced, thereby prolonging the service life of the light emitting element EL.

[0089] Figure 6 is a block diagram of a display device according to an embodiment of the present disclosure. As shown in Figure 6 the display device 600 can include a pixel array 610, a timing controller 620, a source driver 630, and a gate driver 640.

[0090] The pixel array 610 includes a plurality of pixels. The plurality of pixels are located at the intersection regions of the plurality of scan lines S, the plurality of data lines DL, and the plurality of light emission control lines EM.

[0091] The source driver 630 is configured to generate the data signal under the control of the timing controller 620. The gate driver 640 is configured to generate the gate drive signal under the control of the timing controller 620.

[0092] The timing controller 620 is configured to set the timing of the gate drive signal according to the effective time difference between the data signal and the active signal of the gate drive signal, so as to drive the pixel array by the gate drive signal.

[0093] The timing controller 620, the source driver 630, and the gate driver 640 are configured to perform the driving method of the foregoing embodiments to drive the pixel array 610. The timing controller 620 is configured to perform the operation S210 described above, which will not be repeated here.

[0094] For example, the effective time difference includes a first time difference between the application time of the data signal and the start time of the active level of the gate drive signal. The timing controller 620 is further configured to set the timing of the gate drive signal such that, without changing the active duration of the data signal and the active level of the gate drive signal, the first time difference between the application time of the data signal and the start time of the active level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference.

[0095] For example, the ratio of the effective time difference to the scan period of the gate drive signal ranges from 35% to 45%.

[0096] For example, the ratio of the effective time difference to the scan period of the gate drive signal is 39%.

[0097] For example, the ratio of the first time difference to the scan period of the gate drive signal ranges from 22% to 37%.

[0098] For example, the scan period of the gate drive signal is 8.7μs, and the first time difference ranges from 1.9μs to 3.2μs.

[0099] For example, the first time difference is greater than the transition time of the power supply voltage, and the transition time of the power supply voltage is related to the reference voltage of the data signal.

[0100] For example, the timing controller 620 is further configured to set the duration of the latch input period according to the effective time difference, so that the time difference between the end time of the latch input period and the start time of the active level of the gate drive signal of the next scan period is less than the effective time difference.

[0101] For example, the first time difference is greater than the transition time of the power supply voltage, and the transition time of the power supply voltage is related to the reference voltage of the data signal.Figure 7 is a block diagram of a display device according to another embodiment of the disclosure.

[0102] The display device 700 can include a pixel array 710, a timing controller 720, a source driver 730, a gate driver 740, a power IC 750, and a GAM IC 760.

[0103] The pixel array 710, the timing controller 720, the source driver 730, and the gate driver 740 are respectively connected to the pixel array 710, the timing controller 720, the source driver 730, and the gate driver 740. Figure 6 The display device shown in FIG. 6 includes a pixel array 610, a timing controller 620, a source driver 630, and a gate driver 640, which have similar functions. For the sake of brevity, the disclosure will not repeat the description.

[0104] The power IC 750 is configured to input a reference voltage AVDD of a data signal to the GAM IC 760, and the GAM IC 760 is configured to perform gamma correction on the reference voltage AVDD of the data signal and input the corrected reference voltage AVDD of the data signal to the pixel array 610. The power IC 750 is further configured to input an initialization signal VINT to the pixel array 610.

[0105] In the embodiments of the disclosure, the display panel can be tested for water ripple phenomenon and crosstalk phenomenon by setting external devices, such as external filling power, voltage stabilizing capacitor, or filter resistor, at N-point, P-point, and Q-point as shown in FIG. 6. Figure 7 For example, in order to test the water ripple phenomenon and the crosstalk phenomenon of the display panel under different hardware conditions, the display panel including the pixel circuit shown in FIG. 6 is tested for water ripple phenomenon and crosstalk phenomenon. The hardware conditions for testing include setting relevant external devices at N-point, P-point, and Q-point in the path of the reference voltage of the input data signal as shown in FIG. 6, modifying the working mode of the power IC 750, and replacing the power IC 750 with a power IC 2.

[0106] Figure 5A For example, in order to test the water ripple phenomenon and the crosstalk phenomenon of the display panel under different hardware conditions, the display panel including the pixel circuit shown in FIG. 6 is tested for water ripple phenomenon and crosstalk phenomenon. The hardware conditions for testing include setting relevant external devices at N-point, P-point, and Q-point in the path of the reference voltage of the input data signal as shown in FIG. 6, modifying the working mode of the power IC 750, and replacing the power IC 750 with a power IC 2. Figure 7

[0107] Table 4

[0108]

[0109] ​​As shown in Table 4, when the duration of the latch input period is set to 1.5 μs, the display panel of the display device shown in Table 4 all have crosstalk phenomenon. When the duration of the latch input period is set to 0.4 μs, it can be considered that there is no crosstalk phenomenon. When the duration of the latch input period is set to 0.4 μs, by setting the external filling power at the N point or the P point, it can be considered that there is no water wave phenomenon, setting the filter resistance at the N point can also be considered that there is no water wave phenomenon, using the conventional working mode instead of the energy saving mode of the Power IC 750 can be considered that there is no water wave phenomenon, and when the Power IC 750 is replaced by other power supply chips, it can also be considered that there is no water wave phenomenon.

[0110] According to the embodiments of the present disclosure, by setting the external filling power or the filter resistance between the power supply chip Power IC 750 and the gamma correction chip GAM IC 760, the reference voltage of the data signal can be optimized to improve the water wave problem. The external filling power or the filter resistance can also be set between the power supply chip Power IC 750 and the pixel array 710 to optimize the reference voltage of the data signal, thereby alleviating the water wave problem.

[0111] The flowcharts and block diagrams in the drawings illustrate the possible architectural, functional, and operational aspects of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a segment, or a portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in a different order than that shown in the figures. For example, two blocks shown in succession can actually be executed substantially concurrently, or they can sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the flowcharts or block diagrams, and combinations of blocks in the flowcharts or block diagrams, can be implemented by dedicated hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0112] Those skilled in the art can understand that the features described in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations, even if such combinations are not explicitly described in the present disclosure. In particular, the features described in various embodiments and / or claims of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0113] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A driving method for driving a pixel array, comprising: The timing of the gate drive signal is set according to the effective time difference between the effective data signal and the effective gate drive signal. The effective time difference includes a first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal. Within one scan cycle, the application time of the data signal is located before the start time of the effective level of the gate drive signal. The step of setting the timing of the gate drive signal according to the effective time difference includes: setting the timing of the gate drive signal such that, while keeping the effective level duration of the data signal and the gate drive signal unchanged, the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference, wherein the first time difference is greater than the transition time of the power supply voltage; and The pixel array is driven by the gate drive signal, wherein the pixel array includes a plurality of pixels, and each pixel is a light-emitting element OLED.

2. The method according to claim 1, wherein, The ratio of the effective time difference to the scan period of the gate drive signal is in the range of 35~45%.

3. The method according to claim 2, wherein, The ratio of the effective time difference to the scan period of the gate drive signal is 39%.

4. The method according to claim 1, wherein, The ratio of the first time difference to the scan period of the gate drive signal ranges from 22% to 37%.

5. The method according to any one of claims 2 to 4, wherein, The scan period of the gate drive signal is 8.7µs, and the range of the first time difference is 1.9µs to 3.2µs.

6. The method according to claim 1, further comprising: Based on the effective time difference, the duration of the latch input period is set such that the time difference between the end time of the latch input period and the start time of the effective level of the gate drive signal of the next scan cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

7. The method according to claim 1, further comprising: First driving mode, the first time difference is A1; In the second driving mode, the first time difference is A2, and A1 is greater than A2.

8. A display device, comprising: Pixel array; Timing controller; The source driver is configured to generate a data signal under the control of the timing controller; as well as A gate driver, configured to generate a gate drive signal under the control of the timing controller. The timing controller is configured as follows: Based on the effective time difference between the data signal and the effective signal of the gate drive signal, the timing of the gate drive signal is set so as to drive the pixel array by the gate drive signal. The effective time difference includes a first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal. Within one scan cycle, the application time of the data signal is before the start time of the effective level of the gate drive signal. The timing controller is further configured to: The timing of the gate drive signal is set such that, while keeping the effective level duration of the data signal and the gate drive signal unchanged, the first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference, wherein the first time difference is greater than the switching time of the power supply voltage, and the pixel array includes multiple pixels, each of which is a light-emitting element OLED.

9. The display device according to claim 8, wherein, The ratio of the effective time difference to the scan period of the gate drive signal is in the range of 35~45%.

10. The display device according to claim 8, wherein, The ratio of the effective time difference to the scan period of the gate drive signal is 39%.

11. The display device according to claim 8, wherein, The ratio of the first time difference to the scan period of the gate drive signal ranges from 22% to 37%.

12. The display device according to any one of claims 9 to 11, wherein, The scan period of the gate drive signal is 8.7µs, and the range of the first time difference is 1.9µs to 3.2µs.

13. The display device according to claim 8, wherein, The timing controller is further configured to set the duration of the latch input period based on the effective time difference, such that the time difference between the end time of the latch input period and the start time of the effective level of the gate drive signal in the next scan cycle is greater than 0.5 times the effective time difference and less than the effective time difference.

14. The display device according to claim 8, further comprising: An external power supply is provided between the voltage source of the source driver and the pixel array.

15. The display device according to claim 8, further comprising: A resistor is positioned between the voltage source of the source driver and the pixel array.

16. The display device according to claim 8, wherein, The timing controller is further configured to set: a first driving mode, where the first time difference is A1; and a second driving mode, where the first time difference is A2, and A1 is greater than A2.

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