Control circuit for controlling threshold voltage variation of a target mos

Abstract

Embodiments of the present disclosure provide a control circuit for controlling threshold voltage variation of a target MOS transistor. The control circuit comprises a reference threshold voltage generation circuit, a temperature deviation detection circuit, and a back gate voltage adjustment circuit. The reference threshold voltage generation circuit comprises a reference MOS transistor. The reference threshold voltage generation circuit generates a reference threshold voltage according to a threshold voltage of the reference MOS transistor. The temperature deviation detection circuit comprises a control MOS transistor. The control MOS transistor has the same size as the target MOS transistor. The threshold voltage of the control MOS transistor has the same temperature characteristic as the threshold voltage of the target MOS transistor. The temperature deviation detection circuit controls the control MOS transistor to be in the same working state as the target MOS transistor, and generates a control threshold voltage according to the threshold voltage of the control MOS transistor. The back gate voltage adjustment circuit generates a back gate voltage according to a first voltage difference between the reference threshold voltage and the control threshold voltage, and provides the back gate voltage to a back gate of the target MOS transistor and a back gate of the control MOS transistor.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a control circuit for controlling the threshold voltage variation of a target MOS transistor. Background Technology

[0002] In Complementary Metal Oxide Semiconductor (CMOS) integrated circuit design, the parameters of MOSFETs will vary with different processes and temperatures. In addition, the deviation of the circuit supply voltage will also cause changes in the circuit, thus directly affecting the overall performance of the circuit. Therefore, it is crucial to reduce the impact of process-voltage-temperature (PVT) on the circuit.

[0003] Process variations can affect intrinsic doping concentration, thus influencing the threshold voltage of CMOS circuits. Temperature changes can also cause variations in the Fermi level, resulting in temperature-dependent threshold voltage changes. Even slight deviations in the threshold voltage can significantly impact the performance of analog circuits, and in severe cases, can even prevent digital circuits from functioning properly. Summary of the Invention

[0004] The embodiments described herein provide a control circuit for controlling the threshold voltage variation of a target MOSFET.

[0005] According to a first aspect of this disclosure, a control circuit for controlling the threshold voltage variation of a target MOSFET is provided. The control circuit includes: a reference threshold voltage generation circuit, a temperature deviation detection circuit, and a back gate voltage adjustment circuit. The reference threshold voltage generation circuit includes a reference MOSFET. The reference threshold voltage generation circuit is configured to generate a reference threshold voltage based on the threshold voltage of the reference MOSFET. The temperature deviation detection circuit includes a reference MOSFET. The size of the reference MOSFET is the same as that of the target MOSFET. The threshold voltage of the reference MOSFET has the same temperature characteristics as the threshold voltage of the target MOSFET. The temperature deviation detection circuit is configured to control the reference MOSFET to operate in the same state as the target MOSFET and generate a reference threshold voltage based on the threshold voltage of the reference MOSFET. The back gate voltage adjustment circuit is configured to generate a back gate voltage based on a first voltage difference between the reference threshold voltage and the reference threshold voltage, and to provide the back gate voltage to the back gate of both the target MOSFET and the reference MOSFET.

[0006] In some embodiments of this disclosure, the reference MOS transistor and the target MOS transistor are PMOS transistors. The temperature deviation detection circuit further includes a first current source and a first voltage control circuit. The first current source is coupled to the second terminal of the reference MOS transistor. The first current source is configured to provide a first constant current to the reference MOS transistor. The first voltage control circuit is configured to generate a first control voltage. The first control voltage is equal to the sum of the reference threshold voltage and the source-gate voltage of the target MOS transistor. The control terminal of the reference MOS transistor is coupled to the second terminal of the reference MOS transistor. The first control voltage is provided to the first terminal of the reference MOS transistor. The reference threshold voltage is output from the second terminal of the reference MOS transistor.

[0007] In some embodiments of this disclosure, the control MOS transistor and the target MOS transistor are NMOS transistors. The temperature deviation detection circuit further includes a first current source and a second voltage control circuit. The first current source is coupled to a first terminal of the control MOS transistor. The first current source is configured to provide a first constant current to the control MOS transistor. The second voltage control circuit is configured to generate a second control voltage. The second control voltage is equal to the sum of the control threshold voltage and the gate-source voltage of the target MOS transistor. The control terminal of the control MOS transistor is coupled to a second terminal of the control MOS transistor. The second terminal of the control MOS transistor is supplied with the second control voltage. The control threshold voltage is output from the first terminal of the control MOS transistor.

[0008] In some embodiments of this disclosure, the reference MOSFET is a PMOS transistor. The reference threshold voltage generation circuit further includes a second current source, which is coupled to the second terminal of the reference MOSFET. The second current source is configured to provide a second constant current to the reference MOSFET. The control terminal of the reference MOSFET is coupled to the second terminal of the reference MOSFET. The first terminal of the reference MOSFET is coupled to a first voltage terminal. The reference threshold voltage is output from the control terminal of the reference MOSFET.

[0009] In some embodiments of this disclosure, the reference MOSFET is an NMOS transistor. The reference threshold voltage generation circuit further includes a second current source, which is coupled to the second terminal of the reference MOSFET. The second current source is configured to provide a second constant current to the reference MOSFET. The control terminal of the reference MOSFET is coupled to the second terminal of the reference MOSFET. The first terminal of the reference MOSFET is coupled to a second voltage terminal. The reference threshold voltage is output from the control terminal of the reference MOSFET.

[0010] In some embodiments of this disclosure, the reference threshold voltage generation circuit further includes a process deviation detection circuit and a trimming circuit. The process deviation detection circuit is configured to generate a trimming voltage based on a second voltage difference between a reference voltage and the reference threshold voltage. The trimming circuit is configured to generate a trimming current based on the trimming voltage and provide the trimming current to the reference MOSFET from the second terminal of the reference MOSFET, thereby adjusting the reference threshold voltage. The trimming current is negatively correlated with the second voltage difference.

[0011] In some embodiments of this disclosure, the reference threshold voltage generation circuit further includes: a second current source, a process deviation detection circuit, and a trimming circuit. The second current source is coupled to the second terminal of a reference MOSFET. The second current source is configured to provide a second constant current to the reference MOSFET. The control terminal of the reference MOSFET is coupled to the second terminal of the reference MOSFET. The reference MOSFET is a PMOS transistor. The first terminal of the reference MOSFET is coupled to a first voltage terminal. The process deviation detection circuit is configured to generate a trimming voltage based on a second voltage difference between a reference voltage and a reference threshold voltage. The trimming circuit includes: a switch control circuit, a plurality of voltage-controlled switches, a first resistor connected in series between the first voltage terminal and the second voltage terminal, and a plurality of second resistors. The first terminal of the first resistor is coupled to the first voltage terminal. The second terminal of the first resistor is coupled to the control terminal of the reference MOSFET and a first terminal of a second resistor. The first terminal of each second resistor is coupled to the first terminal of a voltage-controlled switch. The second terminal of each voltage-controlled switch is coupled to the output terminal of the trimming circuit. The reference threshold voltage is output from the output terminal. The switch control circuit is configured to control one of the multiple voltage-controlled switches to close based on the adjustment voltage, such that the equivalent resistance between the first voltage terminal and the output terminal is negatively correlated with the second voltage difference.

[0012] In some embodiments of this disclosure, the reference threshold voltage generation circuit further includes: a second current source, a process deviation detection circuit, and a trimming circuit. The second current source is coupled to the second terminal of a reference MOSFET. The second current source is configured to provide a second constant current to the reference MOSFET. The control terminal of the reference MOSFET is coupled to the second terminal of the reference MOSFET. The reference MOSFET is an NMOS transistor. The first terminal of the reference MOSFET is coupled to a second voltage terminal. The process deviation detection circuit is configured to generate a trimming voltage based on a second voltage difference between a reference voltage and a reference threshold voltage. The trimming circuit includes: a switch control circuit, a plurality of voltage-controlled switches, a first resistor connected in series between the first voltage terminal and the second voltage terminal, and a plurality of second resistors. The first terminal of the first resistor is coupled to the first voltage terminal. The second terminal of the first resistor is coupled to the control terminal of the reference MOSFET and the first terminal of a second resistor. The first terminal of each second resistor is coupled to the first terminal of a voltage-controlled switch. The second terminal of each voltage-controlled switch is coupled to the output terminal of the trimming circuit. The reference threshold voltage is output from the output terminal. The switch control circuit is configured to control one of the multiple voltage-controlled switches to close based on the adjustment voltage, such that the equivalent resistance between the first voltage terminal and the output terminal is negatively correlated with the second voltage difference.

[0013] In some embodiments of this disclosure, the back-gate voltage adjustment circuit includes a first operational amplifier and a back-gate driving circuit. A first input terminal of the first operational amplifier is provided with a reference threshold voltage. A second input terminal of the first operational amplifier is provided with a reference threshold voltage. An error voltage is output from the output terminal of the first operational amplifier. The back-gate driving circuit is configured to generate a back-gate voltage based on the error voltage.

[0014] In some embodiments of this disclosure, the back gate voltage adjustment circuit further includes an overvoltage protection circuit. The overvoltage protection circuit is configured to provide an enable signal at an invalid level to the back gate drive circuit when the back gate voltage exceeds a preset safe voltage. The back gate drive circuit is further configured to limit the back gate voltage to a preset safe voltage when the enable signal is at an invalid level.

[0015] In some embodiments of this disclosure, the back gate driving circuit includes: a first voltage-controlled switch, a second voltage-controlled switch, an inverter, a first driving circuit, and a second driving circuit. The first driving circuit is configured to increase the driving force of the error voltage to generate a first driving voltage. The second driving circuit is configured to increase the driving force of a preset safety voltage to generate a second driving voltage. An enable signal is provided to the controlled terminal of the first voltage-controlled switch. The first terminal of the first voltage-controlled switch is provided with the first driving voltage. The second terminal of the first voltage-controlled switch is coupled to the back gate of the target MOSFET. An enable signal is provided to the input terminal of the inverter. The output terminal of the inverter is coupled to the controlled terminal of the second voltage-controlled switch. The first terminal of the second voltage-controlled switch is provided with the second driving voltage. The second terminal of the second voltage-controlled switch is coupled to the back gate of the target MOSFET.

[0016] According to a second aspect of this disclosure, a control circuit for controlling the threshold voltage variation of a target MOSFET is provided. The control circuit includes: a reference MOSFET, a control MOSFET, a first current source, a first voltage control circuit, a second current source, a first operational amplifier, a second operational amplifier, a third operational amplifier, a first voltage-controlled switch, a second voltage-controlled switch, an inverter, a first drive circuit, a second drive circuit, and a trimming circuit. The reference MOSFET, control MOSFET, and target MOSFET are PMOS transistors. The control MOSFET has the same dimensions as the target MOSFET. The back gate of the control MOSFET is coupled to the back gate of the target MOSFET. The first current source is coupled to the second terminal of the control MOSFET. The first current source is configured to provide a first constant current to the control MOSFET. The first voltage control circuit is configured to generate a first control voltage. The first control voltage is equal to the sum of the reference threshold voltage and the source-gate voltage of the target MOSFET. The reference threshold voltage is the voltage at the second terminal of the control MOSFET. The control terminal of the control MOSFET is coupled to the second terminal of the control MOSFET. The first control voltage is provided to the first terminal of the control MOSFET. The second current source is coupled to the second terminal of the reference MOSFET. A second current source is configured to provide a second constant current to a reference MOSFET. The control terminal of the reference MOSFET is coupled to its second terminal. The first terminal of the reference MOSFET is coupled to a first voltage terminal. A reference threshold voltage is output from the control terminal of the reference MOSFET. The first input terminal of a first operational amplifier is provided with the reference threshold voltage. The second input terminal of the first operational amplifier is provided with the reference threshold voltage. An error voltage is output from the output terminal of the first operational amplifier. A preset safety voltage is provided to the first input terminal of a second operational amplifier. The second input terminal of the second operational amplifier is coupled to the back gate of the target MOSFET. An enable signal is output from the output terminal of the second operational amplifier. A first drive circuit is configured to increase the driving force of the error voltage to generate a first drive voltage. A second drive circuit is configured to increase the driving force of the preset safety voltage to generate a second drive voltage. An enable signal is provided to the controlled terminal of a first voltage-controlled switch. The first terminal of the first voltage-controlled switch is provided with the first drive voltage. The second terminal of the first voltage-controlled switch is coupled to the back gate of the target MOSFET. An enable signal is provided to the input terminal of an inverter. The output terminal of the inverter is coupled to the controlled terminal of a second voltage-controlled switch. The first terminal of the second voltage-controlled switch is provided with the second drive voltage. The second terminal of the second voltage-controlled switch is coupled to the back gate of the target MOSFET. A reference voltage is provided to the first input terminal of the third operational amplifier. A reference threshold voltage is provided to the second input terminal of the third operational amplifier. A trimming voltage is output from the output terminal of the third operational amplifier. The trimming circuit is configured to generate a trimming current based on the trimming voltage and provide the trimming current to the reference MOSFET from the second terminal of the reference MOSFET. The trimming current is negatively correlated with the trimming voltage.

[0017] According to a third aspect of this disclosure, a chip is provided. The chip includes the control circuitry described in the first or second aspect of this disclosure.

[0018] According to a fourth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a third aspect of this disclosure. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0020] Figure 1 This is a schematic block diagram of a control circuit for controlling the threshold voltage variation of a target MOSFET according to an embodiment of the present disclosure;

[0021] Figure 2 This is an exemplary circuit diagram of a control circuit for controlling the threshold voltage variation of a target MOS transistor according to an embodiment of the present disclosure;

[0022] Figure 3 This is another exemplary circuit diagram of a control circuit for controlling the threshold voltage variation of a target MOS transistor according to an embodiment of the present disclosure;

[0023] Figure 4 This is yet another exemplary circuit diagram of a control circuit for controlling the threshold voltage variation of a target MOS transistor according to embodiments of the present disclosure;

[0024] Figure 5 yes Figure 4 An exemplary circuit diagram of the back gate drive circuit in the example;

[0025] Figure 6 This is a further exemplary circuit diagram of a control circuit for controlling the threshold voltage variation of a target MOS transistor according to embodiments of the present disclosure;

[0026] Figure 7 This is another further exemplary circuit diagram of a control circuit for controlling the threshold voltage variation of a target MOS transistor according to embodiments of the present disclosure;

[0027] Figure 8 yes Figure 2 An alternative circuit diagram for the reference threshold voltage generation circuit.

[0028] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0031] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0032] In some applications, it is desirable for the absolute values ​​of the threshold voltages of PMOS and NMOS transistors in a circuit to change synchronously. For simplicity, in this article, "threshold voltage" actually refers to the "absolute value of the threshold voltage." For example, at room temperature, the threshold voltage of an NMOS transistor is 0.8V, while that of a PMOS transistor is 0.7V. As the temperature changes, the threshold voltage of the NMOS transistor becomes 0.3V, while that of the PMOS transistor becomes 1.0V. Therefore, the threshold voltage changes of the PMOS and NMOS transistors are asynchronous with temperature variations. This can cause the switching threshold of an inverter implemented using both PMOS and NMOS transistors to change, leading to erroneous output switching. If the threshold voltage changes of the PMOS and NMOS transistors can be kept synchronous, the switching threshold of the inverter can be kept stable. Similar problems may exist in other circuits that use both PMOS and NMOS transistors. If the problems caused by the asynchronous changes in the threshold voltages of the two types of transistors can be avoided, the normal operation of these circuits can be maintained.

[0033] Embodiments of this disclosure provide a control circuit for controlling the threshold voltage variation of a target MOS transistor. The target MOS transistor can be a PMOS transistor or an NMOS transistor. In applications requiring synchronized control of the threshold voltage variations of both PMOS and NMOS transistors, this control circuit can be used to achieve synchronization. Figure 1 A schematic block diagram of a control circuit 100 for controlling the threshold voltage variation of a target MOSFET Mt according to an embodiment of the present disclosure is shown. The control circuit 100 includes: a reference threshold voltage generation circuit 110, a temperature deviation detection circuit 120, and a back gate voltage adjustment circuit 130.

[0034] The output of the reference threshold voltage generation circuit 110 is coupled to the first input of the back gate voltage adjustment circuit 130. The reference threshold voltage generation circuit 110 includes a reference MOSFET (in... Figure 1 (Not shown in the diagram). The reference threshold voltage generation circuit 110 is configured to generate a reference threshold voltage Vthp based on the threshold voltage of the reference MOSFET. The reference threshold voltage generation circuit 110 provides the reference threshold voltage Vthp to the back gate voltage adjustment circuit 130. The reference threshold voltage Vthp can be equal to the threshold voltage of the reference MOSFET, or it can be a voltage value that is linearly related to the threshold voltage of the reference MOSFET.

[0035] The input terminal of the temperature deviation detection circuit 120 is coupled to the back gate of the target MOSFET Mt. The output terminal of the temperature deviation detection circuit 120 is coupled to the second input terminal of the back gate voltage adjustment circuit 130. The temperature deviation detection circuit 120 includes a reference MOSFET (in... Figure 1 (Not shown in the image). The back gate of the reference MOSFET is coupled to the back gate of the target MOSFET Mt. The dimensions of the reference MOSFET are the same as those of the target MOSFET Mt. The reference MOSFET and the target MOSFET Mt are transistors of the same type (both P-type or both N-type). The threshold voltage of the reference MOSFET and the threshold voltage of the target MOSFET Mt have the same temperature characteristics. The temperature deviation detection circuit 120 is configured to control the reference MOSFET to operate in the same state as the target MOSFET Mt, and generate a reference threshold voltage Vtp1 based on the threshold voltage of the reference MOSFET. The reference threshold voltage Vtp1 can be equal to the threshold voltage of the reference MOSFET, or it can be a voltage value linearly related to the threshold voltage of the reference MOSFET. The reference MOSFET is essentially a replica transistor of the target MOSFET Mt. The gate voltage Vtg and source voltage Vts of the target MOSFET Mt are set according to the actual application of the target MOSFET Mt. By setting the source-gate voltage of the reference MOSFET to be the same as the source-gate voltage (Vts-Vtg) of the target MOSFET Mt, the two can be made to operate in the same state.

[0036] The two input terminals of the back gate voltage adjustment circuit 130 are respectively coupled to the output terminal of the reference threshold voltage generation circuit 110 and the output terminal of the temperature deviation detection circuit 120. The back gate voltage adjustment circuit 130 is configured to generate a back gate voltage VBP based on a first voltage difference between the reference threshold voltage Vthp and the control threshold voltage Vtp1, and to provide the back gate voltage VBP to the back gate of the target MOS transistor Mt and the back gate of the control MOS transistor. In some embodiments of this disclosure, the back gate voltage adjustment circuit 130 is configured to decrease the back gate voltage VBP when the first voltage difference increases, provided that the control MOS transistor is a PMOS transistor; and to increase the back gate voltage VBP when the first voltage difference increases, provided that the control MOS transistor is an NMOS transistor.

[0037] Since the dimensions of the control MOSFET are the same as those of the target MOSFET Mt, the threshold voltages of the control MOSFET and the target MOSFET Mt have the same temperature characteristics, and they operate in the same state. Therefore, the threshold voltage of the control MOSFET is equal to that of the target MOSFET Mt. Furthermore, because the back gate of the control MOSFET is coupled to the back gate of the target MOSFET Mt, a change in the back gate voltage of the control MOSFET will synchronously change the back gate voltage of the target MOSFET Mt. Therefore, the threshold voltage of the target MOSFET Mt changes synchronously with the threshold voltage of the control MOSFET.

[0038] According to an embodiment of this disclosure, the control circuit 100 obtains a first voltage difference between a reference threshold voltage Vthp and a control threshold voltage Vtp1 via a back gate voltage adjustment circuit 130. When the control MOS transistor is a PMOS transistor, when the first voltage difference increases, the back gate voltage VBP decreases, thereby pulling down the back gate voltage of the control MOS transistor. This increases the control threshold voltage Vtp1, thereby reducing the first voltage difference and ultimately maintaining its stability. When the first voltage difference decreases, the back gate voltage VBP increases, thereby raising the back gate voltage of the control MOS transistor. This decreases the control threshold voltage Vtp1, thereby increasing the first voltage difference and ultimately maintaining its stability. When the control MOS transistor is an NMOS transistor, when the first voltage difference increases, the back gate voltage VBP increases, thereby raising the back gate voltage of the control MOS transistor. This increases the control threshold voltage Vtp1, thereby reducing the first voltage difference and ultimately maintaining its stability. When the first voltage difference decreases, the back gate voltage VBP decreases, thereby pulling down the back gate voltage of the control MOS transistor. This reduces the threshold voltage Vtp1, thereby increasing the first voltage difference and ultimately maintaining the stability of the first voltage difference.

[0039] Assuming that the reference threshold voltage Vthp increases with temperature change, the reference threshold voltage Vtp1 also increases to maintain a stable first voltage difference. In this case, the back gate voltage VBP changes accordingly so that the threshold voltage of the target MOS transistor Mt also changes synchronously. In short, the change in the threshold voltage of the target MOS transistor Mt follows the change in the threshold voltage of the reference MOS transistor. If the control circuit 100 according to an embodiment of this disclosure is applied to an inverter to simultaneously control the threshold voltage changes of both the PMOS transistor and the NMOS transistor, the changes in the threshold voltages of the PMOS transistor and the NMOS transistor can be kept synchronous, thereby maintaining the stability of the inverter's flip threshold.

[0040] Figure 2 An exemplary circuit diagram of a control circuit 200 for controlling the threshold voltage variation of a target MOSFET Mt, according to an embodiment of the present disclosure, is shown. Figure 2 In the example, the reference MOS transistor M1, the control MOS transistor Mc, and the target MOS transistor Mt are PMOS transistors.

[0041] The temperature deviation detection circuit 220 includes a reference MOSFET Mc, a first current source I1, and a first voltage control circuit 221. The first current source I1 is coupled to the second terminal of the reference MOSFET Mc. The first current source I1 can also be coupled to a second voltage terminal V2. The first current source I1 is configured to provide a first constant current I1 to the reference MOSFET Mc.

[0042] The first voltage control circuit 221 is coupled to the control electrode of the reference MOSFET Mc, thereby obtaining the reference threshold voltage Vtp1. The first voltage control circuit 221 is provided with the source voltage Vts and gate voltage Vtg of the target MOSFET Mt. It should be noted that the first voltage control circuit 221 is not directly coupled to the source and gate of the target MOSFET Mt to avoid affecting the normal operation of the target MOSFET Mt. The signals controlling the source voltage Vts and gate voltage Vtg of the target MOSFET Mt can also be provided to the first voltage control circuit 221, so that the first voltage control circuit 221 obtains the source voltage Vts and gate voltage Vtg of the target MOSFET Mt. The first voltage control circuit 221 is configured to generate a first control voltage Vcs. The first control voltage Vcs is equal to the sum of the reference threshold voltage Vtp1 and the source-gate voltage (Vts-Vtg) of the target MOSFET Mt. The control electrode of the reference MOSFET Mc is coupled to the second electrode of the reference MOSFET Mc. The first electrode of the reference MOSFET Mc is provided with the first control voltage Vcs. The reference threshold voltage Vtp1 is output from the second terminal of the reference MOSFET Mc. In other words, the reference threshold voltage Vtp1 is equal to the voltage at the second terminal of the reference MOSFET Mc.

[0043] The reference threshold voltage generation circuit 210 includes a reference MOSFET M1 and a second current source I2. The second current source I2 is coupled to the second terminal of the reference MOSFET M1. The second current source I2 can also be coupled to a second voltage terminal V2. The second current source I2 is configured to provide a second constant current I2 to the reference MOSFET M1. The control terminal of the reference MOSFET M1 is coupled to the second terminal of the reference MOSFET M1. The first terminal of the reference MOSFET M1 is coupled to the first voltage terminal V1. A reference threshold voltage Vthp is output from the control terminal of the reference MOSFET M1. That is, the reference threshold voltage Vthp is equal to the voltage at the control terminal of the reference MOSFET M1.

[0044] The back-gate voltage adjustment circuit 230 includes a first operational amplifier A1 and a back-gate drive circuit 231. A reference threshold voltage Vthp is provided at the first input terminal of the first operational amplifier A1. A reference threshold voltage Vtp1 is provided at the second input terminal of the first operational amplifier A1. An error voltage Verr is output from the output terminal of the first operational amplifier A1. The back-gate drive circuit 231 is configured to generate a back-gate voltage VBP based on the error voltage Verr.

[0045] exist Figure 2 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the first operational amplifier A1 is the inverting input terminal. The second input terminal of the first operational amplifier A1 is the non-inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 2 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 2 The examples shown have different settings.

[0046] According to an embodiment of this disclosure, the control circuit 200 obtains a first voltage difference between a reference threshold voltage Vthp and a control threshold voltage Vtp1 via a back gate voltage adjustment circuit 230. When the first voltage difference decreases, the back gate voltage VBP increases, thereby raising the voltage of the back gate of the control MOS transistor Mc. This increases the threshold voltage of the control MOS transistor Mc and decreases the control threshold voltage Vtp1, thereby increasing the first voltage difference and ultimately maintaining its stability. When the first voltage difference increases, the back gate voltage VBP decreases, thereby lowering the voltage of the back gate of the control MOS transistor. This decreases the threshold voltage of the control MOS transistor Mc and increases the control threshold voltage Vtp1, thereby decreasing the first voltage difference and ultimately maintaining its stability.

[0047] Assuming that the reference threshold voltage Vthp increases with temperature change, the reference threshold voltage Vtp1 also increases to maintain a stable first voltage difference. In this case, the back gate voltage VBP changes accordingly so that the threshold voltage of the target MOS transistor Mt also changes synchronously. In short, the change in the threshold voltage of the target MOS transistor Mt follows the change in the threshold voltage of the reference MOS transistor M1. If the control circuit 200 according to an embodiment of this disclosure is applied to an inverter to simultaneously control the threshold voltage changes of both the PMOS transistor and the NMOS transistor, the changes in the threshold voltages of the PMOS transistor and the NMOS transistor can be kept synchronous, thereby maintaining the stability of the inverter's flip threshold.

[0048] exist Figure 2 In an alternative embodiment, the control MOS transistor Mc and the target MOS transistor Mt can also be NMOS transistors. Figure 3 An exemplary circuit diagram of the control circuit 300 in such an embodiment is shown.

[0049] exist Figure 3 In the example, the temperature deviation detection circuit 320 includes a reference MOSFET Mc, a first current source I1, and a second voltage control circuit 321. The first current source I1 is coupled to the first terminal of the reference MOSFET Mc. The first current source I1 may also be coupled to a second voltage terminal V2. The first current source I1 is configured to provide a first constant current I1 to the reference MOSFET Mc.

[0050] The second voltage control circuit 321 is coupled to the first terminal of the reference MOSFET Mc, thereby obtaining the reference threshold voltage Vtp1. The second voltage control circuit 321 is supplied with the source voltage Vts and gate voltage Vtg of the target MOSFET Mt. It should be noted that the second voltage control circuit 321 is not directly coupled to the source and gate of the target MOSFET Mt to avoid affecting the normal operation of the target MOSFET Mt. The signals controlling the source voltage Vts and gate voltage Vtg of the target MOSFET Mt can also be provided to the second voltage control circuit 321, so that the second voltage control circuit 321 obtains the source voltage Vts and gate voltage Vtg of the target MOSFET Mt. The second voltage control circuit 321 is configured to generate a second control voltage Vcs'. The second control voltage Vcs' is equal to the sum of the reference threshold voltage Vtp1 and the gate-source voltage (Vtg - Vts) of the target MOSFET Mt. The control terminal of the reference MOSFET Mc is coupled to the second terminal of the reference MOSFET Mc. The second terminal of the reference MOSFET Mc is supplied with the second control voltage Vcs'. The reference threshold voltage Vtp1 is output from the first terminal of the reference MOSFET Mc. In other words, the reference threshold voltage Vtp1 is equal to the voltage at the first terminal of the reference MOSFET Mc.

[0051] exist Figure 3 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the first operational amplifier A1 is the non-inverting input terminal. The second input terminal of the first operational amplifier A1 is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0052] According to an embodiment of this disclosure, the control circuit 300 obtains a first voltage difference between a reference threshold voltage Vthp and a control threshold voltage Vtp1 via a back gate voltage adjustment circuit 330. When the first voltage difference increases, the back gate voltage VBP increases, thereby raising the voltage of the back gate of the control MOS transistor Mc. This reduces the threshold voltage of the control MOS transistor Mc and increases the control threshold voltage Vtp1, thus reducing the first voltage difference and ultimately maintaining its stability. When the first voltage difference decreases, the back gate voltage VBP decreases, thereby lowering the voltage of the back gate of the control MOS transistor. This increases the threshold voltage of the control MOS transistor Mc and decreases the control threshold voltage Vtp1, thereby increasing the first voltage difference and ultimately maintaining its stability.

[0053] Assuming that the reference threshold voltage Vthp increases with temperature change, the reference threshold voltage Vtp1 also increases to maintain a stable first voltage difference. In this case, the back gate voltage VBP changes accordingly so that the threshold voltage of the target MOS transistor Mt also changes synchronously. In short, the change in the threshold voltage of the target MOS transistor Mt follows the change in the threshold voltage of the reference MOS transistor M1. If the control circuit 300 according to an embodiment of this disclosure is applied to an inverter to simultaneously control the threshold voltage changes of both the PMOS transistor and the NMOS transistor, the changes in the threshold voltages of the PMOS transistor and the NMOS transistor can be kept synchronous, thereby maintaining the stability of the inverter's flip threshold.

[0054] In high-temperature environments, the threshold voltage Vtp1 may remain consistently lower than the reference threshold voltage Vthp, causing the back gate voltage VBP to remain at a high level. To prevent the circuit from operating at a high level for extended periods, some embodiments of this disclosure propose adding an overvoltage protection circuit to the back gate voltage adjustment circuit. Figure 4 An exemplary circuit diagram of the control circuit 400 in such embodiments is shown. The back gate voltage adjustment circuit 430 includes a first operational amplifier A1, a back gate drive circuit 431, and an overvoltage protection circuit 432. The overvoltage protection circuit 432 is configured to: provide an inactive enable signal EN to the back gate drive circuit 431 when the back gate voltage VBP is higher than a preset safety voltage Vset; and provide an active enable signal EN to the back gate drive circuit 431 when the back gate voltage VBP is lower than or equal to the preset safety voltage Vset. The back gate drive circuit 431 is configured to: limit the back gate voltage VBP to the preset safety voltage Vset when the enable signal EN is inactive, and use the error voltage Verr output from the first operational amplifier A1 as the back gate voltage VBP when the enable signal EN is active.

[0055] The overvoltage protection circuit 432 includes a second operational amplifier A2. A preset safety voltage Vset is provided to the first input terminal of the second operational amplifier A2. The second input terminal of the second operational amplifier A2 is coupled to the back gate of the target MOSFET Mt, thereby being provided with a back gate voltage VBP. An enable signal EN is output from the output terminal of the second operational amplifier A2. When the back gate voltage VBP is lower than or equal to the preset safety voltage Vset, the enable signal EN is at an active level (e.g., high level), and the back gate voltage VBP is equal to the error voltage Verr output from the first operational amplifier A1. When the back gate voltage VBP is higher than the preset safety voltage Vset, the enable signal EN is at an inactive level (e.g., low level), and the back gate voltage VBP is limited to the preset safety voltage Vset. This prevents the back gate voltage VBP from exceeding the preset safety voltage Vset, which could lead to circuit overheating or disabling of the target MOSFET Mt.

[0056] exist Figure 4 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the first operational amplifier A1 is an inverting input terminal. The second input terminal of the first operational amplifier A1 is a non-inverting input terminal. The first input terminal of the second operational amplifier A2 is a non-inverting input terminal. The second input terminal of the second operational amplifier A2 is an inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 The examples shown have different settings.

[0057] Figure 5 Show Figure 4 An exemplary circuit diagram of the back gate drive circuit 431 is provided. The back gate drive circuit 431 includes: a first voltage-controlled switch S1, a second voltage-controlled switch S2, an inverter NG, a first drive circuit Buff1, and a second drive circuit Buff2. The first drive circuit Buff1 is configured to increase the driving force of the error voltage Verr to generate a first drive voltage. The second drive circuit Buff2 is configured to increase the driving force of a preset safety voltage Vset to generate a second drive voltage. An enable signal EN is provided to the controlled terminal of the first voltage-controlled switch S1. The first terminal of the first voltage-controlled switch S1 is coupled to the output terminal of the first drive circuit Buff1, thereby being provided with the first drive voltage. The second terminal of the first voltage-controlled switch S1 is coupled to the back gate of the target MOSFET Mt. An enable signal EN is provided to the input terminal of the inverter NG. The output terminal of the inverter NG is coupled to the controlled terminal of the second voltage-controlled switch S2. The first terminal of the second voltage-controlled switch S2 is coupled to the output terminal of the second drive circuit Buff2, thereby being provided with the second drive voltage. The second terminal of the second voltage-controlled switch S2 is coupled to the back gate of the target MOSFET Mt.

[0058] When the enable signal EN is active, the first voltage-controlled switch S1 is closed and the second voltage-controlled switch S2 is open, and the first drive voltage is provided as the back gate voltage VBP to the back gate of the target MOSFET Mt. When the enable signal EN is inactive, the first voltage-controlled switch S1 is open and the second voltage-controlled switch S2 is closed, and the second drive voltage is provided as the back gate voltage VBP to the back gate of the target MOSFET Mt, thereby limiting the value of the back gate voltage VBP to the preset safe voltage Vset.

[0059] Furthermore, some embodiments of this disclosure also consider the impact of process variations on the threshold voltage of the MOSFET. Different processes result in different threshold voltages for the MOSFET. Higher intrinsic doping concentrations and slower process corners lead to higher threshold voltages, while lower intrinsic doping concentrations and faster process corners result in lower threshold voltages. Compared to normal process corners, the threshold voltage changes significantly under both fast and slow process corners, requiring adjustment to bring it closer to the threshold voltage near the normal process corner. MOSFET processes include TT, SS, FF, SF, and FS, representing NMOS and PMOS process corners respectively. For example, FS indicates a fast process corner for NMOS and a slow process corner for PMOS. Taking the FS process corner as an example, the threshold voltage difference between the two types of MOSFETs is large, which significantly degrades circuit performance.

[0060] Figure 6 An exemplary circuit diagram of the control circuit 600 in such an embodiment is shown. Figure 4 Based on the example, Figure 6 The reference threshold voltage generation circuit 610 further includes a process deviation detection circuit 612 and a trimming circuit 613. The process deviation detection circuit 612 is configured to generate a trimming voltage Vadj based on a second voltage difference between the reference voltage VR and the reference threshold voltage Vthp. The trimming voltage Vadj is proportional to the second voltage difference. The trimming circuit 613 is configured to generate a trimming current based on the trimming voltage Vadj and provide the trimming current to the reference MOSFET M1 from the second terminal of the reference MOSFET M1, thereby adjusting the reference threshold voltage Vthp. The trimming current is negatively correlated with the trimming voltage Vadj, and therefore also negatively correlated with the second voltage difference.

[0061] The process deviation detection circuit 612 may include a third operational amplifier A3. A reference voltage VR is provided to the first input terminal of the third operational amplifier A3. A reference threshold voltage Vthp is provided to the second input terminal of a reference MOSFET M1. An adjustment voltage Vadj is output from the output terminal of the third operational amplifier A3.

[0062] The tuning circuit 613 may include multiple branches, each branch including a switch connected in series (in Figure 6(Not shown in the diagram) and a current source. These multiple branches can be connected in parallel with the second current source I2. The adjustment circuit 613 controls how many current sources are connected between the second terminal of the reference MOSFET M1 and the second voltage terminal V2 according to the magnitude of the adjustment voltage Vadj.

[0063] If the reference threshold voltage Vthp is less than the reference voltage VR, then under the control of the adjustment voltage Vadj, less current is supplied to the second terminal of the reference MOSFET M1, thereby reducing the current flowing through the reference MOSFET M1 and increasing the reference threshold voltage Vthp. Conversely, if the reference threshold voltage Vthp is greater than the reference voltage VR, then under the control of the adjustment voltage Vadj, more current is supplied to the second terminal of the reference MOSFET M1, thereby increasing the current flowing through the reference MOSFET M1 and decreasing the reference threshold voltage Vthp. In this way, the reference threshold voltage Vthp can remain consistent under different process conditions.

[0064] exist Figure 6 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the first operational amplifier A1 is an inverting input terminal. The second input terminal of the first operational amplifier A1 is a non-inverting input terminal. The first input terminal of the second operational amplifier A2 is a non-inverting input terminal. The second input terminal of the second operational amplifier A2 is an inverting input terminal. The first input terminal of the third operational amplifier A3 is a non-inverting input terminal. The second input terminal of the third operational amplifier A3 is an inverting input terminal. Those skilled in the art should understand that, based on the above inventive concept... Figure 6 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 6 The examples shown have different settings.

[0065] Figure 7 Show Figure 6 An exemplary circuit diagram of an alternative embodiment of the control circuit 600 shown. Figure 7 and Figure 6 The difference lies in the internal structure of the reference threshold voltage generation circuit.

[0066] exist Figure 7 In the example, the reference threshold voltage generation circuit 712 includes: a reference MOSFET M1, a second current source I2, a process deviation detection circuit 712, and a trimming circuit 713. The second current source I2 is coupled to the second terminal of the reference MOSFET M1. The second current source I2 is configured to provide a second constant current I2 to the reference MOSFET M1. The control terminal of the reference MOSFET M1 is coupled to the second terminal of the reference MOSFET M1. The reference MOSFET M1 is a PMOS transistor. The first terminal of the reference MOSFET M1 is coupled to a first voltage terminal V1.

[0067] The process deviation detection circuit 712 is configured to generate a trimming voltage Vadj based on a second voltage difference between the reference voltage VR and the reference threshold voltage Vthp.

[0068] The process deviation detection circuit 712 may include a third operational amplifier A3. A reference voltage VR is provided to the first input terminal of the third operational amplifier A3. The second input terminal of the third operational amplifier A3 is coupled to the output terminal Out of the trimming circuit 713, thereby being provided with a reference threshold voltage Vthp. A trimming voltage Vadj is output from the output terminal of the third operational amplifier A3.

[0069] The adjustment circuit 713 includes: a switch control circuit 7131, a plurality of voltage-controlled switches S, a first resistor R1 and a plurality of second resistors R2 connected in series between a first voltage terminal V1 and a second voltage terminal V2. The first end of the first resistor R1 is coupled to the first voltage terminal V1. The second end of the first resistor R1 is coupled to the control electrode of a reference MOSFET M1 and the first end of a second resistor R2. The first end of each second resistor R2 is coupled to the first end of a voltage-controlled switch S. The second end of each voltage-controlled switch S is coupled to the output terminal Out of the adjustment circuit 713. A reference threshold voltage Vthp is output from the output terminal Out. The switch control circuit 7131 is configured to control one of the voltage-controlled switches S to close according to the adjustment voltage Vadj, such that the equivalent resistance value between the first voltage terminal V1 and the output terminal Out is negatively correlated with the second voltage difference. The resistance values ​​of the first resistor R1 and the second resistors R2 can be set according to the actual application.

[0070] If the reference threshold voltage Vthp is less than the reference voltage VR, the voltage-controlled switch S, located closer to the first voltage terminal, closes under the control of the adjustment voltage Vadj, thereby reducing the equivalent resistance between the first voltage terminal V1 and the output terminal Out. This increases the reference threshold voltage Vthp. If the reference threshold voltage Vthp is greater than the reference voltage VR, the voltage-controlled switch S, located closer to the second voltage terminal, closes under the control of the adjustment voltage Vadj, thereby increasing the equivalent resistance between the first voltage terminal V1 and the output terminal Out. This decreases the reference threshold voltage Vthp. In this way, the reference threshold voltage Vthp can remain consistent under different processes.

[0071] exist Figure 7 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the first operational amplifier A1 is an inverting input terminal. The second input terminal of the first operational amplifier A1 is a non-inverting input terminal. The first input terminal of the second operational amplifier A2 is a non-inverting input terminal. The second input terminal of the second operational amplifier A2 is an inverting input terminal. The first input terminal of the third operational amplifier A3 is a non-inverting input terminal. The second input terminal of the third operational amplifier A3 is an inverting input terminal. Those skilled in the art should understand that, based on the above inventive concept... Figure 7Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 7 The examples shown have different settings.

[0072] Those skilled in the art should understand that Figures 2 to 4 and Figures 6 to 7 The internal structure of the reference threshold voltage generation circuit described herein is exemplary, and other circuits can also be used to implement the reference threshold voltage generation circuit. The embodiments disclosed herein do not limit the specific implementation of the reference threshold voltage generation circuit. Figure 8 Exemplary Figure 2 An alternative implementation of the reference threshold voltage generation circuit 210 in [the circuit]. Figure 8 In the example, the reference MOSFET M1 is an NMOS transistor. The reference threshold voltage generation circuit 810 includes: a reference MOSFET M1 and a second current source I2. The second current source I2 is coupled to the second terminal of the reference MOSFET M1. The second current source I2 is configured to provide a second constant current I2 to the reference MOSFET M1. The control terminal of the reference MOSFET M1 is coupled to the second terminal of the reference MOSFET M1. The first terminal of the reference MOSFET M1 is coupled to a second voltage terminal V2. The reference threshold voltage Vthp is output from the control terminal of the reference MOSFET M1.

[0073] Embodiments of this disclosure also provide an inverter. The inverter includes a control circuit according to embodiments of this disclosure, an NMOS transistor, and a PMOS transistor. The control circuit according to embodiments of this disclosure is used to control the threshold voltages of the NMOS transistor and the PMOS transistor to be consistent.

[0074] Embodiments of this disclosure also provide a chip. This chip includes an inverter according to embodiments of this disclosure. This chip is, for example, a chip for performing high-precision analog-to-digital signal conversion.

[0075] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, an automated testing device and an industrial process control device.

[0076] In summary, the control circuit for controlling the threshold voltage change of a target MOSFET according to embodiments of this disclosure can control the threshold voltage of the target MOSFET to follow the threshold voltage change of a reference MOSFET. In circuits requiring synchronized threshold voltage changes of multiple MOSFETs, the threshold voltages of these multiple MOSFETs can be controlled to change uniformly, thereby achieving circuit stability. In circuits with different process-voltage-temperature (PVT) characteristics, the threshold voltages of different types of MOSFETs can be synchronized, thereby maintaining normal circuit operation.

[0077] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0078] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0079] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A control circuit for controlling threshold voltage variation of a target MOS transistor, comprising: The reference threshold voltage generation circuit, the temperature deviation detection circuit, the back gate voltage adjustment circuit, The reference threshold voltage generation circuit includes a reference MOS tube, and is configured to generate a reference threshold voltage according to a threshold voltage of the reference MOS tube. The temperature deviation detection circuit includes a control MOS tube, the control MOS tube has the same size as the target MOS tube, and has the same temperature characteristic as the threshold voltage of the target MOS tube, and is configured to control the control MOS tube to be in the same working state as the target MOS tube, and generate a control threshold voltage according to the threshold voltage of the control MOS tube. The back gate voltage adjustment circuit is configured to generate a back gate voltage according to a first voltage difference between the reference threshold voltage and the control threshold voltage, and provide the back gate voltage to the back gate of the target MOS tube and the back gate of the control MOS tube. The back gate voltage adjustment circuit includes a first operational amplifier and a back gate driving circuit, The first input end of the first operational amplifier is provided with the reference threshold voltage, the second input end of the first operational amplifier is provided with the control threshold voltage, and an error voltage is output from the output end of the first operational amplifier. The back gate driving circuit is configured to generate the back gate voltage according to the error voltage.

2. The control circuit of claim 1, wherein, The control MOS tube and the target MOS tube are PMOS transistors, and the temperature deviation detection circuit further includes a first current source and a first voltage control circuit, The first current source is coupled to the second electrode of the control MOS tube, and is configured to provide a first constant current to the control MOS tube. The first voltage control circuit is configured to generate a first control voltage, and the first control voltage is equal to the sum of the control threshold voltage and the source-gate voltage of the target MOS tube. The control electrode of the control MOS tube is coupled to the second electrode of the control MOS tube, the first electrode of the control MOS tube is provided with the first control voltage, and the control threshold voltage is output from the second electrode of the control MOS tube.

3. The control circuit of claim 1, wherein, The control MOS tube and the target MOS tube are NMOS transistors, and the temperature deviation detection circuit further includes a first current source and a second voltage control circuit, The first current source is coupled to the first electrode of the control MOS tube, and is configured to provide a first constant current to the control MOS tube. The second voltage control circuit is configured to generate a second control voltage, and the second control voltage is equal to the sum of the control threshold voltage and the gate-source voltage of the target MOS tube. The control electrode of the control MOS tube is coupled to the second electrode of the control MOS tube, the second electrode of the control MOS tube is provided with the second control voltage, and the control threshold voltage is output from the first electrode of the control MOS tube.

4. The control circuit of any one of claims 1 to 3, wherein, The reference MOS tube is a PMOS transistor, and the reference threshold voltage generation circuit further includes a second current source, Wherein, the second current source is coupled to the second terminal of the reference MOS transistor, and the second current source is configured to provide a second constant current to the reference MOS transistor; The control electrode of the reference MOS transistor is coupled to the second electrode of the reference MOS transistor, and the first electrode of the reference MOS transistor is coupled to the first voltage terminal. The reference threshold voltage is output from the control electrode of the reference MOS transistor.

5. The control circuit of any one of claims 1 to 3, wherein, The reference MOS transistor is an NMOS transistor, and the reference threshold voltage generation circuit further includes a second current source. Wherein, the second current source is coupled to the second terminal of the reference MOS transistor, and the second current source is configured to provide a second constant current to the reference MOS transistor; The control terminal of the reference MOS transistor is coupled to the second terminal of the reference MOS transistor, and the first terminal of the reference MOS transistor is coupled to the second voltage terminal. The reference threshold voltage is output from the control terminal of the reference MOS transistor.

6. The control circuit of claim 4 or 5, the reference threshold voltage generation circuit further comprising: Process deviation detection circuit and adjustment circuit, The process deviation detection circuit is configured to generate a trimming voltage based on a second voltage difference between a reference voltage and the reference threshold voltage. The adjustment circuit is configured to: generate an adjustment current based on the adjustment voltage and supply the adjustment current to the reference MOSFET from the second terminal of the reference MOSFET, thereby adjusting the reference threshold voltage; The adjustment current is negatively correlated with the second voltage difference.

7. The control circuit of any one of claims 1-3, the reference threshold voltage generation circuit further comprising: Second current source, process deviation detection circuit and adjustment circuit Wherein, the second current source is coupled to the second terminal of the reference MOS transistor, and the second current source is configured to provide a second constant current to the reference MOS transistor; The control terminal of the reference MOS transistor is coupled to the second terminal of the reference MOS transistor. When the reference MOS transistor is a PMOS transistor, the first terminal of the reference MOS transistor is coupled to the first voltage terminal. When the reference MOS transistor is an NMOS transistor, the first terminal of the reference MOS transistor is coupled to the second voltage terminal. The process deviation detection circuit is configured to generate a trimming voltage based on a second voltage difference between a reference voltage and the reference threshold voltage. The adjustment circuit includes: a switch control circuit, multiple voltage-controlled switches, a first resistor and multiple second resistors connected in series between the first voltage terminal and the second voltage terminal; The first end of the first resistor is coupled to the first voltage terminal, the second end of the first resistor is coupled to the control electrode of the reference MOSFET and the first end of a second resistor, the first end of each second resistor is coupled to the first end of a voltage-controlled switch, the second end of the last second resistor away from the first resistor is coupled to the second voltage terminal, and the second end of each voltage-controlled switch is coupled to the output terminal of the trimming circuit, from which the reference threshold voltage is output; The switch control circuit is configured to control one of the plurality of voltage-controlled switches to close according to the adjustment voltage, such that the equivalent resistance value between the first voltage terminal and the output terminal is negatively correlated with the second voltage difference.

8. The control circuit of claim 1, wherein, The back gate voltage adjustment circuit also includes: an overvoltage protection circuit. The overvoltage protection circuit is configured to provide an enable signal at an invalid level to the back gate drive circuit when the back gate voltage is higher than a preset safe voltage. The back gate drive circuit is further configured to limit the back gate voltage to the preset safe voltage when the enable signal is at the invalid level.

9. A control circuit for controlling threshold voltage variation of a target MOS transistor, comprising: Reference MOSFET, control MOSFET, first current source, first voltage control circuit, second current source, first operational amplifier, second operational amplifier, third operational amplifier, first voltage-controlled switch, second voltage-controlled switch, inverter, first drive circuit, second drive circuit, and adjustment circuit. Wherein, the reference MOS transistor, the control MOS transistor, and the target MOS transistor are PMOS transistors, the size of the control MOS transistor is the same as the size of the target MOS transistor, and the back gate of the control MOS transistor is coupled to the back gate of the control MOS transistor. The first current source is coupled to the second terminal of the control MOS transistor, and the first current source is configured to provide a first constant current to the control MOS transistor; The first voltage control circuit is configured to generate a first control voltage, which is equal to the sum of a reference threshold voltage and the source-gate voltage of the target MOS transistor, wherein the reference threshold voltage is the voltage at the second terminal of the reference MOS transistor; The control electrode of the control MOS transistor is coupled to the second electrode of the control MOS transistor, and the first electrode of the control MOS transistor is provided with the first control voltage; The second current source is coupled to the second terminal of the reference MOSFET, and the second current source is configured to provide a second constant current to the reference MOSFET. The control terminal of the reference MOS transistor is coupled to the second terminal of the reference MOS transistor, and the first terminal of the reference MOS transistor is coupled to the first voltage terminal. A reference threshold voltage is output from the control terminal of the reference MOS transistor. The reference threshold voltage is provided at the first input terminal of the first operational amplifier, the reference threshold voltage is provided at the second input terminal of the first operational amplifier, and an error voltage is output from the output terminal of the first operational amplifier; The first input terminal of the second operational amplifier is provided with a preset safety voltage, the second input terminal of the second operational amplifier is coupled to the back gate of the target MOS transistor, and an enable signal is output from the output terminal of the second operational amplifier; The first driving circuit is configured to increase the driving force of the error voltage to generate a first driving voltage; The second driving circuit is configured to increase the driving force of the preset safety voltage to generate a second driving voltage; The controlled terminal of the first voltage-controlled switch is provided with the enable signal, the first terminal of the first voltage-controlled switch is provided with the first drive voltage, and the second terminal of the first voltage-controlled switch is coupled to the back gate of the target MOS transistor. The inverter's input terminal is provided with the enable signal, and the inverter's output terminal is coupled to the controlled terminal of the second voltage-controlled switch; The first terminal of the second voltage-controlled switch is provided with the second drive voltage, and the second terminal of the second voltage-controlled switch is coupled to the back gate of the target MOS transistor; The first input terminal of the third operational amplifier is provided with a reference voltage, the second input terminal of the third operational amplifier is provided with the reference threshold voltage, and the adjustment voltage is output from the output terminal of the third operational amplifier; The adjustment circuit is configured to: generate an adjustment current based on the adjustment voltage and supply the adjustment current to the reference MOSFET from the second terminal of the reference MOSFET, thereby adjusting the reference threshold voltage; The adjustment current is negatively correlated with the adjustment voltage.

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