One-time-programmable memory cell and memory thereof

Abstract

The present invention relates to a one-time programmable memory cell, a memory cell group and a memory thereof. The memory cell comprises a first select transistor, a sense transistor, a second select transistor and a gate capacitor in a substrate, wherein the first select transistor and the sense transistor are connected in series, the second select transistor and the gate capacitor are connected in series, and the sense transistor and the gate capacitor share a gate. The memory cell and the memory thereof can be prepared with advanced standard process, and have stable and reliable performance, low power consumption, fast programming and reading speed and high sensitivity.

Description

Technical Field

[0001] This invention relates to a non-volatile memory cell and its memory, and more particularly to a one-time programmable non-volatile memory cell and its memory, specifically to an antifuse type one-time programmable non-volatile memory cell and its memory. Background Technology

[0002] Non-volatile memory has the advantage that data stored in it will not disappear even when power is off, and it can retain data for a long time. Therefore, it is currently widely used in electronic devices.

[0003] Non-volatile memory is divided into erasable programmable memory (EPM) and one-time programmable memory (OTP). EEPM generally has large storage cells, which cannot meet the needs of large-capacity storage, and it is also expensive. Therefore, one-time programmable (OTP) memory is popular in some applications and markets.

[0004] Based on their characteristics, once-programmable memories (OTPs) can be categorized into floating-gate, electro-fuse, and anti-fuse types. Floating-gate OTP cells achieve high- and low-resistance switching by changing the threshold voltage of the device after electron or hole injection into the floating gate. Electro-fuse OTP cells are in a low-resistance state before programming and in a high-resistance state after programming, typically achieved through electromigration of the polysilicon gate. Anti-fuse cells are in a high-resistance state before programming and in a low-resistance state after programming.

[0005] Floating-gate OTP memories compatible with standard processes require I / O devices with a gate oxide thickness greater than 65 Å to ensure good data retention. Processes of 90nm and above can meet this requirement. However, on 55nm / 40nm or lower process platforms, the gate oxide thickness of I / O devices at 2.5V and below is less than 60 Å. On these process platforms, floating-gate OTP memories cannot guarantee good data retention, thus failing to achieve full compatibility with standard processes and making them difficult to apply to more advanced processes. Furthermore, with the continuous miniaturization of semiconductor manufacturing processes, electrons or holes trapped by floating-gate OTPs on advanced processes are easily leaked, leading to data loss.

[0006] Electric fuse type OTP is limited by polysilicon gates. If advanced processes replace polysilicon gates with metal gates, its use will be further limited.

[0007] Antifuse-type OTPs are programmed based on the physical breakdown mechanism of the gate oxide layer, eliminating the risk of electron or hole leakage. Furthermore, their breakdown is irreversible, resulting in superior reliability. They are also not limited by polysilicon gates and exhibit high compatibility with advanced processes. Consequently, they have attracted considerable attention and made significant progress in recent years.

[0008] Currently, there is a continuous demand in the industry for antifuse OTP memories with constantly optimized structure and performance, especially for low-power, high-speed antifuse OTP memories. Summary of the Invention

[0009] A first aspect of the present invention relates to a one-time programmable memory cell comprising: a first selection transistor, a detection transistor, a second selection transistor, and a gate capacitor, located in a substrate; wherein the first selection transistor and the detection transistor are connected in series, and the second selection transistor and the gate capacitor are connected in series; and the detection transistor and the gate capacitor share a gate.

[0010] In a preferred embodiment, the gate capacitor has a thin gate oxide layer, which is thinner than that of the two select transistors. More preferably, the detection transistor also has a thin gate oxide layer, which is thinner than that of the two select transistors.

[0011] In another preferred embodiment, the gate capacitor has an ion-doped region below the gate oxide layer, located in the substrate, and completely overlapping the entire lower surface of the gate oxide layer.

[0012] In another preferred embodiment, the two select transistors and the detection transistor are of the same type, and the ion-doped region of the gate capacitor is of the same type as the three transistors. More preferably, the two select transistors and the detection transistor are NMOS transistors, and the ion-doped region beneath the gate oxide layer of the gate capacitor is an N-type doped region.

[0013] In another preferred embodiment, the first selection transistor and the second selection transistor share a common gate.

[0014] The second aspect of the present invention relates to a one-time programmable memory cell group, comprising four memory cells as described above, arranged in a centrally symmetrical array of 2 rows × 2 columns, with the substrates of all memory cells being integrated into one unit; two memory cells in each row of the group are left-right mirror symmetrical, wherein the two detection transistors in the two cells share a common source, and their drains coincide with the sources of the first selection transistors in their respective cells; two gate capacitors are adjacent to each other in the middle of the row, without contacting each other, and the ion-doped region of each gate capacitor is respectively bonded to the source of the second selection transistor in its respective cell; two selection transistors in one cell are arranged on one side of the group, and two selection transistors in another cell are arranged on the other side of the group; two memory cells in each column are vertically mirror symmetrical, all selection transistors in the column are vertically aligned, and the gates of two adjacent second selection transistors or two first selection transistors in two cells are connected.

[0015] In a preferred embodiment, the four storage cells in the group have the same structure, composition, and components.

[0016] In another preferred embodiment, the group further includes: a common line in each row connected to the common source of two detection transistors in that row; a bit line in each row connected to the drain of the first selection transistor of each memory cell in that row; a programming line in each row connected to the drain of the second selection transistor of each memory cell in that row; a programming line in each row connected to the gate capacitance of each memory cell in that row and the common gate of the detection transistor; and two / or one word line in each column connected to the two gates of the first and second selection transistors / or the common gate of the first and second selection transistors in each memory cell in that column.

[0017] A third aspect of the present invention relates to a one-time programmable memory, comprising: at least one group of memory cells as described above, forming an array, wherein each group in the array has the same arrangement and the substrates of the memory cells in each group are merged into one to form the substrate of the array; wherein: in each row, two adjacent first selection transistors in two adjacent groups share a drain, and two adjacent second selection transistors in two adjacent groups also share a drain; in each column, the gates of two adjacent second selection transistors or two adjacent first selection transistors in two adjacent groups are connected; the common line, bit line, programming line, and programming line of each group in each row are respectively connected to form the common line, bit line, programming line, and programming line of that row; and the two / or one word line of each group in each column are respectively connected / or connected to form the two / or one word line of that column.

[0018] In a preferred embodiment, the structures, compositions, and components of each group in the array are identical.

[0019] The antifuse-type one-time programmable memory cell and its memory of the present invention, through optimized structure and arrangement, can quickly and efficiently implement breakdown programming, with stable and reliable performance; moreover, it has low power consumption, fast programming and reading speed, high reading sensitivity, and can be manufactured compatible with advanced standard processes.

[0020] The one-time programmable memory unit and its memory of the present invention can be manufactured using standard processes of 130nm, 110nm, 90nm, or from 55nm down to 7nm. Attached Figure Description

[0021] Figure 1 A top view of a storage cell according to one embodiment of the present invention is shown.

[0022] Figures 1a-1d They are shown respectively Figure 1 The cross-sectional view of the storage cell shown is obtained along the section lines aa, bb, cc, dd.

[0023] Figure 2 A top view of a storage cell according to another embodiment of the present invention is shown.

[0024] Figure 3 A top view of an array of storage cells according to one embodiment of the present invention is shown.

[0025] Figure 4 It shows Figure 3 The array circuit diagram of the storage cell group shown.

[0026] Figure 5 It shows Figure 3 The bias signals connected to the memory cell array shown are displayed during different operations.

[0027] Figure 6 Multiple Figure 3 A top view of the array formed by the shown memory cell groups. Detailed Implementation

[0028] Detailed description of the invention

[0029] The same numbers in the attached figures indicate similar elements.

[0030] The embodiments of the present invention are illustrated by way of example and are not limited to the examples shown in the accompanying drawings. It should be understood that the drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related embodiments and their accompanying drawings can be obtained from these drawings without creative effort.

[0031] The storage cell structure of this invention can be fabricated in accordance with advanced standard processes, and has stable and reliable performance, low power consumption, fast programming and reading speed, and high sensitivity.

[0032] The antifuse-type one-time programmable (OTP) memory cell of the present invention includes two select transistors, a gate capacitor, and a detection transistor. The first select transistor and the detection transistor are connected in series, and the second select transistor is connected in series with the gate capacitor. The detection transistor and the gate capacitor share a common gate.

[0033] Each of the three transistors includes a gate, a gate oxide layer below the gate, and a drain and a source below the gate oxide layer. The gate capacitance includes the gate, the gate oxide layer below the gate, and an ion-doped region below the gate oxide layer. They are located in a P-well (PW) or an N-well; specifically, the drain and source, as well as the ion-doped region, are located within a P-well or N-well. The P-well or N-well is located in a P-type substrate, and the well is preferably a P-well.

[0034] The ion-doped region of the gate capacitor coincides with the source of the second selection transistor. During programming, the second selection transistor is turned on, thereby allowing the ion-doped region beneath the gate oxide layer of the gate capacitor to obtain a low potential through the second selection transistor connected in series with it. Simultaneously, a high potential is applied to the gate of the gate capacitor, causing the gate oxide layer to break down under the voltage difference across it.

[0035] The drain of the detection transistor coincides with the source of the first selection transistor. During programming, the first selection transistor is turned on, thereby the drain of the detection transistor receives a high potential through the first selection transistor connected in series with it. At the same time, a high potential is also applied to the source of the detection transistor. In this way, the detection transistor is protected from breakdown during programming and is not damaged. In the read operation after breakdown programming, the read current is amplified, improving the read speed and sensitivity.

[0036] The gate oxide thickness of the two select transistors is a conventional value, preferably equal in thickness.

[0037] The gate capacitor preferably has a thin gate oxide layer, which is thinner than the two select transistors. This allows for a lower operating voltage, reduced power consumption, and increased programming speed. Simultaneously, in the structure of this invention, the detection transistor also preferably has a thin gate oxide layer, thereby further reducing power consumption and increasing readout speed. More preferably, the gate oxide layer thickness of the gate capacitor is equal to the gate oxide layer thickness of the detection transistor.

[0038] The ratio of the gate oxide layer thickness of the selected transistor to the gate capacitor is 1.1:1-20:1, preferably 1.2:1-15:1, more preferably 1.3:1-10:1, even more preferably 1.4:1-5:1, and most preferably 1.5:1-3.5:1. Similarly, the ratio of the gate oxide layer thickness of the selected transistor to the detection transistor is 1.1:1-20:1, preferably 1.2:1-15:1, more preferably 1.3:1-10:1, even more preferably 1.4:1-5:1, and most preferably 1.5:1-3.5:1.

[0039] The gate capacitor has an ion-doped region beneath the gate oxide layer, located within the substrate. In the case of a well in the substrate, the region is located within the well. The ion-doped region preferably overlaps the entire lower surface of the gate oxide layer. This effectively prevents leakage current between the gate and the substrate during programming and readout processes.

[0040] In the memory cell of this invention, the first selection transistor is of the same type as the detection transistor, and the second selection transistor is of the same type as the ion-doped region of the gate capacitor. Preferably, all three transistors are of the same type, and the ion-doped region of the gate capacitor is of the same type as the source and drain of the three transistors.

[0041] More preferably, the two select transistors and the detector transistor are NMOS transistors, and the ion-doped region below the gate oxide layer of the gate capacitor is an N-type doped region. In this case, it is preferable that there is a P-well in the substrate, and the three NMOS transistors and the gate capacitor are located in the P-well.

[0042] When the two selection transistors are of the same type, it is preferable that the gates of the first selection transistor and the second selection transistor are connected and share a gate. This can further simplify the memory cell structure and make the operation more convenient, as both selection transistors can be turned on or off at the same time.

[0043] The two selection transistors can also be independent of each other's gates. This allows the first selection transistor to be turned on before programming begins, providing a high potential to the drain of the detection transistor and applying a high potential to its source. Then, the second selection transistor is turned on to perform programming. This method better protects the detection transistor from damage during programming.

[0044] The one-time programmable memory cell group of the present invention includes four memory cells as described above, arranged in a centrally symmetrical array of 2 rows × 2 columns, with the substrates of all memory cells merged into one.

[0045] In each row of the group, the two memory cells are mirror-symmetrical from left to right. The two detection transistors of the two cells share a common source, and the two gate capacitors are adjacent to each other in the middle of the row, without touching each other. The two selection transistors of one cell are arranged on one side of the group, and the two selection transistors of the other cell are arranged on the other side of the group. The two memory cells in each column are mirror-symmetrical from top to bottom. The four selection transistors in each column are aligned vertically. The gates of the two adjacent second selection transistors or the two first selection transistors of the two cells are connected vertically to form a single unit.

[0046] In the case where the first and second selection transistors in each cell share a gate, the gates of the four selection transistors in each column are connected to form a common gate.

[0047] Preferably, the four storage cells in the storage cell group have the same structure, composition, and components.

[0048] The memory cell group of the present invention preferably further includes: a common line, a bit line, a programming line, and a programming line in each row, respectively connected to the common source of two detection transistors in the row, the drain of the first selection transistor of each memory cell in the row, the drain of the second selection transistor of each memory cell in the row, and the gate capacitance of each memory cell in the row and the common gate of the detection transistor; and two / or one word line in each column, respectively connected to the two gates of the first and second selection transistors in each memory cell in the column and / or the common gate of the first and second selection transistors.

[0049] The one-time programmable memory of the present invention includes at least one group of memory cells as described above, forming an array. Each group in the array has the same arrangement, and the substrates of the memory cells in each group are merged into one to form the substrate of the array.

[0050] In the array, the two adjacent first selection transistors in each row share a drain, and the two adjacent second selection transistors in each row also share a drain; the gates of the two adjacent second selection transistors or the two first selection transistors in each column are connected; the common lines, bit lines, programming line bottoms, and programming lines of each group in each row are connected to form the common lines, bit lines, programming line bottoms, and programming lines of that row; the two / or one word lines of each group in each column are connected / or connected to form the two / or one word lines of that column.

[0051] In the case where the first and second selection transistors of each cell in each group share a gate, the gates of all selection transistors in each column are connected to form a common gate.

[0052] Preferably, in the array, the structure, composition, and components of each group are completely identical.

[0053] In the storage cell group and array of the present invention, each non-volatile storage cell can be programmed independently.

[0054] The one-time programmable memory unit and its memory of the present invention can be fabricated using conventional processes that are mature in the industry, such as 130nm, 110nm, and 90nm standard processes, or they can be fabricated using advanced processes, such as standard processes from below 55nm to 7nm.

[0055] When the gate oxide layer thicknesses of the two select transistors and the gate capacitor differ, the different gate oxide layer thicknesses are formed using industry-standard growth methods in the fabrication process. For example, using a thermal oxidation method, a gate oxide layer of thickness 1 is first grown in the region where the gate oxide layer of the select transistor and the gate oxide layer of the gate capacitor are to be formed. Then, the existing gate oxide layer 1 in the region where the gate oxide layer of the gate capacitor is to be formed is completely removed by wet etching. Then, a new gate oxide layer is formed simultaneously in the gate oxide regions of the select transistor and the gate capacitor using another thermal oxidation method, achieving the desired gate capacitor thickness. Here, thickness 1 is the difference between the thickness of the gate oxide layer of the select transistor and the gate oxide layer of the gate capacitor. The gate oxide layer of the detection transistor with a thin gate oxide layer is grown in the same way as that of the gate capacitor described above.

[0056] The N-type ion-doped region beneath the gate oxide layer of the gate capacitor preferably overlaps completely with the entire lower surface of the gate oxide layer, and is formed through a doping region extension step or an ion implantation step. Specifically, in the standard process described above, in the conventional steps of forming the source and drain of the transistor, two N-type ion-doped regions are simultaneously formed on both sides of the gate of the gate capacitor, and then the two ion-doped regions are extended to form an N-type extended region for the gate and the channel region beneath the gate oxide layer; or, before forming the two N-type ion-doped regions, N-type ions are implanted into the channel region between the two doped regions to form an N-type doped channel region between the gate and the gate oxide layer, and then two ion-doped regions are formed on both sides of the gate.

[0057] The storage cell and its group structure and array structure of the present invention will now be described with reference to the accompanying drawings. Obviously, the specific embodiments described in the drawings are only a part of the embodiments of the present invention, and not all of them. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0058] Figure 1 A top view of a storage cell according to one embodiment of the present invention is shown. Figures 1a-1dThe cross-sectional views of the storage cell along the profile lines aa, bb, cc, and dd are shown respectively.

[0059] The memory cell includes a first selection transistor S1, a detection transistor T1 connected in series with S1, a second selection transistor S2, and a gate capacitor C1 connected in series with S2. The detection transistor T1 and the gate capacitor C1 share a common gate, and the two selection transistors S1 and S2 also share a common gate.

[0060] S1, S2, and T1 are all of the same type, NMOS transistors, each consisting of a gate, a gate oxide layer below the gate, and an N-type drain and source below the gate oxide layer. The gate capacitance C1 includes the gate, the gate oxide layer below the gate, and an N-type ion-doped region below the gate oxide layer. They are all located in a P-well (PW), which is situated in a P-type substrate.

[0061] The gate oxide thicknesses in the two select transistors S1 and S2 are equal, and the gate oxide thicknesses in T1 and C1 are equal. The gate oxide thicknesses of the two select transistors are standard values, while the gate oxide thicknesses of T1 and C1 are thinner than those of the select transistors. The ratio of the gate oxide thickness of the select transistor to that of the detection transistor T1 (or gate capacitor C1) is 3.5:1.

[0062] The detection transistor T1, gate capacitor C1, and select transistors S1 and S2 are fabricated on the same 110nm standard process platform. Detection transistor T1 and gate capacitor C1 are 1.5V devices, while select transistors S1 and S2 are 5V devices. Detection transistor T1 and gate capacitor C1 are low-voltage devices with thin gate oxide, located in a low-voltage P-well (LVPW), while select transistors S1 and S2 are medium-voltage devices with thick gate oxide, located in a medium-voltage P-well (MVPW).

[0063] The drain of the first selection transistor S1 is connected to the bit line (BL), and its source coincides with the drain of the detection transistor T1. The source of the detection transistor T1 is connected to the common line (COM).

[0064] The drain of the second selection transistor S2 is connected to the programming baseline (PS), and the source is bonded to the N-type doped region of the gate capacitor C1. The N-type doped region of the gate capacitor C1 overlaps the entire lower surface of its gate oxide layer.

[0065] The common gate of the two select transistors is connected to the word line (WL), and the common gate of the sense transistor and the gate capacitor is connected to the programming line (PL). There is only one word line WL in this memory cell.

[0066] Figure 1c-1d The FOX in the diagram is a shallow trench isolation region filled with a thick field oxide layer. Both the transistor and the gate capacitor are surrounded by shallow trenches.

[0067] The gates of the two selection transistors S1 and S2 can also be separate, such as... Figure 2As shown. In this case, the gate of the first selection transistor is connected to word line 1 (WL1), and the gate of the second selection transistor is connected to word line 2 (WL2).

[0068] Figure 3 Four were shown Figure 1 The top view of the array of storage cells shown. Figure 4 This is the circuit diagram of the array.

[0069] The four memory cells in this array are located on the same P-type substrate and arranged in a centrally symmetrical array of 2 rows × 2 columns. The four memory cells in the group are identical, including identical structure, composition, and components, only differing in their arrangement and orientation.

[0070] The two memory cells 101 and 102 in the first row are mirror images of each other. The two detection transistors T1 in both cells share a common source and are connected to a common line COM0. The two gate capacitors C1 are adjacent to each other in the middle of the row, but do not touch. The two selection transistors in cell 101 are located on the right side of the group, and the two selection transistors in cell 102 are located on the left side of the group.

[0071] The two storage cells 103 and 104 in the second row are arranged in the same way as those in the first row, but are mirror images of the first row.

[0072] The two memory cells 101 and 103 in the first column are mirror images of each other, and the gates of the two adjacent second selection transistors S2 in the two cells are connected vertically. Because the first and second selection transistors in each cell share a gate, all four selection transistors in the first column share a gate and are connected to a word line WL0.

[0073] The two storage cells 102 and 104 in the second column are arranged in the same way as those in the first column, but are mirror images of the first column.

[0074] In each row, two adjacent low-pressure P-wells (LVPWs) of two cells are merged into one.

[0075] In each column, the two medium-pressure P-wells (MVPWs) of two cells are merged into one, and the two low-pressure P-wells (LVPWs) are also merged into one.

[0076] In the array, each row has a common line COM connected to the common source of two adjacent detection transistors in that row; each row has a bit line BL and a programming line PS connected to the drain of the first selection transistor S1 and the drain of the second selection transistor S2 of each memory cell in that row, respectively; and a programming line PL connected to the common gate of the gate capacitance and detection transistors of each memory cell in that row. Each column has a word line WL connected to the common gate of the selection transistors of the memory cells in that column.

[0077] Figure 5 It shows Figure 3 The bias signals connected to the memory cell array shown are displayed during different operations.

[0078] Each memory cell in the group can be programmed independently. During programming, a high voltage difference is applied between the gate of the programming cell's gate capacitor and the N-doped region beneath the gate oxide layer, causing the gate oxide layer to break down and forming a conductive path from the N-doped region to the gate.

[0079] For example, memory cell 101 in the designated group is a programming cell. Memory cell 101 is programmed as follows: the word line WL and programming line PL are driven to potentials of 5.0V and 4.5V respectively; the bit line BL and common line COM are driven to potentials of 1.5V; and the PS and P-wells (LVPW and MVPW) are driven to potentials of 0V. The high potential of word line WL causes select transistors S1 and S2 to conduct rapidly, thereby giving the N-ion doped region of gate capacitor C1 a potential of 0V equal to the programming line PS; simultaneously, the drain of detection transistor T1 receives a potential equal to the drain of select transistor S1, i.e., the potential of bit line BL, 1.5V. The gate of the gate capacitor receives a high potential of 4.5V through programming line PL, while the potential of the N-ion doped region below it is 0V, thus creating a high voltage difference across the gate oxide layer, leading to gate oxide layer breakdown and programming. Although the gate of the detection transistor T1 also receives a high potential of 4.5V through the programming line PL, the potential of its drain and source (COM) is 1.5V, and the voltage difference across the gate oxide layer is insufficient to cause breakdown.

[0080] The potential of word line WL in memory cell 102 is 0V, and the other drive potentials are the same as in cell 101. The two select transistors cannot conduct, thus the N-ion doped region below gate capacitor C1 is in a floating state. Although the potential of the gate capacitor (programming line PL) is 4.5V, there is a lack of voltage difference across the gate oxide layer that would cause breakdown, preventing programming.

[0081] The programming line PL of memory cell 103 has a potential of 0V, and the other drive potentials are the same as those of cell 101. The gate potential of the gate capacitor is 0V, which is equal to the potential of the N-ion doped region below it, so the gate oxide layer cannot be broken down.

[0082] The potentials of the word line WL, programming line PL, and programming line PS of memory cell 104 are all 0V. The select transistor cannot be turned on, and the gate potential of the gate capacitor is 0V, so the gate oxide layer cannot be broken down.

[0083] During the readout operation, both the series-connected detection transistor T1 and the selection transistor S1 need to be turned on, and there is a voltage difference between the source (COM) and drain of the detection transistor T1. Then, a readout current is generated between the source (COM) of the detection transistor T1 and the drain (BL) of the selection transistor S1.

[0084] Memory cell 101 is designated as the read cell. The potential of the driving word line WL and bit line BL is 1.5V, the programming line PS is 1V, the common line COM and P-well are 0V, and the programming line PL is in a floating state. The 1.5V potential of the word line WL turns on the select transistors S1 and S2, thereby giving the N-type doped region of the gate capacitor C1 a potential of 1V equal to the programming line PS, and the drain of the detection transistor T1 a potential equal to the drain of the select transistor S1, i.e., the potential of the bit line BL is 1.5V. Due to the breakdown of the gate oxide layer of the gate capacitor, a conductive path is formed, and its gate potential is equal to that of the underlying N-type doped region. This gate potential is greater than the threshold of the thin gate oxide detection transistor T1, causing the detection transistor T1 to turn on. Because there is a voltage difference between the source (COM) potential of 0V and the drain potential of 1.5V of the detection transistor T1, a read current is generated from the source to the drain.

[0085] The word line WL of memory cell 102 is 0V, and the other driving potentials are the same as those of cell 101. The select transistor cannot be turned on, and the gate oxide layer of the gate capacitor C1 has not been broken down for programming. The programming line PL is in a floating state. Therefore, the gate of the gate capacitor cannot obtain a potential. As a result, the detection transistor T1 cannot be turned on, and there is no voltage difference between its source and drain, so no read current can be generated.

[0086] The bit line BL and programming line PS of memory cell 103 have a potential of 0V, while the other drive potentials are the same as those of cell 101. Since the word line WL is 1.5V, select transistors S1 and S2 are turned on, and the N-type doped region below the gate capacitor C1 obtains a potential of 0V. Because the gate oxide layer of the gate capacitor has not been broken down for programming, and the programming line PL is floating, the gate cannot obtain a potential, thus the detection transistor T1 cannot be turned on, and no read current can be generated.

[0087] The relevant drive potentials of memory cell 104 are all 0V, and the programming line PL is floating. Neither of the two select transistors nor the detection transistor T1 can conduct, and no read current can be generated from the source (COM) to the drain (BL) of the detection transistor T1.

[0088] and Figure 1 The storage units shown are the same. Figure 2 The storage units shown can also be arranged as follows: Figure 3The 2×2 array shown has the same array arrangement, array structure, and operation method as described above. Figure 1 The memory cells shown are identical; their bias signals during operation are the same as those shown. Figure 5 The similarities shown are different in that: Figure 2 In the memory cell array shown, each column has two bit lines, which are respectively connected to the first and second selection transistors of each memory cell in that column. The potential values ​​of the two bit lines are the same in each operation process, and are also the same as... Figure 5 The potential is the same in each operation of the bit line BL.

[0089] Figure 6 Multiple Figure 3 The image shows a top view of the array formed by the groups of memory cells. Each group in the array has the same arrangement, and the substrates of the memory cells in each group are merged into one to form the substrate of the array.

[0090] In this array, the two adjacent first selection transistors in each row share a drain, and the two adjacent second selection transistors in each row also share a drain. The gates of the two adjacent first selection transistors S1 in each column are connected vertically. Because the four selection transistors in each group in each column share a gate, all selection transistors in each column are connected, forming a common gate. The common lines, bit lines, programming line base lines, and programming lines of each group in each row are connected to form the common lines, bit lines, programming line base lines, and programming lines of that row; the word lines of each group in each column are connected to form the word lines of that column.

[0091] In each row, the two adjacent medium-pressure P-wells (MVPWs) of two adjacent groups are merged into one. In each column, the low-pressure P-wells (LVPWs) of all groups are merged into one, and the medium-pressure P-wells (MVPWs) are also merged into one.

[0092] The antifuse-type one-time programmable (OTP) memory cell and its memory array of the present invention can be fabricated in compatibility with advanced standard processes, and have stable and reliable performance, low power consumption, fast programming and reading speed, and high sensitivity.

Claims

1. A one-time programmable memory cell, comprising: include: A first selection transistor, a detection transistor, a second selection transistor, and a gate capacitor are located in a substrate; The first selection transistor is connected in series with the detection transistor, and the second selection transistor is connected in series with the gate capacitor; moreover, the detection transistor and the gate capacitor share a common gate.

2. The memory cell of claim 1, wherein the gate capacitor has a thin gate oxide layer, the thickness of which is thinner than that of the two select transistors.

3. The memory cell of claim 2, wherein the detection transistor also has a thin gate oxide layer, the thickness of which is thinner than that of the two selection transistors.

4. The memory cell according to any one of claims 1-3, wherein the gate capacitor has an ion-doped region below the gate oxide layer, located in the substrate, overlapping the entire lower surface of the gate oxide layer.

5. The memory cell according to any one of claims 1-3, wherein the two selection transistors are of the same type as the detection transistors.

6. The memory cell of claim 5, wherein the two select transistors and the detect transistor are NMOS transistors, and the ion-doped region below the gate oxide layer of the gate capacitor is an N-type doped region.

7. The memory cell of claim 5, wherein the first selection transistor and the second selection transistor share a gate.

8. A one-time programmable storage unit group, characterized in that, It includes four memory cells as described in any one of claims 1-7, arranged in a centrally symmetrical array of 2 rows × 2 columns, with the substrates of all memory cells merged into one unit; The two memory cells in each row are mirror images of each other. The two detection transistors in the two cells share a source, and their drains coincide with the source of the first selection transistor in the cell. The two gate capacitors are adjacent to each other in the middle of the row and do not touch each other. The ion-doped region of each gate capacitor is connected to the source of the second selection transistor in the cell. The two selection transistors in one cell are arranged on one side of the group, and the two selection transistors in the other cell are arranged on the other side of the group. The two memory cells in each column are mirror images of each other, and all the select transistors in the column are aligned vertically. The gates of the two adjacent second select transistors or the two first select transistors in the two cells are connected.

9. The storage cell group as described in claim 8, wherein the four storage cells in the group have the same structure, composition, and components.

10. The storage cell group as described in any one of claims 8-9, further comprising: There is a common line in each row, which is connected to the common source of the two detection transistors in that row; Each row has a bit line that connects to the drain of the first selection transistor of each memory cell in that row; Each row has a programming baseline that connects to the drain of the second selection transistor in each memory cell within that row; There is one programming line in each row, which is connected to the gate capacitance of each memory cell in that row and the common gate of the detection transistor; Each column has two / or one word line, which are respectively connected to the two gates of the first and second selection transistors in each memory cell of that column, or the common gate of the first and second selection transistors.

11. A one-time programmable memory, characterized in that, It includes: At least one group of memory cells according to any one of claims 8-10 constitutes an array, wherein each group in the array has the same arrangement, and the substrates of the memory cells in each group are merged into one to form the substrate of the array; wherein: In each row, the two adjacent first selection transistors in two adjacent groups share a drain, and the two adjacent second selection transistors in two adjacent groups also share a drain. In each column, the gates of two adjacent second selection transistors or two first selection transistors in two adjacent groups are connected. The common lines, bit lines, programming bottom lines, and programming lines of each group in each row are connected to form the common lines, bit lines, programming bottom lines, and programming lines of that row; The two / or one word lines in each group of each column are connected / or linked together to form the two / or one word lines of that column.

12. The memory structure of claim 11, wherein the structures, compositions, and components of each group in the array are completely identical.

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