Display panel and display device

Abstract

Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a substrate including a display area and a peripheral area, the display area including an outer boundary; a first electrode layer disposed on the substrate, a first electrode of a plurality of sub-pixels being located on the first electrode layer; a pixel definition layer disposed on a side of the first electrode layer away from the substrate; and a spacer layer disposed on a side of the pixel definition layer away from the substrate. The display panel further includes at least one blocking dam disposed on the substrate, the at least one blocking dam being located in the peripheral area and on a side of the peripheral area away from the display area. The spacer layer includes a plurality of first spacers and a plurality of second spacers, the plurality of first spacers being arranged in the display area, the plurality of second spacers being arranged in the peripheral area, and the plurality of second spacers being located between the outer boundary and the at least one blocking dam; and a distribution density of the plurality of second spacers in the peripheral area is less than a distribution density of the plurality of first spacers in the display area.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, Organic Light Emitting Diode (OLED) display panels are increasingly being used in various electronic devices due to their advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and high response speed. Currently, in OLED display panels and display devices, photospaces (PS) are typically fabricated on the pixel boundary layer to prevent the fine photomask from directly contacting the pixel structure during the evaporation process of the OLED organic light-emitting material, which could scratch the pixel structure and cause defects.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display panel is provided, comprising:

[0005] A substrate, comprising a display area and a peripheral area, wherein the display area includes an outer boundary;

[0006] A plurality of sub-pixels are disposed in the display area, the plurality of sub-pixels are arranged in an array in the display area along a first direction and a second direction, and at least one of the sub-pixels includes a first electrode, a second electrode and a functional layer located between the first electrode and the second electrode;

[0007] A first electrode layer is disposed on the substrate, and the first electrodes of the plurality of sub-pixels are located in the first electrode layer;

[0008] A pixel defining layer disposed on the side of the first electrode layer away from the substrate;

[0009] A spacer layer disposed on the side of the pixel defining layer away from the substrate.

[0010] The display panel further includes at least one barrier dam disposed on the substrate, the at least one barrier dam being located in the peripheral region and on the side of the peripheral region away from the display area;

[0011] In the first and second directions, the outer boundary is adjacent to the outermost row of sub-pixels in the display area, and the outermost row of sub-pixels in the display area faces the side of the peripheral area.

[0012] The septum layer includes a plurality of first septums and a plurality of second septums, the plurality of first septums arranged in an array in the display area, the plurality of second septums arranged in an array in the peripheral area, and the plurality of second septums located between the outer boundary and the at least one barrier dam; and

[0013] The distribution density of the plurality of second spacers in the peripheral area is less than the distribution density of the plurality of first spacers in the display area.

[0014] According to some exemplary embodiments, two adjacent first spacers in a first direction are spaced apart by a first distance in the first direction, two adjacent second spacers in the first direction are spaced apart by a second distance in the first direction, the first distance being less than the second distance; and / or, two adjacent first spacers in a second direction are spaced apart by a third distance in the second direction, two adjacent second spacers in a second direction are spaced apart by a fourth distance in the second direction, the third distance being less than the fourth distance.

[0015] According to some exemplary embodiments, the outermost row of second diaphragms is spaced apart from the at least one barrier dam.

[0016] According to some exemplary embodiments, the display panel further includes a driving voltage lead disposed on the substrate and located in the peripheral region, the driving voltage lead being used to transmit a driving voltage; and the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the driving voltage lead on the substrate.

[0017] According to some exemplary embodiments, the peripheral region includes a first side peripheral region and a second side peripheral region, the first side peripheral region and the second side peripheral region being located on both sides of the display region in a first direction; the display panel further includes a scan driving circuit disposed on the substrate and located in at least one of the first side peripheral region and the second side peripheral region, the scan driving circuit being used to output a scan signal; the peripheral region includes a scan driving circuit region, the scan driving circuit region being located in at least one of the first side peripheral region and the second side peripheral region, the scan driving circuit being disposed in the scan driving circuit region, the scan driving circuit region being located between the driving voltage lead and the at least one blocking dam; the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the scan driving circuit region on the substrate.

[0018] According to some exemplary embodiments, a plurality of scan driving circuit regions are provided in at least one of the first side peripheral region and the second side peripheral region; the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of each of the plurality of scan driving circuit regions on the substrate.

[0019] According to some exemplary embodiments, the display panel further includes a first voltage lead and an auxiliary conductive portion, the first voltage lead being used to provide a first voltage, the auxiliary conductive portion being located on the same layer as the first electrode, and a portion of the auxiliary conductive portion being in direct contact with the first voltage lead; the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the first voltage lead on the substrate; and / or, the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the auxiliary conductive portion on the substrate.

[0020] According to some exemplary embodiments, the pixel defining layer includes a pixel defining layer body, the pixel defining layer body including a first portion and a second portion, the first portion being located in the display area and including an opening corresponding to the plurality of sub-pixels, the orthographic projection of the opening on the substrate being located within the orthographic projection of the first electrode of the plurality of sub-pixels on the substrate; the second portion being located in the peripheral area, and the second portion and the first portion being an integral structure; the pixel defining layer body including an outer boundary away from the display area; the peripheral area including a first side peripheral area and a second side peripheral area, the first side peripheral area and the second side peripheral area being located on both sides of the display area in a first direction; in at least one of the first side peripheral area and the second side peripheral area, the orthographic projection of some of the plurality of second spacers on the substrate is located on the side of the outer boundary of the pixel defining layer body closer to the display area, and the orthographic projection of other of the plurality of second spacers on the substrate is located on the side of the outer boundary of the pixel defining layer body away from the display area.

[0021] According to some exemplary embodiments, in at least one of the first side peripheral region and the second side peripheral region, for a second spacer located on the side of the outer boundary of the pixel defining layer body near the display area, in two adjacent rows of second spacers, the spacing between two adjacent second spacers in one row along the first direction is not equal to the spacing between two adjacent second spacers in the other row along the first direction.

[0022] According to some exemplary embodiments, in at least one of the first side peripheral region and the second side peripheral region, for a second spacer located on the side of the outer boundary of the pixel defining layer body away from the display area, in two adjacent rows of second spacers, the spacing between two adjacent second spacers in one row along the first direction is substantially equal to the spacing between two adjacent second spacers in the other row along the first direction.

[0023] According to some exemplary embodiments, the display panel further includes a planarization layer located on the side of the first electrode layer near the substrate; in at least one of the first side peripheral region and the second side peripheral region, the auxiliary conductive portion includes a plurality of first openings, each of which exposes a portion of the planarization layer; the pixel defining layer further includes a first cover portion covering the plurality of first openings; and the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the first cover portion on the substrate.

[0024] According to some exemplary embodiments, the peripheral region includes a third-side peripheral region located on one side of the display region in a second direction; in the third-side peripheral region, the pixel defining layer further includes a second cover portion, the auxiliary conductive portion includes a plurality of second openings, the plurality of second openings respectively exposing a portion of the planarization layer, and the second cover portion covering the plurality of second openings; in the third-side peripheral region, the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the second cover portion on the substrate.

[0025] According to some exemplary embodiments, in the third peripheral region, the pixel defining layer further includes a third cover portion, the auxiliary conductive portion includes a plurality of third openings, the plurality of third openings respectively expose a portion of the planarization layer, and the third cover portion covers the plurality of third openings.

[0026] According to some exemplary embodiments, in the third peripheral region, the orthographic projection of some of the plurality of second spacers on the substrate does not overlap with the orthographic projection of the plurality of third openings on the substrate.

[0027] According to some exemplary embodiments, the peripheral region includes a fourth side peripheral region located on the other side of the display region in a second direction; in the fourth side peripheral region, the pixel defining layer further includes a fourth cover portion, the auxiliary conductive portion includes a plurality of fourth openings, the plurality of fourth openings respectively exposing a portion of the planarization layer, and the fourth cover portion covering the plurality of fourth openings; in the fourth side peripheral region, the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the fourth cover portion on the substrate.

[0028] According to some exemplary embodiments, at least one row of second spacers located in at least one of the first side peripheral region and the second side peripheral region is substantially aligned with at least one row of first spacers located in the display area in a first direction.

[0029] According to some exemplary embodiments, at least one column of second spacers located in the third side peripheral region is substantially aligned with at least one column of first spacers located in the display region in a second direction.

[0030] According to some exemplary embodiments, the peripheral region includes a fourth side peripheral region located on the other side of the display area in a second direction; in the first side peripheral region, the second side peripheral region, the third side peripheral region and the fourth side peripheral region, the spacing between the orthographic projection of the outermost row of second spacers on the substrate and the orthographic projection of the at least one blocking dam on the substrate is substantially equal to each other.

[0031] According to some exemplary embodiments, the distance between the orthographic projection of the outermost row of second spacers on the substrate and the orthographic projection of the at least one barrier dam on the substrate is between 300 and 1000 micrometers.

[0032] According to some exemplary embodiments, the distribution density of the plurality of second spacers in the peripheral area is 1 / 4 to 2 / 3 of the distribution density of the plurality of first spacers in the display area.

[0033] According to some exemplary embodiments, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The pixel defining layer body includes an opening located in the display area and including an opening corresponding to the plurality of sub-pixels. The orthographic projection of the opening on the substrate is located within the orthographic projection of the first electrode of the plurality of sub-pixels on the substrate. The area of ​​the opening corresponding to the third sub-pixel on the orthographic projection of the substrate is greater than the area of ​​the opening corresponding to the first sub-pixel or the second sub-pixel on the orthographic projection of the substrate. The first spacer is adjacent to the opening corresponding to the third sub-pixel in a second direction.

[0034] According to some exemplary embodiments, the display panel further includes an encapsulation layer disposed on the side of the at least one barrier dam away from the substrate, the encapsulation layer including a first inorganic layer, an organic layer and a second inorganic layer stacked sequentially; the orthogonal projection of the organic layer on the substrate is located on the side of the orthogonal projection of the at least one barrier dam on the substrate closer to the display area, the at least one barrier dam being used to block the flow of the organic solution used to form the organic layer along the display area in the direction pointing towards the peripheral area.

[0035] In another aspect, a display device is provided, wherein the display device includes a display panel as described above. Attached Figure Description

[0036] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0037] Figure 1 This is a plan view of a display device according to some exemplary embodiments of the present disclosure.

[0038] Figure 2 This is a plan view of a display device according to some exemplary embodiments of the present disclosure, wherein pixel units included in the display panel are schematically shown.

[0039] Figure 3 This is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, which schematically shows the display area, the peripheral area and a plurality of spacers.

[0040] Figure 4 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A magnified view of part I in the image.

[0041] Figure 5 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A magnified view of part II in the image.

[0042] Figure 6 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A magnified view of part III in the image.

[0043] Figure 7 This is a partial enlarged view of a display panel according to some exemplary embodiments of the present disclosure, schematically showing the distribution density of the first septum and the second septum.

[0044] Figure 8 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 The enlarged view of part I in the diagram schematically shows a portion of the sub-pixels, the scan drive circuit area, the first spacer, and the second spacer.

[0045] Figure 9 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part I in the diagram, schematically showing the first electrode layer, the first septum, and the second septum.

[0046] Figure 10 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part I in the diagram, schematically showing the pixel defining layer, the first spacer, and the second spacer.

[0047] Figure 11 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part II, schematically showing the first electrode layer, the first septum, and the second septum.

[0048] Figure 12 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part II in the diagram, schematically showing the pixel defining layer, the first spacer, and the second spacer.

[0049] Figure 13 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part III, schematically showing the pixel defining layer, the first spacer, and the second spacer.

[0050] Figure 14 This is a schematic cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, for example, along... Figure 2 The cross-sectional view taken from line AA' in the diagram.

[0051] Figure 15This is a schematic cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, for example, along... Figure 2 The cross-sectional view taken from line BB' in the diagram.

[0052] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0053] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0054] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0055] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0056] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0057] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0058] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0059] It should be noted that, in this paper, the term "same layer" refers to a layer structure formed by using the same film deposition process to create a film layer for forming a specific pattern, and then using the same photomask to pattern this film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0060] In this paper, the term "distribution density" refers to the quantity per unit area. For example, the distribution density of septa can refer to the quantity of septa per unit area.

[0061] The inventors discovered that in current OLED display panels and devices, photospaces (PS) are typically fabricated on the pixel boundary layer to prevent the fine metal mask (FMM) from directly contacting the pixel structure during the OLED organic light-emitting material deposition process, thus preventing scratches and defects. However, in actual production, some OLED display products have relatively large through-holes in the FMM design, resulting in significant sagging due to gravity and a higher likelihood of large-area contact with the display panel. In this case, the FMM not only contacts the display area but also the peripheral area of ​​the display panel (i.e., the bezel area). This can lead to other defects, such as scratching the GOA driving circuitry located in the peripheral area and electrostatic discharge (ESD) caused by contact with the circuitry.

[0062] To address at least one aspect of the above problems, embodiments of this disclosure provide a display panel and a display device. The display panel includes: a substrate including a display area and a peripheral area, the display area including an outer boundary; a plurality of sub-pixels disposed in the display area, the plurality of sub-pixels being arranged in an array along a first direction and a second direction in the display area, at least one of the sub-pixels including a first electrode, a second electrode, and a functional layer located between the first electrode and the second electrode; a first electrode layer disposed on the substrate, the first electrodes of the plurality of sub-pixels being located on the first electrode layer; a pixel defining layer disposed on the side of the first electrode layer away from the substrate; and a spacer layer disposed on the side of the pixel defining layer away from the substrate, wherein the display panel further includes at least one barrier dam disposed on the substrate. At least one barrier dam is located in the peripheral region and on the side of the peripheral region away from the display area; in a first direction and a second direction, the outer boundary is adjacent to the outermost row of sub-pixels in the display area and on the side of the outermost row of sub-pixels in the display area facing the peripheral region; the spacer layer includes a plurality of first spacers and a plurality of second spacers, the plurality of first spacers are arranged in an array in the display area, the plurality of second spacers are arranged in an array in the peripheral region, and the plurality of second spacers are located between the outer boundary and the at least one barrier dam; and the distribution density of the plurality of second spacers in the peripheral region is less than the distribution density of the plurality of first spacers in the display area.

[0063] In the embodiments of this disclosure, spacers are added to the peripheral area of ​​the display panel, and the distribution density of the spacers in the peripheral area is lower than that in the display area. This design avoids contact between the FMM and the peripheral area of ​​the display panel, thus preventing scratches on the GOA driving circuit located in the peripheral area and electrostatic discharge (ESD) caused by contact with the circuit. Furthermore, the lower distribution density of the spacers in the peripheral area reduces the probability of the FMM rubbing against the spacers, thereby reducing the risk of generating a large number of spacer particles.

[0064] Figure 1 This is a plan view of a display device according to some exemplary embodiments of the present disclosure. Figure 2 This is a plan view of a display device according to some exemplary embodiments of the present disclosure, wherein pixel units included in the display panel are schematically shown.

[0065] Combined with reference Figure 1 and Figure 2The display device 1000 may include a display panel. The display panel may include a substrate 10, and the substrate 10 may include a display area AA and a peripheral area NA located on at least one side of the display area. It should be noted that in... Figure 1 In the illustrated embodiment, the peripheral region NA surrounds the display region AA. However, the embodiments of this disclosure are not limited to this. In other embodiments, the peripheral region NA may be located on at least one side of the display region AA, but does not surround the display region AA.

[0066] The display panel may include multiple pixel units P located in the display area AA. It should be noted that the pixel unit P is the smallest unit used to display an image. For example, the pixel unit P may include a light-emitting device that emits white light and / or colored light.

[0067] Pixel units P can be configured in multiple ways, arranged in an array along rows extending in a first direction (e.g., row direction) X and columns extending in a second direction (e.g., column direction) Y. However, embodiments of this disclosure do not specifically limit the arrangement of pixel units P, and pixel units P can be arranged in various forms. For example, pixel units P can be arranged such that the direction inclined relative to the first direction X and the second direction Y is the column direction, and the direction intersecting the column direction is the row direction.

[0068] A pixel unit P can include multiple sub-pixels. For example, a pixel unit P can include three sub-pixels: a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. As another example, a pixel unit P can include four sub-pixels: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. For instance, the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, the third sub-pixel SP3 can be a blue sub-pixel, and the fourth sub-pixel can be a white sub-pixel.

[0069] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, the first sub-pixel SP1 may include a first light-emitting element and a first pixel driving circuit for driving the first light-emitting element, and the first light-emitting element may emit red light; the second sub-pixel SP2 may include a second light-emitting element and a second pixel driving circuit for driving the second light-emitting element, and the second light-emitting element may emit green light; the third sub-pixel SP3 may include a third light-emitting element and a third pixel driving circuit for driving the third light-emitting element, and the third light-emitting element may emit blue light.

[0070] For example, in an OLED display panel, the light-emitting element of a subpixel may include an anode, a light-emitting material layer, and a cathode stacked together. For example, the light-emitting region of a subpixel may be the region corresponding to a portion of the light-emitting material layer sandwiched between and in contact with the anode and cathode. For example, a pixel-defining layer is formed on the anode, the pixel-defining layer has an opening exposing at least a portion of the anode, the light-emitting material layer is at least partially formed within the opening of the pixel-defining layer, and a cathode is formed on top of it; the light-emitting region of the subpixel may be the region defined by the opening of the pixel-defining layer. The light-emitting material layer may include one or more layers selected from hole injection layers, hole transport layers, light-emitting layers, hole blocking layers, electron transport layers, and electron injection layers, and may also include other functional film layers in addition to the above layers. These layers may include organic materials or inorganic materials such as quantum dots.

[0071] Reference Figure 1 The display panel may include components such as a load compensation unit 100, a test circuit 200, a scan drive circuit 300, and a multiplexer 400 located in the peripheral area NA.

[0072] The display area AA may include a first boundary AA1, a second boundary AA2, a third boundary AA3, and a fourth boundary AA4 (e.g., an upper boundary, a lower boundary, a left boundary, and a right boundary) connected sequentially. In embodiments of this disclosure, the display area AA includes an outer boundary. For example, the outer boundary may include the first boundary AA1, the second boundary AA2, the third boundary AA3, and the fourth boundary AA4, that is, the first boundary AA1, the second boundary AA2, the third boundary AA3, and the fourth boundary AA4 are connected to each other to form the outer boundary. Specifically, in the first direction X and the second direction Y, the outer boundary is adjacent to the outermost row of sub-pixels in the display area AA, and is located on the side of the outermost row of sub-pixels in the display area AA facing the surrounding area NA. For example, in the first direction X, the outer boundary is adjacent to the leftmost or rightmost column of sub-pixels in the display area AA, and is located to the left of the leftmost column of sub-pixels or to the right of the rightmost column of sub-pixels in the display area AA.

[0073] In some embodiments of this disclosure, the orthographic projection of the display area AA onto the substrate 10 can be a rounded rectangle. For ease of description, the four rounded corners of the rounded rectangle can be referred to as the first rounded corner 10A, the second rounded corner 10B, the third rounded corner 10C, and the fourth rounded corner 10D, respectively. For example, the first rounded corner 10A can be located at... Figure 1 The second rounded corner 10B can be located at the upper left corner of the middle. Figure 1 The third rounded corner 10C can be located at the upper right corner of the middle. Figure 1 The fourth rounded corner 10D can be located at the bottom left corner of the image. Figure 1It is located in the bottom right corner.

[0074] The test circuit 200 can be located on one side of the peripheral area NA adjacent to the first boundary AA1, and the test circuit 200 is arranged opposite to the first boundary AA1, the first rounded corner 10A and the second rounded corner 10B.

[0075] For example, the test circuit 200 may include a plurality of test pins, which may be used to provide test signals, such as data signals for a plurality of pixel units P in the display area AA.

[0076] The multiplexer 400 can be located on one side of the peripheral area NA adjacent to the second boundary AA2, and the multiplexer 400 is arranged opposite to the second boundary AA2, the third rounded corner 10C and the fourth rounded corner 10D.

[0077] For example, the multiplexer 400 can time-division multiplex signal lines in a wiring area. Figure 1 As shown, the display panel includes an integrated circuit (IC) disposed in the peripheral area NA and a wiring area 500 located between the IC and a multiplexer 400. Each signal output by the IC is transmitted to the multiplexer 400 via signal lines in the wiring area 500. Then, under the control of the signal control terminal of the multiplexer 400, each signal is output to each pixel unit P in the display area AA. By using the multiplexer 400, the number of signal lines arranged in the wiring area can be reduced, thereby reducing the wiring pressure in the wiring area.

[0078] The scan drive circuit 300 can be located on one side of the peripheral region NA adjacent to the third boundary AA3 and on one side of the peripheral region NA adjacent to the fourth boundary AA4. It should be noted that, although... Figure 1 The diagram shows the scan driving circuit located on the left and right sides of the display area AA; however, embodiments of this disclosure are not limited thereto, and the scan driving circuit may be located at any suitable location in the peripheral area NA.

[0079] For example, the scan driving circuit 300 may include at least one of a gate scan driving circuit, an emissive control scan driving circuit, and a reset signal scan driving circuit. For example, the gate scan driving circuit, the emissive control scan driving circuit, and the reset signal scan driving circuit may employ GOA technology, meaning the scan driving circuit 300 may include at least one of Gate GOA, EM GOA, and RST GOA. In GOA technology, the gate scan driving circuit, the emissive control scan driving circuit, and the reset signal scan driving circuit are directly disposed on the array substrate to replace an external driving chip. Each GOA unit serves as a first-level shift register, and each shift register is electrically connected to a gate line, an emissive control line, or a reset signal line. The successive output of turn-on voltages by each shift register sequentially achieves line-by-line scanning of pixels. In some embodiments, each shift register may also be connected to multiple gate lines, multiple emissive control lines, or multiple reset signal lines. This adapts to the development trend of high-resolution and narrow-bezel display panels.

[0080] The display panel may include multiple load compensation units 100. For example... Figure 1 and Figure 2 As shown, some of the multiple load compensation units 100 are located in the peripheral area NA near the first rounded corner 10A, and others are located in the peripheral area NA near the second rounded corner 10B. All the multiple load compensation units 100 are located between the test circuit 200 and the display area AA.

[0081] In embodiments of this disclosure, each sub-pixel SP1, SP2, or SP3 may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, the light-emitting device may include a first electrode, a second electrode, and a light-emitting material layer located between the first and second electrodes. The pixel driving circuit may include components such as transistors and capacitors. The pixel driving circuit receives signals from signal lines disposed on the display panel, generates a current to drive the light-emitting device, and achieves the purpose of driving the light-emitting device to emit light by connecting to one of the first or second electrodes. For example, the pixel driving circuit is disposed on a substrate, and the light-emitting device is located on the side of the pixel driving circuit away from the substrate. For example, the pixel driving circuit may include circuit structures commonly used in the art, such as 3T1C, 3T2C, 7T1C, 7T2C, 8T2C, or 4T1C. For example, the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0082] Figure 14 This is a schematic cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, for example, Figure 14 It can be along Figure 2 A cross-sectional view taken from line AA' in the middle; Figure 15 This is a schematic cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, for example, Figure 15 It can be along Figure 2 The cross-sectional view taken from line BB' in the diagram. (Refer to the reference.) Figure 1 , Figure 2 , Figure 14 and Figure 15 The display substrate may include a pixel driving circuit layer 11, a planarization layer PLN, and a pixel delimiting layer PDL, which are sequentially stacked on the substrate 10.

[0083] The structure of the substrate 10 described above includes various types, and can be selected according to actual needs. For example, the substrate 10 can be a rigid substrate. This rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate. In this case, the display substrate can be a rigid display substrate. Alternatively, the substrate 10 can be a flexible substrate. This flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate dimethyl methacrylate) substrate, or a PI (Polyimide) substrate. In this case, the display substrate can be a flexible display substrate.

[0084] For example, such as Figure 15 As shown, the pixel driving circuit layer 11 may include a semiconductor layer 20, a gate insulating layer IL1, a first conductive layer 21, an interlayer insulating layer IL2, and a second conductive layer 22 stacked sequentially.

[0085] For example, such as Figure 15 As shown, the first conductive layer 21 includes multiple gates 1111, the semiconductor layer 20 includes multiple active patterns 1131, and the second conductive layer 22 includes multiple sources 1151 and multiple drains 1152. Each corresponding active pattern 1131, gate 1111, source 1151, and drain 1152 can, for example, constitute a transistor, and multiple transistors can, for example, constitute a pixel driving circuit P. The pixel driving circuit layer 11 can include multiple pixel driving circuits P. Figure 15 As shown, in this invention, a single transistor schematically represents a pixel driving circuit P.

[0086] In some examples, such as Figure 15As shown, the display substrate further includes a plurality of light-emitting devices 2 located on the side of the planarization layer PLN away from the substrate 10 and located in the display area AA. The light-emitting device 2 may be, for example, an OLED.

[0087] For example, the light-emitting device 2 includes an anode 2a, a light-emitting layer 2b, and a cathode 2c stacked in sequence.

[0088] For example, the anode 2a of the light-emitting device 2 is disposed on the surface of the planarization layer PLN away from the substrate 10. The anode 2a of the light-emitting device 2 can be electrically connected to a pixel driving circuit P through the planarization layer PLN.

[0089] For example, the structure of anode 2a can be a composite structure composed of a transparent conductive oxide film / metal film / transparent conductive oxide film stacked sequentially. The transparent conductive oxide film is made of, for example, any one of ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), and the metal film is made of, for example, any one of gold (Au), silver (Ag), nickel (Ni), and platinum (Pt).

[0090] For example, the structure of anode 2a can also be a single-layer structure, and the material of the single-layer structure can be any one of ITO, IZO, Au, Ag, Ni, and Pt.

[0091] For example, the pixel defining layer (PDL) described above has multiple openings (PO). One opening exposes a portion of an anode (2a). At least a portion of a light-emitting layer (2b) is located within one opening and forms an electrical connection with the corresponding anode (2a). That is, each light-emitting layer (2b) forms an electrical connection with the corresponding anode (2a) through a portion or entirely located within the corresponding opening.

[0092] Here, the arrangement of the light-emitting layer 2b is related to its fabrication process. For example, when the light-emitting layer 2b is formed using a vapor deposition process, a portion of the light-emitting layer 2b can be located within the corresponding opening, while another portion overlaps on the pixel defining layer (PDL) surrounding the opening. When the light-emitting layer 2b is formed using inkjet printing technology, the entire light-emitting layer 2b is located within the corresponding opening.

[0093] For example, such as Figure 15 As shown, the cathode 2c is located on the side of the pixel defining layer PDL away from the substrate 10. The cathodes 2c of each light-emitting device can be electrically connected to each other, forming an integrated structure.

[0094] For example, the cathode 2c can be made of any one of aluminum (Al), silver (Ag) and magnesium (Mg), or any one of magnesium-silver alloy and aluminum-lithium alloy.

[0095] For example, the light-emitting device 2 may further include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer disposed between the anode 2a and the light-emitting layer 2b, and at least one of an electron injection layer, an electron transport layer, and a hole blocking layer disposed between the cathode 2c and the light-emitting layer 2b. By providing at least one of a hole injection layer, a hole transport layer, and an electron blocking layer between the anode 2a and the light-emitting layer 2b of the light-emitting device 2, and providing at least one of an electron injection layer, an electron transport layer, and a hole blocking layer between the cathode 2c and the light-emitting layer 2b of the light-emitting device 2, the luminous efficiency of the light-emitting device 2 can be improved. In the embodiments of this disclosure, the term "functional layer" can be used to refer to at least one of the light-emitting layer, the hole injection layer, the hole transport layer, and the electron blocking layer.

[0096] In some examples, such as Figure 15 As shown, the display substrate further includes an encapsulation layer 3 disposed on the side of the light-emitting device 2 away from the substrate 10. Therefore, the plurality of light-emitting devices 2 are located between the substrate 10 and the encapsulation layer 3.

[0097] For example, such as Figure 15 As shown, the encapsulation layer 3 includes a first inorganic layer 31, an organic layer 32, and a second inorganic layer 33 stacked sequentially.

[0098] The first inorganic layer 31 and the second inorganic layer 33 serve as the main barrier to prevent water and / or oxygen from entering the light-emitting device 2, while the organic layer 32 serves as an auxiliary encapsulation and planarization layer. In other words, the flatter the surface of the organic layer 32 on the side away from the substrate 10, the flatter the surface of the encapsulation layer 3 on the side away from the substrate 10.

[0099] For example, the first inorganic layer 31 and the second inorganic layer 33 may be made of inorganic materials such as nitrides, oxides, nitrogen oxides, nitrates, carbides, or any combination thereof. The organic layer 32 may be made of materials such as acrylic fiber, hexamethyldisiloxane, polyacrylates, polycarbonate, and polystyrene.

[0100] In some examples, such as Figure 15 As shown, the display substrate further includes at least one blocking dam 4 disposed on one side of the substrate 10 and located in the peripheral region NA. The at least one blocking dam 4 is located on the side of the peripheral region NA away from the display region AA, that is, the at least one blocking dam 4 is located on the outer side of the peripheral region NA.

[0101] It should be noted that the aforementioned encapsulation layer 3 is located on the side of the barrier dam 4 away from the backplate 1.

[0102] In the embodiments disclosed herein, the number of barrier dams 4 is not limited and can be selected according to actual needs.

[0103] In some examples, the orthographic projection of the organic layer 32 onto the substrate 10 is located on the side of the orthographic projection of at least one barrier dam 4 onto the substrate 10 closest to the display area AA. That is, the organic layer 32 is located within the area surrounded by at least one barrier dam 4.

[0104] For example, when there are multiple barrier dams 4, the orthographic projection of the organic layer 32 on the substrate 10 is located on the side of the orthographic projection of one of the barrier dams 4 on the substrate 10 that is closer to the display area AA.

[0105] It should be noted that, in the embodiments of this disclosure, the barrier dam 4 can be used to block the flow of the organic solution used to form the organic layer 32 in the direction from the display area AA to the surrounding area NA.

[0106] When preparing the organic layer 32, the organic solution can be stopped from flowing before at least one barrier dam 4, so that the side slope of the prepared organic layer 32 is larger and the surface of the organic layer 32 away from the substrate 10 is closer to the surface parallel to the substrate 10, that is, it is flatter, thereby making the surface of the encapsulation layer 3 away from the substrate 10 flatter.

[0107] Furthermore, since the orthographic projection of the organic layer 32 on the substrate 10 is located on the side of the orthographic projection of at least one barrier dam 4 on the substrate 10 that is close to the display area AA, and the orthographic projection of at least one barrier dam 4 on the substrate 10 is within the orthographic projection range of the second inorganic layer 33 on the substrate 10, it can be ensured that the orthographic projection of the organic layer 32 on the substrate 10 is within the orthographic projection range of the second inorganic layer 33 on the substrate 10. That is, it can be ensured that the second inorganic layer 33 completely covers the organic layer 32, preventing water and / or oxygen from entering the interior of the display substrate through the organic layer 32 and eroding the light-emitting device 2, thereby ensuring the encapsulation effect of the encapsulation layer 3 and avoiding encapsulation failure.

[0108] Reference Figure 14 and Figure 15 In the embodiments of this disclosure, the light-emitting layer 2b of the light-emitting device of each sub-pixel is formed by a vapor deposition process.

[0109] The inventors discovered that a fine metal mask (FMM) is required in the vapor deposition process. In this case, a photo spacer (PS) needs to be fabricated on the pixel boundary layer (PDL) to prevent the OLED organic light-emitting material from directly contacting the FMM with the pixel structure during vapor deposition, which could scratch the pixel structure and cause defects. In actual production, for some OLED display products, the FMM has relatively large vias, resulting in significant sagging due to gravity and increasing the likelihood of large-area contact with the display panel. In this case, the FMM will contact not only the display area but also the peripheral area (NA) of the display panel, leading to other defects such as scratching the GOA driving circuitry located in the NA and electrostatic discharge (ESD) caused by contact with the circuitry. Therefore, in the embodiments of this disclosure, a photo spacer layer (PSL) is fabricated on the pixel boundary layer (PDL).

[0110] like Figure 14 As shown, the display panel may include a substrate 10; a semiconductor layer 20 disposed on the substrate 10; a first conductive layer 21 disposed on the side of the semiconductor layer 20 away from the substrate 10; a second conductive layer 22 disposed on the side of the first conductive layer 21 away from the substrate 10; an interlayer insulating layer 23 disposed on the side of the second conductive layer 22 away from the substrate 10; a third conductive layer 24 disposed on the side of the interlayer insulating layer 23 away from the substrate 10; a planarization layer PLN disposed on the side of the third conductive layer 24 away from the substrate 10; a first electrode layer (e.g., an anode 2a is located in the first electrode layer) disposed on the side of the planarization layer PLN away from the substrate 10; a pixel defining layer PDL disposed on the side of the first electrode layer away from the substrate 10; and a spacer layer PSL disposed on the side of the pixel defining layer PDL away from the substrate 10.

[0111] It should be noted that the display panel according to the embodiments of this disclosure is not limited to the above-described film layers. One or more insulating layers may be disposed between the conductive layers. For example, a first insulating layer IL1 may be disposed between the semiconductor layer 20 and the first conductive layer 21, and a second insulating layer IL2 may be disposed between the first conductive layer 21 and the second conductive layer 22. The planarization layer PLN may include one planarization layer or multiple planarization sublayers.

[0112] Figure 3 This is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, which schematically shows the display area, the peripheral area and a plurality of spacers. Figure 4 The display panel is based on some exemplary embodiments of this disclosure. Figure 1A magnified view of part I in the image. Figure 5 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A magnified view of part II in the image. Figure 6 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A magnified view of part III in the image. Figure 7 This is a partial enlarged view of a display panel according to some exemplary embodiments of the present disclosure, schematically showing the distribution density of the first septum and the second septum. Figure 8 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 The enlarged view of part I in the diagram schematically shows a portion of the sub-pixels, the scan drive circuit area, the first spacer, and the second spacer. Figure 9 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part I in the diagram, schematically showing the first electrode layer, the first septum, and the second septum. Figure 10 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part I in the diagram, schematically showing the pixel defining layer, the first spacer, and the second spacer. Figure 11 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part II, schematically showing the first electrode layer, the first septum, and the second septum. Figure 12 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part II in the diagram, schematically showing the pixel defining layer, the first spacer, and the second spacer. Figure 13 The display panel is based on some exemplary embodiments of this disclosure. Figure 1 A partial enlarged view of part III, schematically showing the pixel defining layer, the first spacer, and the second spacer.

[0113] It should be noted that in the accompanying drawings of this disclosure, for insulating layers such as planarization layers and pixel definition layers, the white portion represents the material portion of these insulating layers, and the filled portion represents the material-free portion of these insulating layers.

[0114] Combined with reference Figures 3 to 14 The spacer layer PSL may include a plurality of first spacers PS1 located in the display area AA and a plurality of second spacers PS2 located in the peripheral area NA.

[0115] like Figure 3As shown, a plurality of first spacers PS1 arrays are arranged in the display area AA, a plurality of second spacers PS2 arrays are arranged in the peripheral area NA, and the plurality of second spacers PS2 are located between the outer boundary and the at least one barrier dam 4.

[0116] like Figure 3 and Figure 7 As shown, in an embodiment of this disclosure, the distribution density of the plurality of second spacers PS2 in the peripheral area NA is less than the distribution density of the plurality of first spacers PS1 in the display area AA.

[0117] In some embodiments of this disclosure, the distribution density of the plurality of second spacers PS2 in the peripheral region NA is 1 / 4 to 2 / 3 of the distribution density of the plurality of first spacers PS1 in the display region AA. For example, in Figure 7 In the illustrated embodiment, the unit area of ​​the surrounding region NA (e.g.) Figure 7 Four second spacers PS2 are provided within the rectangular frame shown in the figure, and the unit area of ​​the display area AA (e.g., ...) is... Figure 7 The rectangular frame shown in the diagram contains nine first spacers PS1, meaning the distribution density of the plurality of second spacers PS2 in the peripheral area NA is 4 / 9 of the distribution density of the plurality of first spacers PS1 in the display area AA. For example, in some embodiments of this disclosure, the distribution density of the plurality of second spacers PS2 in the peripheral area NA is approximately 1 / 2 of the distribution density of the plurality of first spacers PS1 in the display area AA.

[0118] In the embodiments of this disclosure, on the one hand, a spacer design is added to the peripheral area NA of the display panel, that is, a second spacer PS2 is added to the peripheral area NA. This can prevent the FMM from contacting the peripheral area of ​​the display panel, thereby avoiding problems such as scratching the GOA driving circuit located in the peripheral area and electrostatic discharge (i.e., ESD) caused by contact with the circuit. On the other hand, considering the risk that the FMM may scratch the spacer during actual production, resulting in spacer particles, in the embodiments of this disclosure, the distribution density of spacer PS2 in the peripheral area NA is less than the distribution density of spacer PS1 in the display area AA. This can reduce the probability of the FMM scratching the spacer, thereby reducing the risk of generating more spacer particles.

[0119] Specifically, refer to Figure 7 Two adjacent first spacers PS1 in the first direction X are spaced apart by a first distance W1 in the first direction, and two adjacent second spacers PS2 in the first direction X are spaced apart by a second distance W2 in the first direction, wherein the first distance W1 is less than the second distance W2.

[0120] Alternatively or additionally, two adjacent first spacers PS1 in the second direction Y are spaced apart by a third distance H1 in the second direction, and two adjacent second spacers PS2 in the second direction Y are spaced apart by a fourth distance H2 in the second direction, wherein the third distance H1 is less than the fourth distance H2.

[0121] Reference Figure 4 , Figure 5 and Figure 6 The outermost row of second septa PS2 is spaced apart from the at least one barrier dam 4.

[0122] In embodiments of this disclosure, the peripheral region NA may include a first side peripheral region NA1, a second side peripheral region NA2, a third side peripheral region NA3, and a fourth side peripheral region NA4. For example, the first side peripheral region NA1 and the second side peripheral region NA2 are respectively located on both sides of the display region AA in the first direction x, that is, the first side peripheral region NA1 and the second side peripheral region NA2 are respectively located on both sides of the display region AA. Figure 1 The left and right peripheral areas are defined in the image. The third peripheral area NA3 and the fourth peripheral area NA4 are located on either side of the display area AA in the second direction Y. That is, the third peripheral area NA3 and the fourth peripheral area NA4 are respectively... Figure 1 The lower and upper perimeter areas.

[0123] like Figure 4 As shown, in the first side peripheral area NA1, the outermost row of second septa PS2 (i.e., the leftmost row of second septa PS2) is spaced apart from the at least one barrier dam 4, for example, by a spacing of PW1.

[0124] For example, the distribution of septa in the second peripheral region NA2 can be symmetrical to the distribution of septa in the second peripheral region NA2. That is, in the second peripheral region NA2, the outermost row of second septa PS2 (i.e., the rightmost column of second septa PS2) is spaced apart from the at least one barrier dam 4, for example, the spacing is also PW1.

[0125] like Figure 5 As shown, in the third side peripheral area NA3, the outermost row of second spacers PS2 (i.e., the bottommost row of second spacers PS2) is spaced apart from the at least one barrier dam 4, for example, by a spacing of PW3.

[0126] like Figure 6As shown, in the fourth side peripheral area NA4, the outermost row of second spacers PS2 (i.e., the uppermost row of second spacers PS2) is spaced apart from the at least one barrier dam 4, for example, by a spacing of PW4.

[0127] In the embodiments of this disclosure, in the first peripheral region NA1, the second peripheral region NA2, the third peripheral region NA3, and the fourth peripheral region NA4, the spacing between the orthographic projection of the outermost row of second spacers PS2 on the substrate 10 and the orthographic projection of the at least one barrier dam 4 on the substrate 10 is substantially equal to each other. That is, the spacing distances PW1, PW3, and PW4 are substantially equal to each other.

[0128] It should be noted that in this article, the expression "basically equal" can mean that the two objects being compared are strictly equal, or that the two objects being compared are approximately equal. Specifically, here, the fact that the intervals PW1, PW3, and PW4 are basically equal to each other can include that the ratio between any two of the intervals PW1, PW3, and PW4 is between 0.8 and 1.2.

[0129] For example, the distance PW1, PW3, PW4 between the orthographic projection of the outermost row of second spacers on the substrate and the orthographic projection of the at least one blocking dam on the substrate can be between 300 and 1000 micrometers, for example, about 600 micrometers.

[0130] Reference Figure 7 and Figure 8 At least one row of second spacers PS2 located in at least one of the first side peripheral regions NA1 and the second side peripheral regions NA2 is substantially aligned with at least one row of first spacers PS1 located in the display area AA in the first direction X.

[0131] It should be noted that, in this document, the expression "basic alignment" can mean that the two objects being compared are strictly aligned in at least one direction, or that the two objects being compared are approximately aligned in at least one direction. Specifically, here, the basic alignment of at least one row of second spacers PS2 with at least one row of first spacers PS1 in the first direction X can include: in the first spacers PS1 and second spacers PS2 located in the same row, the connecting lines between adjacent first spacers PS1 and second spacers PS2 (e.g., Figure 8 The connecting line CL1 is parallel to the first direction X, or the angle between the connecting line CL1 and the first direction X is between ±10°.

[0132] Reference Figure 7 and Figure 11At least one column of second spacers PS2 located in the third peripheral area NA3 and at least one column of first spacers PS1 located in the display area AA are substantially aligned in the second direction Y.

[0133] It should be noted that, in this document, the expression "basic alignment" can mean that the two objects being compared are strictly aligned in at least one direction, or that the two objects being compared are approximately aligned in at least one direction. Specifically, here, the basic alignment of at least one row of second spacers PS2 with at least one row of first spacers PS1 in the second direction Y can include: in the first spacers PS1 and second spacers PS2 located in the same column, the connecting lines between adjacent first spacers PS1 and second spacers PS2 (e.g., Figure 11 The connecting line CL2 is parallel to the second direction Y, or the angle between the connecting line CL2 and the second direction Y is between ±10°.

[0134] Reference Figure 8 The display panel further includes a driving voltage lead 650 disposed on the substrate 10 and located in the peripheral region NA. The driving voltage lead 650 is used to transmit driving voltage, for example, it can transmit VDD voltage.

[0135] Continue to refer to Figure 8 The display panel further includes a scan driving circuit 300 disposed on the substrate 10 and located in at least one of the first side peripheral region NA1 and the second side peripheral region NA2, the scan driving circuit 300 being used to output a scan signal.

[0136] The peripheral region NA includes a scan drive circuit region CC, which is located in at least one of the first side peripheral region NA1 and the second side peripheral region NA2. The scan drive circuit 300 is disposed in the scan drive circuit region CC, which is located between the drive voltage lead 650 and the at least one blocking dam 4.

[0137] For example, in at least one of the first peripheral region NA1 and the second peripheral region NA2, the scan driving circuit region CC includes at least three GOA sub-regions C1 sequentially distributed along the first direction X. For example, one GOA sub-region closest to the display region AA may include a gate GOA circuit, the second GOA sub-region distributed along the first direction X may include a first reset GOA circuit (RST1 GOA), and the third GOA sub-region distributed along the first direction X may include a second reset GOA circuit (RST2 GOA) and an EM control GOA circuit (EM GOA). Of course, the GOA region CC of the display substrate may also include more GOA sub-regions, which can be determined according to the actual GOA circuit design.

[0138] like Figure 8 As shown, the orthographic projection of some of the plurality of second spacers PS2 on the substrate 10 at least partially overlaps with the orthographic projection of the drive voltage lead 650 on the substrate 10.

[0139] Some of the second spacers PS2 have their orthographic projections on the substrate 10 at least partially overlapping with the orthographic projection of the scanning drive circuit region CC on the substrate 10. In this embodiment, arranging the second spacers PS2 in the region where the drive voltage leads are located can prevent the FMM from scratching the drive voltage leads and avoid defects in the drive voltage leads.

[0140] For example, the orthographic projection of some of the plurality of second spacers PS2 on the substrate J0 at least partially overlaps with the orthographic projection of each of the plurality of scan drive circuit regions C1 on the substrate 10. In this embodiment, arranging the second spacers PS2 in the region where the scan drive circuit is located can prevent the FMM from scratching the scan drive circuit and avoid malfunctions in the scan drive circuit.

[0141] The display panel further includes a first voltage lead 670 and an auxiliary conductive portion 251. The first voltage lead 670 is used to provide a first voltage, such as a VSS voltage. The auxiliary conductive portion 251 is located on the same layer as the first electrode (e.g., anode 2a) of the light-emitting device, and a portion of the auxiliary conductive portion 251 is in direct contact with the first voltage lead 670, thereby forming an electrical connection between them. That is, in the embodiments of this disclosure, the first voltage lead 670 and the auxiliary conductive portion 251, located in different conductive layers, are connected in parallel, and they are both used to transmit the first voltage VSS. In this way, the resistance on the signal line transmitting the first voltage VSS can be reduced.

[0142] Some of the plurality of second spacers PS2 have their orthographic projections on the substrate 10 at least partially overlapping with the orthographic projection of the first voltage lead 670 on the substrate 10. Some of the second spacers PS2 also have their orthographic projections on the substrate 10 at least partially overlapping with the orthographic projection of the auxiliary conductive portion 251 on the substrate 10. In this embodiment, arranging the second spacers PS2 in the area where the first voltage lead is located prevents the FMM from scratching the first voltage lead and avoids defects in the first voltage lead.

[0143] Reference Figure 8 and Figure 9 In the first peripheral region NA1, the orthographic projections of some of the plurality of second spacers PS2 on the substrate 10 at least partially overlap with the orthographic projections of the first voltage lead 670 on the substrate 10. The orthographic projections of some of the plurality of second spacers PS2 on the substrate 10 at least partially overlap with the orthographic projections of the auxiliary conductive portion 251 on the substrate 10.

[0144] Reference Figure 11 In the third peripheral region NA3, the orthographic projections of some of the plurality of second spacers PS2 on the substrate 10 at least partially overlap with the orthographic projections of the first voltage lead 670 on the substrate 10. The orthographic projections of some of the plurality of second spacers PS2 on the substrate 10 at least partially overlap with the orthographic projections of the auxiliary conductive portion 251 on the substrate 10.

[0145] Reference Figure 10 , Figure 12 and Figure 13 The diagram schematically illustrates a pixel definition layer (PDL). For example, a pixel definition layer (PDL) may include a pixel definition layer body (PDL0) and a first cover portion (PDL1). The majority of the pixel definition layer body (PDL0) is located within the display area AA; for example, the pixel definition layer (PDL) includes multiple openings within the display area AA. Within the peripheral area NA, the pixel definition layer (PDL) includes the first cover portion (PDL1).

[0146] For example, such as Figure 3As shown in some exemplary embodiments of this disclosure, the plurality of sub-pixels includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The pixel defining layer body PDL0 includes an opening located in the display area AA and corresponding to the plurality of sub-pixels. The orthographic projection of the opening on the substrate lies within the orthographic projection of the first electrode of the plurality of sub-pixels on the substrate. The area of ​​the opening corresponding to the third sub-pixel SP3 on the orthographic projection of the substrate 10 is larger than the area of ​​the opening corresponding to the first sub-pixel SP1 or the second sub-pixel SP2 on the orthographic projection of the substrate 10. The first spacer PS1 is adjacent to the opening corresponding to the third sub-pixel SP3 in the second direction Y.

[0147] It should be noted that, for the sake of clarity in illustrations and descriptions, Figure 3 The diagram only shows the approximate location and shape of the pixel-defining layer openings of the sub-pixels to represent the distribution of each sub-pixel. For example, in some embodiments of this disclosure, the arrangement of sub-pixels in each pixel repeating unit can refer to conventional pixel arrangement methods, such as RGB, GGRB, RGBG, RGB, etc., and the embodiments of this disclosure do not limit this.

[0148] Reference Figure 9 and Figure 11 For example, the auxiliary conductive part 251 may also include multiple openings. These openings may include a first via 2511 located in the first peripheral region NA1 or the second peripheral region NA2, and a second via 2512 located in the third peripheral region NA3. The planarization layer PLN is typically formed using organic resin materials. The planarization layer PLN contains some organic substances that are easily volatile when heated, such as organic solvents or small molecule materials. These organic substances are easily volatile when heated during subsequent manufacturing processes of the display panel, leading to gas release in the planarization layer. By providing multiple openings in the first electrode layer, it is beneficial for the organic substances in the planarization layer PLN to volatilize when heated during subsequent manufacturing processes of the display panel, thereby preventing the accumulation of bubbles on the surface of the planarization layer PLN from the first electrode layer. This helps ensure the process yield of the display panel, and thus ensures a good display effect.

[0149] The display panel may include multiple first cover portions PDL1 and multiple second cover portions PDL2. The orthographic projections of the multiple first cover portions PDL1 on the substrate respectively cover the orthographic projections of the multiple first openings 2511 on the substrate, and the orthographic projections of the multiple second cover portions PDL2 on the substrate respectively cover the orthographic projections of the multiple second openings 2512 on the substrate. By providing the first cover portions PDL1 and the second cover portions PDL2, the edges of the first electrode layer can be covered, thereby protecting the first electrode layer.

[0150] In embodiments of this disclosure, the pixel defining layer body PDL0 may have a boundary PDLS located away from the display area AA. For example, multiple sub-pixels located in the display area AA may include the outermost column of sub-pixels, that is, the column of sub-pixels closest to the peripheral area NA. The boundary PDLS is spaced a certain distance from the outermost column of sub-pixels. For example, in Figure 8 and Figure 10 In the region shown, the boundary PDLS and the outermost column of sub-pixels ( Figure 8 The distance between the leftmost column of sub-pixels along the first direction X can be a specified value, or in other words, the distance is within a specified range.

[0151] Combined with reference Figure 7 , Figure 10 and Figure 12 The pixel defining layer (PDL) (specifically, the pixel defining layer body PDL0) includes a first part PDL01 and a second part PDL02, which are integrally formed. The first part PDL01 is located in the display area AA and includes openings corresponding to the plurality of sub-pixels. The orthographic projection of the openings onto the substrate lies within the orthographic projection of the first electrodes of the plurality of sub-pixels onto the substrate. The second part PDL02 is located in the peripheral area NA.

[0152] In embodiments of this disclosure, the orthographic projection of the first spacer PS1 onto the substrate lies within the orthographic projection of the first portion PDL01 of the pixel defining layer onto the substrate, and the orthographic projection of some of the second spacers PS2 onto the substrate lies within the orthographic projection of the second portion PDL02 of the pixel defining layer onto the substrate. For example, the orthographic projection of the second spacer PS2 onto the substrate does not overlap with the orthographic projection of the first electrode of the plurality of sub-pixels onto the substrate.

[0153] Reference Figure 10 In at least one of the first side peripheral region NA1 and the second side peripheral region NA2, the orthographic projection of some of the plurality of second spacers PS2 on the substrate 10 is located on the side of the outer boundary PDLS of the pixel defining layer body closer to the display area AA, and the orthographic projection of other of the plurality of second spacers PS2 on the substrate 10 is located on the side of the outer boundary PDLS of the pixel defining layer body away from the display area AA.

[0154] In at least one of the first side peripheral region NA1 and the second side peripheral region NA2, for the second spacer located on the side of the outer boundary of the pixel defining layer body near the display area, in two adjacent rows of second spacers PS2 (e.g. Figure 10 In the two rows of second spacers selected by the dashed box, the spacing between two adjacent second spacers in one row along the first direction X is not equal to the spacing between two adjacent second spacers in the other row along the first direction X.

[0155] In at least one of the first side peripheral region NA1 and the second side peripheral region NA2, for the second spacer located on the side of the outer boundary of the pixel defining layer body away from the display area, in two adjacent rows of second spacers PS2 (e.g. Figure 10 In the two rows of second spacers selected by the dashed-dot box, the spacing between two adjacent second spacers in one row along the first direction is approximately equal to the spacing between two adjacent second spacers in the other row along the first direction.

[0156] It should be noted that, in this document, the expression "substantially equal" can mean that the two objects being compared are strictly equal, or that the two objects being compared are approximately equal. Specifically, here, the interval between two adjacent second spacers in a row of second spacers along the first direction being substantially equal to the interval between two adjacent second spacers in another row along the first direction can include: the ratio between the interval between two adjacent second spacers in a row of second spacers along the first direction and the interval between two adjacent second spacers in another row along the first direction being between 0.8 and 1.2.

[0157] Reference Figure 10 In at least one of the first side peripheral region NA1 and the second side peripheral region NA2, the orthographic projection of some of the plurality of second spacers PS2 on the substrate at least partially overlaps with the orthographic projection of the first cover portion PDL1 on the substrate.

[0158] Reference Figure 12 In the third peripheral region NA3, the orthographic projection of some of the plurality of second spacers PS2 on the substrate at least partially overlaps with the orthographic projection of the second cover PDL2 on the substrate.

[0159] Reference Figure 11 and Figure 12In the third peripheral region NA3, the pixel defining layer PDL further includes a third cover portion PDL3, and the auxiliary conductive portion includes a plurality of third openings 2513, the plurality of third openings 2513 respectively exposing a portion of the planarization layer, and the third cover portion PDL3 covering the plurality of third openings 2513.

[0160] In the third peripheral region NA3, the orthographic projection of some of the plurality of second spacers PS2 on the substrate does not overlap with the orthographic projection of the plurality of third openings 2513 on the substrate.

[0161] Reference Figure 13 In the fourth peripheral region NA4, the pixel defining layer PDL further includes a fourth covering portion PDL4, and the auxiliary conductive portion includes a plurality of fourth openings 2514, each of which exposes a portion of the planarization layer, and the fourth covering portion PDL4 covers the plurality of fourth openings 2514.

[0162] In the fourth peripheral region NA4, the orthographic projection of some of the plurality of second spacers PS2 on the substrate at least partially overlaps with the orthographic projection of the fourth cover portion PDL4 on the substrate.

[0163] In other embodiments of this disclosure, a display device is also provided. The display device may include the display panel described above. For example, the display device may be a smartphone, mobile phone, video phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, or smartwatch), etc.

[0164] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, comprising: A substrate, comprising a display area and a peripheral area, wherein the display area includes an outer boundary; A plurality of sub-pixels are disposed in the display area, the plurality of sub-pixels are arranged in an array in the display area along a first direction and a second direction, and at least one of the sub-pixels includes a first electrode, a second electrode and a functional layer located between the first electrode and the second electrode; A first electrode layer is disposed on the substrate, and the first electrodes of the plurality of sub-pixels are located in the first electrode layer; A pixel defining layer disposed on the side of the first electrode layer away from the substrate; A spacer layer disposed on the side of the pixel defining layer away from the substrate. The display panel further includes at least one barrier dam disposed on the substrate, the at least one barrier dam being located in the peripheral region and on the side of the peripheral region away from the display area; In the first and second directions, the outer boundary is adjacent to the outermost row of sub-pixels in the display area, and the outermost row of sub-pixels in the display area faces the side of the peripheral area. The septum layer includes a plurality of first septums and a plurality of second septums, the plurality of first septums arranged in an array in the display area, the plurality of second septums arranged in an array in the peripheral area, and the plurality of second septums located between the outer boundary and the at least one barrier dam; and The distribution density of the plurality of second spacers in the peripheral area is less than the distribution density of the plurality of first spacers in the display area.

2. The display panel according to claim 1, wherein, Two adjacent first spacers in a first direction are spaced apart by a first distance in the first direction, and two adjacent second spacers in a first direction are spaced apart by a second distance in the first direction, wherein the first distance is less than the second distance; and / or, Two adjacent first spacers in the second direction are spaced a third distance apart in the second direction, and two adjacent second spacers in the second direction are spaced a fourth distance apart in the second direction, wherein the third distance is less than the fourth distance.

3. The display panel according to claim 1 or 2, wherein, The outermost row of second diaphragms is spaced apart from the at least one barrier dam.

4. The display panel according to claim 3, wherein, The display panel further includes a driving voltage lead disposed on the substrate and located in the peripheral region, the driving voltage lead being used to transmit driving voltage; Some of the plurality of second spacers have their orthogonal projections on the substrate at least partially overlapping with the orthogonal projections of the drive voltage leads on the substrate.

5. The display panel according to claim 4, wherein, The surrounding area includes a first side surrounding area and a second side surrounding area, wherein the first side surrounding area and the second side surrounding area are respectively located on both sides of the display area in a first direction; The display panel further includes a scan driving circuit disposed on the substrate and located in at least one of the first side peripheral region and the second side peripheral region, the scan driving circuit being used to output a scan signal; The peripheral area includes a scan drive circuit area, which is located in at least one of the first side peripheral area and the second side peripheral area. The scan drive circuit is disposed in the scan drive circuit area, which is located between the drive voltage lead and the at least one blocking dam. Some of the plurality of second spacers have orthographic projections on the substrate that at least partially overlap with the orthographic projection of the scanning drive circuit region on the substrate.

6. The display panel according to claim 5, wherein, In at least one of the first side peripheral region and the second side peripheral region, a plurality of scanning drive circuit regions are provided; Some of the plurality of second spacers have orthographic projections on the substrate that at least partially overlap with the orthographic projections on the substrate of each of the plurality of scanning drive circuit regions.

7. The display panel according to claim 5 or 6, wherein, The display panel further includes a first voltage lead and an auxiliary conductive part. The first voltage lead is used to provide a first voltage. The auxiliary conductive part is located on the same layer as the first electrode. A portion of the auxiliary conductive part is in direct contact with the first voltage lead. Some of the plurality of second spacers have their orthographic projections on the substrate at least partially overlapping with the orthographic projections of the first voltage lead on the substrate. And / or, the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the auxiliary conductive portion on the substrate.

8. The display panel according to claim 7, wherein, The pixel defining layer includes a pixel defining layer body, which includes a first part and a second part. The first part is located in the display area and includes an opening corresponding to the plurality of sub-pixels. The orthographic projection of the opening onto the substrate is located within the orthographic projection of the first electrode of the plurality of sub-pixels onto the substrate. The second part is located in the peripheral area, and the second part and the first part are integral structures. The pixel defining layer body includes an outer boundary away from the display area. The surrounding area includes a first side surrounding area and a second side surrounding area, wherein the first side surrounding area and the second side surrounding area are respectively located on both sides of the display area in a first direction; In at least one of the first side peripheral region and the second side peripheral region, the orthographic projection of some of the plurality of second spacers on the substrate is located on the side of the outer boundary of the pixel defining layer body closer to the display area, and the orthographic projection of other of the plurality of second spacers on the substrate is located on the side of the outer boundary of the pixel defining layer body away from the display area.

9. The display panel according to claim 8, wherein, In at least one of the first side peripheral region and the second side peripheral region, for the second spacer located on the side of the outer boundary of the pixel defining layer body close to the display area, in two adjacent rows of second spacers, the spacing between two adjacent second spacers in one row along the first direction is not equal to the spacing between two adjacent second spacers in the other row along the first direction.

10. The display panel according to claim 8 or 9, wherein, In at least one of the first side peripheral region and the second side peripheral region, for the second spacer located on the side of the outer boundary of the pixel defining layer body away from the display area, in two adjacent rows of second spacers, the spacing between two adjacent second spacers in one row along the first direction is substantially equal to the spacing between two adjacent second spacers in the other row along the first direction.

11. The display panel according to claim 8, wherein, The display panel further includes a planarization layer, which is located on the side of the first electrode layer near the substrate. In at least one of the first side peripheral region and the second side peripheral region, the auxiliary conductive portion includes a plurality of first openings, the plurality of first openings respectively exposing a portion of the planarization layer; The pixel defining layer further includes a first covering portion, which covers the plurality of first openings; Some of the plurality of second spacers have their orthographic projections on the substrate at least partially overlapping with the orthographic projections of the first cover portion on the substrate.

12. The display panel according to claim 11, wherein, The surrounding area includes a third-side surrounding area, which is located on one side of the display area in the second direction; In the third peripheral region, the pixel defining layer further includes a second covering portion, and the auxiliary conductive portion includes a plurality of second openings, each of which exposes a portion of the planarization layer, and the second covering portion covers the plurality of second openings; In the third peripheral region, the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the second cover on the substrate.

13. The display panel according to claim 12, wherein, In the third peripheral region, the pixel defining layer further includes a third cover portion, and the auxiliary conductive portion includes a plurality of third openings, each of which exposes a portion of the planarization layer, and the third cover portion covers the plurality of third openings.

14. The display panel according to claim 13, wherein, In the third peripheral region, the orthographic projection of some of the plurality of second spacers on the substrate does not overlap with the orthographic projection of the plurality of third openings on the substrate.

15. The display panel according to claim 13, wherein, The surrounding area includes a fourth-side surrounding area, which is located on the other side of the display area in the second direction; In the fourth peripheral region, the pixel defining layer further includes a fourth covering portion, the auxiliary conductive portion includes a plurality of fourth openings, the plurality of fourth openings respectively expose a portion of the planarization layer, and the fourth covering portion covers the plurality of fourth openings; In the fourth peripheral region, the orthographic projection of some of the plurality of second spacers on the substrate at least partially overlaps with the orthographic projection of the fourth cover on the substrate.

16. The display panel according to claim 5 or 8, wherein, At least one row of second spacers located in at least one of the first side peripheral region and the second side peripheral region is substantially aligned with at least one row of first spacers located in the display area in a first direction.

17. The display panel according to claim 12, wherein, At least one column of second spacers located in the peripheral region of the third side is substantially aligned with at least one column of first spacers located in the display region in the second direction.

18. The display panel according to claim 12, wherein, The surrounding area includes a fourth-side surrounding area, which is located on the other side of the display area in the second direction; In the first, second, third, and fourth peripheral regions, the distance between the orthographic projection of the outermost row of second spacers on the substrate and the orthographic projection of the at least one barrier dam on the substrate is substantially equal to that between them.

19. The display panel according to claim 3, wherein, The distance between the orthographic projection of the outermost row of second spacers on the substrate and the orthographic projection of the at least one barrier dam on the substrate is between 300 and 1000 micrometers.

20. The display panel according to claim 1 or 2, wherein, The distribution density of the plurality of second spacers in the peripheral area is 1 / 4 to 2 / 3 of the distribution density of the plurality of first spacers in the display area.

21. The display panel according to claim 8, wherein, The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The pixel defining layer body includes an opening located in the display area and including an opening corresponding to the plurality of sub-pixels. The orthographic projection of the opening on the substrate is located within the orthographic projection of the first electrode of the plurality of sub-pixels on the substrate. The area of ​​the opening corresponding to the third sub-pixel on the orthographic projection of the substrate is greater than the area of ​​the opening corresponding to the first sub-pixel or the second sub-pixel on the orthographic projection of the substrate. The first spacer is adjacent to the opening corresponding to the third sub-pixel in the second direction.

22. The display panel according to claim 1 or 2, wherein, The display panel further includes an encapsulation layer disposed on the side of the at least one barrier dam away from the substrate, the encapsulation layer comprising a first inorganic layer, an organic layer and a second inorganic layer stacked sequentially; The orthographic projection of the organic layer on the substrate is located on the side of the orthographic projection of the at least one barrier dam on the substrate closer to the display area, and the at least one barrier dam is used to block the flow of the organic solution used to form the organic layer along the display area in the direction pointing towards the peripheral area.

23. A display device, wherein, The display device includes a display panel as claimed in any one of claims 1-22.

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