Substrate integrated waveguide phase shifter

Abstract

The application provides a substrate integrated waveguide phase shifter, belonging to the technical field of phased array antennas, comprising a first metal layer; a first dielectric layer is arranged on the first metal layer; a second metal layer is arranged on the first dielectric layer; a second dielectric layer is arranged on the second metal layer; the first metal layer, the first dielectric layer and the second metal layer form a SIW phase shifter structure, and four rows of through holes are arranged, each two rows of through holes form a group, and the two groups of through holes are symmetrically arranged on the two sides of the second metal layer relative to the central axis of the second metal layer; a waveguide gradual change hole is arranged on the first dielectric layer; two rows of offset patches are arranged on the second dielectric layer, and each row of offset patches corresponds to a group of through holes; an offset via hole is arranged on the first offset patch, and the offset via hole corresponds to the waveguide gradual change hole and the inner row of via holes. The application realizes automatic multi-bit digital control by loading multiple pairs of PIN diodes, guarantees the phase shift resolution in a large phase shift range, realizes the adjustment of the phase shift resolution and the phase shift range by using the reconfigurable width SIW.

Description

Technical Field

[0001] This invention relates to the field of phased array antenna technology, and more specifically to a substrate integrated waveguide phase shifter. Background Technology

[0002] Phase shifters are an important component in microwave and millimeter-wave applications. They are widely used in phased array radar systems and massive MIMO antenna arrays in 5G cellular communication networks. To meet the requirements of large scanning range, high scanning resolution, and wide bandwidth for phased array antennas, many phase shifters are based on microstrip line designs because they are easy to manufacture and integrate lumped components.

[0003] Microstrip line phase shifters can be mainly classified into reflective, switching-line, and load-line types. Reflective phase shifters are considered the most commonly used analog phase shifters. They employ a quarter-wavelength 3dB coupler to split the input signal into two orthogonal signals. Due to impedance mismatch, these two signals are reflected back and coupled at the output port. The phase can be controlled by the designed unmatched impedance, typically a variable capacitor or inductor. However, this type of analog phase shifter is not suitable for other widely used digital electronic devices.

[0004] Although mismatched impedances can be designed as switchable LC networks, phase shifters only have two adjustable states, and their bandwidth is limited. Load-line phase shifters are simple in structure and have the advantage of low insertion loss when the phase shift range is less than 90°. Throughout the circuit, two identical switchable admittances are connected in parallel with the microstrip line. The transition between the two admittance states introduces a phase change. However, the phase shift range of this type of phase shifter is very small. As the phase shift range increases, the bandwidth also gradually decreases. Switched-line type is another simple phase shifter. Phase shift is achieved by switching microstrip lines of different lengths. The characteristics of this type of phase shifter make it a good digital phase shifter. In fact, many digital phase shifters employ the concept of switching lines regardless of which sub-phase shifter is being switched. However, the complexity of this type of phase shifter increases as the number of switchable states increases. Furthermore, the phase shift achieved by switching transmission lines is proportional to the operating frequency, indicating that this type of phase shifter is not suitable for broadband applications.

[0005] Despite the extensive development of microstrip line phase shifters, microstrip transmission lines suffer from drawbacks such as low power capacity and high radiation loss. Furthermore, signals transmitted via microstrip lines are susceptible to interference. Some SIW (substrate integrated waveguide)-based phase shifters, such as fixed phase shifters, achieve their phase shift by altering the SIW width, adding additional pillars, slots, stubs, or resonators. To make SIW phase shifters more practical, such as a low-cost, low-profile, high-performance Ka-band continuously adjustable SIW phase shifter, the phase shift mechanism is achieved by perturbing the electric field in the SIW by placing high-dielectric-constant plates in the gaps of the SIW structure; however, the phase shift range is limited by the maximum height between the plates and the slots. A low-loss, electrically controllable two-layer SIW phase shifter uses PIN diodes to change the length of the coupling slot between the two SIW layers, achieving a phase shift range of up to 180°; however, the controllable state in this design is limited by the length of the coupling slot. A compact SIW-based phase shifter implemented in a multilayer ferrite cryogenic co-fired ceramic (LTCC) package with embedded bias windings achieves phase shift ranges of 153° and 73° in two operating modes; however, this phase shifter is an analog phase shifter incompatible with digital circuitry. Another SIW phase shifter, reconfigurable using liquid metal, can provide a phase shift range of up to 180° in 10° steps; however, filling or emptying individual holes with liquid metal requires manual operation, which is inconvenient and difficult to apply in automated systems. Summary of the Invention

[0006] The purpose of this invention is to provide a substrate-integrated waveguide phase shifter to solve at least one of the technical problems existing in the background art.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] Substrate-integrated waveguide phase shifter, including:

[0009] A first metal layer; a first dielectric layer disposed on the first metal layer; a second metal layer disposed on the first dielectric layer; a second dielectric layer disposed on the second metal layer; wherein...

[0010] The SIW phase shifter structure is composed of a first metal layer, a first dielectric layer, and a second metal layer bonded together in sequence. Four rows of through-holes are provided on the first dielectric layer and the second metal layer, with multiple through-holes in each row. Each pair of through-holes forms a group, with the two groups located on opposite sides of the first dielectric layer and symmetrically arranged relative to its central axis. The two rows of through-holes in each group are parallel to each other, and each through-hole corresponds to the other. In each group, the inner row of through-holes is the inner through-hole, and the outer row is the outer through-hole.

[0011] The second dielectric layer has two rows of bias patches, each row of bias patches corresponding to a set of through holes; the bias patches have a first circular patch, the first circular patch has a bias via that passes through the bias patch and the second dielectric layer, and the bias via corresponds to the inner row of vias.

[0012] Furthermore, a PIN diode is soldered between the bias patch and the bias via on top of the second dielectric layer.

[0013] Furthermore, an electrical connection is established between the first circular patch and the inner via.

[0014] Furthermore, the diameter of the bias via is smaller than the diameter of the inner via.

[0015] Furthermore, both the bias via and the internal via are connected to the first metal layer.

[0016] Furthermore, a DC power supply hole is provided on the second dielectric layer, and each pair of symmetrical bias patches is connected to the DC power supply hole through a pair of parallel bias lines.

[0017] Furthermore, the first and second dielectric layers are fabricated using a Rogers 4350B printed circuit board with a dielectric constant ε. r =3.66, with thicknesses of 1.524mm and 0.254mm respectively.

[0018] Furthermore, the SIW phase shifter structure has two tapered microstrip lines at both ends, with the two tapered microstrip lines at each end forming a port.

[0019] Furthermore, an isolation ring is etched around each inner via and each bias via.

[0020] Furthermore, the inner and outer diameters of the isolation ring are 1.7 mm and 2.3 mm, respectively; the length of the bias patch is 8.6 mm and the width is 2.5 mm.

[0021] The beneficial effects of this invention are as follows: Automatic multi-bit digital control is achieved by loading 35 pairs of PIN diodes, which improves the phase shift resolution when a large phase shift range is required; 35-bit / 10° phase resolution and 360° phase shift range are achieved by utilizing reconfigurable width SIW; the number of controllable states can be changed by changing the number of diodes and the length of SIW; and the phase shift step size can be adjusted by adjusting the width difference between the inner and outer vias.

[0022] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of the invention. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is an exploded view of the substrate integrated waveguide phase shifter structure according to an embodiment of the present invention.

[0025] Figure 2 This is a top view of the SIW phase-shifting transmission structure described in an embodiment of the present invention.

[0026] Figure 3 This is a top view of the bias network structure described in an embodiment of the present invention.

[0027] Figure 4 This is a top view of the second dielectric layer according to an embodiment of the present invention.

[0028] Figure 5 This is an insertion loss curve of the phase shifter described in an embodiment of the present invention when the first port is fed.

[0029] Figure 6 This is an insertion loss curve of the phase shifter described in an embodiment of the present invention under partial conditions of second-port feeding.

[0030] Figure 7 This is an insertion loss curve of the phase shifter described in an embodiment of the present invention under partial conditions of first-port feeding.

[0031] Figure 8 This is a graph showing the insertion loss of the phase shifter described in this embodiment of the invention when it is fed from the second port.

[0032] Figure 9 This refers to the relative phase shift between the two states when the first port is powered, as described in this embodiment of the invention.

[0033] Figure 10 This refers to the relative phase shift between the two states when the second port is powered as described in this embodiment of the invention.

[0034] Wherein: 1-First metal layer; 2-First dielectric layer; 3-Second metal layer; 4-Second dielectric layer; 5-First port; 6-Second port; 7-Screw; 8-Inner via; 9-Outer via; 10-Isolation ring; 11-Gradualized microstrip line; 12-First circular patch; 13-Bias via; 14-PIN diode; 15-Inductor; 16-Bias line; 17-Bias patch; 18-DC power supply hole; 19-Second circular patch; 20-Through hole; 21-Waveguide gradualized via. Detailed Implementation

[0035] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0037] It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as here.

[0038] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or groups thereof.

[0039] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0040] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In the description of this specification, the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this technology and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this technology.

[0042] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "setting" should be interpreted broadly. For example, they can refer to fixed connection or setting, detachable connection or setting, or integral connection or setting. Those skilled in the art can understand the specific meaning of these terms in this art according to the specific circumstances.

[0043] To facilitate understanding of the present invention, the present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments. However, the specific embodiments do not constitute a limitation on the embodiments of the present invention.

[0044] Those skilled in the art should understand that the accompanying drawings are merely schematic diagrams of embodiments, and the components in the drawings are not necessarily essential for implementing the present invention.

[0045] like Figure 1 As shown, in one specific embodiment, a substrate integrated waveguide phase shifter is provided, comprising: a first metal layer 1; a first dielectric layer 2 disposed on the first metal layer 1; a second metal layer 3 disposed on the first dielectric layer 2; and a second dielectric layer 4 disposed on the second metal layer 3; wherein the first metal layer 1, the first dielectric layer 2, and the second metal layer 3 are tightly bonded together to form an SIW phase shifter structure; four rows of through holes are provided on the first dielectric layer 2 and the second metal layer 3, each row containing multiple through holes; every two rows of through holes form a group, and the two groups of through holes are respectively located on the first dielectric layer 2. The two sides of layer 2 are symmetrically arranged with respect to the central axis of the first dielectric layer 2; the two rows of through holes in each group are parallel to each other and each through hole corresponds to each other; in each group of through holes, the inner row of through holes is the inner row of through holes 8, and the outer row of through holes is the outer row of through holes 9; each end of each group of through holes is provided with a row of waveguide gradient holes 21; the second dielectric layer 4 is provided with two rows of bias patches 17, each row of bias patches 17 corresponds to a group of through holes; the bias patches are provided with a first circular patch 12, the first circular patch 12 is provided with a bias through hole 13, and the bias through hole 13 corresponds to the inner row of through holes 8.

[0046] Specifically, in this embodiment, for example... Figure 1 The overall structure and working principle of the phase shifter shown are described in detail below:

[0047] The phase shifter consists of a first metal layer 1 and a second metal layer 3, a first dielectric layer 2 and a second dielectric layer 4, and some other structures. In this embodiment, a Rogers 4350B printed circuit board is used for the design of the first dielectric layer 2 and the second dielectric layer 4, and its dielectric constant ε r =3.66, with thicknesses of 1.524 mm and 0.254 mm respectively. The SIW phase shifter structure consists of a first metal layer 1 (as a ground plane), a first dielectric layer 2, a second metal layer 3 (as the top surface), and four rows of metal vias (as sidewalls). The PIN diode and its DC bias network are designed on the second dielectric layer 4. The first dielectric layer 2 and the second dielectric layer 4 are assembled together by screws 7 on both sides.

[0048] In practical applications, the circuit boards used for the design of the first dielectric layer 2 and the second dielectric layer 4 are not limited to the above-mentioned models. Those skilled in the art can select the appropriate printed circuit board model according to the actual situation. Similarly, the thickness is not limited to the above-mentioned values. Those skilled in the art can set the corresponding thickness according to the actual situation.

[0049] In one specific embodiment, Figure 2 This is a top view of the SIW phase shifter structure. To achieve good impedance matching, two tapered microstrip lines 11 and two rows of symmetrical vias (i.e., waveguide tapered vias 21) with tapered waveguide widths are designed at both ends of its second metal layer 3. After the variable width section, the waveguide width is set to 27 mm. Each row of inner vias 8 and outer vias 9 contains 35 vias to achieve 36 reconfigurable states. The waveguide width formed by the outer vias 9 is 27.7 mm, while the waveguide width formed by the inner vias 8 is 23.4 mm. From Figure 2 As can be seen, each inner via 8 corresponds to an isolation ring 10, which is located on the second metal layer. Each isolation ring 10 surrounds an inner via 8. The inner diameter and outer diameter of the isolation ring 10 are 1.7 mm and 2.3 mm, respectively. The diameter and spacing of the inner via 8 and outer via 9 are 1.2 mm and 3 mm, respectively. The total length of the SIW phase-shifting transmission line is 250 mm.

[0050] The structure of the bias network is as follows Figure 3As shown in the figure, two rows of rectangular bias patches 17 are symmetrically arranged on the top of the second dielectric layer 4, with a length of 8.6 mm and a width of 2.5 mm. Each bias patch 17 has a first circular patch 12 in the middle, and a bias via 13 is provided in the center of the first circular patch 12 to establish an electrical connection between the first circular patch 12 and the inner row of vias 8 in the second metal layer 3. An isolation ring is also etched around the periphery of the bias via 13, and the size of this isolation ring is the same as the isolation ring etched on the second metal layer 3. The second dielectric layer 4 also has the same number of second circular patches 19 as the bias patches 17. The second circular patches 19 are located directly below the bias patches 17, and each second circular patch 19 corresponds to a first circular patch 12. Each second circular patch 19 has a through-hole 20, which corresponds to a bias via 13. The diameter of both the through-hole 20 and the bias via 13 is 0.8 mm, smaller than the diameter of the inner via 8, to leave more contact area between the second dielectric layer 4 and the second circular patch 19 for better connection with the inner via 8. Both the bias via 13 and the inner via 8 in the second dielectric layer 4 are connected to the first metal layer 1 and isolated from the bias patches 17. Each pair of symmetrical bias patches 17 is connected to a DC power port 18 via a pair of parallel bias lines 16 to suppress RF current on the bias lines. In this way, each pair of symmetrical inner vias 8 in the first dielectric layer 2 can be simultaneously controlled by a DC power supply through a parallel bias line 16, and each bias line is connected to the bias patch 17 through an inductor 15. Since there are a total of 35 pairs of inner vias, 35 pairs of bias lines are designed, with 18 pairs arranged on the left and 17 pairs arranged on the right.

[0051] like Figure 3 As shown, the PIN diode 14 is soldered between the bias patch 17 and the bias via 13 on top of the second dielectric layer 4. A DC voltage is applied to the positive terminal of the PIN diode through the bias patch and bias line, while the negative terminal of the PIN diode is connected to the ground plane (i.e., the first metal layer 1) through the bias via 13, via 20, and inner via 8. When the diode is forward biased, the switch is on, the inner via 8 is closed, and electromagnetic waves are confined within the inner via 8. This means that the waveguide width of the SIW is determined by the inner via 8. When no bias voltage is applied to the diode, the switch is off, the inner via 8 is isolated, and electromagnetic waves are limited by the outer via.

[0052] According to transmission line theory, the phase difference between the two ports of a transmission line is expressed as:

[0053] Δφ=βL (1)

[0054] In the formula, β is the propagation constant of the transmission line, and L is the length of the transmission line.

[0055] When a two-port network consists of several transmission lines with different propagation constants, equation (1) should be modified as follows:

[0056] Δφ=β1L1+β2L2+…+β n L n (2)

[0057] Where β1, β2, ..., β n These are the propagation constants of different transmission lines, L1, L2, ..., L n These are their lengths. When the sum of L1 and L2 is fixed and L1 is variable, L2 will also change accordingly.

[0058] Therefore, equation (2) can be expressed as:

[0059] Δφ=β1L1+β2(L t -L1)+φ e = (β1-β2)L1+β2L t +φ e (3)

[0060] Where L t It is the total length of L1 and L2, Φ e The phase shift is introduced by the other transmission lines.

[0061] As shown in equation (3), when β1, β2, L t and Φ e The phase difference between the two ports remains constant and is proportional to the variable L1.

[0062] The propagation constant of SIW is determined by the following formula:

[0063]

[0064] Where k0 is the wave number in free space, ε r λ is the relative permittivity, λ0 is the wavelength in free space, and λ c It is TE 10 The cutoff wavelength of the mode is equal to the SIW equivalent width w. e Twice that of the standard SIW. Therefore, different SIW widths can lead to different propagation constants. To obtain two transmission lines with different propagation constants, two different SIW widths are first designed by drilling two rows of metal vias in the traditional SIW structure, such as... Figure 2As shown, this means there are two rows of vias (called inner and outer rows of vias) on each side of the SIW. Then, to electrically change the length of these two transmission lines, the inner row of vias 8 is controlled by switching the state of the PIN diodes, as described above. When the PIN diodes are off, the inner row of vias 8 cannot completely confine electromagnetic waves, and the outer row of vias 9 becomes a sidewall of the SIW. Conversely, when the PIN diodes are on, the electromagnetic waves are confined by the inner vias 8, which become the sidewalls of the SIW. There are 35 pairs of diodes controlling 35 pairs of inner row vias 8. When each pair of diodes is forward biased sequentially from left to right (corresponding to the first port 5 being fed), the lengths of the two transmission lines change accordingly, resulting in a variable phase difference, which means a digital phase shift is achieved. It is worth noting that the biasing of the PIN diodes should be continuous (from left to right or from right to left, with right to left corresponding to the second port 6 being fed), so that the change in the length of the two transmission lines can be continuous, resulting in better impedance matching.

[0065] Figure 5 The proposed phase shifter is shown in partial state |S| when fed from the first port. 11 It can be observed that the proposed phase shifter in the state shown in the figure has |S 11 The voltage level is mostly below -10 dB between 4.2 GHz and 5 GHz. The proposed phase shifter in some states with second-port feeding has a voltage level of |S... 22 |as Figure 6 As shown, the results are roughly consistent with those of the first port power supply. Figure 7 The |S| is shown in the case of first port power supply. 21 As the number of states increases, the insertion loss also increases because the number of PIN diodes increases, leading to a greater overall power consumption. Between 4 and 5.5 GHz, the insertion loss gradually increases from 3 dB to 7 dB. Figure 8 The |S| is shown in the case of second-port power supply. 12 The results are roughly consistent with those of the first port power supply. Figure 9 The relative phase shift between the two states is shown when the first port is powered. For convenience, the phase shift of state 1 is normalized to 0°, and other operating states are compared to it. The results show that, within a 4-5 GHz operating bandwidth, the phase shift step size for each operating state is approximately 10°. Therefore, a 360° phase shift range can be achieved across 36 operating states. Figure 10 The relative phase shift is shown when the device is fed from the second port. The results are in good agreement with those when the device is fed from the first port.

[0066] In summary, the phase shifter described in this embodiment of the invention achieves automatic multi-bit digital control by loading 35 pairs of PIN diodes, improving phase shift resolution when a large phase shift range is required. Utilizing a reconfigurable width SIW, it achieves a 35-bit / 10° phase resolution and a 360° phase shift range. In practical applications, the number of metal vias per row is not limited by the aforementioned number, nor is the number of diodes. By changing the number of diodes and the length of the SIW, the number of controllable states can be changed. Furthermore, the width between the inner and outer via rows is not limited by the aforementioned values; the phase shift step size can be adjusted by adjusting the width difference between the inner and outer via rows.

[0067] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that, based on the technical solutions disclosed in the present invention, various modifications or variations that can be made by those skilled in the art without creative effort should be included within the scope of protection of the present invention.

Claims

1. A substrate-integrated waveguide phase shifter, characterized in that, include: First metal layer; A first dielectric layer is provided on the first metal layer; A second metal layer is disposed on the first dielectric layer; a second dielectric layer is disposed on the second metal layer; wherein, The SIW phase shifter structure is composed of a first metal layer, a first dielectric layer, and a second metal layer bonded together in sequence. Four rows of through-holes are provided on the first dielectric layer and the second metal layer, with multiple through-holes in each row. Each pair of through-holes forms a group, with the two groups located on opposite sides of the first dielectric layer and symmetrically arranged relative to its central axis. The two rows of through-holes in each group are parallel to each other, and each through-hole corresponds to the other. In each group, the inner row of through-holes is the inner through-hole, and the outer row is the outer through-hole. The second dielectric layer has two rows of bias patches, each row of bias patches corresponding to a set of through holes; the bias patches have a first circular patch, the first circular patch has a bias via that passes through the bias patch and the second dielectric layer, and the bias via corresponds to the inner row of vias.

2. The substrate integrated waveguide phase shifter according to claim 1, characterized in that, A PIN diode is soldered between the bias patch and the bias via on top of the second dielectric layer.

3. The substrate integrated waveguide phase shifter according to claim 2, characterized in that, An electrical connection is established between the first circular patch and the inner via.

4. The substrate integrated waveguide phase shifter according to claim 3, characterized in that, The diameter of the offset via is smaller than the diameter of the inner via.

5. The substrate-integrated waveguide phase shifter according to claim 3, characterized in that, Both the bias via and the internal via are connected to the first metal layer.

6. The substrate integrated waveguide phase shifter according to claim 3, characterized in that, The second dielectric layer has a DC power supply hole, and each pair of symmetrical bias patches is connected to the DC power supply hole through a pair of parallel bias lines.

7. The substrate integrated waveguide phase shifter according to any one of claims 1-6, characterized in that, The first and second dielectric layers are fabricated using a Rogers 4350B printed circuit board with a dielectric constant ε. r =3.66, with thicknesses of 1.524mm and 0.254mm respectively.

8. The substrate integrated waveguide phase shifter according to claim 1, characterized in that, The SIW phase shifter structure has two tapered microstrip lines at both ends, and the two tapered microstrip lines at each end form ports.

9. The substrate integrated waveguide phase shifter according to claim 1, characterized in that, An isolation ring is etched around each inner via and each bias via.

10. The substrate-integrated waveguide phase shifter according to claim 9, characterized in that, The inner and outer diameters of the isolation ring are 1.7 mm and 2.3 mm, respectively; the length of the bias patch is 8.6 mm and the width is 2.5 mm.

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