PCB pin identification processing method, device and equipment and storage medium

Abstract

Embodiments of the present application disclose a PCB pin mark processing method, device and equipment and a storage medium. The method comprises the following steps: in response to a received first detection processing instruction, determining a target component in a PCB layout, position information of a first pin mark of the target component, and position information of design elements in the PCB layout except the first pin mark; according to the position information of the first pin mark, the position information of the design elements and a preset overlap condition, confirming an overlap state of the first pin mark and the design elements; and if the first pin mark and the design elements are confirmed to be in the overlap state, adjusting the first pin mark with a pin corresponding to the first pin mark as the center. The scheme can quickly modify and process the first pin mark meeting the overlap condition, thereby improving the processing efficiency.

Description

PCB pin marking processing methods, devices, equipment and storage media Technical Field

[0001] This application relates to the field of printed circuit board technology, and in particular to a PCB pin marking processing method, apparatus, device and storage medium. Background Technology

[0002] A PCB (Printed Circuit Board) is a graphical representation of the parameters of actual electronic components (such as chips, capacitors, inductors, etc.), such as component size, pad size, pin length, and spacing. This allows R&D personnel to access the information in circuit design software during the R&D phase, and facilitates the identification of the size, type, and location of electronic components by machines or personnel during subsequent production processes for soldering.

[0003] The pin 1 marker (or pin 1 marker) is an indispensable silkscreen marking in the PCB package of electronic components that require polarity and do not have foolproof functionality. This marker is used to check whether the component is correctly inserted after machine mounting or manual insertion. Therefore, it is necessary to ensure that the marker is positioned correctly and can be clearly seen, without being obstructed by other silkscreen markings, pads, etc.

[0004] In related technologies, R&D personnel need to screen components with one-pin markings one by one, while also checking whether the markings interfere with other silkscreen markings, pads, or vias. If interference exists, R&D personnel need to manually modify them. However, due to the numerous electronic components integrated on the PCB, this process is time-consuming, has low accuracy, is prone to omissions, and involves complex and inefficient manual modifications, making it difficult to ensure the uniformity of the one-pin markings. Summary of the Invention

[0005] This application provides a PCB pin marking processing method, apparatus, device, and storage medium, which avoids spending a lot of time manually inspecting pin markings on the PCB layout, and can quickly modify pin markings that overlap with design elements, thus improving processing efficiency.

[0006] In a first aspect, embodiments of this application provide a PCB pin marking processing method, including:

[0007] In response to the received first detection processing instruction, the location information of the target component in the PCB layout, the first pin identifier of the target component, and the location information of the design elements in the PCB layout other than the first pin identifier are determined, wherein the target component is a component with a first pin identifier;

[0008] Based on the position information of the first pin identifier, the position information of the design element, and the preset overlap conditions, the overlap state between the first pin identifier and the design element is confirmed.

[0009] If the first pin identifier is confirmed to overlap with the design element, adjust the first pin identifier with the pin corresponding to the first pin identifier as the center.

[0010] Secondly, embodiments of this application also provide a PCB pin marking processing device, comprising:

[0011] The information acquisition unit is configured to, in response to a received first detection processing instruction, determine a target component on a PCB layout, the position information of the first pin identifier of the target component, and the position information of design elements on the PCB layout other than the first pin identifier, wherein the target component is a component with a first pin identifier.

[0012] The overlap determination unit is configured to determine the overlap state between the first pin identifier and the design element based on the position information of the first pin identifier, the position information of the design element, and a preset overlap condition.

[0013] The identification processing unit is configured to adjust the first pin identifier with the pin corresponding to the first pin identifier as the center if the first pin identifier is confirmed to be overlapping with the design element.

[0014] Thirdly, embodiments of this application also provide a PCB pin marking processing device, comprising:

[0015] One or more processors;

[0016] Memory, used to store one or more programs;

[0017] When one or more programs are executed by one or more processors, the one or more processors implement the PCB pin identification processing method as described in the above embodiments.

[0018] Fourthly, embodiments of this application also provide a storage medium storing computationally executable instructions, which, when executed by a processor, are used to perform the PCB pin marking processing method as described above.

[0019] Fifthly, embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, is used to implement the PCB pin marking processing method as described in the above embodiments.

[0020] This application embodiment locates components with a first pin identifier on the PCB layout, determines the position information of the first pin identifier and the position information of design elements other than the first pin identifier on the PCB layout, and thus determines whether the first pin identifier overlaps with the design elements. If they overlap, the first pin identifier is modified so that it can be effectively identified and no longer overlaps with the design elements. This effectively reduces repetitive inspection and processing work, avoids spending a lot of time on manual inspection and modification, and improves processing efficiency. Attached Figure Description

[0021] Figure 1 is a flowchart of the PCB pin identification processing method provided in an embodiment of this application;

[0022] Figure 2 is a schematic diagram of the first pin area on the PCB layout provided in the embodiment of this application;

[0023] Figure 3 is a flowchart of a PCB pin identification processing method provided in another embodiment of this application;

[0024] Figure 4 is a schematic diagram of an overlapping state of a foot mark and design elements provided in an embodiment of this application;

[0025] Figure 5 is a schematic diagram of another overlapping state of the foot mark and design elements provided in the embodiment of this application;

[0026] Figure 6 is a schematic diagram of another overlapping state of the foot mark and design elements provided in the embodiments of this application;

[0027] Figure 7 is a schematic diagram of the rotation and movement of one foot marker provided in an embodiment of this application;

[0028] Figure 8 is a schematic diagram of the replacement of one foot mark according to an embodiment of this application;

[0029] Figure 9 is a schematic diagram of the enlarged one-leg mark provided in an embodiment of this application;

[0030] Figure 10 is a flowchart of a PCB pin marking processing method provided in another embodiment of this application;

[0031] Figure 11 is a schematic diagram of the display interface of the detection and processing tool provided in the embodiment of this application;

[0032] Figure 12 is a schematic diagram of the PCB pin marking processing device provided in an embodiment of this application;

[0033] Figure 13 is a schematic diagram of the PCB pin marking processing device provided in an embodiment of this application. Detailed Implementation

[0034] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the embodiments described herein are for illustrative purposes only and not for limiting the scope of the application. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present application are shown in the accompanying drawings, not the entire structure.

[0035] It should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity, operation, or object from another entity, operation, or object, and do not necessarily require or imply any such actual relationship or order between these entities, operations, or objects. For example, "first" and "second" in "first component" and "second component" are used to distinguish two different components.

[0036] The PCB pin marking processing method provided in this application can be executed by a computing device such as a computer or tablet computer. At least one operating system is installed on the computing device, including but not limited to Linux and Windows systems. The computing device can also install at least one application based on the operating system. For example, a detection and processing tool (application) with PCB pin marking processing functionality is installed on the computing device. This detection and processing tool is an application developed using the Cadenceskill language. This application can be a built-in application of the operating system or an application downloaded from a third-party device or server.

[0037] Figure 1 is a flowchart of a PCB pin identification processing method provided in an embodiment of this application. Referring to Figure 1, the method includes at least the following steps:

[0038] Step S110: In response to the received first detection processing instruction, determine the target component in the PCB layout, the position information of the first pin identifier of the target component, and the position information of the design elements in the PCB layout other than the first pin identifier.

[0039] In the field of printed circuit board (PCB) design, there are usually dedicated design software programs, such as Allegro, which are computer-based circuit diagram design software. Within the editing interface of this software, components related to the printed circuit, such as chips, resistors, and switching transistors, can be added. On the corresponding PCB layout, these components are displayed as pads corresponding to their pins and corresponding area labels. For example, if the component is a resistor, it will be displayed as a rectangle with pads at both ends on the PCB layout. Wiring between components can also be added to the PCB layout, and further, screw holes for mounting can be added, ultimately resulting in a PCB design suitable for production.

[0040] A PCB layout contains numerous design elements, such as pads, silkscreen markings, and vias. Therefore, multiple layers are used to place these design elements on the PCB layout. For example, in a double-sided PCB layout, there are routing layers and silkscreen layers. The routing layer includes a top layer and a bottom layer. Pads and traces can be placed on the top and bottom layers, while vias connect the top and bottom layers and can also be displayed as pads on the top and bottom layers. Silkscreen markings are placed on the silkscreen layer and can be patterns or text used for identification. It's conceivable that an XY coordinate system exists on the PCB layout to determine the position of each component and design element. The origin of the coordinate system can be set at the midpoint or boundary point of the PCB layout.

[0041] The PCB pin marking processing method in this application can be implemented using a detection and processing tool developed based on the Cadence skill language. This tool can be configured by adding a drop-down toolbar to the menu bar of the printed circuit board design software. When the user triggers the control corresponding to the detection and processing tool in the drop-down toolbar, the computing device can run the detection and processing tool to detect and process the printed circuit design drawing, i.e., the PCB layout.

[0042] In the specific implementation of this solution, for ease of description, the first pin identifier will be referred to as a "pin identifier". In response to the received first detection processing instruction, the component with a pin identifier (i.e., the target component) on the PCB layout is determined. It can be understood that a component with a pin identifier is a polarized component without foolproof features, such as a logic chip. When creating the component's package, an attribute indicating that it has a pin identifier can be assigned. Therefore, the detection processing tool can identify the component with a pin identifier by traversing all components on the PCB layout.

[0043] It's conceivable that the positions of pre-placed design elements on the PCB layout are fixed; that is, the location information of a design element can be determined by querying the package attribute information of the component to which it belongs. In circuit diagram design software, you can obtain the package attribute information of a component by clicking on it. This package attribute information includes the component name, number, number of pins, coordinates on the PCB layout, and whether it has pin identifiers. Among these, pin identifiers are used to indicate that the corresponding component has a first pin identifier.

[0044] In one embodiment, in response to a first detection processing instruction, the detection processing tool acquires the package attribute information of each component on the PCB layout. When it is determined that the package attribute information of a component includes pin identifiers, the component is identified as the target component.

[0045] The first pin region of the target component is determined. This first pin region is the area on the target component designated for placing a pin identifier. A pin identifier is a silkscreen identifier located on the silkscreen layer, corresponding to the first pin. When creating the package, the pin identifier is drawn as a first-type element on the silkscreen layer, and the drawn area is defined within the first pin region. It is conceivable that the first-type element is a design element with an independent shape type; it can be a silkscreen identifier in shapes such as triangles, circles, or L-shapes. That is, the shape of the pin identifier can be triangular, circular, L-shaped, etc. If a first-type element is identified within the first pin region, it can be determined that this first-type element is the first pin identifier, and thus its positional information, such as its coordinates on the PCB layout, can be determined. Therefore, the positional information of the first-type element can be used as the positional information of the pin identifier.

[0046] As shown in Figure 2, in one embodiment, the framed area 101 is used to represent the first pin area. It is necessary to determine whether there is a first type element located on the silkscreen layer of the PCB layout within the first pin area. If it exists, the first type element is a pin identifier, and the position of the pin identifier is obtained, such as obtaining the coordinate range of the area covered by the pin identifier on the PCB layout.

[0047] For example, the pin identifier 102 is a triangular identifier. Therefore, within the coordinate range corresponding to the first pin area on the silkscreen layer, the triangular identifier is identified. Silkscreen identifiers that meet the above conditions (i.e., are determined to be the first type element on the silkscreen layer located within the first pin area) can be identified as pin identifiers. As shown in Figure 2, if there is a triangular identifier within the boxed area 101, then the triangular identifier is the pin identifier 102. Furthermore, the coordinate range of the triangular identifier is obtained to determine the position information of the pin identifier on the PCB layout.

[0048] Step S120: Based on the position information of the first pin identifier, the position information of the design element, and the preset overlap conditions, confirm the overlap state between the first pin identifier and the design element.

[0049] Referring to Figure 3, in one embodiment, the determination of whether the foot mark and the design element are overlapping can be achieved through the following steps:

[0050] Step S121: Determine the overlapping area between the first pin identifier and the design element based on the position information of the first pin identifier and the position information of the design element.

[0051] Step S122: If the overlapping area meets the preset overlapping conditions, then confirm that the first pin identifier and the design element are in an overlapping state.

[0052] The overlap conditions are defined as follows: the overlap area between the pin marker and the pad, or the overlap area between the pin marker and the via (or silkscreen marking) is greater than an area threshold, or the overlap area between the pin marker and the silkscreen marking is greater than an area threshold. In other words, if the pin marker overlaps with the pad, it can be considered that the pin marker and the design element are in an overlapping state. The overlap area between the pin marker and the via (or silkscreen marking) needs to be greater than an area threshold. This area threshold is determined based on the completeness and identifiability of the pin marker. For example, if the area threshold is set to 30% of the area covered by the pin marker, when the overlapping area is greater than the area threshold, the pin marker is difficult to identify. This means that in actual production, the pin marker is not complete enough, which is detrimental to the subsequent inspection and identification processes.

[0053] It is understandable that the position information of the marker includes the coordinate range of the area covered by the marker on the PCB layout, and the coordinate range of the already placed design element on the PCB layout is also fixed. Therefore, when it is determined that there is an overlapping area between the marker and the design element and the overlapping area meets the preset overlap conditions, it means that the marker and the design element are in an overlapping state, and the marker needs to be modified.

[0054] For example, the coordinate range corresponding to a foot marker can be compared with the coordinate range corresponding to adjacent design elements. For instance, when the coordinate range corresponding to the covered area overlaps with the coordinate range corresponding to the adjacent pad, the foot marker and the pad are in an overlapping state.

[0055] As shown in Figure 4, on the PCB layout, there is a transistor Q1 on one side of the first disconnecting switch fuse QSA1, and a pin mark 102 is provided at the first pin of QSA1. The pin mark 102 overlaps with the pad 103 of one pin of Q1, making it difficult to detect and identify the pin mark 102 in actual production.

[0056] Alternatively, if the coordinate range corresponding to a foot mark overlaps with the coordinate range corresponding to a nearby silkscreen mark (or via), and the area of ​​the overlapping area is greater than the area threshold, it can be determined that the foot mark and the silkscreen mark (or via) are in an overlapping state.

[0057] As shown in Figure 5, on the PCB layout, QSA2 represents the silkscreen mark 104 of the second disconnecting switch fuse QSA2 on the silkscreen layer. On the silkscreen layer of the PCB layout, when the silkscreen mark 104 and the foot mark 102 have an overlapping area, and the area of ​​the overlapping area is greater than 30% of the area covered by the foot mark 102, then the foot mark 102 and the silkscreen mark 104 are in an overlapping state.

[0058] As shown in Figure 6, on the PCB layout, there is a via 105 on one side of the third disconnecting switch fuse QSA3. The one-leg mark 102 of QSA3 overlaps with the via 105, and the area of ​​the overlap is greater than 30% of the coverage area corresponding to the one-leg mark 102. Therefore, the one-leg mark 102 and the via 105 are in an overlapping state.

[0059] Step S130: If the first pin identifier and the design element are confirmed to be in an overlapping state, adjust the first pin identifier with the pin corresponding to the first pin identifier as the center.

[0060] In one embodiment, when a foot marker overlaps with a design element, the foot marker can be adjusted by rotating and moving it around the first pin of the target component.

[0061] It is understandable that there is a gap between the first-pin marker and the first pin. The first-pin marker is centered on the first pin, and its rotation and movement are centered on the center point of the first pin, maintaining this gap during rotation and movement. It should be considered that when the first-pin marker is a directional shape, such as a triangle, L-shape, or other non-circular shape with corners, it is considered a directional shape. Therefore, during rotation and movement, the first-pin marker maintains its directional nature. For example, if the first-pin marker points to the first pin before rotation and movement, it will still point to the first pin after rotation and movement.

[0062] In one embodiment, during the rotation and movement of the foot marker, in addition to using the first pin of the target component as the rotation center and maintaining the distance between the foot marker and the first pin, a preset step angle and direction can be used to rotate and move the foot marker. For example, the step angle is 5°, and the step direction is clockwise. Therefore, the rotation and movement of the foot marker is adjusted by 5° clockwise each time until the foot marker and the design element are no longer overlapping. It should be understood that the preset step angle and direction can be set according to design requirements.

[0063] Figure 7 is a schematic diagram of the rotating and moving one-pin identifier provided in the embodiment of this application. The one-pin identifier 102 rotates and moves around the first pin as the center. For example, when it moves to above the pad corresponding to the pin of transistor Q1, the one-pin identifier 102 maintains a distance from the first pin and points towards the first pin. As shown in Figure 7, the one-pin identifier 102 does not overlap with the pad of the Q1 pin. Therefore, the adjusted one-pin identifier 102 no longer overlaps with the pad, making it convenient and effective to detect and identify the one-pin identifier in actual production. It should be noted that the path of the rotating and moving one-pin identifier can be an arc with the center point of the first pin as the center and the radius being the distance between the two (such as the distance between the center point of the one-pin identifier and the center point of the first pin). Therefore, the one-pin identifier rotates and moves by one step angle clockwise along the above path each time.

[0064] In one embodiment, for adjusting the one-foot marker, the original one-foot marker can be deleted, and a new one-foot marker can be regenerated on the path of rotation and movement, and the regenerated one-foot marker does not overlap with the design element.

[0065] In one embodiment, for adjusting a pin marker, the replacement shape of the pin marker can be determined based on a pre-stored marker shape, and the replacement size of the pin marker can be determined based on the side width information of the target component on the PCB layout solid layer, thereby replacing the pin marker. It is understood that in printed circuit design, a place-bound layer (i.e., a solid layer) is typically used on the PCB layout to define the dimensions of components, such as side width and height.

[0066] Figure 8 is a schematic diagram of the replacement of the pin identifier provided in the embodiment of this application. The pre-stored identifier shape can be L-shaped, circular, etc. If the pre-stored identifier shape is L-shaped, the original triangular pin identifier 102 is replaced with the L-shaped pin identifier 120. Moreover, it is conceivable that the minimum size of the pin identifier 102 is limited, that is, the pin identifier 102 is set in the first pin area of ​​the component with a certain size. Therefore, it is necessary to determine the size of the replaced pin identifier 102 according to the side width information of the component on the PCB layout.

[0067] It is understandable that the replaced pin marking is set according to a first size ratio, which can be set according to design requirements. For example, the minimum size of the pin marking, i.e., the first size ratio, is: the length is 0.1 times the width of the component, and the width is 0.35 times the length of the pin marking. Therefore, when the component's side width information is 8×6mm, the corresponding dimensions of the L-shaped pin marking are: length 0.6mm and width 0.21mm. It should be noted that the L-shaped pin marking maintains the original spacing; that is, if the original triangular pin marking's spacing from the first pin is 0.15mm, then the spacing between the L-shaped pin marking and the first pin will also remain at 0.15mm.

[0068] In one embodiment, the adjustment of the pin mark can also be to expand the coverage area of ​​the pin mark until the area of ​​the overlapping area of ​​the pin mark and the silkscreen mark is greater than the area threshold, or until the area of ​​the overlapping area of ​​the first pin mark and the via is less than the area threshold.

[0069] As shown in Figure 9, which is a schematic diagram of the enlarged pin identifier provided in this embodiment of the application, the coverage area of ​​the pin identifier 102 is enlarged, that is, the pin identifier 102 is enlarged on the PCB layout, so that the area of ​​the overlapping area between the pin identifier 102 and the via 105 is less than the area threshold. That is, when the area of ​​the overlapping area in the coverage area of ​​the pin identifier 102 is less than the threshold (e.g., 30%), the expansion of the coverage area of ​​the pin identifier 102 is stopped. It is worth noting that during the process of expanding the pin identifier 102, the distance between the pin identifier 102 and the first pin remains unchanged.

[0070] It should be considered that the foot marker can be adjusted using at least one of the adjustment methods provided in the above embodiments.

[0071] As can be seen from the above solution, the embodiment of this application adjusts the corresponding first pin as the center for the one-foot mark that overlaps with the design element, thereby effectively reducing repetitive inspection and processing work, avoiding R&D personnel from spending a lot of time on manual inspection and manual modification, and thus improving processing efficiency.

[0072] Figure 10 is a flowchart of a PCB pin marking processing method provided in another embodiment of this application. Referring to Figure 10, after adjusting the pin marking, it is also necessary to confirm the pin marking. The specific steps are as follows:

[0073] Step S150: Determine whether the first pin identifier and the design element are still in an overlapping state.

[0074] Step S160: If the first pin identifier is still overlapping with the design element, then the first pin identifier is determined to be an identifier to be processed.

[0075] Step S170: In response to the received second detection processing instruction, adjust the identifier to be processed with the pin corresponding to the identifier to be processed as the center until the identifier to be processed and the design element are not in an overlapping state.

[0076] Based on the above embodiments, for the processing of one-foot markings, after receiving the first detection processing instruction, the application program that applies the PCB pin marking processing method of the present application embodiment can automatically perform batch processing of one-foot markings that overlap with design elements.

[0077] After processing, it can be checked again whether the one-leg mark still overlaps with the design element. If the one-leg mark is still overlapping with the design element, it means that the automatic processing of the one-leg mark cannot make it no longer overlap with the design element, and thus the one-leg mark is identified as a mark to be processed. It is conceivable that, in the case of the existence of marks to be processed, the detection tool can also generate a list of marks to be processed for the reference of the R&D personnel.

[0078] The pending list records the number and location information of the markers that still overlap with design elements (i.e., markers to be processed), such as the defined number and coordinates of the markers on the PCB layout. It's conceivable that the marker number can be manually defined by the R&D personnel during the circuit design process, or it can be customized by the application. Furthermore, markers correspond to components, so the marker number can also be associated with the corresponding component number. The coordinates of the marker on the PCB layout can be represented by a set of coordinates in the coordinate system representing the PCB layout area covered by the marker, or by the coordinates of any point on the marker, such as the center point or boundary point.

[0079] When a second detection processing instruction is received, which is a control instruction for controlling the application to adjust one or more identifiers to be processed, the application adjusts the selected identifiers to be processed until the identifiers to be processed and the design elements are no longer overlapping.

[0080] It should be considered that the application can execute the processing steps provided in this embodiment after processing each one-legged identifier, or it can execute the processing steps provided in this embodiment after processing all one-legged identifiers. This embodiment does not limit this. Furthermore, in this embodiment, after adjusting the identifier to be processed, it can be determined again whether the adjusted identifier still overlaps with the design element. If it still overlaps, it is adjusted again. It is conceivable that when a list of identifiers to be processed is set, if the adjusted identifier no longer overlaps with the design element, the list of identifiers to be processed is updated, and the relevant information of the corresponding identifier is deleted.

[0081] This application embodiment processes one-leg markers in batches using the above-described adjustment method, reducing the workload of R&D personnel. Furthermore, it re-evaluates whether the adjusted one-leg markers still overlap with design elements, thereby identifying one-leg markers that the application's automatic adjustment strategy failed to adjust. This allows R&D personnel to quickly process non-compliant one-leg markers, and the entire process can be handled automatically by the application according to the adjustment strategy configured by the R&D personnel, eliminating the need for manual modification and improving work efficiency.

[0082] In one embodiment, a user can quickly adjust a pin marker using a detection processing tool. Referring to Figure 11, which is a schematic diagram of the display interface of the detection processing tool provided in this embodiment, multiple controls are provided on the display interface. Users can select the corresponding control using a mouse, keyboard, or other devices to execute the corresponding function. For example, after selecting the "Check&Deal" control, the detection processing tool executes the PCB pin marker processing method described in this embodiment. That is, the detection processing tool checks whether the pin markers on the PCB layout meet the overlap condition. If the pin markers meet the overlap condition, the pin markers on the PCB layout are adjusted with the first pin as the center. After adjustment, if there are still pin markers that meet the overlap condition, the detection processing tool generates a list of pin markers to be processed and displays the list on the display interface, such as displaying the number and position information of the pin markers to be processed. The position information can be represented by the coordinates of the center point of the pin marker corresponding to the pin marker to be processed.

[0083] Users can select the pending identifiers in the processing list using the "Previous" or "Next" controls. It's also possible to select multiple identifiers in the list. After selecting the identifiers, users can choose the adjustment method, such as the "Move" option for rotation, the "Replace" option for replacement, or the "Enlarge" option for enlarging. Therefore, users can adjust the pending identifiers using the "Deal" control according to the pre-defined adjustment method.

[0084] Figure 12 is a schematic diagram of the PCB pin marking processing device provided in an embodiment of this application. This device is used to execute the PCB pin marking processing method provided in the above embodiment, and has corresponding functional modules and beneficial effects for executing the method. As shown in the figure, the device includes:

[0085] The information acquisition unit 201 is configured to, in response to the received first detection processing instruction, determine the target component in the PCB layout, the position information of the first pin identifier of the target component, and the position information of the design elements in the PCB layout other than the first pin identifier.

[0086] The overlap determination unit 202 is configured to determine the overlap state between the first pin identifier and the design element based on the position information of the first pin identifier, the position information of the design element, and the preset overlap conditions.

[0087] The identification processing unit 203 is configured to adjust the first pin identifier with the pin corresponding to the first pin identifier as the center if the first pin identifier is confirmed to be overlapping with the design element.

[0088] Based on the above embodiments, the information acquisition unit 201 is further configured as follows:

[0089] In response to the first detection and processing command, the package attribute information of each component in the PCB layout is obtained;

[0090] The component whose package attribute information includes pin identifiers is identified as the target component. The pin identifier is used to indicate that the corresponding component has a first pin identifier.

[0091] Determine the first pin region of the target component;

[0092] Identify the first type element and determine the first type element as the first pin identifier. The first type element is an independent shape type element in the first pin area on the silkscreen layer of the PCB layout.

[0093] Determine the position information of the first type of element in order to obtain the position information of the first pin identifier accordingly.

[0094] Based on the above embodiments, the design elements include pads, silkscreen markings, and vias, and the overlap determination unit 202 is further configured as follows:

[0095] Based on the position information of the first pin identifier and the position information of the design element, determine the overlapping area between the first pin identifier and the design element;

[0096] If the overlapping area meets the preset overlapping conditions, then it is determined that the first pin identifier and the design element are in an overlapping state.

[0097] The overlap condition is that the first pin identifier and the pad have an overlapping area, or the area of ​​the overlapping area between the first pin identifier and the via is greater than the area threshold, or the area of ​​the overlapping area between the first pin identifier and the silkscreen identifier is greater than the area threshold.

[0098] Based on the above embodiments, the identification processing unit 204 is further configured to rotate and move the first pin identifier with the first pin of the target component as the center.

[0099] Based on the above embodiments, the identification processing unit 204 is further configured as follows:

[0100] Using the first pin of the target component as the rotation center, maintain the distance between the first pin label and the first pin, and rotate and move the first pin label by a preset step angle and direction until the first pin label and the design element are no longer overlapping.

[0101] Based on the above embodiments, the identification processing unit 204 is further configured as follows:

[0102] Based on the pre-stored identifier shape, determine the replacement shape of the first pin identifier;

[0103] Based on the side width information of the target component on the physical layer of the PCB layout, determine the replacement size of the first pin identifier;

[0104] Replace the first pin identifier according to the replacement shape and replacement size.

[0105] Based on the above embodiments, the marking processing unit 204 is further configured to: expand the coverage area of ​​the first pin mark until the area of ​​the overlapping area of ​​the first pin mark and the silkscreen mark is less than the area threshold, or until the area of ​​the overlapping area of ​​the first pin mark and the via is less than the area threshold.

[0106] Based on the above embodiments, a detection processing unit is also included, which is configured as follows:

[0107] Determine whether the first pin identifier and the design element are still overlapping;

[0108] If the first pin identifier still overlaps with the design element, then the first pin identifier is determined to be an identifier to be processed.

[0109] In response to the received second detection processing instruction, the identifier to be processed is adjusted with the first pin corresponding to the identifier to be processed as the center until the identifier to be processed and the design element are no longer in an overlapping state.

[0110] It is worth noting that in the embodiments of the PCB pin marking processing device described above, the various units included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of this application.

[0111] Figure 13 is a schematic diagram of the PCB pin marking processing device provided in an embodiment of this application. As shown in the figure, the device can be used to execute the PCB pin marking processing method provided in the above embodiment, and has the corresponding functional modules and beneficial effects of the execution method. The device includes a processor 301, a memory 302, an input device 303, and an output device 304. The number of processors 301 in the device can be one or more. Figure 13 shows an example of one processor 301. The processor 301, memory 302, input device 303, and output device 304 in the device can be connected by a bus or other means. Figure 13 shows an example of connection via a bus. The memory 302, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the PCB pin marking processing method in the embodiment of this application. The processor 301 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 302, thereby realizing the above-mentioned PCB pin marking processing method.

[0112] The memory 302 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 302 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 302 may further include memory remotely located relative to the processor 310, which can be connected to the terminal device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0113] Input device 303 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the device. Output device 304 may include display devices such as a display screen.

[0114] Furthermore, embodiments of this application also provide a storage medium storing computationally executable instructions. When executed by a computer processor, the computer-executable instructions are used to perform relevant operations in the PCB pin identification processing method provided in any embodiment of this application, and have corresponding functions and beneficial effects.

[0115] This application also provides a computer program product, which includes a computer program that, when executed by a processor, performs related operations as provided in any embodiment of the PCB pin marking processing method, and has corresponding functions and beneficial effects.

[0116] Those skilled in the art will understand that embodiments of this application may be provided as methods, systems, or computer program products.

[0117] Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams. These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0118] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory. Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0119] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0120] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0121] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for processing PCB pin markings, characterized in that, include: In response to the received first detection processing instruction, the position information of the target component, the first pin identifier of the target component, and the position information of the design elements in the PCB layout other than the first pin identifier are determined. The target component is a component with a first pin identifier. Based on the position information of the first pin identifier, the position information of the design element, and a preset overlap condition, the overlap state between the first pin identifier and the design element is confirmed. If the first pin identifier and the design element are confirmed to be in an overlapping state, the first pin identifier is adjusted with the pin corresponding to the first pin identifier as the center.

2. The PCB pin marking processing method according to claim 1, characterized in that, The step of determining the target component on the PCB layout, the position information of the first pin identifier of the target component, and the position information of the design element on the PCB layout in response to the received first detection processing instruction includes: in response to the first detection processing instruction, acquiring the package attribute information of each component in the PCB layout; determining that the component whose package attribute information includes a pin identifier is the target component, wherein the pin identifier is used to indicate that the corresponding component has the first pin identifier; determining the first pin area of ​​the target component; identifying a first type element and determining the first type element as the first pin identifier, wherein the first type element is an independent shape type element in the first pin area on the silkscreen layer of the PCB layout; and determining the position information of the first type element to correspondingly acquire the position information of the first pin identifier.

3. The PCB pin marking processing method according to claim 1 or 2, characterized in that, The design elements include pads, silkscreen markings, and vias. Correspondingly, confirming the overlap state between the first pin marking and the design element based on the position information of the first pin marking, the position information of the design element, and a preset overlap condition includes: determining the overlap area between the first pin marking and the design element based on the position information of the first pin marking and the position information of the design element; if the overlap area satisfies the preset overlap condition, then confirming that the first pin marking and the design element are in an overlap state; the overlap condition is that there is an overlap area between the first pin marking and the pad, or that the area of ​​the overlap area between the first pin marking and the via is greater than an area threshold, or that the area between the first pin marking and the silkscreen marking is greater than the area threshold.

4. The PCB pin marking processing method according to claim 1, characterized in that, If the first pin identifier is confirmed to be overlapping with the design element, the first pin identifier is adjusted with the pin corresponding to the first pin identifier as the center, including: rotating and moving the first pin identifier with the first pin of the target component as the center.

5. The PCB pin marking processing method according to claim 4, characterized in that, The step of rotating and moving the first pin identifier with the first pin of the target component as the center includes: using the first pin of the target component as the rotation center, maintaining the distance between the first pin identifier and the first pin, and rotating and moving the first pin identifier with a preset step angle and direction until the first pin identifier and the design element are no longer in the overlapping state.

6. The PCB pin marking processing method according to claim 1, characterized in that, If the first pin identifier is confirmed to overlap with the design element, the first pin identifier is adjusted with the pin corresponding to the first pin identifier as the center, including: determining the replacement shape of the first pin identifier based on a pre-stored identifier shape; determining the replacement size of the first pin identifier according to the side width information of the target component on the solid layer of the PCB layout; and replacing the first pin identifier according to the replacement shape and the replacement size.

7. The PCB pin marking processing method according to claim 3, characterized in that, If the first pin identifier is confirmed to be overlapping with the design element, the first pin identifier is adjusted with the pin corresponding to the first pin identifier as the center, including: expanding the coverage area of ​​the first pin identifier until the area of ​​the overlapping area between the first pin identifier and the silkscreen identifier is less than the area threshold, or until the area of ​​the overlapping area between the first pin identifier and the via is less than the area threshold.

8. The PCB pin marking processing method according to any one of claims 1 or 2, 4-7, characterized in that, If the first pin identifier and the design element are confirmed to be in an overlapping state, after adjusting the first pin identifier with the pin corresponding to the first pin identifier as the center, the method further includes: determining whether the first pin identifier and the design element are still in an overlapping state; if the first pin identifier and the design element are still in an overlapping state, determining the first pin identifier as an identifier to be processed; in response to the received second detection processing instruction, adjusting the identifier to be processed with the first pin corresponding to the identifier to be processed as the center until the identifier to be processed and the design element are no longer in an overlapping state.

9. A PCB pin marking processing device, characterized in that, include: The information acquisition unit is configured to, in response to a received first detection processing instruction, determine a target component on a PCB layout, the position information of the first pin identifier of the target component, and the position information of design elements on the PCB layout other than the first pin identifier, wherein the target component is a component with a first pin identifier. The overlap determination unit is configured to determine the overlap state between the first pin identifier and the design element based on the position information of the first pin identifier, the position information of the design element, and a preset overlap condition; the identifier processing unit is configured to adjust the first pin identifier with the pin corresponding to the first pin identifier as the center if the first pin identifier and the design element are confirmed to be in an overlap state.

10. A PCB pin marking processing device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When one or more of the programs are executed by one or more of the processors, the one or more of the processors implement the PCB pin identification processing method as described in any one of claims 1-8.

11. A storage medium storing computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a processor, are used to perform the PCB pin identification processing method as described in any one of claims 1-8.

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