A driving circuit of a goa unit and a display panel

Abstract

The application provides a driving circuit of a GOA unit and a display panel. The driving circuit comprises a timing controller, a horizontal shifter and a timing voltage adjusting circuit. The timing controller is configured to output a first GOA timing voltage to the horizontal shifter. The horizontal shifter is configured to generate a second GOA timing voltage by using the first GOA timing voltage and output the second GOA timing voltage to the GOA unit. The timing voltage adjusting circuit is configured to adjust the first GOA timing voltage or the second GOA timing voltage after receiving a start-up signal, so that the horizontal shifter outputs the second GOA timing voltage at a high level in a period from start-up to display, thereby enabling the GOA unit to be normally discharged and set. The application pulls up the voltage for driving the GOA unit at start-up, thereby enabling the GOA unit to be normally discharged and set, and effectively avoiding the horizontal display residual image caused by the residual charge of the GOA unit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit and display panel for a GOA unit. 。 Background Technology

[0002] Currently, in GOA (Gate Driver on Array) screens, due to residual point charge on the PU (pull-up) / OUTPUT of the GOA cells after power-off, the output GOUT causes the TFTs (thin-film transistors) in the AA (operable) area to turn on to varying degrees. When the GOA screen is quickly powered on again within approximately 500ms after power-off, varying degrees of lateral ghosting appear on the screen.

[0003] There is currently no effective solution to the aforementioned technical problems. Summary of the Invention

[0004] In view of this, this application provides a driving circuit and display panel for a GOA unit. By pulling up the voltage driving the GOA unit during the power-on to display period, the GOA unit is normally discharged and set, effectively avoiding the GOA unit charge causing the TFT to turn on incorrectly, and avoiding horizontal display ghosting that occurs during power-on.

[0005] In a first aspect, embodiments of this application provide a driving circuit for a GOA unit, including: a timing controller, a horizontal shifter, and a timing voltage adjustment circuit;

[0006] The timing controller is used to output a first GOA timing voltage to the horizontal shifter;

[0007] The horizontal shifter is used to generate a second GOA timing voltage using the first GOA timing voltage, and outputs the second GOA timing voltage to the GOA unit;

[0008] The timing voltage adjustment circuit is used to adjust the first GOA timing voltage or the second GOA timing voltage after receiving the power-on signal, so that the horizontal shifter outputs a high-level second GOA timing voltage during the power-on to display period, thereby enabling the GOA unit to discharge and be set normally.

[0009] In one possible implementation, the timing voltage adjustment circuit includes: a power supply, a power management chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, a first MOSFET switch, a second MOSFET switch, and a third MOSFET switch; the power management chip has an XON terminal; the first and second MOSFET switches are both N-type; the third MOSFET switch is P-type; wherein,

[0010] The sixth resistor is connected to the timing controller and the horizontal shifter; the seventh resistor is connected to the horizontal shifter and the GOA unit;

[0011] The operating power supply is connected to the source of the power management chip and the first MOSFET switch respectively; the XON terminal of the power management chip is connected to the first terminal of the first resistor and the gate of the first MOSFET switch respectively; the drain of the first MOSFET switch is connected to the first terminal of the second resistor; the second terminal of the first resistor is connected to the second terminal of the second resistor.

[0012] The first end of the third resistor is connected to the first end of the fourth resistor; the second end of the third resistor is connected to the operating power supply; the second end of the fourth resistor is connected to the drain of the second MOS transistor switch; the gate of the second MOS transistor switch is connected to the drain of the first MOS transistor switch; the source of the first MOS transistor switch and the source of the second MOS transistor switch are both grounded.

[0013] The gate of the third MOS transistor switch is connected to the connection line between the third resistor and the fourth resistor, and the source of the third MOS transistor switch is connected to the operating power supply; the first end of the fifth resistor is connected to the connection line between the sixth resistor and the horizontal shifter; the second end of the fifth resistor is connected to the drain of the third MOS transistor switch.

[0014] In one possible implementation, during the power-on to display period, the voltage at the XON terminal of the power management chip is pulled low, and the first MOSFET switch reverses the voltage output at the XON terminal; the second and third MOSFET switches are simultaneously turned on, and the first GOA timing voltage output by the timing controller is 0; the voltage of the operating power supply is divided by the fifth and sixth resistors and then inputs a high-level voltage to the horizontal shifter; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit.

[0015] In one possible implementation, the timing voltage adjustment circuit includes: a power supply, a power management chip, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a fourth MOSFET switch; wherein the power management chip has an XON terminal and a first voltage output terminal; and the fourth MOSFET switch is an N-type switch.

[0016] The operating power supply is connected to the power management chip and the first terminal of the eleventh resistor respectively; the second terminal of the eleventh resistor is connected to the XON terminal of the power management chip; the gate of the fourth MOSFET switch is connected to the XON terminal of the power management chip; the eighth resistor is connected to the timing controller and the drain of the fourth MOSFET switch respectively; the source of the fourth MOSFET switch is connected to the horizontal shifter; the first terminal of the ninth resistor is connected to the first voltage output terminal of the power management chip, and the second terminal of the ninth resistor is connected to the connection line between the source of the fourth MOSFET switch and the horizontal shifter; the tenth resistor is connected to the horizontal shifter and the GOA unit respectively.

[0017] In one possible implementation, during the power-on to display period, the voltage at the XON terminal of the power management chip is pulled low, the fourth MOSFET switch is turned off, and the first voltage output terminal of the power management chip inputs a high-level voltage to the horizontal shifter through the ninth resistor; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit.

[0018] In one possible implementation, the timing voltage adjustment circuit includes: a power supply, a power management chip, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a voltage comparator, and a fifth MOSFET switch; the fifth MOSFET switch is N-type; the power management chip has an XON terminal, a second voltage output terminal, and a third voltage output terminal; the second voltage output terminal outputs a VGH voltage; the third voltage output terminal outputs a VGL voltage.

[0019] The first end of the twelfth resistor is connected to the timing controller; the horizontal shifter is connected to the second voltage output terminal, the third voltage output terminal, the second end of the twelfth resistor, and the source of the fifth MOS transistor switch.

[0020] The first end of the thirteenth resistor is connected to the second voltage output terminal of the power management chip; the second end of the thirteenth resistor is connected to the connection line between the drain of the fifth MOS transistor switch and the GOA unit.

[0021] The first end of the fourteenth resistor is connected to the operating power supply, and the second end of the fourteenth resistor is connected to the XON terminal of the power management chip.

[0022] The first end of the fifteenth resistor is connected to the working power supply, the second end of the fifteenth resistor is connected to the first end of the sixteenth resistor, and the second end of the sixteenth resistor is grounded.

[0023] The voltage comparator is connected to the second voltage output terminal and the third voltage output terminal; the non-inverting input terminal of the voltage comparator is connected to the XON terminal of the power management chip; the inverting input terminal of the voltage comparator is connected to the connection line between the fifteenth resistor and the sixteenth resistor; the output terminal of the voltage comparator is connected to the gate of the fifth MOS transistor switch.

[0024] In one possible implementation, the fifteenth resistor and the sixteenth resistor have the same resistance value; when the XON terminal outputs a low-level voltage, the output terminal of the voltage comparator outputs a VGL voltage; when the XON terminal outputs a high-level voltage, the output terminal of the voltage comparator outputs a VGH voltage.

[0025] In one possible implementation, during the period from power-on to display, the XON terminal voltage of the power management chip is pulled low, the voltage comparator outputs VGL voltage, and the fifth MOS transistor is switched off; the second voltage output terminal inputs a high-level voltage to the horizontal shifter through the thirteenth resistor; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit.

[0026] In one possible implementation, during the display period, the power management chip is in a floating mode, and the timing voltage adjustment circuit does not adjust the first GOA timing voltage and the second GOA timing voltage.

[0027] Secondly, embodiments of this application provide a display panel, including: a driving circuit for a GOA unit according to embodiments of this application.

[0028] This application raises the voltage driving the GOA unit during the power-on and display periods, thereby enabling the GOA unit to discharge and be set normally, effectively avoiding horizontal display ghosting caused by residual charge in the GOA unit. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the GOA model in an embodiment of this application;

[0030] Figure 2 This is a timing diagram of the GOA drive when residual fast power-on charge occurs according to an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of the driving circuit of the GOA unit in an embodiment of this application;

[0032] Figure 4 This is a schematic diagram of the timing voltage adjustment circuit of the first structure according to an embodiment of this application;

[0033] Figure 5 This is a schematic diagram of the timing voltage adjustment circuit of the second structure according to an embodiment of this application;

[0034] Figure 6 This is a timing diagram of GOA driving under the action of the timing voltage adjustment circuit of the first and second structures in the embodiments of this application;

[0035] Figure 7 This is a schematic diagram of the timing voltage adjustment circuit of the third structure according to an embodiment of this application;

[0036] Figure 8 This is a timing diagram of GOA driving under the action of the timing voltage adjustment circuit of the third structure in this application embodiment.

[0037] Attached image labels:

[0038] R1: First resistor; R2: Second resistor; R3: Third resistor; R4: Fourth resistor;

[0039] R5: Fifth resistor; R6: Sixth resistor; R7: Seventh resistor;

[0040] Q1: First MOSFET switch; Q2: Second MOSFET switch; Q3: Third MOSFET switch;

[0041] VDDIN: Power supply; R8: Eighth resistor; R9: Ninth resistor; R10: Tenth resistor;

[0042] R11: Eleventh resistor; Q4: Fourth MOSFET switch;

[0043] VDDIO: First voltage output terminal; R12: Twelfth resistor; R13: Thirteenth resistor;

[0044] R14: Fourteenth resistor; R15: Fifteenth resistor; R16: Sixteenth resistor;

[0045] U1: Voltage comparator; Q5: Fifth MOSFET switch;

[0046] VGH: Second voltage output terminal; VGL: Third voltage output terminal. Detailed Implementation

[0047] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0048] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0049] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0050] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0051] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0052] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0053] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0054] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0055] First, a brief introduction to the design concept of the embodiments of this application will be given.

[0056] In the timing generation of current conventional TFT-LCD GOA products, the level shifter generates the corresponding T-RST_LS signal based on the T-RST_OUT signal output by the TCON (timing controller). This drives the PU (pull-up) and OUTPUT (output point) of the GOA cell to discharge normally, preventing residual charge at the PU / OUTPUT points from causing erroneous outputs from the GOA cell. For example, the PU / OUTPUT points... Figure 1 As shown.

[0057] In practical applications, the following two situations may occur:

[0058] The first scenario: When the device is powered on, if the high level of the TCON output T-RST_OUT does not intersect with the Level Shifter operating voltage VGH, then the Level Shifter output T-RST_LS is the VGL output by the Level Shifter automatic mechanism.

[0059] The second scenario is that the T-RST_OUT output controlled by TCON is too late, causing T-RST_LS to start too late, during which time it is continuously outputting VGL by the Level Shifter automatic mechanism.

[0060] In both cases, the T-RST_LS signal output to the GOA unit driver can be regarded as an abnormal signal. The GOA unit cannot be reset and discharged normally, resulting in abnormal residual charge at power-on.

[0061] Figure 2 This is the timing diagram for the GOA driver during rapid power-on when residual charge occurs. The timing T-RST_LS for driving the GOA is generated based on the combined effect of the T-RST_OUT output of the front-end TCON and the operation of the Level Shifter.

[0062] The reason for the first situation mentioned above is that when the TCON sends a short high-level T-RST_OUT to the LevelShifter (not controlled by TCON, but only a short external pull-up or TCON internal floating state), and the LevelShifter has not yet fully turned on the operating voltage VGH, the T-RST_LS output by the Level Shifter is VGL, without the pulse that is turned on.

[0063] The second scenario described above occurs because, after power-on, when the Level Shifter is working normally, the T-RST_OUT signal from the TCON has not yet been pulled high (the T-CON cannot control the output for a short period after power-on). At this time, the T-RST_LS output by the Level Shifter is VGL, lacking the pulse required for startup. This VGL signal prevents the GOA unit from properly resetting the PU and OUTPUT, causing residual charge to fail to dissipate properly. This results in residual charge at the PU / OUTPUT points causing incorrect output to the GOA unit, resulting in display ghosting.

[0064] To solve the above-mentioned technical problems, this application adds a timing voltage adjustment circuit to ensure that the T-RST control signal of the GOA unit is high at power-on and the width is controllable. This ensures that the T-RST_LS signal driving the GOA unit is a normal signal, thereby allowing the GOA unit to discharge and be set normally (causing PU / OUTPUT to discharge). This effectively avoids the GOA unit charge causing incorrect TFT activation and avoids display ghosting that occurs at power-on.

[0065] This application designs three types of timing voltage adjustment circuits. The timing settings for driving the GOA unit during power-on ensure that T-RST of driving the GOA unit is high, thereby allowing the GOA unit to discharge and be set normally. Furthermore, the duration of T-RST being high is adjustable, without affecting the normal display timing, thus solving the fast power-on garbage problem in existing products.

[0066] After introducing the application scenarios and design concepts of the embodiments of this application, the technical solutions provided by the embodiments of this application will be described below.

[0067] like Figure 3 As shown, this application embodiment provides a driving circuit for a GOA unit, including: a timing controller, a horizontal shifter, and a timing voltage adjustment circuit;

[0068] The timing controller is used to output the first GOA timing voltage to the horizontal shifter;

[0069] The horizontal shifter is used to generate a second GOA timing voltage using the first GOA timing voltage, and outputs the second GOA timing voltage to the GOA unit;

[0070] The timing voltage adjustment circuit is used to adjust the first GOA timing voltage or the second GOA timing voltage after receiving the power-on signal, so that the horizontal shifter outputs a high-level second GOA timing voltage during the period from power-on to display, thereby enabling the GOA unit to discharge and be set normally.

[0071] The timing voltage range of the first GOA output by the timing controller is 0 to 3.3V; the timing voltage of the second GOA output by the horizontal shifter is the driving voltage of the GOA unit.

[0072] This application presents three structures for timing voltage regulation circuits. For example... Figure 4 As shown, the timing voltage adjustment circuit of the first structure includes: a working power supply VDDIN, a power management chip PMIC, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7, a first MOSFET switch Q1, a second MOSFET switch Q2, and a third MOSFET switch Q3; the power management chip is set to an XON terminal; the first MOSFET switch Q1 and the second MOSFET switch Q2 are both N-type; the third MOSFET switch Q3 is P-type; wherein,

[0073] The sixth resistor R6 connects to the timing controller TCON and the level shifter; the seventh resistor R7 connects to the level shifter and the GOA unit.

[0074] The operating power supply VDDIN is connected to the source of the power management chip PMIC and the first MOSFET switch Q1, respectively; the XON terminal of the power management chip PMIC is connected to the first terminal of the first resistor R1 and the gate of the first MOSFET switch Q1, respectively; the drain of the first MOSFET switch Q1 is connected to the first terminal of the second resistor R2; the second terminal of the first resistor R1 is connected to the second terminal of the second resistor R2.

[0075] The first end of the third resistor R3 is connected to the first end of the fourth resistor R4; the second end of the third resistor R3 is connected to the operating power supply VDDIN; the second end of the fourth resistor R4 is connected to the drain of the second MOSFET switch Q2; the gate of the second MOSFET switch Q2 is connected to the drain of the first MOSFET switch Q1; the source of the first MOSFET switch Q1 and the source of the second MOSFET switch Q2 are both grounded.

[0076] The gate of the third MOSFET switch Q3 is connected to the connection line between the third resistor R3 and the fourth resistor R4, and the source of the third MOSFET switch Q3 is connected to the operating power supply VDDIN; the first end of the fifth resistor R5 is connected to the connection line between the sixth resistor R6 and the horizontal shifter; the second end of the fifth resistor R5 is connected to the drain of the third MOSFET switch Q3.

[0077] Specifically, the working power supply VDDIN output voltage is 3.3V. After the power management chip PMIC starts working, the output voltage of the XON terminal is pulled low by default until the PMIC enters floating mode. The time to enter floating mode can be set. Figure 3 In the above, T-RST_OUT is the TRST (Total Reset) signal output by TCON, which is normally 1.8V; T-RST_IN is the TRST signal input to the Level Shifter, i.e., the first GOA timing voltage; T-RST_LS is the TRST signal output by the Level Shifter; and T-RST_GOA is the TRST signal input to the GOA unit, i.e., the second GOA timing voltage.

[0078] During the period from power-on to display, the voltage at the XON terminal of the power management chip (PMIC) is pulled low, and the first MOSFET switch Q1 reverses the voltage at the XON terminal; the second MOSFET switch Q2 and the third MOSFET switch Q3 are turned on simultaneously, and the first GOA timing voltage output by the timing controller TCON is 0; the voltage of the operating power supply VDDIN is divided by the fifth resistor R5 and the sixth resistor R6 and then inputs a high-level voltage to the horizontal shifter; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit to discharge the residual charge in the GOA unit.

[0079] During the display period, the power management chip PMIC is in floating mode. The voltage at the XON terminal is pulled up to a high level externally. The first MOSFET switch Q1 reverses the voltage at the XON terminal. The second MOSFET switch Q2 and the third MOSFET switch Q3 are turned off simultaneously. The T-RST_IN timing completely follows the T-RST_OUT timing, and the GOA unit works normally.

[0080] like Figure 5 As shown, the timing voltage adjustment circuit of the second structure includes: working power supply VDDIN, power management chip PMIC, eighth resistor R8, ninth resistor R9, tenth resistor R10, eleventh resistor R11 and fourth MOSFET switch Q4; wherein, the power management chip PMIC is provided with XON terminal and first voltage output terminal VDDIO; the fourth MOSFET switch Q4 is N type.

[0081] The operating power supply VDDIN is connected to the first terminal of the power management chip PMIC and the eleventh resistor R11, respectively; the second terminal of the eleventh resistor R11 is connected to the XON terminal of the power management chip; the gate of the fourth MOSFET switch Q4 is connected to the XON terminal of the power management chip; the eighth resistor R8 is connected to the timing controller TCON and the drain of the fourth MOSFET switch Q4, respectively; the source of the fourth MOSFET switch Q4 is connected to the horizontal shifter; the first terminal of the ninth resistor R9 is connected to the first voltage output terminal VDDIO of the power management chip, and the second terminal of the ninth resistor R9 is connected to the connection line between the source of the fourth MOSFET switch Q4 and the horizontal shifter; the tenth resistor R10 is connected to the horizontal shifter and the GOA unit, respectively.

[0082] During the period from power-on to display, the voltage at the XON terminal of the power management chip is pulled low, the fourth MOSFET switch Q4 is turned off, and the first voltage output terminal VDDIO of the power management chip inputs a high-level voltage to the horizontal shifter through the ninth resistor; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit. That is, when the T-RST_IN voltage is high (VDDIO), after the Level Shifter operating voltage VGH rises, T-RST_LS and T-RST_GOA are pulled high, causing the residual charge in the GOA unit to discharge.

[0083] During the display phase, the power management chip PMIC is in floating mode, the voltage at the XON terminal is pulled up to a high level externally, the fourth MOSFET switch Q4 is turned on, the T-RST_IN timing completely follows the T-RST_OUT timing, and the GOA unit works normally.

[0084] like Figure 6 As shown, through the timing voltage adjustment circuits of the above two structures, both signals T-RST_LS and T-RST_GOA are pulled high, and the residual charge of the GOA unit is discharged.

[0085] like Figure 7 As shown, the third type of timing voltage adjustment circuit includes: a working power supply VDDIN, a power management chip PMIC, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a voltage comparator U1, and a fifth MOSFET switch Q5; the fifth MOSFET switch Q5 is an N-type; the power management chip has an XON terminal, a second voltage output terminal VGH, and a third voltage output terminal VGL; the second voltage output terminal outputs VGH voltage; the third voltage output terminal outputs VGL voltage.

[0086] The first terminal of the twelfth resistor R12 is connected to the timing controller TCON; the horizontal shifter is connected to the second voltage output terminal VGH, the third voltage output terminal VGL, the second terminal of the twelfth resistor R12, and the source of the fifth MOSFET switch Q5, respectively.

[0087] The first end of the thirteenth resistor R13 is connected to the second voltage output terminal VGH of the power management chip PMIC; the second end of the thirteenth resistor R13 is connected to the connection line between the drain of the fifth MOSFET switch Q5 and the GOA unit.

[0088] The first end of the fourteenth resistor R14 is connected to the working power supply VDDIN, and the second end of the fourteenth resistor R14 is connected to the XON terminal of the power management chip.

[0089] The first end of the fifteenth resistor R15 is connected to the working power supply VDDIN, the second end of the fifteenth resistor R15 is connected to the first end of the sixteenth resistor R16, and the second end of the sixteenth resistor R16 is grounded.

[0090] Voltage comparator U1 is connected to the second voltage output terminal VGH and the third voltage output terminal VGL; the non-inverting input terminal + of voltage comparator U1 is connected to the XON terminal of the power management chip; the inverting input terminal - of voltage comparator U1 is connected to the connection line between the fifteenth resistor R15 and the sixteenth resistor R16; the output terminal of voltage comparator U1 is connected to the gate of the fifth MOSFET switch Q5.

[0091] Specifically, the VGH voltage range is 10V-25V, and the VGL voltage range is -6V-14V.

[0092] Preferably, the fifteenth resistor R15 and the sixteenth resistor R16 have the same resistance value; when the XON terminal outputs a low-level voltage, the output terminal of the voltage comparator U1 outputs a VGL voltage; when the XON terminal outputs a high-level voltage, the output terminal of the voltage comparator U1 outputs a VGH voltage.

[0093] During the period from power-on to display, the XON terminal voltage of the power management chip is pulled low, the voltage comparator U1 outputs VGH voltage, and the fifth MOSFET switch Q5 is turned off; the second voltage output terminal VGH inputs a high-level voltage to the horizontal shifter through the thirteenth resistor R13; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit.

[0094] During the display phase, the power management chip (PMIC) is in floating mode. The voltage at the XON terminal is pulled high externally, and the voltage comparator U1 outputs VGL. When T-RST_LS is low, the fifth MOSFET switch Q5 is open, and both the T-RST_GOA and T-RST_LS signals are low. When T-RST_LS is high, the fifth MOSFET switch Q5 is closed, and T-RST_GOA is pulled high through R2. In other words, after the XON terminal is released, the T-RST_GOA and T-RST_LS signals are synchronized, allowing for normal display control.

[0095] like Figure 8 As shown, through the timing voltage adjustment circuit of the third structure, although T-RST_LS is at a low level during the period from power-on to display, T-RST_GOA is pulled high, causing the residual charge of the GOA unit to discharge.

[0096] Based on the same inventive concept, this application provides a display panel including the driving circuit of the GOA unit in the above embodiments.

[0097] Since the display panel of this embodiment includes the driving circuit of the GOA unit of this application embodiment, it has the technical advantages of the driving circuit of the GOA unit of this application embodiment: the timing setting of driving the GOA unit at power-on can ensure that T-RST of driving the GOA unit is high level, so that the GOA unit can be discharged and set normally; and the time when T-RST is high level is adjustable, while not affecting the normal display part Timing, thus solving the fast power-on garbage problem of existing products.

[0098] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A driving circuit for a GOA unit, characterized in that, include: Timing controller, horizontal shifter, and timing voltage adjustment circuit; The timing controller is used to output a first GOA timing voltage to the horizontal shifter; The horizontal shifter is used to generate a second GOA timing voltage using the first GOA timing voltage, and outputs the second GOA timing voltage to the GOA unit; The timing voltage adjustment circuit is used to adjust the first GOA timing voltage or the second GOA timing voltage after receiving the power-on signal, so that the horizontal shifter outputs a high-level second GOA timing voltage during the power-on to display period, thereby enabling the GOA unit to discharge and be set normally. The timing voltage adjustment circuit includes a sixth resistor and a seventh resistor, wherein the sixth resistor is connected to the timing controller and the horizontal shifter; The seventh resistor is connected to the horizontal shifter and the GOA unit.

2. The driving circuit of the GOA unit according to claim 1, characterized in that, The timing voltage adjustment circuit includes: a power supply, a power management chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first MOSFET switch, a second MOSFET switch, and a third MOSFET switch; the power management chip has an XON terminal; the first and second MOSFET switches are both N-type; the third MOSFET switch is P-type; wherein, The operating power supply is connected to the source of the power management chip and the first MOSFET switch respectively; the XON terminal of the power management chip is connected to the first terminal of the first resistor and the gate of the first MOSFET switch respectively; the drain of the first MOSFET switch is connected to the first terminal of the second resistor; the second terminal of the first resistor is connected to the second terminal of the second resistor. The first end of the third resistor is connected to the first end of the fourth resistor; the second end of the third resistor is connected to the operating power supply; the second end of the fourth resistor is connected to the drain of the second MOS transistor switch; the gate of the second MOS transistor switch is connected to the drain of the first MOS transistor switch; the source of the first MOS transistor switch and the source of the second MOS transistor switch are both grounded. The gate of the third MOS transistor switch is connected to the connection line between the third resistor and the fourth resistor, and the source of the third MOS transistor switch is connected to the operating power supply; the first end of the fifth resistor is connected to the connection line between the sixth resistor and the horizontal shifter; the second end of the fifth resistor is connected to the drain of the third MOS transistor switch.

3. The driving circuit of the GOA unit according to claim 2, characterized in that, During the period from power-on to display, the voltage at the XON terminal of the power management chip is pulled low, and the first MOSFET switch reverses the voltage output from the XON terminal; the second and third MOSFET switches are simultaneously turned on, and the first GOA timing voltage output by the timing controller is 0; the voltage of the operating power supply is divided by the fifth and sixth resistors and then inputs a high-level voltage to the horizontal shifter; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit.

4. The driving circuit of the GOA unit according to claim 1, characterized in that, The timing voltage adjustment circuit includes: a power supply, a power management chip, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a fourth MOSFET switch; the power management chip has an XON terminal and a first voltage output terminal; the fourth MOSFET switch is an N-type switch; wherein... The working power supply is connected to the first end of the power management chip and the eleventh resistor respectively; the second end of the eleventh resistor is connected to the XON terminal of the power management chip. The gate of the fourth MOS transistor switch is connected to the XON terminal of the power management chip; the eighth resistor is connected to the timing controller and the drain of the fourth MOS transistor switch respectively; the source of the fourth MOS transistor switch is connected to the horizontal shifter. The first end of the ninth resistor is connected to the first voltage output terminal of the power management chip, and the second end of the ninth resistor is connected to the source of the fourth MOS transistor switch and the connection line of the horizontal shifter. The tenth resistor is connected to the horizontal shifter and the GOA unit, respectively.

5. The driving circuit of the GOA unit according to claim 4, characterized in that, During the period from power-on to display, the voltage at the XON terminal of the power management chip is pulled low, the fourth MOSFET switch is turned off, and the first voltage output terminal of the power management chip inputs a high-level voltage to the horizontal shifter through the ninth resistor; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit.

6. The driving circuit of the GOA unit according to claim 1, characterized in that, The timing voltage adjustment circuit includes: a power supply, a power management chip, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a voltage comparator, and a fifth MOSFET switch; the fifth MOSFET switch is N-type; the power management chip has an XON terminal, a second voltage output terminal, and a third voltage output terminal; the second voltage output terminal outputs VGH voltage; the third voltage output terminal outputs VGL voltage; wherein, The first end of the twelfth resistor is connected to the timing controller; the horizontal shifter is connected to the second voltage output terminal, the third voltage output terminal, the second end of the twelfth resistor, and the source of the fifth MOS transistor switch. The first end of the thirteenth resistor is connected to the second voltage output terminal of the power management chip; the second end of the thirteenth resistor is connected to the connection line between the drain of the fifth MOS transistor switch and the GOA unit. The first end of the fourteenth resistor is connected to the operating power supply, and the second end of the fourteenth resistor is connected to the XON terminal of the power management chip. The first end of the fifteenth resistor is connected to the working power supply, the second end of the fifteenth resistor is connected to the first end of the sixteenth resistor, and the second end of the sixteenth resistor is grounded. The voltage comparator is connected to the second voltage output terminal and the third voltage output terminal; the non-inverting input terminal of the voltage comparator is connected to the XON terminal of the power management chip; the inverting input terminal of the voltage comparator is connected to the connection line between the fifteenth resistor and the sixteenth resistor; the output terminal of the voltage comparator is connected to the gate of the fifth MOS transistor switch.

7. The driving circuit of the GOA unit according to claim 6, characterized in that, The fifteenth and sixteenth resistors have the same resistance value; when the XON terminal outputs a low-level voltage, the output terminal of the voltage comparator outputs a VGL voltage; when the XON terminal outputs a high-level voltage, the output terminal of the voltage comparator outputs a VGH voltage.

8. The driving circuit of the GOA unit according to claim 7, characterized in that, During the period from power-on to display, the XON terminal voltage of the power management chip is pulled low, the voltage comparator outputs VGL voltage, and the fifth MOSFET switch is turned off; the second voltage output terminal inputs a high-level voltage to the horizontal shifter through the thirteenth resistor; the horizontal shifter outputs a high-level second GOA timing voltage to the GOA unit.

9. The driving circuit of the GOA unit according to claim 2, 4, or 6, characterized in that, During the display period, the power management chip is in floating mode, and the timing voltage adjustment circuit does not adjust the first GOA timing voltage and the second GOA timing voltage.

10. A display panel, characterized in that, include: The driving circuit of the GOA unit according to any one of claims 1-9.

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