Data receiving circuit, data receiving system and storage device

Abstract

The embodiment of the present disclosure provides a data receiving circuit, a data receiving system and a storage device. The data receiving circuit comprises: a first amplification module, wherein the first amplification module comprises: an amplification unit having a first node, a second node, a third node and a fourth node; a first NMOS transistor having one end connected to the first node and the other end connected to one end of a second NMOS transistor, the second NMOS transistor having the other end connected to the second node, the gate of one of the first NMOS transistor and the second NMOS transistor receiving a first complementary feedback signal, and the gate of the other receiving an enable signal; a third NMOS transistor having one end connected to the third node and the other end connected to one end of a fourth NMOS transistor, the fourth NMOS transistor having the other end connected to the fourth node, the gate of one of the third NMOS transistor and the fourth NMOS transistor receiving a second complementary feedback signal, and the gate of the other receiving the enable signal; and a second amplification module. The embodiment of the present disclosure is at least beneficial to improving the receiving performance of the data receiving circuit while improving the processing speed of the data signal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a data receiving circuit, a data receiving system, and a storage device. Background Technology

[0002] In memory applications, as signal transmission rates increase, channel loss has a greater impact on signal quality, easily leading to inter-symbol interference. In addition, the difference in level between the data signal received by the data receiving circuit in the memory and the reference signal can affect the data receiving circuit's judgment of the data signal, thereby affecting the accuracy of the signal output by the data receiving circuit.

[0003] Currently, equalization circuits are commonly used to compensate for channel imbalances. These circuits can be either CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer). However, the accuracy of the output signal from these current equalization circuits needs improvement, as does their receiving performance and data signal processing speed. Summary of the Invention

[0004] This disclosure provides a data receiving circuit, a data receiving system, and a storage device, which at least improve the receiving performance of the data receiving circuit while increasing its data signal processing speed.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a data receiving circuit, including: a first amplification module configured to receive an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal, and a second reference signal; during a period when the enable signal has a first level value, in response to a sampling clock signal and based on the first feedback signal, selecting the data signal and the first reference signal for a first comparison and outputting a first signal pair as the result of the first comparison, or, in response to the sampling clock signal and based on the second feedback signal, selecting the data signal and the second reference signal for a second comparison and outputting a second signal pair as the result of the second comparison; during a period when the enable signal has a second level value, in response to the sampling clock signal, performing the first comparison and outputting the first signal pair; the first feedback signal and the second feedback signal have opposite levels, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal; wherein the first amplification module includes: an amplification unit having a first node, a second node, a third node, and a fourth node, the first node outputting the first signal, the second node outputting the second signal, the third node outputting the third signal, and the fourth node outputting the fourth signal. The system is configured to receive the data signal, the first reference signal, and the second reference signal; a first NMOS transistor and a second NMOS transistor, one end of the first NMOS transistor being connected to the first node, the other end of the first NMOS transistor being connected to one end of the second NMOS transistor, and the other end of the second NMOS transistor being connected to the second node, the gate of one of the first NMOS transistors and the second NMOS transistor receiving a first complementary feedback signal, and the gate of the other receiving the enable signal, the first complementary feedback signal being at an opposite level to the first feedback signal; a third NMOS transistor and a fourth NMOS transistor, one end of the third NMOS transistor being connected to the third node, the other end of the third NMOS transistor being connected to one end of the fourth NMOS transistor, and the other end of the fourth NMOS transistor being connected to the fourth node, the gate of one of the third NMOS transistors and the fourth NMOS transistor receiving a second complementary feedback signal, and the gate of the other receiving the enable signal, the second complementary feedback signal being at an opposite level to the second feedback signal; and a second amplification module, configured to receive the output signal of the first amplification module as an input signal pair, amplify the voltage difference of the input signal pair, and output a first output signal and a second output signal as the result of the amplification process.

[0006] In some embodiments, the first amplification module further includes a fifth NMOS transistor and a sixth NMOS transistor, one end of the fifth NMOS transistor is connected to the first node, the other end of the fifth NMOS transistor is connected to one end of the sixth NMOS transistor, the other end of the sixth NMOS transistor is connected to the second node, the gate of one of the fifth NMOS transistor and the sixth NMOS transistor receives the first complementary feedback signal, and the gate of the other receives the enable signal.

[0007] In some embodiments, the gate of the first NMOS transistor receives the enable signal, and the gate of the second NMOS transistor receives the first complementary feedback signal, wherein the channel width of the first NMOS transistor is greater than the channel width of the second NMOS transistor; the gate of the fifth NMOS transistor receives the first complementary feedback signal, and the gate of the sixth NMOS transistor receives the enable signal, wherein the channel width of the fifth NMOS transistor is less than the channel width of the sixth NMOS transistor.

[0008] In some embodiments, the channel width of the fifth NMOS transistor is equal to the channel width of the second NMOS transistor; the channel width of the sixth NMOS transistor is equal to the channel width of the first NMOS transistor; and the channel lengths of the first NMOS transistor, the second NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all equal.

[0009] In some embodiments, the first amplification module further includes a seventh NMOS transistor and an eighth NMOS transistor, one end of the seventh NMOS transistor is connected to the third node, the other end of the seventh NMOS transistor is connected to one end of the eighth NMOS transistor, the other end of the eighth NMOS transistor is connected to the fourth node, the gate of one of the seventh NMOS transistor and the eighth NMOS transistor receives the second complementary feedback signal, and the gate of the other receives the enable signal.

[0010] In some embodiments, the gate of the third NMOS transistor receives the enable signal, and the gate of the fourth NMOS transistor receives the second complementary feedback signal, wherein the channel width of the third NMOS transistor is greater than the channel width of the fourth NMOS transistor; the gate of the seventh NMOS transistor receives the second complementary feedback signal, and the gate of the eighth NMOS transistor receives the enable signal, wherein the channel width of the seventh NMOS transistor is less than the channel width of the eighth NMOS transistor.

[0011] In some embodiments, the channel width of the seventh NMOS transistor is equal to the channel width of the fourth NMOS transistor; the channel width of the eighth NMOS transistor is equal to the channel width of the third NMOS transistor; and the channel lengths of the third NMOS transistor, the fourth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all equal.

[0012] In some embodiments, the sampling clock signal includes a first sampling clock signal and a second sampling clock signal; the amplification unit includes: a first comparison circuit having a first node and a second node, configured to receive the data signal and the first reference signal and perform the first comparison in response to the first sampling clock signal; a clock generation circuit configured to receive the enable signal and the original sampling clock signal, and output the second sampling clock signal, wherein, during the period when the enable signal has the first level value, the phase of the second sampling clock signal is opposite to the phase of the original sampling clock signal, and during the period when the enable signal has the second level value, the second sampling clock signal is a logic high level signal; a second comparison circuit having the third node and the fourth node, configured to receive the data signal and the second reference signal, and, during the period when the enable signal has the first level value, perform the second comparison in response to the second sampling clock signal; and, during the period when the enable signal has the second level value, conduct the connection path between the third node and ground, and conduct the connection path between the fourth node and ground.

[0013] In some embodiments, the first comparison circuit includes: a first current source configured to be connected between a power supply node and a fifth node, providing current to the fifth node in response to a first sampling clock signal; a first comparison unit connected to the first node, the second node, and the fifth node, configured to receive the data signal and the first reference signal, perform the first comparison when the first current source provides current to the fifth node, and output the first signal and the second signal; and a first reset unit connected to the first node and the second node, configured to reset the first node and the second node in response to the first sampling clock signal. The second comparison circuit includes: a second current source configured to be connected between a power supply node and a sixth node, providing current to the sixth node in response to a second sampling clock signal; a second comparison unit connected to the third node, the fourth node, and the sixth node, configured to receive the data signal and the second reference signal, perform the second comparison when the second current source provides current to the sixth node, and output the third signal and the fourth signal; and a second reset unit connected between the third node and the fourth node, configured to reset the third node and the fourth node in response to the second sampling clock signal.

[0014] In some embodiments, the first current source includes: a first PMOS transistor connected between the power supply node and the fifth node, the gate of the first PMOS transistor receiving the first sampling clock signal; the second current source includes: a second PMOS transistor connected between the power supply node and the sixth node, the gate of the second PMOS transistor receiving the second sampling clock signal.

[0015] In some embodiments, the first comparison unit includes: a third PMOS transistor connected between the first node and the fifth node, the gate of the third PMOS transistor receiving the data signal; and a fourth PMOS transistor connected between the second node and the fifth node, the gate of the fourth PMOS transistor receiving the first reference signal; the second comparison unit includes: a fifth PMOS transistor connected between the third node and the sixth node, the gate of the fifth PMOS transistor receiving the data signal; and a sixth PMOS transistor connected between the fourth node and the sixth node, the gate of the sixth PMOS transistor receiving the second reference signal.

[0016] In some embodiments, the first reset unit includes: a ninth NMOS transistor connected between the first node and ground, with its gate receiving the first sampling clock signal; and a tenth NMOS transistor connected between the second node and ground, with its gate receiving the first sampling clock signal; the second reset unit includes: an eleventh NMOS transistor connected between the third node and ground, with its gate receiving the second sampling clock signal; and a twelfth NMOS transistor connected between the fourth node and ground, with its gate receiving the second sampling clock signal.

[0017] In some embodiments, the clock generation circuit includes: a first NAND gate circuit, one input of the first NAND gate circuit receiving the original sampled clock signal, the other input connected to a power supply node, and the output output of the first sampled clock signal.

[0018] In some embodiments, the clock generation circuit includes: a second NAND gate circuit, wherein one input terminal of the second NAND gate circuit receives the original sampled clock signal, another input terminal receives the enable signal, and the output terminal outputs the second sampled clock signal.

[0019] In some embodiments, the second amplification module includes: a first input unit connected to the seventh node and the eighth node, configured to receive the first signal pair and perform a third comparison, and provide signals to the seventh node and the eighth node respectively as the result of the third comparison; a second input unit connected to the seventh node and the eighth node, configured to receive the second signal pair and perform a fourth comparison, and provide signals to the seventh node and the eighth node respectively as the result of the fourth comparison; and a latching unit connected to the seventh node and the eighth node, configured to amplify and latch the signals of the seventh node and the eighth node, and output the first output signal and the second output signal through the first output node and the second output node respectively.

[0020] In some embodiments, the first input unit includes: a thirteenth NMOS transistor, the drain of which is connected to the seventh node, the source of which is connected to ground, and the gate of which receives the first signal; and a fourteenth NMOS transistor, the drain of which is connected to the eighth node, the source of which is connected to ground, and the gate of which receives the second signal; the second input unit includes: a fifteenth NMOS transistor, the drain of which is connected to the seventh node, the source of which is connected to ground, and the gate of which receives the third signal; and a sixteenth NMOS transistor, the drain of which is connected to the eighth node, the source of which is connected to ground, and the gate of which receives the fourth signal.

[0021] In some embodiments, the latching unit includes: a seventeenth NMOS transistor and a seventh PMOS transistor, wherein the gate of the seventeenth NMOS transistor and the gate of the seventh PMOS transistor are both connected to the second output node, the source of the seventeenth NMOS transistor is connected to the seventh node, the drain of the seventeenth NMOS transistor and the drain of the seventh PMOS transistor are both connected to the first output node, and the source of the seventh PMOS transistor is connected to a power supply node; an eighteenth NMOS transistor and an eighth PMOS transistor, wherein the gate of the eighteenth NMOS transistor and the gate of the eighth PMOS transistor are both connected to the first output node, the source of the eighteenth NMOS transistor is connected to the eighth node, the drain of the eighteenth NMOS transistor and the drain of the eighth PMOS transistor are both connected to the second output node, and the source of the eighth PMOS transistor is connected to the power supply node.

[0022] In some embodiments, the second amplification module further includes: a third reset unit connected between the power supply node and the output terminal of the latch unit, configured to reset the output terminal of the latch unit.

[0023] In some embodiments, the third reset unit includes: a 139th PMOS transistor connected between the first output node and the power supply node, the gate of the 13th PMOS transistor receiving the original sampling clock signal; and a 14th PMOS transistor connected between the second output node and the power supply node, the gate of the 14th PMOS transistor receiving the original sampling clock signal.

[0024] In some embodiments, the data receiving circuit further includes: a first inverting circuit configured to receive the first feedback signal and output the first complementary feedback signal; and a second inverting circuit configured to receive the second feedback signal and output the second complementary feedback signal.

[0025] In some embodiments, the first inverter circuit includes a first inverter; the second inverter circuit includes a second inverter.

[0026] In some embodiments, the first inverter circuit includes a third NAND gate, the two inputs of which receive the first feedback signal and the enable signal respectively, and the output of which outputs the first complementary feedback signal; the second inverter circuit includes a fourth NAND gate, the two inputs of which receive the second feedback signal and the enable signal respectively, and the output of which outputs the second complementary feedback signal.

[0027] According to some embodiments of this disclosure, another aspect of this disclosure also provides a data receiving system, including: a plurality of cascaded data transmission circuits, each of the data transmission circuits including a data receiving circuit as described in any of the preceding claims and a latching circuit connected to the data receiving circuit; the output signal of the previous stage data transmission circuit serving as the feedback signal of the next stage data transmission circuit; and the output signal of the last stage data transmission circuit serving as the feedback signal of the first stage data transmission circuit.

[0028] In some embodiments, the data receiving circuit receives data in response to a sampling clock signal; and the data receiving system includes four cascaded data transmission circuits, with a 90° phase difference between the sampling clock signals of adjacent data receiving circuits.

[0029] In some embodiments, the first output signal and the second output signal output by the second amplification module of the preceding data receiving circuit serve as the feedback signal of the subsequent data receiving circuit; or, the signal output by the latch circuit of the preceding stage serves as the feedback signal of the subsequent data receiving circuit.

[0030] According to some embodiments of the present disclosure, another aspect of the present disclosure also provides a storage device, including: a plurality of data ports; a plurality of data receiving systems as described in any of the preceding claims, each of the data receiving systems corresponding to one of the data ports.

[0031] The technical solutions provided in this disclosure have at least the following advantages:

[0032] While receiving the data signal, the first reference signal, and the second reference signal, the first amplification module can also utilize the first and second NMOS transistors to receive the enable signal and the first complementary feedback signal to control the potentials of the first and second nodes, and utilize the third and fourth NMOS transistors to receive the enable signal and the second complementary feedback signal to control the potentials of the third and fourth nodes. Specifically, when the enable signal is at a first level value, one of the first and second NMOS transistors and one of the third and fourth NMOS transistors is turned on based on the enable signal; the other of the first and second NMOS transistors is turned on or off in response to the first complementary feedback signal; and the other of the third and fourth NMOS transistors is turned on or off in response to the second complementary feedback signal. Since the levels of the first feedback signal and the second feedback signal are opposite, the levels of the first complementary feedback signal and the first feedback signal are opposite, and the levels of the second complementary feedback signal and the second complementary feedback signal are opposite, when the enable signal is at the first level value, one of the first NMOS transistor and the second NMOS transistor, as well as one of the third NMOS transistor and the fourth NMOS transistor, is turned on while the other is turned off. This allows the first amplification module to selectively perform either the first comparison or the second comparison in response to the sampling clock signal, so that one of the output first signal pair and the second signal pair is valid while the other is invalid. This reduces the impact of inter-symbol interference of the received data signal on the data receiving circuit. Moreover, in the first amplification module, only one of the circuits performing the first comparison and the circuit performing the second comparison is in the working state, while the other can be in the non-working state, which helps to reduce the power consumption of the data receiving circuit. Furthermore, since the on-resistance of an NMOS transistor is much smaller than that of a PMOS transistor under the same conditions, the first, second, third, and fourth NMOS transistors in the first amplification module can turn on or off faster in response to the signals received at their respective gates compared to PMOS transistors. This makes it easier for the first amplification module to perform only one of the first and second comparisons at any given time, thereby improving the processing effect and speed of the data signal. This benefits both the receiving performance of the data receiving circuit and its data signal processing speed.

[0033] Furthermore, when the enable signal is at the second level, the first amplification module only performs a first comparison in response to the sampling clock signal and outputs a valid first signal pair. At this time, the circuit in the first amplification module used to output the second signal pair can be in a non-operating state, which helps to further reduce the power consumption of the data receiving circuit. Attached Figure Description

[0034] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure;

[0036] Figure 2 Another functional block diagram of a data receiving circuit provided in an embodiment of this disclosure;

[0037] Figure 3 A functional block diagram of a first amplification module in a data receiving circuit provided in an embodiment of this disclosure;

[0038] Figure 4 This is yet another functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure;

[0039] Figure 5 and Figure 6 A schematic diagram of two circuit structures of a first amplification module, a first inverting circuit, and a second inverting circuit in a data receiving circuit provided in an embodiment of this disclosure;

[0040] Figure 7 This is a schematic diagram of a circuit structure of a second amplification module in a data receiving circuit provided in an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of another circuit structure of the second amplification module, the first inverting circuit, and the second inverting circuit in a data receiving circuit provided in an embodiment of this disclosure;

[0042] Figure 9 A functional block diagram of a data receiving system provided in another embodiment of this disclosure. Detailed Implementation

[0043] As can be seen from the background technology, the signal adjustment capability of equalization circuits needs to be improved, and the power consumption of equalization circuits needs to be reduced.

[0044] This disclosure provides a data receiving circuit, a data receiving system, and a storage device. In the data receiving circuit, an enable signal, a first feedback signal, and a second feedback signal can be used to further control the first amplification module to select whether to consider the impact of inter-symbol interference of the data received by the data receiving circuit on the data receiving circuit. For example, when it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit, even when the enable signal is at the first level value, the first amplification module responds to the sampling clock signal and uses the first, second, third, and fourth NMOS transistors to select one of the first comparison and the second comparison, so that one of the output first signal pair and the second signal pair is valid and the other is invalid, and the signal level difference in the valid signal pair is greater, so as to ensure that the second amplification module receives a pair of differential signals with a greater difference in signal level value. In addition, the low on-resistance of the NMOS transistors is used to avoid the first amplification module from performing the first comparison and the second comparison at the same time, and to improve the processing effect and processing speed of the data signal by the first amplification module. When there is no need to consider the impact of inter-symbol interference on the data receiving circuit, when the enable signal is at the second level value, the first amplification module responds to the sampling clock signal and only performs the first comparison, fixing the output of the valid first signal pair, so as to reduce the power consumption of the data receiving circuit.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0046] This disclosure provides a data receiving circuit according to an embodiment. The data receiving circuit provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure; Figure 2 Another functional block diagram of a data receiving circuit provided in an embodiment of this disclosure; Figure 3 A functional block diagram of a first amplification module in a data receiving circuit provided in an embodiment of this disclosure; Figure 4 This is yet another functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure; Figure 5 and Figure 6 A schematic diagram of two circuit structures of a first amplification module, a first inverting circuit, and a second inverting circuit in a data receiving circuit provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of a circuit structure of a second amplification module in a data receiving circuit provided in an embodiment of the present disclosure; Figure 8This is a schematic diagram of another circuit structure of the second amplification module, the first inverting circuit, and the second inverting circuit in a data receiving circuit provided in an embodiment of this disclosure.

[0047] refer to Figure 1 The data receiving circuit 100 may include: a first amplification module 101, configured to receive an enable signal EnDfe, a first feedback signal fbp, a second feedback signal fbn, a data signal DQ, a first reference signal VR+, and a second reference signal VR-; during the period when the enable signal EnDfe has a first level value, in response to the sampling clock signal clkN and based on the first feedback signal fbp, select the data signal DQ and the first reference signal VR+ for a first comparison and output a first signal pair as the result of the first comparison; or, in response to the sampling clock signal clkN and based on the second feedback signal fbn, select the data signal DQ and the second reference signal VR- for a second comparison and output a second signal pair as the result of the second comparison; during the period when the enable signal EnDfe has a second level value, in response to the sampling clock signal clkN, perform a first comparison and output a first signal pair; the levels of the first feedback signal fbp and the second feedback signal fbn are opposite; the first signal pair includes a first signal Sn+ and a second signal Sp+; the second signal pair includes a third signal Sn- and a fourth signal Sp-.

[0048] Among them, continue to refer to Figure 1The first amplification module 101 includes: an amplification unit 131 having a first node net1, a second node net2, a third node net3, and a fourth node net4. The first node net1 outputs a first signal Sn+, the second node net2 outputs a second signal Sp+, the third node net3 outputs a third signal Sn-, and the fourth node net4 outputs a fourth signal Sp-. It is configured to receive a data signal DQ, a first reference signal VR+, and a second reference signal VR-; a first NMOS transistor MN1 and a second NMOS transistor MN2. One end of the first NMOS transistor MN1 is connected to the first node net1, and the other end of the first NMOS transistor MN1 is connected to one end of the second NMOS transistor MN2. The other end of the second NMOS transistor MN2 is connected to the second node net2. The gate of one of the first NMOS transistors MN1 and the second NMOS transistor MN2 receives a first complementary feedback signal fbpN, and the gate of the other is connected to... The first complementary feedback signal fbpN is opposite in level to the first feedback signal fbp. A third NMOS transistor MN3 and a fourth NMOS transistor MN4 are connected. One end of the third NMOS transistor MN3 is connected to the third node net3, and the other end of the third NMOS transistor MN3 is connected to one end of the fourth NMOS transistor MN4. The other end of the fourth NMOS transistor MN4 is connected to the fourth node net4. The gate of one of the third node net3 and the fourth NMOS transistor MN4 receives the second complementary feedback signal fbnN, and the gate of the other receives the enable signal EnDfe. The second complementary feedback signal fbnN is opposite in level to the second feedback signal fbn. A second amplification module 102 is configured to receive the output signal of the first amplification module 101 as an input signal pair, amplify the voltage difference of the input signal pair, and output a first output signal Vout and a second output signal VoutN as the result of the amplification process.

[0049] It should be noted that the first level period of the enable signal EnDfe refers to the range of levels that cause the first amplification module 101 to determine that the enable signal EnDfe is logic level 1, i.e., a high level; the second level period of the enable signal EnDfe refers to the range of levels that cause the first amplification module 101 to determine that the enable signal EnDfe is logic level 0, i.e., a low level. Furthermore, the opposite levels of the first feedback signal fbp and the second feedback signal fbn mean that when one of the first feedback signal fbp and the second feedback signal fbn is high, the other is low. The opposite levels of the first complementary feedback signal fbpN and the first feedback signal fbp mean that when one of the first complementary feedback signal fbpN and the first feedback signal fbp is high, the other is low. The opposite levels of the second complementary feedback signal fbnN and the second feedback signal fbn mean that when one of the second complementary feedback signal fbnN and the second feedback signal fbn is high, the other is low. Thus, the levels of the first complementary feedback signal fbpN and the second complementary feedback signal fbnN are opposite.

[0050] Thus, when it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit 100, during the period when the enable signal EnDfe is at the first level value, that is, when the enable signal EnDfe is at logic level 1, one of the first NMOS transistor MN1 and the second NMOS transistor MN2, and one of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on based on the enable signal EnDfe, the other of the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on or off in response to the first complementary feedback signal fbpN, and the other of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on or off in response to the second complementary feedback signal fbnN. Since one of the first complementary feedback signal fbpN and the second complementary feedback signal fbnN is at a high level while the other is at a low level, one of the other of the first NMOS transistor MN1 and the second NMOS transistor MN2, as well as one of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, can be turned on while the other is turned off. This allows the first amplification module 101 to selectively perform either a first comparison or a second comparison in response to the sampling clock signal clkN, so that one of the output first signal pair and the second signal pair is valid while the other is invalid. This reduces the impact of inter-symbol interference of the received data signal on the data receiving circuit 100. Moreover, in the first amplification module 101, only one of the circuits performing the first comparison and the circuit performing the second comparison is in a working state, while the other can be in a non-working state, which helps to reduce the power consumption of the data receiving circuit 100. It should be noted that, based on the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn at this time, the first NMOS transistor MN1 and the second NMOS transistor MN2 conduct the connection path between the first node net1 and the second node net2, or the third NMOS transistor MN3 and the fourth NMOS transistor MN4 conduct the connection path between the third node net3 and the fourth node net4. In this case, the two nodes of the conduction path cannot output a valid signal pair, thereby enabling the amplification unit 131 to selectively perform the first comparison or the second comparison.

[0051] Furthermore, since the on-resistance of an NMOS transistor is much smaller than that of a PMOS transistor under the same conditions, the first NMOS transistors MN1, MN2, MN3, and MN4 in the first amplification module 101 can turn on or off faster in response to the signals received at their respective gates compared to PMOS transistors. This makes it easier for the first amplification module 101 to perform only one of the first and second comparisons at any given time, thereby improving the processing effect and speed of the first amplification module 101 on the data signal DQ. Thus, it is beneficial to improve both the receiving performance of the data receiving circuit 100 and its processing speed for the data signal DQ.

[0052] Understandably, while the enable signal EnDfe is at its first level, the first amplification module 101 selectively performs either a first comparison or a second comparison, resulting in the first amplification module 101 outputting either a valid first signal pair or a valid second signal pair, while the other is an invalid signal pair. It should be noted that a valid first signal pair means that the level values ​​of the first signal Sn+ and the second signal Sp+ in the first signal pair have a significant difference; a valid second signal pair means that the level values ​​of the third signal Sn- and the fourth signal Sp- in the second signal pair have a significant difference. This ensures that the second amplification module 102 receives a pair of differential signals with significantly different signal levels, thereby reducing the impact of intersymbol interference (ISI) of the received data signal DQ on the data receiving circuit 100.

[0053] Furthermore, without considering the impact of inter-symbol interference on the data receiving circuit 100, during the period when the enable signal EnDfe is at the second level value, even when the enable signal EnDfe is at logic level 0, based on the enable signal EnDfe at this time, one of the first NMOS transistors MN1 and MN2 is turned off, disconnecting the connection path between the first node net1 and the second node net2, and one of the third node net3 and the fourth NMOS transistor MN4 is turned off, disconnecting the connection path between the third node net3 and the fourth node net4. The amplification unit 131 performs only the first comparison through its own control. In addition, the first NMOS transistors MN1, MN2, MN3, and MN4 are all integrated in the first amplification module 101, which helps to further reduce the overall layout area of ​​the data receiving circuit 100.

[0054] It should be noted that inter-symbol interference needs to be considered when the data signal DQ received by the data receiving circuit 100 is high-speed data, that is, when the data transmission rate is very fast; inter-symbol interference does not need to be considered when the data signal DQ received by the data receiving circuit 100 is generally low-speed data, that is, when the data transmission rate is relatively slow.

[0055] In some embodiments, the level value of the first reference signal VR+ is different from the level value of the second reference signal VR-. For data signals DQ with different level values, the difference between the data signal DQ and either the first reference signal VR+ or the second reference signal VR- can be greater. If the first amplification module 101 can simultaneously perform the first comparison and the second comparison, then the first amplification module 101 can output a set of signal pairs with a greater level difference. In one embodiment of this disclosure, when inter-symbol interference exists in the data signal DQ received by the data receiving circuit 100, the first amplification module 101 can selectively perform the first comparison or the second comparison based on the first feedback signal fbp and the second feedback signal fbn. One of the output first signal pair and the second signal pair is valid, while the other is invalid. The valid set of signal pairs refers to the set of signal pairs with a greater level difference when the first comparison and the second comparison can be performed simultaneously, thereby reducing the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100. Understandably, while the enable signal EnDfe is at its first level, the first amplification module 101 can select the better comparison for processing the data signal DQ based on the received first feedback signal fbp and second feedback signal fbn. That is, it can selectively perform either the first comparison or the second comparison to obtain a better signal pair. Thus, while the enable signal EnDfe is at its first level, the first amplification module 101 will only perform the one that is better between the first and second comparisons, while the other remains inactive, which helps reduce the power consumption of the data receiving circuit.

[0056] Furthermore, while the enable signal EnDfe is at the second level, regardless of how the levels of the first feedback signal fbp and the second feedback signal fbn obtained based on the previously received data change, the first amplification module 101 performs a fixed first comparison based on the enable signal EnDfe at this time. That is, the first amplification module 101 outputs a valid first signal pair at this time. The first amplification module 101 does not perform a second comparison at this time, meaning that the circuit in the first amplification module 101 used to output the second signal pair can be in a non-operating state, which is beneficial to further reduce the power consumption of the data receiving circuit.

[0057] Regarding how the data receiving circuit 100 reduces the impact of intersymbol interference of the received data signal DQ on the data receiving circuit 100, the following detailed explanation is provided with a specific example.

[0058] In some embodiments, the level of the first reference signal VR+ is higher than the level of the second reference signal VR-. If the data signal DQ is low and inter-symbol interference exists in the data signal DQ received by the data receiving circuit 100, the enable signal EnDfe is at the first level. During this period, the first amplification module 101 performs a first comparison based on the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn, that is, it outputs a valid first signal pair. At this time, the level difference between the data signal DQ and the first reference signal VR+ is greater than the level difference between the data signal DQ and the second reference signal VR-. Therefore, performing the first comparison at this time will produce an output signal pair with a larger level difference than performing the second comparison. Thus, the second amplification module 102 receiving a valid first signal pair is beneficial to improving the accuracy of the output first output signal Vout and the second output signal VoutN, thereby helping to reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0059] Furthermore, if the data signal DQ is high and inter-symbol interference exists in the data signal DQ received by the data receiving circuit 100, and the enable signal EnDfe is at the first level, the first amplification module 101 performs a second comparison based on the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn. That is, the output is a valid second signal pair. At this time, the level difference between the data signal DQ and the first reference signal VR+ is less than the level difference between the data signal DQ and the second reference signal VR-. Therefore, performing the second comparison at this time will produce an output signal pair with a larger level difference than performing the first comparison. Thus, the second amplification module 102 receiving a valid second signal pair is beneficial to improving the accuracy of the output first output signal Vout and the second output signal VoutN, thereby helping to reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0060] Understandably, in practical applications, the level of the first reference signal VR+ can also be lower than the level of the second reference signal VR-.

[0061] It should be noted that, Figure 1The example uses the gates of the first NMOS transistor MN1 and the third NMOS transistor MN3 receiving the enable signal EnDfe, the gate of the second NMOS transistor MN2 receiving the first complementary feedback signal fbpN, and the gate of the fourth NMOS transistor MN4 receiving the second complementary feedback signal fbnN. In practical applications, the gate of the first NMOS transistor MN1 can also receive the first complementary feedback signal fbpN, and the gate of the third NMOS transistor MN3 can also receive the second complementary feedback signal fbnN. Similarly, the gates of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 can also receive the enable signal EnDfe.

[0062] In some embodiments, reference Figure 2 Based on the first amplification module 101 including the first NMOS transistor MN1 and the second NMOS transistor MN2, the first amplification module 101 may further include: a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. One end of the fifth NMOS transistor MN5 is connected to the first node net1, and the other end of the fifth NMOS transistor MN5 is connected to one end of the sixth NMOS transistor MN6. The other end of the sixth NMOS transistor MN6 is connected to the second node net2. The gate of one of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 receives the first complementary feedback signal fbpN, and the gate of the other receives the enable signal EnDfe.

[0063] It is understandable that the branch formed by the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 is connected in parallel with the branch formed by the first NMOS transistor MN1 and the second NMOS transistor MN2. In this way, when the connection path between the first node net1 and the second node net2 is turned on, it is beneficial to reduce the total path resistance of the connection path between the first node net1 and the second node net2, so as to improve the turn-on speed of the connection path between the first node net1 and the second node net2 in response to the enable signal EnDfe and the first complementary feedback signal fbpN.

[0064] In some embodiments, the channel width-to-length ratio of one of the first NMOS transistors MN1 and MN2 receiving the enable signal EnDfe is greater than that of the other, and the channel width-to-length ratio of one of the fifth NMOS transistors MN5 and MN6 receiving the enable signal EnDfe is greater than that of the other.

[0065] It is understandable that when the signal level received by the gate of an NMOS transistor changes frequently, the larger the channel width of the NMOS transistor, the larger its gate capacitance. Conversely, this reduces the sensitivity to changes in the signal level sensed by the gate. Therefore, for NMOS transistors whose gate receives frequently changing signal levels, reducing the channel width of the NMOS transistor helps to reduce the impact of its gate capacitance on the NMOS transistor. Thus, when the enable signal EnDfe is at its first level, the level of the enable signal EnDfe is fixed. For the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6, the gate capacitance of the two NMOS transistors receiving the enable signal EnDfe has little impact on the data receiving circuit 100. At this time, the level of the first complementary feedback signal fbpN changes frequently, making the channel width of the two NMOS transistors receiving the first complementary feedback signal fbpN smaller, which helps to reduce the impact of their gate capacitance on the NMOS transistor.

[0066] Furthermore, a larger channel width-to-length ratio (VW / L) of an NMOS transistor results in lower on-resistance and faster switching speed between on and off. While ensuring the channel widths of the two NMOS transistors receiving the first complementary feedback signal fbpN are relatively small, a larger VW / L ratio for the two NMOS transistors receiving the enable signal EnDfe is beneficial for reducing the total on-resistance of the connection path between the first node net1 and the second node net2. Therefore, considering both the gate capacitance and on-resistance of the NMOS transistors, when the enable signal EnDfe is at its first level, it is advantageous for the two NMOS transistors receiving the first complementary feedback signal fbpN to sensitively sense changes in its level, and for improving the speed at which the connection path between the first node net1 and the second node net2 is switched on or off.

[0067] In one example, continue to refer to Figure 2The gate of the first NMOS transistor MN1 receives the enable signal EnDfe, and the gate of the second NMOS transistor MN2 receives the first complementary feedback signal fbpN. The channel width of the first NMOS transistor MN1 is greater than the channel width of the second NMOS transistor MN2. This is advantageous because the channel width-to-length ratio of the first NMOS transistor MN1 receiving the enable signal EnDfe is greater than that of the second NMOS transistor MN2 receiving the first complementary feedback signal fbpN. Furthermore, the gate of the fifth NMOS transistor MN5 receives the first complementary feedback signal fbpN, and the gate of the sixth NMOS transistor MN6 receives the enable signal EnDfe. The channel width of the fifth NMOS transistor MN5 is less than that of the sixth NMOS transistor MN6. This is advantageous because the channel width-to-length ratio of the sixth NMOS transistor MN6 receiving the enable signal EnDfe is greater than that of the fifth NMOS transistor MN5 receiving the first complementary feedback signal fbpN.

[0068] It should be noted that, Figure 2 The example uses the gates of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 receiving the enable signal EnDfe, and the gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5 receiving the first complementary feedback signal fbpN. In practical applications, the gates of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 can also receive the first complementary feedback signal fbpN, and the gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5 can also receive the enable signal EnDfe.

[0069] In some embodiments, the channel width of the fifth NMOS transistor MN5 is equal to the channel width of the second NMOS transistor MN2; the channel width of the sixth NMOS transistor MN6 is equal to the channel width of the first NMOS transistor MN1; and the channel lengths of the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are all equal. This ensures that the total equivalent capacitance of the first NMOS transistor MN1 and the fifth NMOS transistor MN5 at the first node net1 is no different from the total equivalent capacitance of the second NMOS transistor MN2 and the sixth NMOS transistor MN6 at the second node net2, thus making the load at the first node net1 consistent with the load at the second node net2.

[0070] In some embodiments, reference Figure 2Based on the first amplification module 101 including the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the first amplification module 101 may further include: a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8. One end of the seventh NMOS transistor MN7 is connected to the third node net3, and the other end of the seventh NMOS transistor MN7 is connected to one end of the eighth NMOS transistor MN8. The other end of the eighth NMOS transistor MN8 is connected to the fourth node net4. The gate of one of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 receives the second complementary feedback signal fbnN, and the gate of the other receives the enable signal EnDfe.

[0071] It is understandable that the branch formed by the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 is connected in parallel with the branch formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4. In this way, when the connection path between the third node net3 and the fourth node net4 is turned on, it is beneficial to reduce the total path resistance of the connection path between the third node net3 and the fourth node net4, so as to improve the turn-on speed of the connection path between the third node net3 and the fourth node net4 in response to the enable signal EnDfe and the second complementary feedback signal fbnN.

[0072] In some embodiments, the channel width-to-length ratio of one of the third NMOS transistors MN3 and MN4 receiving the enable signal EnDfe is greater than the channel width-to-length ratio of the other, and the channel width-to-length ratio of one of the seventh NMOS transistors MN7 and MN8 receiving the enable signal EnDfe is greater than the channel width-to-length ratio of the other.

[0073] As described above, when the signal level received by the gate of an NMOS transistor changes frequently, the larger the channel width of the NMOS transistor, the larger its gate capacitance. Conversely, this reduces the sensitivity to changes in the signal level sensed by the gate. Therefore, for NMOS transistors whose gate receives frequently changing signal levels, reducing the channel width of the NMOS transistor helps to reduce the impact of its gate capacitance on the NMOS transistor. Thus, when the enable signal EnDfe is at its first level, the level of the enable signal EnDfe is fixed. For the third NMOS transistor MN3, the fourth NMOS transistor MN4, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8, the gate capacitance of the two NMOS transistors receiving the enable signal EnDfe has little impact on the data receiving circuit 100. At this time, the level of the second complementary feedback signal fbnN changes frequently, making the channel width of the two NMOS transistors receiving the second complementary feedback signal fbnN smaller, which helps to reduce the impact of their gate capacitance on the NMOS transistor.

[0074] Furthermore, a larger channel width-to-length ratio (VWHR) of an NMOS transistor results in lower on-resistance and faster switching speed. While ensuring the two NMOS transistors receiving the second complementary feedback signal fbnN have relatively small channel widths, a larger VWHR of the two NMOS transistors receiving the enable signal EnDfe is beneficial for reducing the total on-resistance of the connection path between the third node net3 and the fourth node net4. Therefore, considering both the gate capacitance and on-resistance of the NMOS transistors, when the enable signal EnDfe is at its first level, it is advantageous for the two NMOS transistors receiving the second complementary feedback signal fbnN to sensitively sense changes in its level, and for improving the speed at which the connection path between the third node net3 and the fourth node net4 is switched on or off.

[0075] It is understandable that, in the first NMOS transistor MN1 and the second NMOS transistor MN2, the channel width-to-length ratio of one receiving the enable signal EnDfe is greater than that of the other; in the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, the channel width-to-length ratio of one receiving the enable signal EnDfe is greater than that of the other; in the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the channel width-to-length ratio of one receiving the enable signal EnDfe is greater than that of the other; and in the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, the channel width-to-length ratio of the enable signal E... The channel width-to-length ratio of one of the nDfe channels is greater than that of the other. In this way, while increasing the speed of turning on or off the connection path between the first node net1 and the second node net2, the speed of turning on or off the connection path between the third node net3 and the fourth node net4 is also increased. This is beneficial to ensure that when one of the connection paths between the first node net1 and the second node net2 and the connection path between the third node net3 and the fourth node net4 is turned on quickly, the other is turned off quickly, so as to avoid the first amplification module 101 performing the first comparison and the second comparison at the same time.

[0076] In one example, continue to refer to Figure 2The gate of the third NMOS transistor MN3 receives the enable signal EnDfe, and the gate of the fourth NMOS transistor MN4 receives the second complementary feedback signal fbnN. In practical applications, the channel width of the third NMOS transistor MN3 is greater than the channel width of the fourth NMOS transistor MN4. This is beneficial because the channel width-to-length ratio of the third NMOS transistor MN3 receiving the enable signal EnDfe is greater than that of the fourth NMOS transistor MN4 receiving the second complementary feedback signal fbnN. Furthermore, the gate of the seventh NMOS transistor MN7 receives the second complementary feedback signal fbnN, and the gate of the eighth NMOS transistor MN8 receives the enable signal EnDfe. The channel width of the seventh NMOS transistor MN7 is less than that of the eighth NMOS transistor MN8. This is also beneficial because the channel width-to-length ratio of the eighth NMOS transistor MN8 receiving the enable signal EnDfe is greater than that of the seventh NMOS transistor MN7 receiving the second complementary feedback signal fbnN.

[0077] It should be noted that, Figure 2 The example uses the gates of the third NMOS transistor MN3 and the eighth NMOS transistor MN8 receiving the enable signal EnDfe, and the gates of the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 receiving the second complementary feedback signal fbnN. In practical applications, the gates of the third NMOS transistor MN3 and the eighth NMOS transistor MN8 can also receive the second complementary feedback signal fbnN, and the gates of the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 can also receive the enable signal EnDfe.

[0078] In some embodiments, the channel width of the seventh NMOS transistor MN7 is equal to the channel width of the fourth NMOS transistor MN4; the channel width of the eighth NMOS transistor MN8 is equal to the channel width of the third NMOS transistor MN3; and the channel lengths of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 are all equal. This ensures that the total equivalent capacitance of the third NMOS transistor MN3 and the seventh NMOS transistor MN7 at the third node net3 is no different from the total equivalent capacitance of the fourth NMOS transistor MN4 and the eighth NMOS transistor MN8 at the fourth node net4, thus making the load at the third node net3 consistent with the load at the fourth node net4.

[0079] Understandably, with Figure 2For example, the channel width-to-length ratio of the first NMOS transistor MN1 and the sixth NMOS transistor MN6 receiving the enable signal EnDfe is larger than that of the second NMOS transistor MN2 and the fifth NMOS transistor MN5 receiving the first complementary feedback signal fbpN. Furthermore, the channel width-to-length ratio of the third NMOS transistor MN3 and the eighth NMOS transistor MN8 receiving the enable signal EnDfe is larger than that of the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 receiving the second complementary feedback signal fbnN. Therefore, during the period when the enable signal EnDfe is at the first level, the first NMOS transistor MN1, the sixth NMOS transistor MN6, the third NMOS transistor MN3, and the eighth NMOS transistor MN8 are all fixedly turned on based on the enable signal EnDfe. The second NMOS transistor... MOS transistors MN2 and MN5 can sensitively detect changes in the level of the first complementary feedback signal fbpN, and NMOS transistors MN4 and MN7 can sensitively detect changes in the level of the second complementary feedback signal fbnN. Therefore, when MN2 and MN5 rapidly turn on in response to the first complementary feedback signal fbpN, MN4 and MN7 can rapidly turn off in response to the second complementary feedback signal fbnN; or, when MN2 and MN5 rapidly turn off in response to the first complementary feedback signal fbpN, MN4 and MN7 can rapidly turn on in response to the second complementary feedback signal fbnN. Thus, during the period when the enable signal EnDfe is at the first level, it is beneficial to ensure that the first amplification module 101 performs only one of the first and second comparisons.

[0080] It should be noted that all subsequent descriptions will be in the format of "..." Figure 2 The illustration is based on the example shown in the image.

[0081] In some embodiments, reference Figure 3 and Figure 4The sampling clock signal clkN includes a first sampling clock signal clkN1 and a second sampling clock signal clkN2; the amplification unit 131 includes: a first comparison circuit 111, having a first node net1 and a second node net2, configured to receive a data signal DQ and a first reference signal VR+ and perform a first comparison in response to the first sampling clock signal clkN1; a clock generation circuit 151, configured to receive an enable signal EnDfe and the original sampling clock signal clk, and output the second sampling clock signal clkN2, wherein, during the period when the enable signal EnDfe has a first level value, the second sampling clock signal clkN2... The phase is opposite to that of the original sampling clock signal clk. During the period when the enable signal EnDfe has a second level value, the second sampling clock signal clkN2 is a logic high level signal. The second comparison circuit 121, having a third node net3 and a fourth node net4, is configured to receive the data signal DQ and the second reference signal VR-, and to perform a second comparison in response to the second sampling clock signal clkN2 during the period when the enable signal EnDfe has a first level value. During the period when the enable signal EnDfe has a second level value, the connection path between the third node net3 and the ground is turned on, and the connection path between the fourth node net4 and the ground is turned on.

[0082] It is understandable that when the enable signal EnDfe is at the first level value, and the second NMOS transistor MN2 and the fifth NMOS transistor MN5 disconnect the connection path between the first node net1 and the second node net2 in response to the first complementary feedback signal fbpN, the first comparison circuit 111 can perform a first comparison in response to the first sampling clock signal clkN1; when the enable signal EnDfe is at the second level value, and the first NMOS transistor MN1 and the sixth NMOS transistor MN6 disconnect the connection path between the first node net1 and the second node net2 based on the enable signal EnDfe at this time, the first comparison circuit 111 can also perform a first comparison in response to the first sampling clock signal clkN1. Therefore, regardless of whether the enable signal EnDfe is at the first level value or the second level value, i.e., regardless of whether the impact of inter-symbol interference on the data receiving circuit 100 needs to be considered, the first comparison circuit 111 may perform a first comparison in response to the first sampling clock signal clkN1. However, the second comparator circuit 121 can only perform the second comparison in response to the changing level of the second sampling clock signal clkN2 when the enable signal EnDfe is at the first level and the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 disconnect the connection path between the third node net3 and the fourth node net4 in response to the second complementary feedback signal fbnN. When the enable signal EnDfe is at the second level, the second sampling clock signal clkN2 is a logic high level signal. The second comparator circuit 121 conducts the connection path between the third node net3 and the ground terminal and the connection path between the fourth node net4 and the ground terminal, pulling down the level value of the third signal Sn- output by the third node net3 and the level value of the fourth signal Sp- output by the fourth node net4 to 0. That is, the second comparator circuit 121 does not perform the second comparison and cannot output a valid second signal pair.

[0083] In some embodiments, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. When the enable signal EnDfe is at a first level value, the phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk. Then, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2 at this time, so that the first comparison circuit 111 can perform a first comparison in response to the first sampling clock signal clkN1, or the second comparison circuit 121 can perform a second comparison in response to the second sampling clock signal clkN2. Meanwhile, based on the enable signal EnDfe, the first complementary feedback signal fbpN, and the second complementary feedback signal fbnN, the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 further control the potentials at the first node net1 and the second node net2, and the third NMOS transistor MN3, the fourth NMOS transistor MN4, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 further control the potentials at the third node net3 and the fourth node net4. For example, the potentials at the first node net1 and the second node net2 are made the same, so that the amplification unit 131 does not actually perform the first comparison and cannot output a valid first signal pair, or the potentials at the third node net3 and the fourth node net4 are the same, so that the amplification unit 131 does not actually perform the second comparison and cannot output a valid second signal pair. In this way, it is beneficial for the amplification unit 131 to selectively perform the first comparison or the second comparison.

[0084] In some embodiments, continue to refer to Figure 3 and Figure 4 The first comparator circuit 111 may include: a first current source 1111, configured to be connected to the power supply node Vcc (reference). Figure 5 Between the first node net1 and the fifth node net5, current is supplied to the fifth node net5 in response to the first sampling clock signal clkN1; the first comparison unit 1112, connected to the first node net1, the second node net2 and the fifth node net5, is configured to receive the data signal DQ and the first reference signal VR+, perform a first comparison when the first current source 1111 supplies current to the fifth node net5, and output the first signal Sn+ and the second signal Sp+; the first reset unit 1113, connected to the first node net1 and the second node net2, is configured to reset the first node net1 and the second node net2 in response to the first sampling clock signal clkN1.

[0085] The second comparison circuit 121 may include: a second current source 1211, configured to be connected between the power supply node Vcc and the sixth node net6, providing current to the sixth node net6 in response to the second sampling clock signal clkN2; a second comparison unit 1212, connected to the third node net3, the fourth node net4 and the sixth node net6, configured to receive the data signal DQ and the second reference signal VR-, perform a second comparison when the second current source 1211 provides current to the sixth node net6, and output a third signal Sn- and a fourth signal Sp-; and a second reset unit 1213, connected between the third node net3 and the fourth node net4, configured to reset the third node net3 and the fourth node net4 in response to the second sampling clock signal clkN2.

[0086] Understandably, the first comparison unit 1112 can control the difference between the current supplied to the first node net1 and the current supplied to the second node net2 based on the voltage difference between the data signal DQ and the first reference signal VR+, so as to output the first signal Sn+ and the second signal Sp+; the second comparison unit 1212 can control the difference between the current supplied to the third node net3 and the current supplied to the fourth node net4 based on the voltage difference between the data signal DQ and the second reference signal VR-, so as to output the third signal Sn- and the fourth signal Sp-. Furthermore, after the data receiving circuit 100 completes the reception of the data signal DQ, the first reference signal VR+ and the second reference signal VR-, and the output of the first output signal Vout and the second output signal VoutN, the first reset unit 1113 can restore the level values ​​of the first node net1 and the second node net2 to their initial values, and the second reset unit 1213 can restore the level values ​​of the third node net3 and the fourth node net4 to their initial values, so that the subsequent data receiving circuit 100 can perform the next data reception and processing.

[0087] In some embodiments, the circuit structure of the first current source 1111 is the same as that of the second current source 1211; the circuit structure of the first comparison unit 1112 is the same as that of the second comparison unit 1212. This is advantageous because the difference between the first signal pair output by the first comparison circuit 111 and the second signal pair output by the second comparison circuit 121 is mainly affected by the first reference signal VR+, or the difference between the second signal pair output by the second comparison circuit 121 and the second reference signal VR- is mainly affected by the second reference signal VR-. This further benefits the data receiving circuit 100 by reducing the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100 based on the first reference signal VR+ and the second reference signal VR-, thereby further improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102.

[0088] In some embodiments, reference Figure 5 and Figure 6 The first current source 1111 may include: a first PMOS transistor MP1, connected between the power supply node Vcc and the fifth node net5, and the gate of the first PMOS transistor MP1 receives the first sampling clock signal clkN1; the second current source 1112 may include: a second PMOS transistor MP2, connected between the power supply node Vcc and the sixth node net6, and the gate of the second PMOS transistor MP2 receives the second sampling clock signal clkN2.

[0089] Thus, when the first sampling clock signal clkN1 is low, the gate of the first PMOS transistor MP1 receives the first sampling clock signal clkN1 and is turned on, providing current to the fifth node net5, causing the first comparison unit 1112 to be in working state, that is, to perform a first comparison between the received data signal DQ and the first reference signal VR+. At the same time, the enable signal EnDfe is high, the first complementary feedback signal fbpN is low, the second NMOS transistor MN2 and the fifth NMOS transistor MN5 are both turned off, and the connection path between the first node net1 and the second node net2 is broken. When the second sampling clock signal clkN2 is low, the gate of the second PMOS transistor MP2 receives the second sampling clock signal clkN2 and is turned on, providing current to the sixth node net6, so that the second comparison unit 1212 is in working state, and performs a second comparison on the received data signal DQ and the second reference signal VR-. At the same time, the enable signal EnDfe is high, the second complementary feedback signal fbnN is low, the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 are both turned off, and the connection path between the third node net3 and the fourth node net4 is broken.

[0090] In one example, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. When it is necessary to reduce the impact of intersymbol interference on the data receiving circuit 100, the enable signal EnDfe is in the first level period, i.e., high level. The phase of the second sampling clock signal clkN2 is also opposite to the phase of the original sampling clock signal clk. At this time, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2, so that the first current source 1111 can provide current to the fifth node net5 to prepare for the first comparison unit 121 to perform the first comparison, while the second current source 1211 can provide current to the sixth node net6 to prepare for the second comparison unit 122 to perform the second comparison. At this time, the enable signal EnDfe is high. If the first complementary feedback signal fbpN is low, the connection path between the first node net1 and the second node net2 is broken, and the first comparison unit 121 performs the first comparison. At this time, the second complementary feedback signal fbnN is high, and the connection path between the third node net3 and the fourth node net4 is connected, and the second comparison unit 122 cannot perform the second comparison. If the first complementary feedback signal fbpN is high, the connection path between the first node net1 and the second node net2 is connected, and the first comparison unit 121 cannot perform the first comparison. At this time, the second complementary feedback signal fbnN is low, and the connection path between the third node net3 and the fourth node net4 is broken, and the second comparison unit 122 performs the second comparison.

[0091] Furthermore, when there is no need to consider the impact of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at the second level value, i.e., low level, the second sampling clock signal clkN2 is a logic high level signal, and the second PMOS transistor MP2 is always off, so that the current in the second comparison unit 1212 is almost 0, thereby reducing the power consumption of the data receiving circuit 100. Moreover, at this time, the second comparison unit 1212 cannot perform the second comparison and cannot output a valid second signal pair. At this time, the first sampling clock signal clkN1 is a clock signal, and the first PMOS transistor MP1 can be turned on in response to the clock signal, so that the first comparison unit 1112 performs the first comparison and outputs a valid first signal pair, so that the data receiving circuit 100 can work normally as a whole.

[0092] In some embodiments, continue to refer to Figure 5 and Figure 6The first comparison unit 1112 may include: a third PMOS transistor MP3, connected between the first node net1 and the fifth node net5, the gate of the third PMOS transistor MP3 receiving the data signal DQ; a fourth PMOS transistor MP4, connected between the second node net2 and the fifth node net5, the gate of the fourth PMOS transistor MP4 receiving the first reference signal VR+; the second comparison unit 1212 may include: a fifth PMOS transistor MP5, connected between the third node net3 and the sixth node net6, the gate of the fifth PMOS transistor MP5 receiving the data signal DQ; a sixth PMOS transistor MP6, connected between the fourth node net4 and the sixth node net6, the gate of the sixth PMOS transistor MP6 receiving the second reference signal VR-.

[0093] It should be noted that, for the first comparison unit 1112, the level changes of the data signal DQ and the first reference signal VR+ are asynchronous. This causes the turn-on time of the third PMOS transistor MP3, which receives the data signal DQ, to differ from the turn-on time of the fourth PMOS transistor MP4, which receives the first reference signal VR+. Furthermore, at the same time, the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4. Understandably, because the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4, the current shunting capabilities of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 at the fifth node net5 are also different. This results in a difference between the voltage at the first node net1 and the voltage at the second node net2, which is beneficial for outputting the first signal Sn+ and the second signal Sp+ as a first signal pair with a significant difference in signal level.

[0094] For the second comparison unit 1212, the level changes of the data signal DQ and the second reference signal VR- are asynchronous. This causes the turn-on time of the fifth PMOS transistor MP5, which receives the data signal DQ, to differ from the turn-on time of the sixth PMOS transistor MP6, which receives the second reference signal VR-. Furthermore, at the same time, the conduction degree of the fifth PMOS transistor MP5 differs from that of the sixth PMOS transistor MP6. It is understandable that, based on the difference in conduction degree between the fifth and sixth PMOS transistors MP5 and MP6, their current shunting capabilities at the sixth node net6 also differ. This results in a difference between the voltage at the third node net3 and the voltage at the fourth node net4, which is beneficial for outputting the third signal Sn- and the fourth signal Sp- as a second signal pair with a significant difference in signal level.

[0095] In one example, the first amplification module 101 performs a first comparison. When the level of the data signal DQ is lower than the level of the first reference signal VR+, the conduction degree of the third PMOS transistor MP3 is greater than that of the fourth PMOS transistor MP4. This causes more current to flow into the path of the third PMOS transistor MP3 at the fifth node net5, making the current at the first node net1 greater than the current at the second node net2. Consequently, the level of the first signal Sn+ output by the first node net1 is higher, and the level of the second signal Sp+ output by the second node net2 is lower. In another example, the first amplification module 101 performs a second comparison. When the level of the data signal DQ is lower than the level of the second reference signal VR-, the conduction degree of the fifth PMOS transistor MP5 is greater than that of the sixth PMOS transistor MP6. This causes more current to flow into the path of the fifth PMOS transistor MP5 at the sixth node net6, making the current at the third node net3 greater than the current at the fourth node net4. Consequently, the level of the third signal Sn- output by the third node net3 is higher, and the level of the fourth signal Sp- output by the fourth node net4 is lower.

[0096] Similarly, when the level of the data signal DQ is higher than the level of the first reference signal VR+, the conduction degree of the third PMOS transistor MP3 is less than that of the fourth PMOS transistor MP4, the level of the first signal Sn+ output by the first node net1 is low, and the level of the second signal Sp+ output by the second node net2 is high; when the level of the data signal DQ is higher than the level of the second reference signal VR-, the conduction degree of the fifth PMOS transistor MP5 is less than that of the sixth PMOS transistor MP6, the level of the third signal Sn- output by the third node net3 is low, and the level of the fourth signal Sp- output by the fourth node net4 is high.

[0097] In some embodiments, continue to refer to Figure 5 and Figure 6 The first reset unit 1113 may include: a ninth NMOS transistor MN9, connected between the first node net1 and ground, with its gate receiving the first sampling clock signal clkN1; and a tenth NMOS transistor MN10, connected between the second node net2 and ground, with its gate receiving the first sampling clock signal clkN1. The second reset unit 1213 may include: an eleventh NMOS transistor MN11, connected between the third node net3 and ground, with its gate receiving the second sampling clock signal clkN2; and a twelfth NMOS transistor MN12, connected between the fourth node net4 and ground, with its gate receiving the second sampling clock signal clkN2.

[0098] In one example, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. When it is necessary to reduce the impact of intersymbol interference on the data receiving circuit, the enable signal EnDfe is at the first level. During this period, the phase of the second sampling clock signal clkN2 is also opposite to the phase of the original sampling clock signal clk. At this time, the phases of the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are synchronized. If both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are low, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned on. At this time, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, and the eleventh NMOS transistor MN11 are... When both the 10th and 12th NMOS transistors MN12 are turned off, one of the connection paths between the first node ne1 and the second node net2 and the connection path between the third node ne3 and the fourth node net4 is turned on based on the first complementary feedback signal fbp and the second complementary feedback signal fbnN, so as to enable the first amplification module 101 to selectively perform the first comparison or the second comparison. At the same time, the 9th NMOS transistor MN9 and the 10th NMOS transistor MN10 can be used as the load of the first comparison unit 1112 to increase the amplification gain of the first comparison unit 1112, and the 11th NMOS transistor MN11 and the 12th NMOS transistor MN12 can be used as the load of the second comparison unit 1212 to increase the amplification gain of the second comparison unit 1212.

[0099] If both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are high, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned off, and no current flows through the first comparison unit 1112 and the second comparison unit 1212. At this time, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the twelfth NMOS transistor MN12 are all turned on, pulling down the voltage at the first node net1, the second node net2, the third node net3, and the fourth node net4 to reset the first node net1, the second node net2, the third node net3, and the fourth node net4, so that the subsequent data receiving circuit 100 can perform the next data reception and processing.

[0100] Furthermore, when there is no need to consider the impact of inter-symbol interference on the data receiving circuit 100, during the period when the enable signal EnDfe is at the second level value, the second sampling clock signal clkN2 is a logic high level signal, the second PMOS transistor MP2 is always off, and the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 are both turned on to connect the connection path between the third node net3 and the ground terminal, and to connect the connection path between the fourth node net4 and the ground terminal, thereby resetting the third node net3 and the fourth node net4. At this time, the current in the second comparison unit 1212 is almost 0, which helps to reduce the power consumption of the data receiving circuit 100. At this time, if the first sampling clock signal clkN1 is low, the first PMOS transistor MP1 is turned on, and the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are both turned off, so as to ensure that the first comparison circuit 111 performs the first comparison and outputs a valid first signal pair, so that the subsequent second amplification module 102 can receive the first signal pair in a fixed manner; or, if the first sampling clock signal clkN1 is high, the first PMOS transistor MP1 is turned off, and the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are both turned on, pulling down the voltage at the first node net1 and the voltage at the second node net2 to realize the reset of the first node net1 and the second node net2, so that the subsequent data receiving circuit 100 can perform the next data reception and processing.

[0101] In some embodiments, continue to refer to Figure 5 and Figure 6 The clock generation circuit 151 may include: a first NAND gate circuit 1511, one input of the first NAND gate circuit 1511 receives the original sampling clock signal clk, the other input is connected to the power supply node Vcc, and the output outputs the first sampling clock signal clkN1.

[0102] Understandably, the input terminal of the first NAND gate 1511 connected to the power supply node Vcc receives a high level. At this time, if the original sampling clock signal clk received at the other input terminal of the first NAND gate 1511 is high, then the first sampling clock signal clkN1 is low; if the original sampling clock signal clk received at the other input terminal of the first NAND gate 1511 is low, then the first sampling clock signal clkN1 is high. Thus, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. Therefore, when it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2. The first amplification module 101 can selectively perform the first comparison or the second comparison.

[0103] In some embodiments, continue to refer to Figure 5 and Figure 6 The clock generation circuit 151 may include: a second NAND gate circuit 1512, one input of the second NAND gate circuit 1512 receives the original sampling clock signal clk, the other input receives the enable signal EnDfe, and the output outputs the second sampling clock signal clkN2.

[0104] Understandably, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. When it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is high. If the original sampling clock signal clk is high, then the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is low. At this time, the first sampling clock signal clkN1 is also low. The first amplification module 101 selectively performs a first comparison or a second comparison based on the first complementary feedback signal fbpN and the second complementary feedback signal fbnN, and processes the one that is better. Subsequently, the second amplification module 102 receives a valid first signal pair or a valid second signal pair, and the other signal pair is invalid. To reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100; if the original sampling clock signal clk is low, then the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is high. At this time, the first sampling clock signal clkN1 is also high. At this time, the first comparison unit 1112 and the second comparison unit 1212 are both in a non-working state. The level values ​​at the first node net1 and the second node net2 can be restored to the initial value by the first reset unit 1113, and the level values ​​at the third node net3 and the fourth node net4 can be restored to the initial value by the second reset unit 1213, so that the subsequent data receiving circuit 100 can perform the next data reception and processing.

[0105] When the impact of inter-symbol interference on the data receiving circuit 100 is not considered, the enable signal EnDfe is at a low level. At this time, regardless of whether the original sampling clock signal clk is at a high level or a low level, the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is at a high level. Therefore, regardless of whether the first sampling clock signal clkN1 is at a high level or a low level, that is, regardless of whether the first comparison unit 1112 performs the first comparison, the connection path between the third node net3 and the ground terminal and the connection path between the fourth node net4 and the ground terminal in the second comparison circuit 121 will be conducted, so that the current in the second comparison circuit 121 is almost 0, and the second comparison will not be performed.

[0106] In some embodiments, reference Figure 4The second amplification module 102 includes: a first input unit 112, connected to the seventh node net7 and the eighth node net8, configured to receive a first signal pair and perform a third comparison, and provide signals to the seventh node net7 and the eighth node net8 as the result of the third comparison; a second input unit 122, connected to the seventh node net7 and the eighth node net8, configured to receive a second signal pair and perform a fourth comparison, and provide signals to the seventh node net7 and the eighth node net8 as the result of the fourth comparison; and a latching unit 132, connected to the seventh node net7 and the eighth node net8, configured to amplify and latch the signals of the seventh node net7 and the eighth node net8, and output a first output signal Vout and a second output signal VoutN through the first output node net9 and the second output node net10, respectively.

[0107] Understandably, when it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit, during the period when the enable signal EnDfe is at the first level value, the first amplification module 101 selectively performs a first comparison and a second comparison based on the first complementary feedback signal fbpN and the second complementary feedback signal fbnN. One of the output first signal pair and the second signal pair is valid, while the other is invalid. Furthermore, the input units that can be turned on at this time receive valid signal pairs. A valid signal pair refers to a pair of signal pairs that, if the first comparison and the second comparison can be performed simultaneously, have a larger difference in output level values, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102. When it is not necessary to consider the impact of inter-symbol interference on the data receiving circuit 100, during the period when the enable signal EnDfe is at the second level value, the first amplification module 101 consistently outputs valid first signal pairs. The first input unit 112 turns on or off in response to valid first signal pairs, and the signal pairs received by the second input unit 122 are invalid and in an off state, thereby reducing the power consumption of the data receiving circuit.

[0108] The latch unit 132 is used to output a high-level signal to the first output node net9 and a low-level signal to the second output node net10 according to the signal of the seventh node net7 and the signal of the eighth node net8, or to output a low-level signal to the first output node net9 and a high-level signal to the second output node net10.

[0109] In some embodiments, reference Figure 7 and Figure 8The first input unit 112 may include: a thirteenth NMOS transistor MN13, the drain of which is connected to the seventh node net7, the source of which is connected to ground, and the gate of which receives the first signal Sn+; a fourteenth NMOS transistor MN14, the drain of which is connected to the eighth node net8, the source of which is connected to ground, and the gate of which receives the second signal Sp+; the second input unit 122 may include: a fifteenth NMOS transistor MN15, the drain of which is connected to the seventh node net7, the source of which is connected to ground, and the gate of which receives the third signal Sn-; and a sixteenth NMOS transistor MN16, the drain of which is connected to the eighth node net8, the source of which is connected to ground, and the gate of which receives the fourth signal Sp-.

[0110] In one example, when the first amplification module 101 performs the first comparison, if the level of the data signal DQ is higher than the level of the first reference signal VR+, then the level of the first signal Sn+ is low, and the level of the second signal Sp+ is high. Consequently, the conduction level of the fourteenth NMOS transistor MN14 is greater than that of the thirteenth NMOS transistor MN13, resulting in a voltage at the eighth node net8 being lower than the voltage at the seventh node net7. Similarly, if the level of the data signal DQ is lower than the level of the first reference signal VR+, then the level of the first signal Sn+ is high, and the level of the second signal Sp+ is low. Consequently, the conduction level of the thirteenth NMOS transistor MN13 is greater than that of the fourteenth NMOS transistor MN14, resulting in a voltage at the seventh node net7 being lower than the voltage at the eighth node net8.

[0111] In another example, when the first amplification module 101 performs the second comparison, if the level of the data signal DQ is higher than the level of the second reference signal VR-, then the level of the third signal Sn- is low, and the level of the fourth signal Sp- is high. Consequently, the conduction level of the sixteenth NMOS transistor MN16 is greater than that of the fifteenth NMOS transistor MN15, resulting in a voltage at the eighth node net8 being lower than the voltage at the seventh node net7. Similarly, if the level of the data signal DQ is lower than the level of the second reference signal VR-, then the level of the third signal Sn- is high, and the level of the fourth signal Sp- is low. Consequently, the conduction level of the fifteenth NMOS transistor MN15 is greater than that of the sixteenth NMOS transistor MN16, resulting in a voltage at the seventh node net7 being lower than the voltage at the eighth node net8.

[0112] In some embodiments, continue to refer to Figure 7 and Figure 8The latch unit 132 may include: a seventeenth NMOS transistor MN17 and a seventh PMOS transistor MP7, the gates of the seventeenth NMOS transistor MP7 and the seventh PMOS transistor MP7 are both connected to the second output node net10, the source of the seventeenth NMOS transistor MN17 is connected to the seventh node net7, the drains of the seventeenth NMOS transistor MN17 and the seventh PMOS transistor MP7 are both connected to the first output node net9, and the source of the seventh PMOS transistor MP7 is connected to the power supply node Vcc; an eighteenth NMOS transistor MN18 and an eighth PMOS transistor MP8, the gates of the eighteenth NMOS transistor MN18 and the eighth PMOS transistor MP8 are both connected to the first output node net9, the source of the eighteenth NMOS transistor MN18 is connected to the eighth node net8, the drains of the eighteenth NMOS transistor MN18 and the eighth PMOS transistor MP8 are both connected to the second output node net10, and the source of the eighth PMOS transistor MP8 is connected to the power supply node Vcc.

[0113] In one example, when the first amplification module 101 performs the first comparison, if the level of the data signal DQ is higher than the level of the first reference signal VR+, the level of the first signal Sn+ is low, and the level of the second signal Sp+ is high, then the voltage at the eighth node net8 is less than the voltage at the seventh node net7, thereby making the conduction degree of the eighteenth NMOS transistor MN18 greater than that of the seventeenth NMOS transistor MN17. The voltage at the second output node net10 is less than the voltage at the first output node net9, so the conduction degree of the eighth PMOS transistor MP8 is less than that of the seventh PMOS transistor MP7. The latch unit 132 forms positive feedback amplification, further making the first output signal Vout output by the first output node net9 high and the second output signal VoutN output by the second output node net10 low. Similarly, if the level of the data signal DQ is lower than the level of the first reference signal VR+, then the voltage at the seventh node net7 is less than the voltage at the eighth node net8, the first output signal Vout output by the first output node net9 is low, and the second output signal VoutN output by the second output node net10 is high.

[0114] In another example, when the first amplification module 101 performs the second comparison, if the level of the data signal DQ is higher than the level of the second reference signal VR-, the level of the third signal Sn- is low, and the level of the fourth signal Sp- is high. Therefore, the conduction level of the sixteenth NMOS transistor MN16 is greater than that of the fifteenth NMOS transistor MN15, causing the voltage at the eighth node net8 to be lower than the voltage at the seventh node net7. This results in the first output signal Vout output by the first output node net9 being high, and the second output signal VoutN output by the second output node net10 being low. Similarly, if the level of the data signal DQ is lower than the level of the second reference signal VR-, the level of the third signal Sn- is high, and the level of the fourth signal Sp- is low. In this case, the first output signal Vout output by the first output node net9 is low, and the second output signal VoutN output by the second output node net10 is high.

[0115] In some embodiments, reference Figure 4 The second amplification module 102 may further include a third reset unit 142, connected between the power supply node Vcc and the output terminal of the latch unit 132, configured to reset the output terminal of the latch unit 132. Thus, after the data receiving circuit 100 completes the reception of a data signal DQ, a first reference signal VR+, and a second reference signal VR-, and the output of a first output signal Vout and a second output signal VoutN, the third reset unit 142 can restore the level values ​​at the first output node net9 and the second output node net10 to their initial values, so that the subsequent data receiving circuit 100 can receive and process the next data.

[0116] In some embodiments, reference Figure 7 and Figure 8 The third reset unit 142 may include: a ninth PMOS transistor MP9, connected between the first output node net9 and the power supply node Vcc, the gate of the ninth PMOS transistor MP9 receiving the original sampling clock signal clk; and a tenth PMOS transistor MP10, connected between the second output node net10 and the power supply node Vcc, the gate of the tenth PMOS transistor MP10 receiving the original sampling clock signal clk.

[0117] In one example, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. When it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at logic level 1. The phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk. When the original sampling clock signal clk is high, both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are low. Then, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. At this time, the first amplification module 101 selectively performs either a first comparison or a second comparison based on the first complementary feedback signal fbpN and the second complementary feedback signal fbnN, so that the first amplification module 101 can only output one of the valid first signal pair and the valid second signal pair. For example, when the first complementary feedback signal fbpN is low and the second complementary feedback signal fbnN is high, the first comparison unit 121 performs the first comparison, and the second comparison unit 122 cannot perform the second comparison. At this time, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 are all turned off.

[0118] When the original sampling clock signal clk is low, the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are both high. Therefore, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned off. At this time, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the twelfth NMOS transistor MN12 are all turned on. The voltage at the first node net1, the second node net2, the third node net3, and the fourth node net4 are pulled down to reset the first node net1, the second node net2, the third node net3, and the fourth node net4. The ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are also turned on. The voltage at the first output node net9 and the second output node net10 are pulled up to reset the first output node net9 and the second output node net10.

[0119] When there is no need to consider the impact of intersymbol interference on the data receiving circuit 100, the enable signal EnDfe is at logic level 0. At this time, regardless of whether the original sampling clock signal clk is high or low, the second sampling clock signal clkN2 is always high. Therefore, the second PMOS transistor MP2 is always turned off to reduce the current in the second comparator circuit 121, thereby reducing the power consumption of the data receiving circuit 100.

[0120] In some embodiments, reference Figure 4The data receiving circuit 100 may further include: a first inverting circuit 114 configured to receive a first feedback signal fbp and output a first complementary feedback signal fbpN; and a second inverting circuit 124 configured to receive a second feedback signal fbn and output a second complementary feedback signal fbnN. Thus, the first inverting circuit 114 converts the first feedback signal fbp into the first complementary feedback signal fbpN and provides it to the gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5, and the second inverting circuit 124 converts the second feedback signal fbn into the second complementary feedback signal fbnN and provides it to the gates of the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7.

[0121] In some embodiments, reference Figures 4 to 6 The first inverter circuit 114 may include a first inverter 1141; the second inverter circuit 124 includes a second inverter 1241.

[0122] It should be noted that the reference Figure 9 The data receiving circuit 100 and the latching circuit 110 connected to the data receiving circuit 100 can constitute multiple data transmission circuits 120, and the multiple cascaded data transmission circuits 120 constitute a data receiving system; the output signal of the previous stage data transmission circuit 120 serves as the feedback signal fb of the next stage data transmission circuit 120; the output signal of the last stage data transmission circuit 120 serves as the feedback signal fb of the first stage data transmission circuit 120. The feedback signal fb includes a first feedback signal fbp and a second feedback signal fbn.

[0123] It is understandable that when multiple data receiving circuits 100 are cascaded, the first output signal Vout and the second output signal VoutN output by the data receiving circuit 100 of the previous stage serve as the first feedback signal fbp and the second feedback signal fbn of the data receiving circuit 100 of the next stage, respectively. The data receiving circuit 100 of the next stage selectively performs a first comparison or a second comparison based on the received first feedback signal fbp and the second feedback signal fbn. The first output signal Vout and the second output signal VoutN output by the last stage data receiving circuit 100 serve as the first feedback signal fbp and the second feedback signal fbn of the first stage data receiving circuit 100, respectively. The data receiving circuit 100 of the first stage selectively performs a first comparison or a second comparison based on the received first feedback signal fbp and the second feedback signal fbn.

[0124] Specifically, the first output signal Vout output by the first output node net9 of the previous stage data receiving circuit 100 serves as the first feedback signal fbp of the next stage data receiving circuit 100, and the second output signal VoutN output by the second output node net10 of the previous stage data receiving circuit 100 serves as the second feedback signal fbn of the next stage data receiving circuit 100. Then, the first inverter 1141 in the next stage data receiving circuit 100 converts the first feedback signal fbp into a first complementary feedback signal fbpN and provides it to the gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5 in this stage. The second inverter 1241 in the next stage data receiving circuit 100 converts the second feedback signal fbn into a second complementary feedback signal fbnN and provides it to the gates of the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 in this stage.

[0125] It is understandable that if the first output signal Vout output by the first output node net9 of the previous stage data receiving circuit 100 is high and the second output signal VoutN output by the second output node net10 is low, then the first feedback signal fbp received by the next stage data receiving circuit 100 is high and the second feedback signal fbn is low. In this case, the first complementary feedback signal fbpN is low and the second complementary feedback signal fbnN is high.

[0126] In some embodiments, reference Figure 4 and Figure 8 The first inverter circuit 114 may include a third NAND gate 1142, the two inputs of which receive the first feedback signal fbp and the enable signal EnDfe respectively, and the output outputs the first complementary feedback signal fbpN; the second inverter circuit 124 may include a fourth NAND gate 1242, the two inputs of which receive the second feedback signal fbn and the enable signal EnDfe respectively, and the output outputs the second complementary feedback signal fbnN.

[0127] Specifically, when the enable signal EnDfe is at the first level value, i.e., logic level 1, the level change of the first feedback signal fbp received by the third NAND gate 1142 is opposite to the level change of the first complementary feedback signal fbpN output, i.e., the level of the first complementary feedback signal fbpN is opposite to the level of the first feedback signal fbp. Moreover, the level change of the second feedback signal fbn received by the fourth NAND gate 1242 is opposite to the level change of the second complementary feedback signal fbnN output, i.e., the level of the second complementary feedback signal fbnN is opposite to the level of the second feedback signal fbn.

[0128] It should be noted that, in one example, the reference Figure 4 and Figure 8When multiple data receiving circuits 100 are cascaded, the first output signal Vout output by the first output node net9 of the previous-level data receiving circuit 100 serves as the first feedback signal fbp. The third NAND gate 1142 in the previous-level data receiving circuit 100 receives the first feedback signal fbp and the enable signal EnDfe, and outputs a first complementary feedback signal fbpN to the next-level data receiving circuit 100. The second output signal VoutN output by the second output node net10 of the previous-level data receiving circuit 100 serves as the second feedback signal fbn. The fourth NAND gate 1242 in the previous-level data receiving circuit 100 receives the second feedback signal fbn and the enable signal EnDfe, and outputs a second complementary feedback signal fbnN to the next-level data receiving circuit 100. Then, the next-level data receiving circuit 100 selectively performs a first comparison or a second comparison based on the received first complementary feedback signal fbpN and second complementary feedback signal fbnN. It is understandable that the first complementary feedback signal fbpN is obtained by processing the third NAND gate 1142, which is beneficial to enhance the driving capability of the first complementary feedback signal fbpN by using the third NAND gate 1142. The second complementary feedback signal fbnN is obtained by processing the fourth NAND gate 1242, which is beneficial to enhance the driving capability of the second complementary feedback signal fbnN by using the fourth NAND gate 1242. Thus, when the first complementary feedback signal fbpN and the second complementary feedback signal fbnN are transmitted from the previous stage to the next stage and the transmission path is long, it is beneficial to enhance the driving capability of the first complementary feedback signal fbpN and the second complementary feedback signal fbnN to the next stage data transmission circuit 100 by using the third NAND gate 1142 and the fourth NAND gate 1242.

[0129] In another example, when multiple data receiving circuits 100 are cascaded, the first output signal Vout and the second output signal VoutN output by the previous stage data receiving circuit 100 serve as the first feedback signal fbp and the second feedback signal fbn of the next stage data receiving circuit 100, respectively. The third NAND gate 1142 in the next stage data receiving circuit 100 converts the first feedback signal fbp into a first complementary feedback signal fbpN and provides it to the gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5 in this stage. The fourth NAND gate 1242 in the next stage data receiving circuit 100 converts the second feedback signal fbn into a second complementary feedback signal fbnN and provides it to the gates of the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 in this stage. Furthermore, the third NAND gate 1142 can be positioned near the gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5, and the fourth NAND gate 1242 can be positioned near the gates of the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7.

[0130] The following combination Figure 5 , Figure 7 Table 1 provides a detailed description of the specific working principle of the data receiving circuit 100 provided in one embodiment of this disclosure.

[0131] In one example, when multiple data receiving circuits 100 are cascaded, the first output signal Vout output by the first output node net9 of the previous level data receiving circuit 100 serves as the first feedback signal fbp of the next level data receiving circuit 100, and the second output signal VoutN output by the second output node net10 of the previous level data receiving circuit 100 serves as the second feedback signal fbn of the next level data receiving circuit 100.

[0132] The following explanation uses the example of the received first reference signal VR+ being greater than the second reference signal VR- as an example. When the data signal DQ is at logic level 1, it indicates that the level of the data signal DQ is greater than the level of the first reference signal VR+; when the data signal DQ is at logic level 0, it indicates that the level of the data signal DQ is less than the level of the second reference signal VR-. It should be noted that in Table 1, 1 represents a high level and 0 represents a low level.

[0133] When the impact of intersymbol interference on the data receiving circuit 100 needs to be considered, the enable signal EnDfe is high. At this time, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned on, the second NMOS transistor MN2 is turned on or off in response to the first complementary feedback signal fbpN, and the fourth NMOS transistor MN4 is turned on or off in response to the second complementary feedback signal fbnN.

[0134] Referring to Table 1, if the data signal DQ1 received by the previous stage data receiving circuit 100 is at logic level 1, the first output signal Vout of the previous stage data receiving circuit 100, i.e., the first feedback signal fbp of the next stage data receiving circuit 100, is at a high level, and the second output signal VoutN of the previous stage data receiving circuit 100, i.e., the second feedback signal fbn of the next stage data receiving circuit 100, is at a low level. At this time, the first complementary feedback signal fbpN is at a low level, the second complementary feedback signal fbnN is at a high level, the second NMOS transistor MN2 is turned off, the fourth NMOS transistor MN4 is turned on, the first amplification module 101 performs a first comparison, and outputs the first signal Sn+ and the second signal Sp+ through the first node net1 and the second node net2. The first input unit 112 is used to perform a third comparison on the first signal Sn+ and the second signal Sp+ to provide signals to the seventh node net7 and the eighth node net8. No current flows through the second input unit 122.

[0135] When the data signal DQ1 received by the previous stage data receiving circuit 100 is logic level 1, the data signal DQ2 received by the next stage data receiving circuit 100 will have the following two cases:

[0136] Scenario 1: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 0, the level difference between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is large, resulting in significant inter-symbol interference. In this case, the first amplification module 101 in the next-stage data receiving circuit 100 performs a first comparison and outputs the first signal Sn+ and the second signal Sp+, causing the first input unit 112 to be turned on. That is, the second amplification module 102 in the next-stage data receiving circuit 100 receives the first signal Sn+ and the second signal Sp+. At this time, in the next-stage data receiving circuit 100, the data signal DQ2 is at logic level 0, and the voltage difference between the data signal DQ2 and the first reference signal VR+ is greater than the voltage difference between the data signal DQ2 and the second reference signal VR-. If a second comparison can be performed at this time, the difference in the level value of the effective first signal pair obtained by the first comparison is greater than the difference in the level value of the effective second signal pair obtained by the second comparison. At this time, the second amplification module 102 receiving the effective first signal pair is more conducive to outputting the first output signal Vout and the second output signal VoutN with higher accuracy, so as to reduce the impact of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100. Moreover, not performing a second comparison at this time is conducive to reducing the power consumption of the data receiving circuit 100.

[0137] Scenario 2: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 1, the difference in level between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is small, indicating minimal or no inter-symbol interference. In this case, the first amplification module 101 in the next-stage data receiving circuit 100 performs a first comparison and outputs the first signal Sn+ and the second signal Sp+, causing the first input unit 112 to be turned on. That is, the second amplification module 102 in the next-stage data receiving circuit 100 receives the first signal Sn+ and the second signal Sp+.

[0138] Referring to Table 1, if the data signal DQ1 received by the previous stage data receiving circuit 100 is at logic level 0, the first output signal Vout of the previous stage data receiving circuit 100, i.e., the first feedback signal fbp of the next stage data receiving circuit 100, is at a low level, and the second output signal VoutN of the previous stage data receiving circuit 100, i.e., the second feedback signal fbn of the next stage data receiving circuit 100, is at a high level. At this time, the first complementary feedback signal fbpN is at a high level, the second complementary feedback signal fbnN is at a low level, the second NMOS transistor MN2 is turned on, the fourth NMOS transistor MN4 is turned off, the first amplification module 101 performs a second comparison, and outputs the third signal Sn- and the fourth signal Sp- through the third node net3 and the fourth node net4. The second input unit 122 is used to perform a fourth comparison on the third signal Sn- and the fourth signal Sp- to provide signals to the seventh node net7 and the eighth node net8. No current flows through the first input unit 112.

[0139] When the data signal DQ1 received by the previous stage data receiving circuit 100 is at logic level 0, the data signal DQ2 received by the next stage data receiving circuit 100 will fall into the following two categories:

[0140] Scenario 3: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 0, the difference in level between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is small, indicating minimal or no inter-symbol interference. In this case, the first amplification module 101 in the next-stage data receiving circuit 100 performs a second comparison and outputs the third signal Sn- and the fourth signal Sp-, causing the second input unit 122 to be turned on. That is, the second amplification module 102 in the next-stage data receiving circuit 100 receives the third signal Sn- and the fourth signal Sp-.

[0141] Scenario 4: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 1, the level difference between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is large, resulting in significant inter-symbol interference. In this case, the first amplification module 101 in the next-stage data receiving circuit 100 performs a second comparison and outputs the third signal Sn- and the fourth signal Sp-, which turns on the second input unit 122. That is, the second amplification module 102 in the next-stage data receiving circuit 100 receives the third signal Sn- and the fourth signal Sp-. At this time, in the next-stage data receiving circuit 100, the data signal DQ2 is at logic level 1, and the voltage difference between the data signal DQ2 and the second reference signal VR- is greater than the voltage difference between the data signal DQ2 and the first reference signal VR+. If the first comparison can be performed at this time, the difference in the level value of the effective second signal pair obtained by the second comparison is greater than the difference in the level value of the effective first signal pair obtained by the first comparison. At this time, the second amplification module 102 receiving the effective second signal pair is more conducive to outputting the first output signal Vout and the second output signal VoutN with higher accuracy, so as to reduce the impact of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100. Moreover, not performing the first comparison at this time is conducive to reducing the power consumption of the data receiving circuit 100.

[0142] Table 1

[0143]

[0144] When there is no need to consider the impact of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is low. At this time, the first NMOS transistor MN1 and the third NMOS transistor MN3 are both turned off. The first amplification module 101 performs the first comparison and outputs the first signal Sn+ and the second signal Sp+. The first input unit 112 responds to the first signal pair to turn on or off. At this time, the third signal Sn- and the fourth signal Sp- output by the second comparison circuit 121 are both logic low level signals, causing the second input unit 122, which responds to the third signal Sn- and the fourth signal Sp-, to turn off.

[0145] It should be noted that in the above descriptions of high and low levels, a high level can be a voltage level greater than or equal to the power supply voltage, and a low level can be a voltage level less than or equal to the ground voltage. Furthermore, high and low levels are relative terms, and the specific range of voltage levels they encompass can be determined based on the specific device. For example, for an NMOS transistor, a high level refers to the range of gate voltage levels that enable the NMOS transistor to conduct, and a low level refers to the range of gate voltage levels that enable the NMOS transistor to turn off. For a PMOS transistor, a low level refers to the range of gate voltage levels that enable the PMOS transistor to conduct, and a high level refers to the range of gate voltage levels that enable the PMOS transistor to turn off. Additionally, a high level can be logic level 1 as described above, and a low level can be logic level 0 as described above.

[0146] In summary, the first amplification module 101 is further controlled by the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn, so as to select whether to consider the impact of intersymbol interference of the data received by the data receiving circuit 100 on the data receiving circuit 100. For example, when it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit 100, even when the enable signal EnDfe is at the first level value, the first amplification module 101 responds to the sampling clock signal clkN and uses the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 to select one of the first comparison and the second comparison, so that one of the output first signal pair and the second signal pair is valid and the other is invalid, and the signal level difference in the valid signal pair is greater, so as to ensure that the second amplification module 102 receives a pair of differential signals with a greater difference in signal level. In addition, the low on-resistance of the NMOS transistors is used to avoid the first amplification module 101 from performing the first comparison and the second comparison at the same time, and to improve the processing effect and processing speed of the first amplification module 101 on the data signal DQ. When it is not necessary to consider the impact of inter-symbol interference on the data receiving circuit 100, when the enable signal EnDfe is at the second level value, the first amplification module 101 responds to the sampling clock signal clkN to perform only the first comparison and fixes the output of the valid first signal pair, so as to reduce the power consumption of the data receiving circuit 100.

[0147] Another embodiment of this disclosure also provides a data receiving system, which will be described in detail below with reference to the accompanying drawings. Figure 9 A functional block diagram of a data receiving system provided in another embodiment of this disclosure.

[0148] refer to Figure 9The data receiving system includes: multiple cascaded data transmission circuits 120, each data transmission circuit 120 including a data receiving circuit 100 as described in an embodiment of the present disclosure and a latching circuit 110 connected to the data receiving circuit 100; the output signal of the previous level data transmission circuit 120 serves as the feedback signal fb of the next level data transmission circuit 120; the output signal of the last level data transmission circuit 120 serves as the feedback signal fb of the first level data transmission circuit 120.

[0149] The latch circuit 110 is configured to correspond one-to-one with the data receiving circuit 100. The latch circuit 110 is used to latch and output the signal output by the data receiving circuit 100 corresponding to the latch circuit 110.

[0150] In some embodiments, the data receiving circuit 100 receives data in response to a sampling clock signal; and the data receiving system includes four cascaded data receiving circuits 100, with a 90° phase difference between the sampling clock signals clkN of adjacent data receiving circuits 100. Thus, the period of the sampling clock signal clkN is twice the period of the data signal DQ received by the data port, which is beneficial for clock routing and saves power consumption.

[0151] It should be noted that, Figure 9 The Sino-Israeli data receiving system includes four cascaded data receiving circuits 100. Taking the phase difference of the sampling clock signals of adjacent data receiving circuits 100 as an example, the number of cascaded data receiving circuits 100 included in the data receiving system is not limited in practical applications. The phase difference of the sampling clock signals of adjacent data receiving circuits 100 can be reasonably set based on the number of cascaded data receiving circuits 100.

[0152] In some embodiments, the first output signal Vout and the second output signal VoutN output by the second amplification module 102 of the preceding data receiving circuit 100 are used as the feedback signal fb of the following data receiving circuit 100. In this way, the output of the data receiving circuit 100 is directly transmitted to the next-stage data transmission circuit 120 without passing through the latch circuit 110, which helps to reduce the data transmission delay; or, the signal output by the latch circuit 110 of the preceding stage is used as the feedback signal fb of the following data receiving circuit 100.

[0153] In summary, the data receiving system provided in another embodiment of this disclosure can use the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn to further control the first amplification module 101, so as to select whether to consider the influence of inter-symbol interference of the data received by the data receiving circuit 100 on the data receiving circuit 100. For example, when it is necessary to reduce the impact of inter-symbol interference on the data receiving circuit 100, even when the enable signal EnDfe is at the first level value, the first amplification module 101 responds to the sampling clock signal clkN and selects to perform a first comparison or a second comparison based on the first feedback signal fbp and the second feedback signal fbn, so that one of the first signal pair and the second signal pair is valid and the other is invalid, and the signal level difference in the valid signal pair is greater, so as to ensure that the second amplification module 102 receives a pair of differential signals with a greater difference in signal level value. In addition, the low on-resistance of the NMOS transistor is used to avoid the first amplification module 101 performing the first comparison and the second comparison at the same time, and to improve the processing effect and processing speed of the first amplification module 101 on the data signal DQ. When it is not necessary to consider the impact of inter-symbol interference on the data receiving circuit 100, when the enable signal EnDfe is at the second level value, the first amplification module 101 responds to the sampling clock signal clkN and only performs the first comparison, fixing the output of the valid first signal pair, so as to reduce the power consumption of the data receiving circuit 100.

[0154] Another embodiment of this disclosure provides a storage device, including: a plurality of data ports; and a plurality of data receiving systems as described in any of the preceding claims, each of the data receiving systems corresponding to one of the data ports. Thus, when it is necessary to reduce the impact of inter-symbol interference on the storage device, each data port in the storage device can flexibly adjust the received data signal DQ through the data receiving system, and improve the adjustment capability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the storage device; when the impact of inter-symbol interference on the storage device does not need to be considered, during the period when the enable signal EnDfe is at the second level value, the first amplification module 101 responds to the sampling clock signal clkN by only performing a first comparison and fixedly outputting a valid first signal pair, thereby reducing the power consumption of the storage device.

[0155] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A data receiving circuit, characterized in that, include: A first amplification module is configured to receive an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal, and a second reference signal. During a period when the enable signal has a first level value, in response to a sampling clock signal and based on the first feedback signal, it selects the data signal and the first reference signal to perform a first comparison and outputs a first signal pair as the result of the first comparison; or, in response to the sampling clock signal and based on the second feedback signal, it selects the data signal and the second reference signal to perform a second comparison and outputs a second signal pair as the result of the second comparison. During the period when the enable signal has a second level value, the first comparison is performed in response to the sampling clock signal and the first signal pair is output; the first feedback signal has the opposite level to the second feedback signal, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal; The first amplification module includes: an amplification unit having a first node, a second node, a third node, and a fourth node, wherein the first node outputs the first signal, the second node outputs the second signal, the third node outputs the third signal, and the fourth node outputs the fourth signal, configured to receive the data signal, the first reference signal, and the second reference signal; a first NMOS transistor and a second NMOS transistor, wherein one end of the first NMOS transistor is connected to the first node, the other end of the first NMOS transistor is connected to one end of the second NMOS transistor, and the other end of the second NMOS transistor is connected to the second node, wherein the gate of one of the first NMOS transistor and the second NMOS transistor receives a first complementary feedback signal, and the gate of the other NMOS transistor receives the enable signal, wherein the level of the first complementary feedback signal is opposite to that of the first feedback signal; a third NMOS transistor and a fourth NMOS transistor, wherein one end of the third NMOS transistor is connected to the third node, the other end of the third NMOS transistor is connected to one end of the fourth NMOS transistor, and the other end of the fourth NMOS transistor is connected to the fourth node, wherein the gate of one of the third NMOS transistor and the fourth NMOS transistor receives a second complementary feedback signal, and the gate of the other NMOS transistor receives the enable signal, wherein the level of the second complementary feedback signal is opposite to that of the second feedback signal; The second amplification module is configured to receive the output signal of the first amplification module as an input signal pair, amplify the voltage difference of the input signal pair, and output a first output signal and a second output signal as the result of the amplification process.

2. The data receiving circuit as described in claim 1, characterized in that, The first amplification module also includes: A fifth NMOS transistor and a sixth NMOS transistor are provided. One end of the fifth NMOS transistor is connected to the first node, and the other end of the fifth NMOS transistor is connected to one end of the sixth NMOS transistor. The other end of the sixth NMOS transistor is connected to the second node. The gate of one of the fifth NMOS transistors and the sixth NMOS transistor receives the first complementary feedback signal, and the gate of the other NMOS transistor receives the enable signal.

3. The data receiving circuit as described in claim 2, characterized in that, The gate of the first NMOS transistor receives the enable signal, and the gate of the second NMOS transistor receives the first complementary feedback signal, wherein the channel width of the first NMOS transistor is greater than the channel width of the second NMOS transistor; the gate of the fifth NMOS transistor receives the first complementary feedback signal, and the gate of the sixth NMOS transistor receives the enable signal, wherein the channel width of the fifth NMOS transistor is less than the channel width of the sixth NMOS transistor.

4. The data receiving circuit as described in claim 2, characterized in that, The channel width of the fifth NMOS transistor is equal to the channel width of the second NMOS transistor; the channel width of the sixth NMOS transistor is equal to the channel width of the first NMOS transistor; the channel lengths of the first NMOS transistor, the second NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all equal.

5. The data receiving circuit as described in claim 1, characterized in that, The first amplification module also includes: A seventh NMOS transistor and an eighth NMOS transistor are provided. One end of the seventh NMOS transistor is connected to the third node, and the other end of the seventh NMOS transistor is connected to one end of the eighth NMOS transistor. The other end of the eighth NMOS transistor is connected to the fourth node. The gate of one of the seventh NMOS transistors and the eighth NMOS transistor receives the second complementary feedback signal, and the gate of the other NMOS transistor receives the enable signal.

6. The data receiving circuit as described in claim 5, characterized in that, The gate of the third NMOS transistor receives the enable signal, and the gate of the fourth NMOS transistor receives the second complementary feedback signal, wherein the channel width of the third NMOS transistor is greater than the channel width of the fourth NMOS transistor; the gate of the seventh NMOS transistor receives the second complementary feedback signal, and the gate of the eighth NMOS transistor receives the enable signal, wherein the channel width of the seventh NMOS transistor is less than the channel width of the eighth NMOS transistor.

7. The data receiving circuit as described in claim 5, characterized in that, The channel width of the seventh NMOS transistor is equal to the channel width of the fourth NMOS transistor; the channel width of the eighth NMOS transistor is equal to the channel width of the third NMOS transistor; the channel lengths of the third NMOS transistor, the fourth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all equal.

8. The data receiving circuit as described in claim 1, characterized in that, The sampling clock signal includes a first sampling clock signal and a second sampling clock signal; the amplification unit includes: A first comparison circuit, having the first node and the second node, is configured to receive the data signal and the first reference signal and perform the first comparison in response to the first sampling clock signal; A clock generation circuit is configured to receive the enable signal and the original sampling clock signal, and output the second sampling clock signal, wherein, during the period when the enable signal has the first level value, the phase of the second sampling clock signal is opposite to the phase of the original sampling clock signal, and during the period when the enable signal has the second level value, the second sampling clock signal is a logic high level signal. The second comparison circuit, having the third node and the fourth node, is configured to receive the data signal and the second reference signal, and to perform the second comparison in response to the second sampling clock signal during the period when the enable signal has the first level value; and to enable the connection path between the third node and ground during the period when the enable signal has the second level value, and to enable the connection path between the fourth node and ground.

9. The data receiving circuit as described in claim 8, characterized in that, The first comparator circuit includes: A first current source is configured to be connected between the power supply node and the fifth node, and to provide current to the fifth node in response to the first sampling clock signal; The first comparison unit, connected to the first node, the second node, and the fifth node, is configured to receive the data signal and the first reference signal, perform the first comparison when the first current source provides current to the fifth node, and output the first signal and the second signal. A first reset unit, connected to the first node and the second node, is configured to reset the first node and the second node in response to the first sampling clock signal; The second comparator circuit includes: A second current source is configured to be connected between the power supply node and the sixth node, and to provide current to the sixth node in response to the second sampling clock signal; The second comparison unit, connected to the third node, the fourth node, and the sixth node, is configured to receive the data signal and the second reference signal, perform the second comparison when the second current source provides current to the sixth node, and output the third signal and the fourth signal. A second reset unit, connected between the third node and the fourth node, is configured to reset the third node and the fourth node in response to the second sampling clock signal.

10. The data receiving circuit as described in claim 9, characterized in that, The first current source includes: A first PMOS transistor is connected between the power supply node and the fifth node, and the gate of the first PMOS transistor receives the first sampling clock signal. The second current source includes: A second PMOS transistor is connected between the power supply node and the sixth node, and the gate of the second PMOS transistor receives the second sampling clock signal.

11. The data receiving circuit as described in claim 9, characterized in that, The first comparison unit includes: A third PMOS transistor is connected between the first node and the fifth node, and the gate of the third PMOS transistor receives the data signal. A fourth PMOS transistor is connected between the second node and the fifth node, and the gate of the fourth PMOS transistor receives the first reference signal; The second comparison unit includes: A fifth PMOS transistor is connected between the third node and the sixth node, and the gate of the fifth PMOS transistor receives the data signal. A sixth PMOS transistor is connected between the fourth node and the sixth node, and the gate of the sixth PMOS transistor receives the second reference signal.

12. The data receiving circuit as described in claim 9, characterized in that, The first reset unit includes: The ninth NMOS transistor is connected between the first node and ground, and its gate receives the first sampling clock signal; The tenth NMOS transistor is connected between the second node and the ground terminal, and its gate receives the first sampling clock signal; The second reset unit includes: The eleventh NMOS transistor is connected between the third node and ground, and its gate receives the second sampling clock signal. The twelfth NMOS transistor is connected between the fourth node and ground, and its gate receives the second sampling clock signal.

13. The data receiving circuit as described in claim 8, characterized in that, The clock generation circuit includes: The first NAND gate circuit has one input terminal receiving the original sampling clock signal, another input terminal connected to a power supply node, and an output terminal outputting the first sampling clock signal.

14. The data receiving circuit as described in claim 8, characterized in that, The clock generation circuit includes: The second NAND gate circuit has one input terminal receiving the original sampling clock signal, another input terminal receiving the enable signal, and an output terminal outputting the second sampling clock signal.

15. The data receiving circuit as described in claim 1, characterized in that, The second amplification module includes: The first input unit, connecting the seventh node and the eighth node, is configured to receive the first signal pair and perform a third comparison, and provide signals to the seventh node and the eighth node respectively as the result of the third comparison; The second input unit, connecting the seventh node and the eighth node, is configured to receive the second signal pair and perform a fourth comparison, and provide signals to the seventh node and the eighth node respectively as the result of the fourth comparison; The latching unit, connected to the seventh node and the eighth node, is configured to amplify and latch the signals of the seventh node and the eighth node, and output the first output signal and the second output signal through the first output node and the second output node, respectively.

16. The data receiving circuit as described in claim 15, characterized in that, The first input unit includes: The thirteenth NMOS transistor has its drain connected to the seventh node, its source connected to ground, and its gate receiving the first signal. The fourteenth NMOS transistor has its drain connected to the eighth node, its source connected to ground, and its gate receiving the second signal. The second input unit includes: The fifteenth NMOS transistor has its drain connected to the seventh node, its source connected to ground, and its gate receiving the third signal. The sixteenth NMOS transistor has its drain connected to the eighth node, its source connected to ground, and its gate receiving the fourth signal.

17. The data receiving circuit as described in claim 15, characterized in that, The latch unit includes: The seventeenth NMOS transistor and the seventh PMOS transistor are connected to the second output node, the source of the seventeenth NMOS transistor is connected to the seventh node, the drain of the seventeenth NMOS transistor and the drain of the seventh PMOS transistor are connected to the first output node, and the source of the seventh PMOS transistor is connected to the power supply node. The eighteenth NMOS transistor and the eighth PMOS transistor are connected to the first output node, the source of the eighteenth NMOS transistor is connected to the eighth node, the drain of the eighteenth NMOS transistor and the drain of the eighth PMOS transistor are connected to the second output node, and the source of the eighth PMOS transistor is connected to the power supply node.

18. The data receiving circuit as described in claim 17, characterized in that, The second amplification module also includes: The third reset unit, connected between the power supply node and the output of the latch unit, is configured to reset the output of the latch unit.

19. The data receiving circuit as described in claim 18, characterized in that, The third reset unit includes: The ninth PMOS transistor is connected between the first output node and the power supply node, and the gate of the ninth PMOS transistor receives the original sampling clock signal. The tenth PMOS transistor is connected between the second output node and the power supply node, and the gate of the tenth PMOS transistor receives the original sampling clock signal.

20. The data receiving circuit as described in claim 1, characterized in that, Also includes: The first inverting circuit is configured to receive the first feedback signal and output the first complementary feedback signal. The second inverting circuit is configured to receive the second feedback signal and output the second complementary feedback signal.

21. The data receiving circuit as described in claim 20, characterized in that, The first inverting circuit includes a first inverter; the second inverting circuit includes a second inverter.

22. The data receiving circuit as described in claim 20, characterized in that, The first inverter circuit includes a third NAND gate, whose two inputs receive the first feedback signal and the enable signal respectively, and whose output outputs the first complementary feedback signal; the second inverter circuit includes a fourth NAND gate, whose two inputs receive the second feedback signal and the enable signal respectively, and whose output outputs the second complementary feedback signal.

23. A data receiving system, characterized in that, include: Multiple cascaded data transmission circuits, each of the data transmission circuits including a data receiving circuit as described in any one of claims 1-22 and a latching circuit connected to the data receiving circuit; The output signal of the data transmission circuit described in the previous stage serves as the feedback signal of the data transmission circuit described in the next stage. The output signal of the final stage data transmission circuit serves as the feedback signal of the first stage data transmission circuit.

24. The data receiving system as described in claim 23, characterized in that, The data receiving circuit receives data in response to a sampling clock signal; and the data receiving system includes four cascaded data transmission circuits, with a 90° phase difference between the sampling clock signals of adjacent data receiving circuits.

25. The data receiving system as described in claim 23, characterized in that, The first output signal and the second output signal output by the second amplification module of the previous stage data receiving circuit serve as the feedback signal of the next stage data receiving circuit. Alternatively, the signal output by the latch circuit of the preceding stage can be used as the feedback signal of the data receiving circuit of the following stage.

26. A storage device, characterized in that, include: Multiple data ports; Multiple data receiving systems as described in any one of claims 23 to 25, each of the data receiving systems corresponding to one of the data ports.

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