A Polarized Superjunction Gallium Oxide Device Structure and Its Manufacturing Method

Abstract

The present invention relates to the technical field of semiconductor devices, and particularly relates to a polarized superjunction gallium oxide device structure and a manufacturing method thereof. A GaN / Al x Ga 1‑x N / β-Ga2O3 heterojunction is fabricated in the channel region of the polarized superjunction gallium oxide device structure. The GaN / Al x Ga 1‑x N / β-Ga2O3 heterojunction is formed by sequentially stacking an unintentionally doped β-Ga2O3 epitaxial layer, an Al x Ga 1‑x N layer, and an unintentionally doped GaN layer, where 0.1 ≤ x ≤ 0.3. By forming a GaN / Al x Ga 1‑x N / β-Ga2O3 heterojunction in the channel region, a polarized superjunction (PSJ) structure is introduced. 2DHG and polarized negative charges are formed at the GaN / Al x Ga 1‑x N heterojunction interface. Polarized positive charges and 2DEG are formed at the Al x Ga 1‑x N / β-Ga2O3 heterojunction interface. When the device is in the off state, 2DHG and 2DEG are respectively discharged from the gate and the drain, leaving only the polarized fixed negative charges and positive charges on the upper and lower interfaces of the Al x Ga 1‑x N layer. The electric field intensity in the entire PSJ region becomes uniform, and the electric field between the drain and the gate can be evenly distributed, thereby alleviating the electric field concentration phenomenon at the gate edge, improving the breakdown voltage of the HEMT device while also improving the heat dissipation performance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a polarized superjunction gallium oxide device structure and a manufacturing method thereof. Background Art

[0002] The electric field distribution in a uniform channel is the main idea and method for improving the breakdown voltage of Ga2O3-based HEMT devices. Currently, the commonly used method is the field plate (FP) technology, that is, depositing metal on the passivation layer between the gate and the drain. Since the potential of the metal layer is different from that of the space charge region, a longitudinal electric field perpendicular to the surface will be generated between the two, improving the bending degree of the electric field at the gate edge, reducing the concentration degree of the power lines, and making the electric field more evenly distributed. This method has the following problems:

[0003] (1) The field plate formed on the gate can suppress the electric field concentration to a certain extent, but it is difficult to completely eliminate it;

[0004] (2) The FP process in the chip manufacturing process is relatively complex, which will bring problems in terms of cost and production efficiency;

[0005] (3) The strong electric field near the gate makes the high heat generation phenomenon there more severe, and the extremely poor thermal conductivity of the gallium oxide material (thermal conductivity is about 0.27 W / (cm·K)) further increases the heat dissipation challenge of the device. Summary of the Invention

[0006] Based on the above description, the present invention provides a polarized superjunction gallium oxide device structure, which can at least solve one of the problems in the background art.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: A polarized superjunction gallium oxide device structure, in which a GaN / Al x Ga 1-x N / β-Ga2O3 heterojunction is fabricated in the channel region of the device structure, and the GaN / Al x Ga 1-x N / β-Ga2O3 heterojunction is formed by successively stacking an unintentionally doped β-Ga2O3 epitaxial layer, an Al x Ga 1-x N layer and an unintentionally doped GaN layer, where 0.1 ≤ x ≤ 0.3.

[0008] As a preferred embodiment, the polarized superjunction gallium oxide device structure further includes being fabricated on the Al x Ga 1-xSource electrodes, gate electrodes, drain electrodes, and trenches on the N layer, where the gate electrodes, trenches, and GaN layer are all located between the source electrodes and the drain electrodes and have the same extending direction. The trenches are opened adjacent to the edge of the GaN layer near the source region side, and one side of the GaN layer adjacent to the trenches is inclined towards the trenches to form an inclined surface. A P-type material is deposited on the trenches and the inclined surface, and the gate electrode is fabricated at least on the P-type material and Al x Ga 1-x N layer.

[0009] As a preferred implementation, the gate electrode is fabricated at least on the Al x Ga 1-x upper surface of the N layer, the side surface and the upper surface of the P-type material away from the GaN.

[0010] As a preferred implementation, the P-type material includes but is not limited to p-GaN, p-type oxides, and p-type diamond.

[0011] As a preferred implementation, the polarization superjunction gallium oxide device structure further includes an insulating substrate.

[0012] As a preferred implementation, the insulating substrate includes but is not limited to a gallium oxide substrate, SiC, Si, and sapphire.

[0013] As a preferred implementation, the height of the P-type material is the same as the height of the unintentionally doped GaN layer.

[0014] As a preferred implementation, the Al x Ga 1-x N layer is a silicon-doped Al x Ga 1-x N layer.

[0015] The present invention also provides a preparation method of the above polarization superjunction gallium oxide device structure, including the following steps:

[0016] Epitaxially grow an unintentionally doped β-Ga2O3 epitaxial layer, an Al x Ga 1-x N layer, and an unintentionally doped GaN layer on the insulating substrate in sequence. Subsequently, etch both sides of the GaN layer to the AlGaN surface, and the etched regions serve as the source region and the drain region of the device;

[0017] Deposit a layer of dielectric on the surface of the Al x Ga 1-x N layer and the GaN layer and selectively etch the dielectric layer to expose a part of the Al x Ga 1-x N and a part of the GaN. Using this dielectric layer as a mask, etch the exposed Al x Ga 1-xN and GaN, the etched Al x Ga 1-x The N part forms a groove, and the etched GaN part forms an inclined plane;

[0018] Grow P-type material at the groove and inclined plane positions, remove the dielectric layer, fabricate a source electrode in the source region, fabricate a drain electrode in the drain region, and fabricate a gate electrode on the Al x Ga 1-x N surface and the P-type material.

[0019] Compared with the prior art, the present invention has at least the following beneficial technical effects:

[0020] (1) By forming a GaN / Al x Ga 1-x N / β-Ga2O3 heterojunction in the channel region, introducing a polarization superjunction (PSJ) structure, two-dimensional hole gas (2DHG) and polarization negative charges are formed at the GaN / Al x Ga 1-x N heterojunction interface, and polarization positive charges and two-dimensional electron gas (2DEG) are formed at the Al x Ga 1-x N / β-Ga2O3 heterojunction interface. When the device is in the off state, the 2DHG and 2DEG are respectively discharged from the gate and the drain, leaving only the polarization fixed negative charges and positive charges on the upper and lower interfaces of the Al x Ga 1-x N layer. The electric field intensity in the entire PSJ region becomes uniform, and the electric field between the drain and the gate can be evenly distributed, thereby alleviating the electric field concentration phenomenon at the gate edge and improving the breakdown voltage of the HEMT device;

[0021] (2) Etch part of the Al x Ga 1-x N to form a groove, etch part of the GaN to form an inclined plane, grow P-type material in the groove to realize an enhancement-mode HEMT device; grow P-type material on the sidewall of GaN to provide holes for the formation of 2DHG, and when charging / discharging the 2DHG, the holes always move in the horizontal direction, ensuring the hole mobility and improving the device switching speed;

[0022] (3) The heat dissipation coefficient of the GaN material is better than that of Ga2O3, and the thermal conductivity of GaN is 8 times that of Ga2O3, which can improve the heat dissipation performance and device reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic longitudinal cross-sectional structure diagram of a polarization superjunction gallium oxide device structure provided by an embodiment of the present invention;

[0024] Figure 2 is Figure 1Electric field situation in the PSJ region when the device is in the off state;

[0025] Figure 3 Process flow chart of a polarized superjunction gallium oxide device structure provided by an embodiment of the present invention; In the drawings, the list of components represented by each reference numeral is as follows:

[0026] 1 β-Ga2O3 epitaxial layer, 2Al x Ga 1-x N layer, 3 GaN layer, 4 source electrode, 5 drain electrode, 6 gate electrode, 7 P-type material, 8 substrate. Detailed implementation manners

[0027] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0028] It should be noted that in the description of the present application, the description of the drawings and embodiments is illustrative rather than restrictive, and the same reference numerals throughout the embodiments of the specification identify the same structures. In addition, for the sake of understanding and easy description, some layers, films, panels, regions, etc. may be exaggerated in thickness in the drawings. In addition, "on" means positioning an element on or below another element, but essentially does not mean positioning on the upper side of another element according to the direction of gravity. The orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application.

[0029] As Figure 1 shown, a polarized superjunction gallium oxide device structure, the main difference between this polarized superjunction gallium oxide device structure and the prior art is that a GaN / Al x Ga 1-x N / β-Ga2O3 heterojunction is fabricated in the channel region. Specifically, this heterojunction is formed by an unintentionally doped β-Ga2O3 epitaxial layer 1, an Al x Ga 1-x N layer 2 and an unintentionally doped GaN layer 3 stacked in sequence, where 0.1 ≤ x ≤ 0.3.

[0030] For the above-mentioned polarized superjunction gallium oxide device structure, by forming a GaN / Al x Ga 1-x N / β-Ga2O3 heterojunction in the channel region, 0.1 ≤ x ≤ 0.3, in Alx Ga 1-x 2DHG is generated near the GaN interface above GaN, and in Al x Ga 1-x 2DEG is generated near the Ga2O3 interface below GaN. When the device is in the off state, 2DHG and 2DEG are discharged, leaving only Al x Ga 1-x The polarization fixed negative charges and positive charges on the upper and lower interfaces of the GaN layer. The electric field intensity in the entire polarization superjunction (PSJ) region becomes uniform, and the electric field between the drain and the gate can be evenly distributed. See Figure 2 . By increasing the length of the PSJ part (corresponding to the channel length), the breakdown voltage can be increased. In addition, the heat dissipation coefficient of the GaN material is better than that of Ga2O3, which can improve the heat dissipation performance of the device. The device has a certain heat dissipation ability while having high breakdown voltage.

[0031] Furthermore, the device structure also includes a source electrode 3, a gate electrode 6, a drain electrode 5 and a trench fabricated on the Al x Ga 1-x N layer 2, where the gate electrode 6, the trench and the GaN layer 3 are located between the source electrode 3 and the drain electrode 5 and have the same extension direction. The trench is opened adjacent to the edge of the GaN near the source region, and the side of the GaN layer 3 adjacent to the trench is inclined towards the trench direction to form an inclined surface. A P-type material 7 is deposited on the trench and the inclined surface. The gate electrode 6 is fabricated at least on the P-type material 7 and the Al x Ga 1-x N layer.

[0032] By etching part of the Al x Ga 1-x N to form a trench and growing a P-type material in the trench, an enhancement-mode HEMT device can be realized. By etching part of the GaN to form an inclined surface and growing a P-type material on the sidewall of the GaN, holes are provided for the formation of 2DHG. When charging / discharging 2DHG, the holes always move in the horizontal direction, ensuring the hole mobility and improving the switching speed of the device.

[0033] Specifically, that is, the width of the GaN layer is less than that of the Al x Ga 1-x N layer. The two sides of the GaN layer are the source region and the drain region of the device respectively. The edge of the GaN layer near the source electrode has an inclined surface structure. The surface of this inclined surface structure and the trench opened on the Al x Ga 1-x N layer are simultaneously deposited with a P-type material. The gate electrode 6 is fabricated at least on the Al x Ga 1-x N layer, the side surface of the P-type material near the source electrode and the upper surface.

[0034] It can be understood that the gate electrode 6 can be fabricated simultaneously on the Alx Ga 1-x On the AlGaN layer, on the side surface of the P-type material close to the source electrode and on the upper surface, and on the upper surface of the unintentionally doped GaN layer, it can also be fabricated only on the AlGaN layer x Ga 1-x On the AlGaN layer, on the side surface of the P-type material close to the source electrode and on the upper surface.

[0035] In the present invention, the P-type material includes but is not limited to p-GaN, p-type oxide, p-type diamond, and preferably p-GaN, which has no lattice mismatch problem with the GaN layer 3.

[0036] In the present invention, the structure further includes an insulating substrate 8. Further, the substrate 8 includes but is not limited to a gallium oxide substrate, SiC, Si, and sapphire.

[0037] In the present invention, the height of the P-type material 7 is preferably the same as that of the unintentionally doped GaN layer.

[0038] Furthermore, silicon δ-doping of AlGaN can be carried out by metal-organic chemical vapor deposition (MOCVD), which can increase the density of 2DEG. x Ga 1-x N to increase the density of 2DEG.

[0039] In the present invention, the β-Ga2O3 epitaxial layer 1 is an unintentionally doped gallium oxide epitaxial layer, the GaN layer 3 is an unintentionally doped gallium nitride layer, and the AlGaN layer 2 is a silicon-doped AlGaN layer. x Ga 1-x N layer 2 is a silicon-doped AlGaN layer. x Ga 1-x N layer.

[0040] The present invention also provides a method for preparing the above-mentioned polarization superjunction gallium oxide device structure, including the following steps:

[0041] Epitaxially grow an unintentionally doped β-Ga2O3 epitaxial layer 1, an AlGaN layer 2, and an unintentionally doped GaN layer 3 in sequence on the insulating substrate 8, and then etch both sides of the GaN layer 3 to the AlGaN surface, and the etched area serves as the source region and the drain region of the device; x Ga 1-x N layer 2 and the unintentionally doped GaN layer 3, and then etch both sides of the GaN layer 3 to the AlGaN surface, and the etched area serves as the source region and the drain region of the device;

[0042] Deposit a layer of dielectric on the surface of the AlGaN layer 2 and the GaN layer 3 and selectively etch the dielectric layer to expose a part of the AlGaN and a part of the GaN on the side close to the source region, and use this dielectric layer as a mask to etch the exposed AlGaN and GaN, and the etched AlGaN and GaN x Ga 1-x N layer 2 and the GaN layer 3, and then selectively etch the dielectric layer to expose a part of the AlGaN and a part of the GaN on the side close to the source region, and use this dielectric layer as a mask to etch the exposed AlGaN and GaN, and the etched AlGaN and GaN x Ga 1-x N and part of the GaN, and use this dielectric layer as a mask to etch the exposed AlGaN and GaN, and the etched AlGaN and GaN x Ga 1-x N and GaN, and the etched AlGaN and GaN x Ga 1-xThe N part forms a groove, and the etched GaN part forms an inclined plane;

[0043] At the groove and inclined plane positions, a P-type material 7 is grown, the dielectric layer is removed, a source electrode is fabricated in the source region, a drain electrode is fabricated in the drain region, and a gate electrode is fabricated on the Al x Ga 1-x N surface and the P-type material.

[0044] The following further elaborates on the present invention with the preparation process of a specific implementation case. The process flow is shown in Figure 3 , specifically as follows:

[0045] (1) On the β-phase insulating gallium oxide substrate, a layer of unintentionally doped gallium oxide epitaxial layer is grown by hydride vapor phase epitaxy (HVPE). This unintentionally doped gallium oxide epitaxial layer serves as the channel layer;

[0046] (2) On the unintentionally doped gallium oxide epitaxial layer, an Al x Ga 1-x N layer is epitaxially grown by HVPE or metalorganic chemical vapor deposition (MOCVD). Polarized positive charges and 2DEG are formed at the Al x Ga 1-x N / β-Ga2O3 heterojunction interface. The thickness of the Al x Ga 1-x N layer is 20 - 50 nm, and the Al component is 10 - 30%;

[0047] (3) On the Al x Ga 1-x N layer, a layer of unintentionally doped gallium nitride epitaxial layer is grown by MOCVD. 2DHG and polarized negative charges are formed at the GaN / Al x Ga 1-x N heterojunction interface. The thickness of the GaN layer is 10 - 30 nm. Subsequently, the GaN layers on both sides of the cell are selectively etched to the Al x Ga 1-x N surface. The etched area serves as the source and drain regions of the device;

[0048] (4) Using chemical vapor deposition (CVD), a dielectric layer is deposited on the Al x Ga 1-x N and GaN surfaces and the dielectric layer is selectively etched to expose a part of the Al x Ga 1-x N and a part of the GaN. Subsequently, using this dielectric layer as a mask, the exposed Al x Ga 1-x N and GaN are etched. By controlling the etching process with dry etching and wet etching, part of the Al x Ga 1-xN forms a groove, and part of the GaN is etched away to form an inclined plane;

[0049] (5) Grow p-GaN material in the etched area, Al x Ga 1-x The p-GaN in the N groove can deplete the electrons below to achieve enhancement. The p-GaN on the sidewalls of GaN provides holes for the unintentionally doped GaN, which is beneficial to the formation of 2DHG. At the same time, when 2DHG fills and discharges, the holes always move in the horizontal direction, ensuring the hole mobility and improving the device switching speed. Then, remove Al x Ga 1-x N and the dielectric material on the GaN surface;

[0050] (6) Deposit source and drain metals, perform metal lift-off and ohmic annealing to form source and drain electrodes, deposit gate metal, and perform lift-off to form gate electrodes.

[0051] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A polarized superjunction gallium oxide device structure, characterized in that, The channel region of the device structure is fabricated with GaN / Al x Ga 1-x N / β-Ga2O3 heterojunction. The GaN / Al x Ga 1-x N / β-Ga2O3 heterojunction is formed by successively stacking an unintentionally doped β-Ga2O3 epitaxial layer, an Al x Ga 1-x N layer, and an unintentionally doped GaN layer, where 0.1 ≤ x ≤ 0.

3.

2. The polarized superjunction gallium oxide device structure according to claim 1, characterized in that, It also includes a source electrode, a gate electrode, a drain electrode, and a trench fabricated on the Al x Ga 1- x N layer. The gate electrode, the trench, and the GaN layer are all located between the source electrode and the drain electrode and have the same extending direction. The trench is opened adjacent to the edge of the GaN layer close to the source region, and one side of the GaN layer adjacent to the trench is inclined towards the trench direction to form an inclined surface. A P-type material is deposited on the trench and the inclined surface. The gate electrode is fabricated at least on the P-type material and the Al x Ga 1-x N layer.

3. The polarized superjunction gallium oxide device structure according to claim 2, wherein, The gate electrode is fabricated at least on the upper surface of the Al x Ga 1-x N layer, the side surface and the upper surface of the P-type material away from the GaN.

4. The polarized superjunction gallium oxide device structure according to claim 2 or 3, characterized in that, The P-type material is any one of p-GaN, p-type oxide, and p-type diamond.

5. The polarized superjunction gallium oxide device structure according to any one of claims 1 to 3, characterized in that, It further includes an insulating substrate.

6. The polarization superjunction gallium oxide device structure according to claim 5, wherein The insulating substrate is any one of a gallium oxide substrate, SiC, Si, and sapphire.

7. The polarization superjunction gallium oxide device structure according to claim 2 or 3, characterized in that, The height of the P-type material is consistent with the height of the unintentionally doped GaN layer.

8. The polarized superjunction gallium oxide device structure according to any one of claims 1 to 3, characterized in that, The Al x Ga 1- x The N layer is a silicon-doped Al x Ga 1-x N layer.

9. The preparation method of the polarized superjunction gallium oxide device structure according to any one of claims 1 to 8, characterized in that, It includes the following steps: An unintentionally doped β-Ga2O3 epitaxial layer and Al are sequentially epitaxially grown on an insulating substrate x Ga 1-x N layer and an unintentionally doped GaN layer, and then both sides of the GaN layer are etched to the AlGaN surface, and the etched regions serve as the source and drain regions of the device; On Al x Ga 1-x Deposit a layer of dielectric on the surface of the AlGaN layer and selectively etch the dielectric layer to expose a part of the AlGaN near the source region x Ga 1-x and a part of the GaN. Using this dielectric layer as a mask, etch the exposed AlGaN x Ga 1-x and GaN. The etched AlGaN part forms a groove, and the etched GaN part forms an inclined plane; x Ga 1- x The etched AlGaN part forms a groove, and the etched GaN part forms an inclined plane; Grow P-type material at the groove and bevel positions, remove the dielectric layer, fabricate a source electrode in the source region, fabricate a drain electrode in the drain region, and fabricate a gate electrode on the Al x Ga 1-x N surface and the P-type material.

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