Electronic device and display driving method

Abstract

The electronic device and the display driving method provided by the embodiments of the present disclosure include a plurality of device groups and a plurality of driving elements; a first end of at least one device group in the plurality of device groups is coupled with a positive signal line, a second end of the at least one device group in the plurality of device groups is coupled with an output end of any one driving element in the plurality of driving elements, and a reference voltage end of any one driving element in the plurality of driving elements is configured to be coupled with a reference signal line; any one driving element in the plurality of driving elements is configured to: control the positive signal line and the reference voltage end thereof to form an electrical loop in a working time period of a light emitting period; and adjust the potential of the second end of the device group coupled therewith before the working time period of the light emitting period.

Description

Technical Field

[0001] This disclosure relates to the field of light-emitting technology, and in particular to electronic devices and display driving methods. Background Technology

[0002] Light-emitting diode (LED) display refers to the technology of arraying and miniaturizing traditional LEDs and then massively transferring them onto a circuit board to form ultra-small pitch LEDs. This further miniaturizes the length of LEDs from millimeters to micrometers to achieve ultra-high pixel count and ultra-high resolution, theoretically adaptable to screens of various sizes. Summary of the Invention

[0003] The electronic device provided in this disclosure includes:

[0004] Multiple device groups and multiple driving elements;

[0005] At least one of the plurality of device groups has its first terminal coupled to a positive signal line, and its second terminal is coupled to the output terminal of any one of the plurality of driving elements. The reference voltage terminal of any one of the plurality of driving elements is configured to be coupled to a reference signal line.

[0006] Any one of the plurality of driving elements is configured to: control the positive signal line and its reference voltage terminal to form an electrical circuit during the operating time period of one light emission cycle; and, before the operating time period of the light emission cycle, adjust the potential of the second terminal of the device group coupled thereto.

[0007] In some examples, any one of the plurality of driving elements is further configured to control the second terminal of the device group coupled thereto to conduct with its reference voltage terminal for a first compensation time before the operating time period.

[0008] In some examples, any one of the plurality of driving elements is further configured to: at the end of the first compensation time, control the positive signal line to form an electrical loop at least sequentially via a group of devices coupled to the driving element, the output terminal of the driving element, and the reference voltage terminal.

[0009] In some examples, any one of the plurality of driving elements is further configured to control the second terminal of the device group coupled thereto to conduct a second compensation time with its reference voltage terminal during the operating time period.

[0010] In some examples, the first compensation time and the second compensation time are consecutive time periods.

[0011] In some examples, for at least one of the plurality of device groups, the second compensation time corresponding to the device group is less than the first compensation time.

[0012] In some examples, for at least one of the plurality of device groups, the second compensation time corresponding to the device group is less than half of the first compensation time.

[0013] In some examples, the at least one device group includes multiple devices;

[0014] Each of the plurality of devices corresponds to a first compensation time and a second compensation time, and the second compensation time corresponding to each of the plurality of devices is less than half of the first compensation time.

[0015] In some examples, at least two of the plurality of devices correspond to different first compensation times; wherein the device with the larger first compensation time corresponds to a device with the larger second compensation time.

[0016] In some examples, at least some of the plurality of devices correspond to the same second compensation time.

[0017] In some examples, any one of the plurality of driving elements is further configured to: control the second terminal of the device group coupled to it to conduct the potential compensation time with its reference voltage terminal according to the pre-stored potential compensation time corresponding to the device group coupled to it; wherein the potential compensation time is the first compensation time; or, the potential compensation time is the sum of the first compensation time and the second compensation time.

[0018] In some examples, any one of the plurality of driving elements includes: a processing control circuit and a data driving circuit; the data driving circuit is coupled to the processing control circuit, the output terminal, and the reference voltage terminal, respectively.

[0019] The processing control circuit is configured to generate a light emission control signal during the light emission cycle and send the light emission control signal to the data driving circuit; and to generate a potential adjustment control signal according to the potential compensation time and send the potential adjustment control signal to the data driving circuit.

[0020] The data driving circuit is configured to, during the light emission cycle, control the positive signal line to sequentially form an electrical circuit via a device group coupled to the driving element, the output terminal of the driving element, and a reference voltage terminal according to the received light emission control signal; and control the second terminal of the corresponding device group to be connected to its reference voltage terminal according to the effective level of the received potential adjustment control signal; wherein the effective level duration of the potential adjustment control signal corresponding to the device group is the potential compensation time.

[0021] In some examples, the data driving circuit includes: at least one data driving sub-circuit; one of the data driving sub-circuits is coupled to one of the output terminals;

[0022] The data driving sub-circuit is configured to receive a light emission control signal and a potential adjustment control signal corresponding to the coupled device group, and, in response to the light emission control signal, control the positive signal line to form an electrical loop sequentially via the device group coupled to the driving element, the output terminal of the driving element, and the reference voltage terminal; and, in response to the potential adjustment control signal, control the second terminal of the coupled device group to be connected to its reference voltage terminal.

[0023] In some examples, the light emission control signal includes a drive control signal and a current control signal;

[0024] The data driving sub-circuit includes: a modulation circuit, a constant current source circuit, and a potential adjustment circuit; wherein, the constant current source circuit is coupled to the processing control circuit and the modulation circuit respectively, and the modulation circuit is coupled to the corresponding output terminal; the potential adjustment circuit is coupled to the processing control circuit and the corresponding output terminal respectively.

[0025] The constant current source circuit is configured to receive the current control signal of the corresponding device group, and output a current with a constant amplitude corresponding to the received current control signal.

[0026] The modulation circuit is configured to receive the drive control signal of the corresponding device group, and according to the effective level of the received drive control signal, to couple the current generated by the constant current source circuit to the output terminal, so as to control the positive signal line to form an electrical circuit at least sequentially through the device group coupled to the drive element, the output terminal of the drive element, and the reference voltage terminal during the working time period.

[0027] The potential adjustment circuit is configured to receive a potential adjustment control signal for the corresponding device group, and control the second terminal of the coupled device group to be connected to its reference voltage terminal according to the received potential adjustment control signal.

[0028] In some examples, the electronic device further includes: a control circuit; the control circuit is coupled to the plurality of driving elements respectively;

[0029] The control circuit is configured to store the potential compensation time of the device group corresponding to each of the coupled driving elements; and to send the potential compensation time of the device group corresponding to each of the driving elements to each driving element when the electronic device is powered on.

[0030] The driving element is configured to receive and store the potential compensation time sent by the system circuit when the electronic device is powered on, and to clear the stored potential compensation time when the electronic device is powered off.

[0031] In some examples, the drive signal terminal of any one of the plurality of drive elements is configured to be coupled to a drive signal line;

[0032] The control circuit is further configured to be coupled to the drive signal line and to store the addresses of each of the coupled drive elements; and to transmit drive data carrying the addresses of the corresponding drive elements to the drive signal line.

[0033] The driving element is further configured to receive the driving data and generate the light emission control signal based on the driving data when the corresponding address in the driving data is identified.

[0034] In some examples, the addressing signal terminal of any one of the plurality of driving elements is configured to be coupled to the addressing signal line;

[0035] The control circuit is also configured to be coupled to the address signal line and to input a power supply voltage to the address signal line;

[0036] The driving element is also configured to receive the supply voltage via the addressing signal terminal.

[0037] The display driving method provided in this disclosure is applied to an electronic device, which includes multiple device groups and multiple driving elements.

[0038] The display driving method includes:

[0039] The positive signal line and its reference voltage terminal are controlled to form an electrical circuit within the working time period of one light emission cycle;

[0040] Specifically, before the working time period of the light emission cycle, the potential of the second terminal of the device group coupled thereto is adjusted. Attached Figure Description

[0041] Figure 1 Some structural schematic diagrams of the electronic device provided in the embodiments of this disclosure;

[0042] Figure 2 Some structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0043] Figure 3 These are schematic diagrams of some partial structures of the display panel provided in embodiments of this disclosure;

[0044] Figure 4 These are some other partial structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0045] Figure 5 Further partial structural schematic diagrams of the display panel provided in embodiments of this disclosure;

[0046] Figure 6 These are schematic diagrams illustrating some layout structures of the display panel provided in embodiments of this disclosure;

[0047] Figure 7 for Figure 6 The schematic diagram of the layout structure shown is a cross-sectional view along the AA' direction;

[0048] Figure 8 Other structural schematic diagrams of the electronic device provided in the embodiments of this disclosure;

[0049] Figure 9 Some signal timing diagrams provided for embodiments of this disclosure;

[0050] Figure 10 Other signal timing diagrams provided for embodiments of this disclosure;

[0051] Figure 11 Further signal timing diagrams provided for embodiments of this disclosure;

[0052] Figure 12 Further signal timing diagrams provided for embodiments of this disclosure;

[0053] Figure 13 Some structural schematic diagrams of the driving element provided in the embodiments of this disclosure;

[0054] Figure 14 These are some partial structural schematic diagrams of the driving element provided in the embodiments of this disclosure;

[0055] Figure 15 Other partial structural schematic diagrams of the driving element provided in the embodiments of this disclosure;

[0056] Figure 16 Further signal timing diagrams provided for embodiments of this disclosure;

[0057] Figure 17 Further signal timing diagrams are provided for embodiments of this disclosure. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0060] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0061] In specific implementations, in the embodiments of this disclosure, the electronic device can be a display device, and the functional unit is a pixel unit. Exemplarily, the display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0062] like Figure 1As shown, the electronic device includes multiple driving elements arranged in an array, arranged in M ​​rows and N columns. For example, when N=4 and M=4, the multiple driving elements can be arranged in 4 rows and 4 columns, and are labeled according to their physical positions on the substrate as follows: A(1,1), A(1,2), A(1,3), A(1,4), A(2,1), A(2,2), A(2,3), A(2,4), A(3,1), A(3,2), A(3,3), A(3,4), A(4,1), A(4,2), A(4,3), A(4,4). It should be noted that... Figure 1 This is merely a possible illustration of the position of the driving elements on the substrate. In practical applications, the number of driving elements (i.e., the specific values ​​of N and M) can be determined according to the requirements of the application, and is not limited here.

[0063] In some embodiments of this disclosure, the electronic device further includes multiple device groups, a first end of which can be coupled to a positive signal line, and a second end of which can be coupled to the output of a driving element 112. Figures 2 to 4 As shown, a device group ZL and a driving element 112 constitute a functional unit P. In each functional unit P, the first terminal of the device group ZL is coupled to the positive signal line, and the second terminal of the device group ZL is coupled to the output terminal of the driving element 112. Figure 5 As shown, four device groups ZL_1 to ZL_4 and one driving element 112 constitute a functional unit P. In each functional unit P, the first terminal of device groups ZL_1 to ZL_4 is coupled to the positive signal line, and the second terminal of device groups ZL_1 to ZL_4 is coupled to different output terminals of driving element 112. This disclosure does not limit the number of device groups in each functional unit.

[0064] In some embodiments of this disclosure, a device group includes at least one device. For example, a device group includes multiple devices. Exemplarily, the device can be configured as a light-emitting device, then a device group may include at least one light-emitting device. Exemplarily, a first end of the device group can be the positive electrode of the light-emitting device, and a second end can be the negative electrode of at least one light-emitting device. For example, as... Figures 2 to 5 As shown, each device group can include three light-emitting devices (such as 1111 to 1113). Of course, in practical applications, the functional type and specific number of devices in a device group can be determined according to the actual application requirements, and are not limited here. The following explanation uses the example of each device group including three light-emitting devices.

[0065] In some embodiments of this disclosure, a device group ZL includes multiple devices. When one driving element controls one device group, the number of output terminals of the driving element 112 can be the same as the number of devices in the device group ZL. For example, as... Figure 2 and 3 As shown, if a device group ZL includes three light-emitting devices, then the driving element 112 can have three output terminals, and one output terminal is coupled to the negative terminal of the light-emitting device in a sub-pixel. Of course, it is not limited to this. For example, as... Figure 4 As shown, a device group ZL includes six light-emitting devices, but the six light-emitting devices are divided into three groups. Two light-emitting devices in each group are connected in parallel. Each group is set in a sub-pixel in a one-to-one correspondence. Then the driving element 112 can still have only three output terminals. Furthermore, one output terminal is simultaneously coupled to the negative terminals of the two light-emitting devices that are connected in parallel.

[0066] In some embodiments of this disclosure, when one driving element controls multiple device groups, the number of output terminals of the driving element 112 can be related to the number of all devices in the multiple device groups ZL. For example, as... Figure 5 As shown, one driving element controls four device groups ZL_1 to ZL_4. Each device group includes three light-emitting devices. The driving element 112 has 12 output terminals, and each output terminal is coupled to the negative terminal of a light-emitting device.

[0067] In some embodiments of this disclosure, such as Figure 2As shown, the display panel may further include: multiple first positive signal lines Va1…Van…VaN (1≤n≤N, n is an integer), multiple second positive signal lines Vb1…Vbn…VbN, multiple reference signal lines G1…Gn…GN, multiple addressing signal lines S1…Sm…SM (1≤m≤M, m is an integer), multiple addressing signal adapter lines Q1…Qm…QM, multiple drive signal lines D1…Dn…DN, and multiple auxiliary signal lines W1…Wm…WM. For example, a column of functional units P can correspond to at least one of the multiple first positive signal lines, at least one of the multiple second positive signal lines, at least one of the multiple reference signal lines, and at least one of the multiple drive signal lines. Furthermore, a row of functional units P can correspond to at least one address signal line, at least one auxiliary signal line, and at least one address signal adapter line from a plurality of address signal lines. For example, a column of functional units P can correspond to one first positive signal line, one second positive signal line, one reference signal line, and one drive signal line. Also, a row of functional units P can correspond to one address signal line, one auxiliary signal line, and one address signal adapter line. Optionally, each first positive signal line, each second positive signal line, each reference signal line, and each drive signal line can be disposed in the gap between two adjacent columns of functional units. Each address signal line, each auxiliary signal line, and each address signal adapter line can be disposed in the gap between two adjacent rows of functional units. Of course, in practical applications, the correspondence between functional units and the aforementioned signal lines can be determined according to the actual application requirements and is not limited here.

[0068] In some embodiments of this disclosure, such as Figure 2 As shown, each auxiliary signal line Wm can be coupled to at least one reference signal line Gn to reduce the resistance of the reference signal line Gn, reduce the voltage drop of the reference signal line Gn, and reduce the signal delay on the reference signal line Gn. Furthermore, each addressing signal adapter line Qm can be configured to correspond one-to-one with an addressing signal line Sm. For example, each auxiliary signal line Wm can be coupled to each reference signal line Gn, addressing signal adapter line Q1 is coupled to addressing signal line S1, addressing signal adapter line Qm is coupled to addressing signal line Sm, and addressing signal adapter line QM is coupled to addressing signal line SM.

[0069] In some embodiments of this disclosure, a first positive voltage VLED1 can be transmitted on the first positive signal line Van, a second positive voltage VLED2 can be transmitted on the second positive signal line Vbn, a reference voltage VSS can be transmitted on the reference signal line Gn, a power supply voltage VCC and addressing information can be transmitted on the addressing signal line Sm, and driving data can be transmitted on the driving signal line Dn.

[0070] In some embodiments of this disclosure, such as Figures 2 to 5 As shown, each device group may include three different colored light-emitting devices (such as a first-color light-emitting device 1111, a second-color light-emitting device 1112, and a third-color light-emitting device 1113). The driving element 112 may have output terminals O1-O3, a driving signal terminal O4, an addressing signal terminal O5, and a reference voltage terminal O6. Specifically, output terminal O1 is coupled to the negative terminal R- of the first-color light-emitting device 1111, output terminal O2 is coupled to the negative terminal G- of the second-color light-emitting device 1112, and output terminal O3 is coupled to the negative terminal B- of the third-color light-emitting device 1113. The driving signal terminal O4 is coupled to the driving signal line Dn through a first via p1, the addressing signal terminal O5 is coupled to the addressing signal line Sm, the reference voltage terminal O6 is coupled to the reference signal line Gn through a first via p2, and the auxiliary signal line Vm is coupled to the reference signal line Gn through a first via p5. The positive terminal R+ of the first color light-emitting device 1111 is coupled to the first positive signal line Van. The positive terminal G+ of the second color light-emitting device 1112 is coupled to the second positive signal line Vbn through the first via p4. The positive terminal B+ of the third color light-emitting device 1113 is coupled to the second positive signal line Vbn through the first via p4. The address signal line Sm is coupled to the address signal adapter line Qm through the first via p3. It should be noted that, in order to clearly highlight the connection relationship of each structure, Figure 6 The diagram only shows the terminals of the driving element 112 (e.g., O1 to O6) and the positive and negative terminals of the light-emitting device (e.g., R+, R-, G+, G-, B+, B-), omitting the main body of the driving element 112 and the light-emitting device.

[0071] In some embodiments of this disclosure, the first color light-emitting device 1111 can be a red light-emitting device, the second color light-emitting device 1112 can be a green light-emitting device, and the third color light-emitting device 1113 can be a blue light-emitting device. When driving the red, green, and blue light-emitting devices to emit light of the same brightness, the voltage required to be applied to the positive electrode R+ of the red light-emitting device is usually greater than the voltage required to be applied to the positive electrode G+ of the green light-emitting device and the voltage required to be applied to the positive electrode B+ of the blue light-emitting device. Therefore, if the positive electrodes of the red, green, and blue light-emitting devices are all coupled to the same positive signal line, the voltage required to be applied to that positive signal line will be relatively large. This not only increases power consumption but also causes the voltage applied to the positive electrodes of the green and blue light-emitting devices to be too high, reducing their lifespan. Therefore, a first positive signal line Van and a second positive signal line Vbn are respectively set, the positive electrode R+ of the red light-emitting device is coupled to the second positive signal line Vbn, and the positive electrodes G+ of the green light-emitting device and B+ of the blue light-emitting device are coupled to the first positive signal line Van. In practical applications, the second positive voltage VLED2 applied to the second positive signal line Vbn can be higher than the first positive voltage VLED1 applied to the first positive signal line Van. This not only enables the red light-emitting device to achieve its luminous brightness, but also reduces power consumption and improves the lifespan of the green and blue light-emitting devices.

[0072] In some examples, combined Figure 2 , Figure 3 , Figure 6 as well as Figure 7 As shown, the display panel may include: a substrate 010, a buffer layer 011 on the substrate 010, a first metal layer 012 on the side of the buffer layer 011 facing away from the substrate 010, an insulating layer 013 on the side of the first metal layer 012 facing away from the substrate 010, a second metal layer 014 on the side of the insulating layer 013 facing away from the substrate 010, a planarization layer 015 on the side of the second metal layer 014 facing away from the substrate 010, and a passivation layer 016 on the side of the planarization layer 015 facing away from the substrate 010. Furthermore, the light-emitting device and the driving element 112 are disposed on the side of the passivation layer 016 away from the substrate 010.

[0073] In some examples, combined Figure 2 , Figure 3 , Figure 6 as well as Figure 7As shown, the first metal layer 012 may include multiple first positive signal lines Van, multiple second positive signal lines Vbn, multiple reference signal lines Gn, multiple addressing signal transfer lines Qm, and multiple drive signal lines Dn, which are spaced apart from each other. Exemplarily, the multiple first positive signal lines Van, multiple second positive signal lines Vbn, multiple reference signal lines Gn, multiple addressing signal transfer lines Qm, and multiple drive signal lines Dn may be arranged along a first direction FS1 and extend along a second direction FS2. Exemplarily, as... Figure 3 As shown, the second direction FS2 is perpendicular to the first direction FS1. In practical applications, the second direction FS2 can be a column direction, and the first direction FS1 can be a row direction. Alternatively, the second direction FS2 can be a row direction, and the first direction FS1 can be a column direction.

[0074] For example, such as Figure 6 and Figure 7 As shown, the second metal layer 014 may include a plurality of first electrodes 144, a plurality of signal connection portions 141, a plurality of connection pads 142, and a plurality of connection traces 143. Exemplarily, a single functional unit may contain a plurality of first electrodes 144, a signal connection portion 141, a plurality of connection pads 142, and a plurality of connection traces 143. Furthermore, the plurality of connection pads 142 can be used to connect the light-emitting device and the driving element 112. It should be noted that some of the first electrodes 144 can be coupled to the reference signal line Gn through a first via p2, some of the first electrodes 144 can be coupled to the driving signal line Dn through a first via p1, and some of the first electrodes 144 can be coupled to the addressing signal line Sm.

[0075] In some embodiments, different types of signal lines have different line widths because they transmit different types of signals. If a signal line extends along a first direction FS1, the width of the signal line refers to its width perpendicular to its main extension direction (e.g., a second direction FS2). For example, as... Figure 6 As shown, the width of the reference signal line Gn is greater than the width of the data line Dn.

[0076] For example, such as Figure 6 and Figure 7As shown, the planarization layer 015 includes a plurality of second vias a2, which penetrate the planarization layer 015 to expose the second metal layer 014. The passivation layer 016 may include a plurality of third vias a3, which penetrate the planarization layer 015. Each third via a3 corresponds to a second via a2, forming a through-via that extends from the passivation layer 016 to the connection pads 142 of the second metal layer 014. For example, a light-emitting device can be connected to two connection pads 142 through the through-vias penetrating the planarization layer 015 and the passivation layer 016, and a driving element 112 can be connected to six connection pads 142 through the through-vias penetrating the planarization layer 015 and the passivation layer 016, thereby driving the light-emitting device to emit light under the control of the signal transmitted by the signal line and the driving element 112.

[0077] For example, such as Figure 6 and Figure 7 As shown, the positive and negative terminals of the light-emitting device and the output terminal of the driving element 112 to the reference voltage terminal O6 can be coupled to the corresponding connection pads 142 via soldering material S (e.g., solder, tin-silver-copper alloy, tin-copper alloy, etc.). For example, the output terminal O3 of the driving element 112 can be coupled to a connection pad 142 via soldering material S. The negative terminal B- of the third color light-emitting device 1113 can also be coupled to a connection pad 142 via soldering material S, and the connection pad 142 coupled to the negative terminal B- can be coupled to the connection pad 142 coupled to the reference voltage terminal O6 via connection trace 143. The positive terminal B+ of the third color light-emitting device 1113 can also be coupled to a connection pad 142 via soldering material S. The connection pad 142 coupled to the positive terminal B+ can be coupled via a signal connection portion 141, which can be coupled to the first positive signal line Va1 via a first via p4. Additionally, the reference voltage terminal O6 of the drive element 112 can also be coupled to a connection pad 142 via soldering material S. The connection pad 142 coupled to the reference voltage terminal O6 is coupled to a first electrode 144, which can be coupled to the reference signal line Gn via a first via p2.

[0078] For example, such as Figure 6 and Figure 7As shown, each first positive signal line Van is not a signal line with the same width everywhere. To facilitate reasonable layout of the signal lines, the width of the first positive signal line Van is wider in some positions and narrower in others. In some embodiments of this disclosure, the width of the first positive signal line Van can be the average width of the first positive signal line Van in its extension direction (first direction FS1), and the average width of the first positive signal line Van in the first direction FS1 refers to the value obtained by weighted summation of the widths of the first positive signal line Van at each position. Similarly, the second positive signal line Vbn, the reference signal line Gn, the address signal adapter line Qn, and the drive signal line Dn all have similar characteristics.

[0079] For example, the average width L3 of the reference signal line Gn can be greater than the average width L2 of the first positive signal line Van, or the average width L1 of the second positive signal line Vbn, or the average width L5 of the address signal transfer line Qn, or the average width L4 of the drive signal line Dn, without limitation.

[0080] In some embodiments of this disclosure, the light-emitting device may be, for example, a mini LED or a micro LED. Exemplarily, the orthographic projection of the light-emitting device onto the substrate may be quadrilateral, with the length or width of its side ranging from 80 μm to 350 μm. The light-emitting device can be mounted on the substrate using surface mount technology (SMT) or mass transfer technology.

[0081] In some embodiments of this disclosure, the electronic device may further include control circuitry coupled to each of the plurality of drive elements 112. For example... Figure 1 As shown, the control circuit may include a logic control circuit 200 and a system circuit 300. The system circuit 300 receives initial signals related to the display image from a television network interface, etc., performs a series of rendering and decoding processes on the initial signals to generate image signals, and simultaneously generates a frame refresh signal FB. When the pulse of the frame refresh signal FB reaches a set edge, the image signal is output to the logic control circuit 200. The logic control circuit 200 receives the image signal from the system circuit 300, and after further conversion processing, outputs corresponding drive signals to the driving elements or device groups through the first positive signal line Va1, the second positive signal line Vb1, the reference signal line Gn, the addressing signal conversion line Qm, and the drive signal line Dn in the display panel 100.

[0082] For example, such as Figure 8As shown, the electronic device may include multiple display panels (such as 100_1, 100_2) and multiple logic control circuits (such as 200_1, 200_2). Each display panel corresponds to one logic control circuit, and all logic control circuits (such as 200_1, 200_2) are coupled to a system circuit 300. By splicing multiple display panels, a larger display panel can be obtained.

[0083] In some embodiments of this disclosure, when a set edge occurs on the pulse of the frame refresh signal, the system circuit 300 can send the image signal of a corresponding display frame to the logic control circuit. Exemplarily, the set edge of the frame refresh signal can be a falling edge. Exemplarily, such as... Figure 9 As shown, FB represents the frame refresh signal, which has multiple pulses. At the falling edge of each pulse, the image signal of the next display frame is sent to the logic control circuit. Furthermore, at the falling edge of each pulse, the system circuit 300 outputs the image signal of the corresponding display frame to the logic control circuit. For example, at the falling edge of the first pulse of the frame refresh signal FB, the logic control circuit receives the image signal of display frame F1. At the falling edge of the second pulse of the frame refresh signal FB, the logic control circuit receives the image signal of display frame F2. At the falling edge of the third pulse of the frame refresh signal FB, the logic control circuit receives the image signal of display frame F3. It should be noted that the setting edge of the frame refresh signal can also be a rising edge; the implementation method can refer to the method where the setting edge of the frame refresh signal is a falling edge, which will not be elaborated here.

[0084] In some embodiments of this disclosure, each display frame includes multiple display subframes. Within a display frame, the logic control circuit repeatedly sends the same driving data K times to the driving element at a first frequency. The first frequency is the product of the frequency of the frame refresh signal FB and K. The value of K can be 32, 64, etc., and is not limited here.

[0085] In some embodiments of this disclosure, the logic control circuit pre-stores the address of each driving element coupled to it. Furthermore, to ensure that each driving element coupled to the logic control circuit operates as synchronously as possible, the logic control circuit can generate a horizontal synchronization signal within each display frame, and output corresponding driving data to the coupled driving element when a set edge appears on the pulse of the generated horizontal synchronization signal. The frequency of the horizontal synchronization signal is a first frequency. For example, within a display frame, the number of set edges of the horizontal synchronization signal can be K, thus allowing driving data to be sent to the driving element when a set edge appears on the pulse of the horizontal synchronization signal.

[0086] For example, combined Figure 8 and Figure 9As shown, the setting edge of the horizontal synchronization signal HB is a falling edge, and the setting edge of the frame refresh signal FB is a falling edge. System circuit 300 receives initial signals related to the image to be displayed in display frame Fn. For example, system circuit 300 receives initial signals related to the image to be displayed in display frame F1, performs a series of rendering and decoding processes on these initial signals, and then decomposes them according to the pre-stored address ID_1 corresponding to logic control circuit 200_1 and address ID_2 corresponding to logic control circuit 200_2, separating the image signal TX1 corresponding to logic control circuit 200_1 and the image signal (TX1) corresponding to logic control circuit 200_2 respectively. Figure 9 Taking the image signal TX1 corresponding to logic control circuit 200_1 as an example (the image signal corresponding to logic control circuit 200_2 is not shown), a frame refresh signal FB is generated. When the falling edge of the frame refresh signal FB appears, the image signal TX1 corresponding to logic control circuit 200_1 can be sent to logic control circuit 200_1, and the image signal corresponding to logic control circuit 200_2 can be sent to logic control circuit 200_2. Taking logic control circuit 200_1 as an example, after receiving the image signal TX1, logic control circuit 200_1 generates driving data corresponding to the coupled driving element 112 based on the image signal TX1, and generates a line synchronization signal HB. When the k-th falling edge of the line synchronization signal HB appears (k is a positive integer, and 1≤k≤K), logic control circuit 200_1 can provide driving data to driving element 112. Each driving element 112 can decode and process the part of the driving data corresponding to its own address, and then drive the coupled light-emitting device to emit light.

[0087] The operation of logic control circuit 200_2 can be referred to the operation of logic control circuit 200_1, and will not be elaborated here. It should be noted that the setting edge of the horizontal synchronization signal can also be set to the rising edge, and the implementation method can refer to the implementation method when the setting edge of the horizontal synchronization signal is the falling edge, which will not be elaborated here.

[0088] In some embodiments of this disclosure, any one of the driving elements 112 can control the positive signal line to form an electrical circuit with its reference voltage terminal O6 within the working time period of one light-emitting cycle. Since the positive signal line is coupled to the first terminal of the light-emitting device in the device group, and the reference voltage terminal O6 of the driving element 112 is coupled to the second terminal of the light-emitting device in the device group, when the positive signal line forms an electrical circuit sequentially through the coupled device group, the output terminal of the driving element 112, and the reference voltage terminal O6, the light-emitting device can be controlled to emit light under the control of current signals with different current amplitudes and / or different duty cycles. For example, each light-emitting cycle corresponds to a display subframe, and the working time period is the time stage for forming the aforementioned electrical circuit. For instance, the positive signal line includes a first positive signal line and a second positive signal line. Any one of the driving elements 112 can control the first positive signal line to form an electrical circuit sequentially through the coupled first color light-emitting device 1111, the output terminal of the driving element 112, and the reference voltage terminal O6 within the working time period of each display subframe, thereby causing the first color light-emitting device 1111 to emit light. Furthermore, the control of the second positive signal line to sequentially pass through the coupled second color light-emitting device 1112, the output terminal of the driving element 112, and its reference voltage terminal O6 to form an electrical circuit during the working time period of each display subframe can cause the second color light-emitting device 1112 to emit light. Also, the control of the second positive signal line to sequentially pass through the coupled third color light-emitting device 1113, the output terminal of the driving element 112, and its reference voltage terminal O6 to form an electrical circuit during the working time period of each display subframe can cause the third color light-emitting device 1113 to emit light.

[0089] In some embodiments of this disclosure, the operation of the electronic device may include an address allocation stage t1 and a data signal transmission stage t3. Taking the logic control circuit 200_1 and the display panel 110_1 of the electronic device as examples, combined with... Figure 10 and Figure 11 The signal timing diagram shown is used for illustration.

[0090] During the address allocation phase t1, the logic control circuit 200_1 can sequentially input address information sm (m is a positive integer, and 1≤m≤M) to each address signal line Sm. The driving element 112 can receive the corresponding address information sm. Figure 11This is a timing diagram illustrating the addressing information in an embodiment of this disclosure. For example, logic control circuit 200_1 transmits addressing information s1, including address ID 00000001, to addressing signal line S1. Multiple driving elements 112 arranged along the first direction FS1 and connected to addressing signal line S1 receive addressing information s1. Similarly, logic control circuit 200_1 transmits addressing information s2, including address ID 00000010, to addressing signal line S2. Multiple driving elements 112 arranged along the first direction FS1 and connected to addressing signal line S2 receive addressing information s2. The same principle applies to other functions, thus completing the address allocation process to the driving elements 112 in each functional unit.

[0091] Furthermore, during the data signal transmission phase t3, i.e., when the first falling edge of the horizontal synchronization signal HB appears, the logic control circuit 200_1 can provide each drive signal line Dn with drive data da containing the address of each drive element 112 coupled thereto. The drive element 112 can receive the drive data upon recognizing the corresponding address in the drive data, and generate a light-emitting control signal based on the drive data to control the positive signal line to sequentially form an electrical loop via the device group coupled to the drive element 112, the output terminal of the drive element 112, and the reference voltage terminal O6. For example, each drive data da can include multiple sub-data information dam (m is a positive integer, and 1≤m≤M) arranged in a specific order (e.g., the specific order can be the sequential arrangement of the physical positions of the drive elements). This allows multiple sub-data information dam to be sequentially input to each drive signal line Dn, thereby enabling the drive signal line Dn to sequentially transmit the corresponding sub-data information dam to each drive element 112 in the corresponding functional unit column. The sub-data information may include: the address ID corresponding to each functional unit P, and the pixel data information of the functional unit P corresponding to the address ID and coupled to the driving signal line Dn. When the driving element 112 recognizes that the address ID in the sub-data information dam is the same as the address ID received in the address allocation stage t1, it can receive the sub-data information dam and generate the light emission control signal corresponding to each output terminal of the driving element 112 according to the driving data, so as to control the coupled positive signal line (e.g., the first positive signal line and / or the second positive signal line) to form an electrical circuit in sequence through the device group coupled to the driving element 112, the output terminal of the driving element 112, and the reference voltage terminal O6.

[0092] In some examples, with Figure 3Taking the structure of the display panel, the logic control circuit 200_1, and the display panel 100_1 as an example, in the data signal transmission stage t3, the logic control circuit 200_1 inputs data information including sub-data information da1 to daM to the drive signal line Dn. The drive element 112, coupled to the drive signal line Dn, obtains the sub-data information matching its address ID from the data information including sub-data information da1 to daM. The drive element 112 can generate a light emission control signal EM1 corresponding to the first color light emission device 1111 coupled to the output terminal O1, a light emission control signal EM2 corresponding to the second color light emission device 1112 coupled to the output terminal O2, and a light emission control signal EM3 corresponding to the third color light emission device 1113 coupled to the output terminal O3, based on the sub-data information. Under the control of the light emission control signal EM1, at least one positive signal line can sequentially form an electrical circuit with the first color light-emitting device 1111, the output terminal O1 of the driving element 112, and the reference voltage terminal O6, thereby causing the first color light-emitting device 1111 to emit light; under the control of the light emission control signal EM2, at least one positive signal line can sequentially form an electrical circuit with the second color light-emitting device 1112, the output terminal O2 of the driving element 112, and the reference voltage terminal O6, thereby causing the second color light-emitting device 1112 to emit light; under the control of the light emission control signal EM3, at least one positive signal line can sequentially form an electrical circuit with the third color light-emitting device 1113, the output terminal O4 of the driving element 112, and the reference voltage terminal O6, thereby causing the third color light-emitting device 1113 to emit light.

[0093] It should be noted that each drive data da includes a set of sub-data information corresponding to the M drive elements arranged in the second direction FS2. The sub-data information includes the drive information of the device group connected to each of the M drive elements.

[0094] For example, such as Figure 11 As shown, the addressing information sm may include: a start instruction SoT, an address ID, an interval instruction DCX, and an end instruction EoT, set sequentially. In practical applications, the address ID in the addressing information sm corresponding to each addressing signal line Sm is different, thereby distinguishing addresses located in different row driving elements. For example, the length of the addressing information sm can be set to 12 bits, where the start instruction SoT can be set to 1 bit, the address ID can be set to 8 bits, the interval instruction DCX can be set to 1 bit, and the end instruction EoT can be set to 2 bits.

[0095] In some embodiments of the present disclosure, the logic control circuit may also input a supply voltage to the address selection signal line Sm, and the driving element 112 may receive the supply voltage transmitted by the address selection signal line Sm through the address signal terminal O5. Exemplarily, as Figure 11 shown, the address selection function (such as transmitting address selection information) and other functions (such as transmitting the supply voltage VCC) can be distinguished by differentiating the signal amplitude transmitted by the address selection signal line Sm. For example, the address selection function is executed when the signal amplitude is at the level V2 (for example, the voltage value is 3.3V), and the display function (such as transmitting the supply voltage VCC) is executed when the signal amplitude is at the level V1 (for example, the voltage value is 1.8V). During actual operation, first, the signal amplitude transmitted by the address selection signal line Sm needs to increase from the level V0 (for example, 0V) to the level V1 to enable the components connected to the address selection signal line Sm to enter the working state. Subsequently, when the signal amplitude changes from the level V1 to fluctuate with the level V2 as the reference, the address selection signal line Sm executes the address selection function by modulating the fluctuation change rule of the signal transmitted by the address selection signal line Sm. For example, the signal changes between the first amplitude V2H and the second amplitude V2L, and V1 < V2L < V2 < V2H. By modulating the change rules of the first amplitude V1 and the second amplitude V2, the address selection information sm can be modulated into the signal, so that the corresponding address can be transmitted while transmitting electrical energy. For example, the address selection information sm starts with the start instruction SoT, then transmits the address ID and the interval instruction DCX, and finally ends the address allocation of the pixel row with the end instruction EoT. When the signal amplitude returns from fluctuating with the level V2 as the reference to the level V1 and keeps the level V1 all the time, the address selection signal line Sm can be used to transmit the supply voltage. That is to say, the level V1 transmitted by the address selection signal line Sm can be used as the supply voltage.

[0096] In some embodiments of the present disclosure, taking the Figure 3 shown structure as an example, as Figure 3 compared with Figure 10As shown, the aforementioned sub-data information (taking da1 as an example) may include: start instruction SoT, address ID, data transmission instruction DCX, interval instruction IoT, pixel data information Rda, Gda, Bda, and end instruction EoT. When the data transmission instruction DCX is a set value, it indicates data transmission; for example, when DCX = 1, it indicates data transmission. When the driving element 112 recognizes that the value of DCX is 1, it transmits the pixel data information from the sub-data information to the corresponding light-emitting diode. Furthermore, the pixel data information Rda represents the information required to drive the first color light-emitting device 1111 to emit light, the pixel data information Gda represents the information required to drive the second color light-emitting device 1112 to emit light, and the pixel data information Bda represents the information required to drive the third color light-emitting device 1113 to emit light. For example, the length of each sub-data information can be set to 63 bits. Taking sub-data information da1 as an example, the length of sub-data information da1 can be set to 63 bits, where the start instruction SoT occupies 1 bit, the address ID occupies 8 bits, the data transmission instruction DCX occupies 1 bit, the interval instruction IoT occupies 1 bit, the pixel data information Rda, Gda or Bda each occupy 16 bits, and the end instruction EoT occupies 2 bits. In addition, the interval instruction IoT can also be set between adjacent pixel data information.

[0097] It is understood that before stage t1, the drive element 112 of this disclosure may be in a sleep state, which is a low-power operating mode or a non-operating state. The supply voltage VCC is input to the address signal terminal O5 of the drive element 112 via the address signal line Sm to release the drive element 112 from the sleep state. Figure 10 The t0 stage in the middle.

[0098] In other examples, with Figure 5 Taking the structure of the display panel, the logic control circuit 200_1, and the display panel 100_1 shown as examples, combined with... Figure 12 During the data signal transmission stage t3, the logic control circuit 200_1 sequentially inputs sub-data information da1 to daM to the drive signal line Dn. The drive element 112 coupled to the drive signal line Dn obtains the sub-data information that matches its address ID from the drive data including the sub-data information da1 to daM.

[0099] The driving element 112 can generate, based on the sub-data information, a light-emitting control signal EM1_1 corresponding to the first color light-emitting device 1111 coupled to output terminal O1_1, a light-emitting control signal EM1_2 corresponding to the first color light-emitting device 1111 coupled to output terminal O1_2, a light-emitting control signal EM1_3 corresponding to the first color light-emitting device 1111 coupled to output terminal O1_3, a light-emitting control signal EM1_4 corresponding to the first color light-emitting device 1111 coupled to output terminal O1_4, a light-emitting control signal EM2_1 corresponding to the second color light-emitting device 1112 coupled to output terminal O2_1, and a light-emitting control signal EM2_1 corresponding to the second color light-emitting device 1112 coupled to output terminal O2_2. The light-emitting control signal EM2_2, the light-emitting control signal EM2_3 corresponding to the second color light-emitting device 1112 coupled to the output terminal O2_3, the light-emitting control signal EM2_4 corresponding to the second color light-emitting device 1112 coupled to the output terminal O2_4, the light-emitting control signal EM3_1 corresponding to the third color light-emitting device 1113 coupled to the output terminal O3_1, the light-emitting control signal EM3_2 corresponding to the third color light-emitting device 1113 coupled to the output terminal O3_2, the light-emitting control signal EM3_3 corresponding to the third color light-emitting device 1113 coupled to the output terminal O3_3, and the light-emitting control signal EM3_4 corresponding to the third color light-emitting device 1113 coupled to the output terminal O3_4. Under the control of the light emission control signals EM1_1 to EM1_4, at least one positive signal line can be sequentially connected to the first color light-emitting device 1111, the output terminal O1 of the driving element 112 (including any one of O1_1 to O1_4), and the reference voltage terminal O6 to form an electrical circuit, thereby causing the corresponding first color light-emitting device 1111 to emit light; under the control of the light emission control signals EM2_1 to EM2_4, at least one positive signal line can be sequentially connected to the second color light-emitting device 1112, the driving element 112, and the reference voltage terminal O6 to form an electrical circuit, thereby causing the corresponding first color light-emitting device 1111 to emit light; The output terminal O2 of the drive element 112 (including any one of O2_1 to O2_4) and the reference voltage terminal O6 form an electrical circuit, thereby causing the corresponding second color light-emitting device 1112 to emit light; under the control of the light emission control signals EM3_1 to EM3_4, at least one positive signal line can be made to form an electrical circuit with the third color light-emitting device 1113, the output terminal O2 of the drive element 112 (including any one of O3_1 to O3_4), and the reference voltage terminal O6 in sequence, thereby causing the corresponding third color light-emitting device 1113 to emit light.

[0100] It should be noted that, Figure 5 The operation of the display panel shown in the address allocation stages t1 and t0 can be compared with the aforementioned... Figure 3 The operation of the display panel shown is basically the same in the address allocation stages t1 and t0, and will not be described in detail here.

[0101] In some embodiments of this disclosure, when a functional unit includes multiple device groups, combined with Figure 5 and Figure 12 As shown, the sub-data information (taking da1 as an example) may include: start instruction SoT, address ID, data transmission instruction DCX, interval instruction IoT, pixel data information Rda1~Rda4, Gda1~Gda4, Bda1~Bda4, and end instruction EoT. When the data transmission instruction DCX is a set value, it indicates data transmission. For example, when DCX = 1, it indicates data transmission. When the driving element 112 recognizes that the value of DCX is 1, it transmits the pixel data information in the sub-data information to the corresponding light-emitting diode. Furthermore, the pixel data information Rda1~Rda4 represents the information required to drive the four first-color light-emitting devices 1111 coupled to the driving element 112 to emit light; the pixel data information Gda1~Gda4 represents the information required to drive the four second-color light-emitting devices 1112 coupled to the driving element 112 to emit light; and the pixel data information Bda1~Bda4 represents the information required to drive the four third-color light-emitting devices 1113 coupled to the driving element 112 to emit light. For example, the length of each sub-data information can be set to 63 bits. Taking sub-data information da1 as an example, the start instruction SoT occupies 1 bit, the address ID occupies 8 bits, the data transmission instruction DCX occupies 1 bit, the interval instruction IoT occupies 1 bit, the sub-pixel data Rda1, Rda2, Rda3, and Rda4 occupy a total of 16 bits, the sub-pixel data Gda1, Gda2, Gda3, and Gda4 occupy a total of 16 bits, the sub-pixel data Bda1, Bda2, Bda3, and Bda4 occupy a total of 16 bits, and the end instruction EoT occupies 2 bits. In addition, an interval instruction IoT can be set between any two adjacent sub-data information. It can be understood that since one driving element 112 drives 12 light-emitting devices, the sequence relationship between the four pixels 1 connected to the driving element 112 can be implemented by the digital logic circuit inside the driving element 112 to accurately distribute the sub-pixel data corresponding to each light-emitting device in the pixel data information to the corresponding output terminal.

[0102] In some embodiments of this disclosure, each display frame may further include a current setting stage t2 prior to the data signal transmission stage t3, for example, the current setting stage t2 may be located between the address allocation stage t1 and the data signal transmission stage t3. In the current setting stage t2, the logic control circuit 200_1 inputs current setting information Co, which is assigned an address ID, to each drive signal line Dn. The drive element 112 can receive the current setting information Co when it identifies the address corresponding to the current setting information Co, so as to control the magnitude of the drive current of the drive element 112 according to the received current setting information Co, thereby further precisely controlling the light output brightness of the corresponding functional unit. For example, in conjunction with... Figure 8 and Figure 10 As shown, during the current setting stage t2, the logic control circuit 200_1 inputs current setting information Co to each drive signal line Dn. The current setting information Co may contain an address ID. The drive element 112 receives the current setting information corresponding to its address from the current setting information Co transmitted on the drive signal line Dn.

[0103] Optionally, the current setting information Co can be 63 bits long, specifically including: a 1-bit start instruction SoT, an 8-bit address ID, a 1-bit current setting instruction DCX, a 1-bit interval instruction IoT, 16 bits of data consisting of a frame start instruction C and a control instruction P1 (e.g., indicating that the current amplitude correction coefficient of a certain output terminal coupled to an LED needs to be provided), a 1-bit interval instruction IoT, 16 bits of reserved control instruction bits P2+P3, a 1-bit interval instruction IoT, 16 bits of reserved control instruction bits P4+P5, and a 2-bit end instruction EoT. Wherein, a current setting instruction DCX of a set value indicates that current setting is being performed; for example, when DCX is 0, it indicates that current setting is being performed.

[0104] It is understandable that, during the process of displaying images frame by frame, the display panel can choose not to display any image in the first display frame after the electronic device is powered on (e.g., displaying a completely black screen), and instead perform the t0 and t1 stages in that first frame. In the second and subsequent display frames, the electronic device only needs to execute the t2 and t3 stages. This allows each subframe within each display frame to have both the t2 and t3 stages. Alternatively, the t0, t1, and t2 stages can be performed in the first display frame, and in the second and subsequent display frames, the electronic device only needs to execute the t3 stage. This allows each subframe within each display frame to have its own t3 stage. In other words, in situations like... Figure 9In the signal timing diagram shown, before display frame F1, there can also be display frame F0. Display frame F0 can execute the processes of stages t0 and t1, or the processes from stage t0 to stage t2. Each display subframe in display frames F1 to F3 executes the process of stage t3.

[0105] In some embodiments of this disclosure, such as Figure 13 As shown, any one of the multiple driving elements 112 may include a processing control circuit 1122 and a data driving circuit 1121. The processing control circuit 1122 is coupled to the driving signal terminal O4 and the addressing signal terminal O5, respectively. The data driving circuit 1121 is coupled to the processing control circuit 1122, the output terminal of the driving element 112, the addressing signal terminal O5, and the reference voltage terminal O6, respectively. Furthermore, the data driving circuit 1121 is coupled to the second terminal of the light-emitting device in the corresponding device group via its output terminal. During the light-emitting period (which may be, for example, a display subframe), when the corresponding address in the driving data is identified, the processing control circuit 1122 receives the driving data via the driving signal terminal O4, generates a light-emitting control signal based on the driving data, and sends the light-emitting control signal to the data driving circuit 1121. Furthermore, during the light emission cycle, the data driving circuit 1121 controls the positive signal line (such as the first positive signal line and the second positive signal line) to sequentially pass through the light-emitting device in the device group coupled to the driving element 112, the output terminal of the driving element 112, and the reference voltage terminal O6 to form an electrical circuit, so as to control each light-emitting device to emit light through the formed electrical circuit.

[0106] In some embodiments of this disclosure, such as Figure 13 and Figure 14As shown, the data driving circuit 1121 may include at least one data driving sub-circuit (such as 11211, 11212, 11213). Each data driving sub-circuit (such as 11211, 11212, 11213) is coupled to the processing control circuit 1122, the addressing signal terminal O5, and the reference voltage terminal O6, respectively. Each data driving sub-circuit is coupled to an output terminal, meaning that each data driving sub-circuit can be coupled to the negative terminal of the light-emitting device in a sub-pixel through its corresponding output terminal. When a supply voltage VCC is input through the addressing signal terminal O5, this supply voltage VCC can be input to the data driving sub-circuit to power it. When a reference voltage VSS is input through the reference voltage terminal O6, this reference voltage VSS can be input to the data driving sub-circuit to provide a low voltage. The data driving sub-circuit (such as 11211, 11212, 11213) can receive the light emission control signal corresponding to the coupled device group during the light emission cycle, and in response to the light emission control signal, control the positive electrode signal line to sequentially pass through the device group coupled to the driving element 112, the output terminal of the driving element 112, and the reference voltage terminal O6 to form an electrical loop. For example, combined with... Figure 3 , Figure 13 as well as Figure 14As shown, the data driving sub-circuit 11211 is coupled to the output terminal O1, and the output terminal O1 is coupled to the negative terminal of the first color light-emitting device 1111. The positive terminal of the first color light-emitting device 1111 is coupled to the first positive signal line. The data driving sub-circuit 11211 can receive the corresponding light-emitting control signal EM1 of the first color light-emitting device 1111. In response to the light-emitting control signal EM1, it can drive the first positive signal line Van, the first color light-emitting device 1111, the output terminal O1 and the reference voltage terminal O6 to form an electrical circuit, so that the first color light-emitting device 1111 has current flowing through it and emits light. Furthermore, the data driving sub-circuit 11212 is coupled to the output terminal O2, the output terminal O2 is coupled to the negative terminal of the second color light-emitting device 1112, and the positive terminal of the second color light-emitting device 1112 is coupled to the second positive signal line Vbn. The data driving sub-circuit 11212 can receive the corresponding light-emitting control signal EM2 of the second color light-emitting device 1112. In response to the light-emitting control signal EM2, it can drive the second positive signal line Vbn, the second color light-emitting device 1112, the output terminal O2, and the reference voltage terminal O6 to form an electrical circuit so that the second color light-emitting device 1112 has current flowing through it and emits light. Furthermore, the data driving sub-circuit 11213 is coupled to the output terminal O3, the output terminal O3 is coupled to the negative terminal of the third color light-emitting device 1113, and the positive terminal of the third color light-emitting device 1113 is coupled to the second positive signal line Vbn. The data driving sub-circuit 11213 can receive the corresponding light-emitting control signal EM3 of the third color light-emitting device 1113. In response to the light-emitting control signal EM3, it can drive the second positive signal line Vbn, the third color light-emitting device 1113, the output terminal O3, and the reference voltage terminal O6 to form an electrical circuit so that the third color light-emitting device 1113 has current flowing through it and emits light.

[0107] In some embodiments of this disclosure, the light emission control signal may include a drive control signal and a current control signal. Each data drive sub-circuit may include a modulation circuit and a constant current source circuit; wherein the constant current source circuit is coupled to the processing control circuit 1122 and the modulation circuit respectively, and the modulation circuit is coupled to the corresponding output terminal. The constant current source circuit can receive the current control signal of the corresponding device group and output a current with a constant amplitude corresponding to the received current control signal. The modulation circuit can receive the drive control signal of the corresponding device group and, based on the effective level of the received drive control signal, input the current generated by the constant current source to the coupled output terminal, so as to control the positive signal line to form an electrical loop at least sequentially through the device group coupled to the drive element, the output terminal of the drive element, and the reference voltage terminal during the working period.

[0108] For example, combined Figure 9 , Figure 14 and Figure 15As shown, the light emission control signal EM1 may include a drive control signal PWM1 and a current control signal DAC1. The data drive sub-circuit 11211 includes a modulation circuit 112111 and a constant current source circuit 112112. The constant current source circuit 112112 can receive the current control signal DAC1 corresponding to the first color light emission device 1111, and output a current IL1 with a constant amplitude corresponding to the received current control signal DAC1. The modulation circuit 112111 can receive the drive control signal PWM1 corresponding to the first color light emission device 1111, and input the current IL1 generated by the constant current source circuit 112112 to the coupled output terminal O1 according to the effective level (e.g., high level) of the received drive control signal PWM1, so as to control the first positive signal line Van to form an electrical circuit at least sequentially through the first color light emission device 1111, the output terminal O1 of the drive element 112, and the reference voltage terminal O6 during the working period, so as to make the first color light emission device 1111 emit light. In other words, the effective duration of the drive control signal PWM1 can be considered as the working period of the first color light-emitting device 1111. Thus, by combining the drive control signal PWM1 and the current control signal DAC1, the brightness of the first color light-emitting device 1111 in each display sub-frame of each display frame can be controlled.

[0109] Furthermore, the light emission control signal EM2 may include a drive control signal PWM2 and a current control signal DAC2. The data drive sub-circuit 11212 includes a modulation circuit 112121 and a constant current source circuit 112122. The constant current source circuit 112122 can receive the current control signal DAC2 corresponding to the second color light emission device 1112, and output a current IL2 with a constant amplitude corresponding to the current control signal DAC2 according to the received current control signal DAC2. The modulation circuit 112121 can receive the drive control signal PWM2 corresponding to the second color light emission device 1112, and input the current IL2 generated by the constant current source circuit 112122 to the coupled output terminal O2 according to the effective level (e.g., high level) of the received drive control signal PWM2, so as to control the second positive signal line Vbn to form an electrical circuit at least sequentially through the second color light emission device 1112, the output terminal O2 of the drive element 112, and the reference voltage terminal O6 during the working period, so as to make the second color light emission device 1112 emit light. In other words, the effective duration of the drive control signal PWM2 can be considered as the working period of the second color light-emitting device 1112. Thus, by combining the drive control signal PWM2 and the current control signal DAC2, the brightness of the second color light-emitting device 1112 in each display sub-frame of each display frame can be controlled.

[0110] Furthermore, the light emission control signal EM3 may include a drive control signal PWM3 and a current control signal DAC3. The data drive sub-circuit 11213 includes a modulation circuit 112131 and a constant current source circuit 112132. The constant current source circuit 112132 can receive the current control signal DAC3 corresponding to the third color light emission device 1113, and output a current IL3 with a constant amplitude corresponding to the current control signal DAC3 according to the received current control signal DAC3. The modulation circuit 112131 can receive the drive control signal PWM3 corresponding to the third color light emission device 1113, and input the current IL3 generated by the constant current source circuit 112132 to the coupled output terminal O3 according to the effective level (e.g., high level) of the received drive control signal PWM3, so as to control the second positive signal line Vbn to form an electrical circuit at least sequentially through the third color light emission device 1113, the output terminal O3 of the drive element 112, and the reference voltage terminal O6 during the working period, so as to make the third color light emission device 1113 emit light. In other words, the effective duration of the drive control signal PWM3 can be considered as the working period of the third color light-emitting device 1113. Thus, by combining the drive control signal PWM3 and the current control signal DAC3, the brightness of the third color light-emitting device 1113 in each display sub-frame of each display frame can be controlled.

[0111] It should be noted that the effective level of the drive control signal can also be low, and this is not limited here.

[0112] In summary, when the modulation circuit is on, the aforementioned electrical circuit is open, and the device group emits light. When the modulation circuit is off, the aforementioned electrical circuit is closed, and the device group does not emit light. Therefore, the modulation circuit can modulate the current flowing through the device group under the control of the drive control signal PWM, making the current flowing through the device group a current signal that can be modulated by pulse width modulation. Therefore, the drive control signal PWM can be used as a pulse width modulation signal. Furthermore, the modulation circuit can modulate the current flowing through the device group according to parameters such as the duty cycle of the drive control signal PWM, thereby controlling the operating state of the device group. For example, when the device group contains light-emitting devices, by increasing the duty cycle of the drive control signal PWM, the total light-emitting time of the light-emitting devices in a display frame (or display subframe) can be increased, thereby increasing the total brightness of the light-emitting devices in that display frame (or display subframe), thus increasing the brightness of the device group containing the light-emitting devices. Conversely, by adjusting the duty cycle of the PWM control signal, the total duration of light emission of the light-emitting device within a display frame (or sub-frame) can be reduced, thereby reducing the total brightness of the light-emitting device in that display frame (or sub-frame) and thus reducing the brightness of the device group to which the light-emitting device is located.

[0113] For example, the modulation circuit can be a switching element, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a thin-film transistor (TFT). Of course, in practical applications, the specific implementation of the modulation circuit can be determined according to the needs of the application, and is not limited here.

[0114] For example, a constant current source circuit can be implemented in various ways. It can be a circuit composed of a constant current diode, a digital-to-analog converter, and a trigger, or a current mirror circuit. Of course, in practical applications, the specific implementation of the constant current source circuit can be determined according to the needs of the application and is not limited here.

[0115] In some examples, taking the 16-bit pixel data information Rda corresponding to the first color light-emitting device 1111 as an example, the 16-bit pixel data information corresponding to other light-emitting devices adopts the same data type and encoding rules. For example, if the pixel data information Rda is 16 bits, it can have, but is not limited to, the following implementations: the current control signal DAC1 occupies 6 bits and the drive control signal PWM1 occupies 10 bits; or the current control signal DAC1 occupies 5 bits and the drive control signal PWM1 occupies 11 bits; or the current control signal DAC1 occupies 4 bits and the drive control signal PWM1 occupies 12 bits; or the current control signal DAC1 occupies 3 bits and the drive control signal PWM1 occupies 13 bits.

[0116] Taking the current control signal DAC1 occupying 6 bits and the drive control signal PWM1 occupying 10 bits as an example, the current control signal DAC1 can control the constant current source circuit 112112 to output 64(2 6 The constant current source circuit 112112 can have different current levels, such as 2uA, 3uA, 5uA, etc. Taking the current level of 2uA as an example, the maximum value of the current IL1 that the constant current source circuit 112112 can output is 128uA (2uA*64), and the minimum value is 2uA (2uA*1), so there are a total of 64 selectable values ​​for the current IL1, which can meet the different brightness requirements of the first color light-emitting device 1111. The drive control signal PWM1 occupies 10 bits, so the duty cycle of the drive control signal PWM1 can have 1024 (2... 10 There are 10 different scenarios. The more bits the drive control signal PWM1 occupies, the more types of duty cycle scenarios there are.

[0117] Since the positive and negative terminals of each light-emitting device are connected to corresponding bonding pads on the substrate, a capacitance is formed between the bonding pads when there is a voltage difference. This capacitance is the parasitic capacitance of the light-emitting device itself, with a value ranging from a few pF picofarads to tens of pF. In the equivalent circuit, this capacitance is connected in parallel with the light-emitting device. Because electronic devices include multiple device groups, each including at least one light-emitting device, the parasitic capacitance of each light-emitting device varies due to variations in manufacturing processes or different light-emitting states. Therefore, the time it takes for different light-emitting devices to switch from the off state (ZT-off) to the light-emitting state (ZT-on) or from the light-emitting state (ZT-on) to the off state (ZT-off) differs. This results in different light-emitting devices displaying different brightness levels when they should display the same brightness, thus affecting visual perception.

[0118] It is understood that although capacitance will be formed between the connection pads and signal lines due to overlap, the capacitance value is small and will not be discussed in this embodiment.

[0119] For example, taking the first color light-emitting device 1111 as an example, combined with Figures 13 to 16 As shown, Figure 16 In this diagram, FL1 represents the theoretical value of the voltage change at the negative terminal of the first color light-emitting device 1111, and FL2 represents the actual value of the voltage change at the negative terminal of the first color light-emitting device 1111. The positive terminal of the first color light-emitting device 1111 is coupled to the first positive signal line Van, and the negative terminal of the first color light-emitting device 1111 is coupled to the reference voltage terminal O6 through the modulation circuit 112111 and the constant current source circuit 112112. Due to the parasitic capacitance of the first color light-emitting device 1111 itself, the voltage at the negative terminal of the first color light-emitting device 1111 cannot be instantly pulled down from a high level (e.g., 2V) to the reference voltage VSS (e.g., 1V). That is, the first color light-emitting device 1111 cannot quickly switch from the off state (i.e., off state ZT-off) to the emitting state (i.e., on state ZT-on), thus shortening the emitting time of the first color light-emitting device 1111. Similarly, when the driving element 112 is working, it will also generate a similar parasitic capacitance. This parasitic capacitance will also cause the first color light-emitting device 1111 to be unable to quickly switch from the off state (i.e., off state ZT-off) to the light-emitting state (i.e., on state ZT-on), thus shortening the light-emitting time of the first color light-emitting device 1111 (i.e., the time of on state ZT-on).

[0120] It is understandable that when a light-emitting device is in the emitting state (i.e., on state ZT-on), it can emit light as long as the voltage difference between its positive and negative electrodes is greater than its turn-on voltage. Therefore, the negative electrode voltage of the light-emitting device does not need to be reduced to the reference voltage VSS for the device to emit light. Instead, the sum of the negative electrode voltage and the turn-on voltage of the device must be less than the positive electrode voltage for the device to be in the emitting state (i.e., on state ZT-on).

[0121] To improve the above-mentioned problems, the driving element 112 provided in this embodiment can also adjust the potential of the second terminal of the device group coupled to it before the working time period of the light emission cycle, for example, by pulling down the potential of the second terminal of the device group. Exemplarily, in conjunction with... Figure 13 and Figure 16As shown, the device group includes a first-color light-emitting device 1111, a second-color light-emitting device 1112, and a third-color light-emitting device 1113. The second terminal of the device group includes the negative terminals of the first-color light-emitting device 1111, the second-color light-emitting device 1112, and the third-color light-emitting device 1113. The negative terminal of the first-color light-emitting device 1111 is connected to the output terminal O1 of the driving element 112, the negative terminal of the second-color light-emitting device 1112 is connected to the output terminal O2 of the driving element 112, and the negative terminal of the third-color light-emitting device 1113 is connected to the output terminal O3 of the driving element 112. FL3 represents the actual value of the voltage at the negative terminal of the first-color light-emitting device 1111 after adjustment by the potential adjustment circuit. The driving element 112 can adjust the potential of the negative electrode of the first color light-emitting device 1111 before the working time period of the first color light-emitting device 1111. This can reduce the potential of the negative electrode of the first color light-emitting device 1111 to the critical state that allows the first color light-emitting device 1111 to light up in advance. This allows the first color light-emitting device 1111 to quickly switch from the off state (i.e., off state ZT-off) to the light-emitting state (i.e., on state ZT-on) at the beginning of the working time period. As a result, the actual time that the first color light-emitting device 1111 is in the light-emitting state (i.e., on state ZT-on) can be as close as possible to the theoretical value. Similarly, the driving element 112 can adjust the potential of the negative electrode of the second color light-emitting device 1112 before the working period of the second color light-emitting device 1112. This can reduce the potential of the negative electrode of the second color light-emitting device 1112 to the critical state that allows the second color light-emitting device 1112 to light up in advance. This allows the second color light-emitting device 1112 to quickly switch from the off state (i.e., off state ZT-off) to the light-emitting state (i.e., on state ZT-on) at the beginning of the working period. As a result, the actual time that the second color light-emitting device 1112 is in the light-emitting state (i.e., on state ZT-on) can be as close as possible to the theoretical value. Similarly, the driving element 112 can adjust the potential of the negative electrode of the third color light-emitting device 1113 before the working period of the third color light-emitting device 1113. This can reduce the potential of the negative electrode of the third color light-emitting device 1113 to the critical state that allows the third color light-emitting device 1113 to light up in advance. This allows the third color light-emitting device 1113 to quickly switch from the off state (i.e., off state ZT-off) to the light-emitting state (i.e., on state ZT-on) at the beginning of the working period. As a result, the actual time that the third color light-emitting device 1113 is in the light-emitting state (i.e., on state ZT-on) can be as close as possible to the theoretical value.

[0122] In some embodiments of this disclosure, any one of a plurality of driving elements can control the second terminal of the device group coupled thereto to conduct with its reference voltage terminal for a first compensation time before the operating time period, so as to adjust the potential of the second terminal of the device group coupled thereto during the first compensation time using a reference voltage applied to the reference voltage terminal. For example, in conjunction with... Figure 9 and Figure 13 as well as Figure 17 As shown, the driving element 112 can, before the operating time period of the first color light-emitting device 1111 (e.g., within a display subframe F1_1, before the first rising edge of the drive control signal PWM1 arrives), turn on the negative terminal of the first color light-emitting device 1111 and the reference voltage terminal O6 for a first compensation time ts1, so as to adjust the potential of the negative terminal of the first color light-emitting device 1111 within the first compensation time ts1 using the reference voltage VSS applied to the reference voltage terminal O6. Similarly, before the operating time period of the second color light-emitting device 1112, the driving element 112 can turn on the negative terminal of the second color light-emitting device 1112 and the reference voltage terminal O6 for a first compensation time, so as to adjust the potential of the negative terminal of the second color light-emitting device 1112 within the first compensation time using the reference voltage applied to the reference voltage terminal O6. Furthermore, before the operating time of the third color light-emitting device 1113, the negative terminal of the third color light-emitting device 1113 is connected to the reference voltage terminal O6 for a first compensation time, so as to adjust the potential of the negative terminal of the third color light-emitting device 1113 by using the reference voltage applied by the reference voltage terminal O6 within the first compensation time.

[0123] In some embodiments of this disclosure, any one of the plurality of driving elements can, at the end of the first compensation time, control the positive signal line to form an electrical circuit at least sequentially through the device group coupled to the driving element, the output terminal of the driving element, and the reference voltage terminal. Exemplarily, in conjunction with... Figure 9 , Figure 13 as well as Figure 17 As shown, the driving element 112 can control the first positive signal line Van, the first color light-emitting device 1111, the output terminal O1, and the reference voltage terminal O6 to form an electrical circuit at the end of the first compensation time ts1 when the negative terminal of the first color light-emitting device 1111 is connected to the reference voltage terminal O6. Similarly, at the end of the first compensation time when the negative terminal of the second color light-emitting device 1112 is connected to the reference voltage terminal O6, the driving element 112 can control the second positive signal line, the second color light-emitting device 1112, the output terminal O2, and the reference voltage terminal O6 to form an electrical circuit. Furthermore, at the end of the first compensation time when the negative terminal of the third color light-emitting device 1113 is connected to the reference voltage terminal O6, the driving element 112 can control the second positive signal line, the third color light-emitting device 1113, the output terminal O3, and the reference voltage terminal O6 to form an electrical circuit.

[0124] In some embodiments of this disclosure, any one of a plurality of driving elements can control the second terminal of the device group coupled thereto to conduct a second compensation time with its reference voltage terminal within an operating time period. Exemplarily, in conjunction with... Figure 9 and Figure 13 as well as Figure 17 As shown, taking the first color light-emitting device 1111 as an example, the driving element 112 can connect the negative terminal of the first color light-emitting device 1111 to the reference voltage terminal O6 for a second compensation time ts2 within the working time period of the first color light-emitting device 1111 (for example, within a display subframe F1_1, within any effective level time period of the driving control signal PWM1, such as within the first effective level time period of the driving control signal PWM1). This allows the reference voltage applied by the reference voltage terminal O6 to adjust the potential of the negative terminal of the first color light-emitting device 1111 within the second compensation time ts2.

[0125] In some embodiments of this disclosure, the first compensation time and the second compensation time can be sequentially consecutive time periods. For example, in combination with... Figure 9 and Figure 13 as well as Figure 17 As shown, the first compensation time ts1 and the second compensation time ts2 corresponding to the first color light-emitting device 1111 are sequentially consecutive time periods. The first compensation time and the second compensation time corresponding to the second color light-emitting device 1112 are sequentially consecutive time periods. The first compensation time and the second compensation time corresponding to the third color light-emitting device 1113 are sequentially consecutive time periods.

[0126] In some embodiments of this disclosure, the device group includes multiple devices (e.g., light-emitting devices), and the second end of the device group may include the negative terminals of multiple light-emitting devices. The negative terminal of each light-emitting device is connected to different output terminals of the same driving element. Therefore, the first compensation time and / or the second compensation time corresponding to each light-emitting device are not the same, so that the potential of the negative terminals of different light-emitting devices can be precisely adjusted.

[0127] Since the second compensation time overlaps with the operating time of the light-emitting device, to avoid the second compensation time affecting the brightness of the light-emitting device during normal operation, in some embodiments of this disclosure, for at least one device group among multiple device groups, the second compensation time corresponding to the device group is less than the first compensation time. Specifically, the second compensation time corresponding to each device in the device group can be less than the first compensation time; for example, the second compensation time corresponding to each light-emitting device can be less than the first compensation time. In specific implementations, the second compensation time is less than half of the first compensation time.

[0128] In some embodiments of this disclosure, at least two of the multiple device groups correspond to different first compensation times and / or second compensation times; multiple devices belonging to the same device group can correspond to different first compensation times and / or second compensation times when achieving a specific grayscale. For example, a device group includes a first color light-emitting device 1111, a second color light-emitting device 1112, and a third color light-emitting device 1113. The first compensation time corresponding to the first color light-emitting device 1111 is 60 ns, the first compensation time corresponding to the second color light-emitting device 1112 is 35 ns, and the first compensation time corresponding to the third color light-emitting device 1113 is 8 ns; then the second compensation time corresponding to the first color light-emitting device 1111 can be 10 ns, the second compensation time corresponding to the second color light-emitting device 1112 can be 5 ns, and the second compensation time corresponding to the third color light-emitting device 1113 can be 2 ns.

[0129] In some embodiments of this disclosure, at least some of the device groups among multiple device groups may have the same second compensation time. For example, the second compensation time for at least some device groups may all be set to 1 ns, which can reduce the design difficulty of the second compensation time.

[0130] In some embodiments of this disclosure, any one of the plurality of driving elements 112 can control the potential compensation time for the second terminal of the coupled device group to be connected to the reference voltage terminal O6 according to the pre-stored potential compensation time corresponding to the coupled device group; wherein, the potential compensation time is the sum of the first compensation time and the second compensation time. Of course, the potential compensation time is the first compensation time. The following description takes the example of the potential compensation time being the sum of the first compensation time and the second compensation time. When the potential compensation time is the first compensation time, the working process can be deduced by analogy, and will not be elaborated here.

[0131] In some embodiments of this disclosure, the parasitic capacitance of the light-emitting device is discharged prematurely by adjusting the potential of its negative electrode before it emits light. However, it is necessary to avoid the light-emitting device emitting light during non-working periods due to premature adjustment of the negative electrode potential. Therefore, the first compensation time ts1 has a maximum value ts1-max. In specific implementations, the first compensation time ts1 should not exceed this maximum value ts1-max. For example, it can be based on the formula: Determine the maximum value of the first compensation time ts1, ts1-max. Where V + V represents the voltage at the positive terminal of a light-emitting device. F V represents the turn-on voltage of a light-emitting device. s R represents the voltage at the negative terminal of the light-emitting device before the start of the first compensation time ts1. LEDC represents the resistance value of the light-emitting device itself, which is its equivalent resistance. LED This represents the capacitance value of the parasitic capacitance of the light-emitting device itself. For example, combined with... Figure 16 As shown, taking the first color light-emitting device as an example, the voltage at the positive electrode of the first color light-emitting device is VLED1, then V + =VLED1,V F V represents the turn-on voltage of the first color light-emitting device. s R represents the voltage at the negative electrode of the first color light-emitting device before the start of the first compensation time ts1. LED C represents the resistance value of the first color light-emitting device itself, which is its equivalent resistance. LED The capacitance value represents the parasitic capacitance of the first color light-emitting device. Substituting this into the above formula, the maximum value of the first compensation time ts1 corresponding to the first color light-emitting device can be determined. The calculation method for the maximum value of the first compensation time ts1 of the other light-emitting devices is similar and will not be elaborated here.

[0132] In some embodiments of this disclosure, the processing control circuit 1122 can further generate a potential adjustment control signal based on the potential compensation time during the light emission cycle, and send the potential adjustment control signal to the data driving circuit. The data driving circuit can control the second terminal of the corresponding device group to conduct with its reference voltage terminal based on the effective level of the received potential adjustment control signal; wherein, the effective level duration of the potential adjustment control signal corresponding to the device group is the potential compensation time. For example, in conjunction with... Figure 3 , Figures 13 to 15As shown, the processing control circuit 1122 can also generate a potential adjustment control signal OVS1 based on the potential compensation time ts corresponding to the output terminal O1 during the light emission cycle, and send the potential adjustment control signal OVS1 to the data driving circuit 1121. The data driving circuit 1121 can control the negative terminal of the first color light-emitting device 1111 to conduct with its reference voltage terminal O6 based on the effective level (e.g., high level) of the received potential adjustment control signal OVS1. The processing control circuit 1122 can also generate a potential adjustment control signal OVS2 based on the potential compensation time corresponding to the output terminal O2 during the light emission cycle, and send the potential adjustment control signal OVS2 to the data driving circuit 1121. The data driving circuit 1121 can control the negative terminal of the second color light-emitting device 1112 to conduct with its reference voltage terminal O6 based on the effective level (e.g., high level) of the received potential adjustment control signal OVS2. Furthermore, the processing control circuit 1122 can also generate a potential adjustment control signal OVS3 according to the potential compensation time corresponding to the output terminal O3 during the light emission cycle, and send the potential adjustment control signal OVS3 to the data driving circuit 1121. The data driving circuit 1121 can control the negative terminal of the third color light-emitting device 1113 to conduct with its reference voltage terminal O6 according to the effective level (e.g., high level) of the received potential adjustment control signal OVS3.

[0133] In some embodiments of this disclosure, when the data driving circuit includes a data driving sub-circuit, the data driving sub-circuit can receive a potential adjustment control signal output by the processing control circuit 1122, and in response to the potential adjustment control signal, control the second terminal of the coupled device group to conduct with its reference voltage terminal. Exemplarily, in conjunction with... Figure 3 , Figures 13 to 15 As shown, the data driving sub-circuit 11211 can receive the potential adjustment control signal OVS1 and, in response to the effective level (e.g., high level) of the potential adjustment control signal OVS1, control the negative terminal of the first color light-emitting device 1111 to conduct with its reference voltage terminal O6. The data driving sub-circuit 11212 can receive the potential adjustment control signal OVS2 and, in response to the effective level (e.g., high level) of the potential adjustment control signal OVS2, control the negative terminal of the second color light-emitting device 1112 to conduct with its reference voltage terminal O6. The data driving sub-circuit 11213 can receive the potential adjustment control signal OVS3 and, in response to the effective level (e.g., high level) of the potential adjustment control signal OVS3, control the negative terminal of the third color light-emitting device 1113 to conduct with its reference voltage terminal O6.

[0134] In some embodiments of this disclosure, the data driving sub-circuit may further include a potential adjustment circuit, which is coupled to the processing control circuit and the corresponding output terminal. Furthermore, the potential adjustment circuit can receive a potential adjustment control signal for the corresponding device group and control the second terminal of the coupled device group to conduct with its reference voltage terminal according to the received potential adjustment control signal. For example, in conjunction with… Figure 3 , Figures 13 to 15 As shown, the data driving sub-circuit 11211 includes a potential adjustment circuit 112113, which can receive a potential adjustment control signal OVS1 and, in response to the effective level of the potential adjustment control signal OVS1, can connect the negative terminal of the first color light-emitting device 1111 to the reference voltage terminal O6. The data driving sub-circuit 11212 includes a potential adjustment circuit 112123, which can receive a potential adjustment control signal OVS2 and, in response to the effective level of the potential adjustment control signal OVS2, can connect the negative terminal of the second color light-emitting device 1112 to the reference voltage terminal O6. The data driving sub-circuit 11213 includes a potential adjustment circuit 112133, which can receive a potential adjustment control signal OVS3 and, in response to the effective level of the potential adjustment control signal OVS3, can connect the negative terminal of the third color light-emitting device 1113 to the reference voltage terminal O6.

[0135] For example, the potential adjustment circuit may include a switching element, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a thin-film transistor (TFT). Of course, in practical applications, the specific implementation of the potential adjustment circuit can be determined according to the needs of the application and is not limited here.

[0136] In some embodiments of this disclosure, such as Figures 13 to 15As shown, the processing control circuit 1122 may include a processor 11221 and a control circuit 11222. The processor 11221 can generate drive control signals corresponding to each device group coupled to the received pixel data information Rda, Gda, and Bda, and send them to the corresponding data drive sub-circuit of each device group. The processor 11221 can also generate current amplitude control information and potential adjustment information corresponding to each device group coupled to it, based on the received pixel data information and pre-stored potential compensation time corresponding to each device group, and provide them to the control circuit 11222. Furthermore, the control circuit 11222 can generate current control signals in the light emission control signals corresponding to each device group based on the received current amplitude control information, and generate potential adjustment control signals corresponding to each device group based on the received potential adjustment information, and send the generated current control signals and potential adjustment control signals to the corresponding data drive sub-circuit of each device group.

[0137] For example, combined Figure 3 , Figures 13 to 15 As shown, processor 11221 can generate a drive control signal PWM1 and current amplitude control information corresponding to the first color light-emitting device 1111 based on the received pixel data information Rda, and generate potential adjustment information corresponding to the first color light-emitting device 1111 based on the pre-stored potential compensation time corresponding to the first color light-emitting device 1111; processor 11221 can generate a drive control signal PWM2 and current amplitude control information corresponding to the second color light-emitting device 1112 based on the received pixel data information Gda, and generate potential adjustment information corresponding to the second color light-emitting device 1112 based on the pre-stored potential compensation time corresponding to the second color light-emitting device 1112; processor 11221 can generate a drive control signal PWM3 and current amplitude control information corresponding to the third color light-emitting device 1113 based on the received pixel data information Bda, and generate potential adjustment information corresponding to the third color light-emitting device 1113 based on the pre-stored potential compensation time corresponding to the third color light-emitting device 1113.

[0138] Subsequently, processor 11221 sends drive control signal PWM1 to data drive sub-circuit 11211, drive control signal PWM2 to data drive sub-circuit 11212, and drive control signal PWM3 to data drive sub-circuit 11213. It also sends current amplitude control information and potential adjustment information corresponding to each color light-emitting device to control circuit 11222. Control circuit 11222 can generate current control signals DAC1, DAC2, and DAC3 based on the current amplitude control information, and generate potential adjustment control signals OVS1, OVS2, and OVS3 based on the potential adjustment information. Then, control circuit 11222 can send current control signal DAC1 and potential adjustment control signal OVS1 to data drive sub-circuit 11211, current control signal DAC2 and potential adjustment control signal OVS2 to data drive sub-circuit 11212, and current control signal DAC3 and potential adjustment control signal OVS3 to data drive sub-circuit 11213.

[0139] The potential adjustment circuit 112113 in the data driving sub-circuit 11211 can receive the potential adjustment control signal OVS1, and in response to the effective level of the potential adjustment control signal OVS1, can connect the negative terminal of the first color light-emitting device 1111 to the reference voltage terminal O6. The constant current source circuit 112112 can receive the current control signal DAC1 corresponding to the first color light-emitting device 1111, and output a current IL1 with a constant amplitude corresponding to the received current control signal DAC1. The modulation circuit 112111 can receive the drive control signal PWM1 corresponding to the first color light-emitting device 1111, and input the current IL1 generated by the constant current source circuit 112112 to the coupled output terminal O1 according to the effective level (e.g., high level) of the received drive control signal PWM1, so as to control the first positive signal line to form an electrical circuit at least sequentially through the first color light-emitting device 1111, the output terminal O1 of the driving element 112, and the reference voltage terminal O6 during the working period, so as to make the first color light-emitting device 1111 emit light. In this way, the brightness and duration of the first color light-emitting device 1111 within the display subframe can be controlled by the combination of the drive control signal PWM1, the current control signal DAC1, and the potential adjustment control signal OVS1.

[0140] The potential adjustment circuit 112123 in the data drive sub-circuit 11212 can receive the potential adjustment control signal OVS2, and in response to the effective level of the potential adjustment control signal OVS2, can connect the negative terminal of the second color light-emitting device 1112 to the reference voltage terminal O6. The constant current source circuit 112122 can receive the current control signal DAC2 corresponding to the second color light-emitting device 1112, and output a current IL2 with a constant amplitude corresponding to the received current control signal DAC2. The modulation circuit 112121 can receive the drive control signal PWM2 corresponding to the second color light-emitting device 1112, and input the current IL2 generated by the constant current source circuit 112122 to the coupled output terminal O2 according to the effective level (e.g., high level) of the received drive control signal PWM2, so as to control the second positive signal line to form an electrical circuit at least sequentially through the second color light-emitting device 1112, the output terminal O2 of the drive element 112, and the reference voltage terminal O6 during the working period, so as to make the second color light-emitting device 1112 emit light. In other words, the effective duration of the drive control signal PWM2 can be considered as the working period of the second color light-emitting device 1112. Thus, the brightness and duration of the second color light-emitting device 1112 within a display subframe can be controlled by combining the drive control signal PWM2, the current control signal DAC2, and the current control signal DAC2.

[0141] The potential adjustment circuit 112133 in the data drive sub-circuit 11213 can receive the potential adjustment control signal OVS3, and in response to the effective level of the potential adjustment control signal OVS3, can connect the negative terminal of the third color light-emitting device 1113 to the reference voltage terminal O6. The constant current source circuit 112132 can receive the current control signal DAC3 corresponding to the third color light-emitting device 1113, and output a current IL3 with a constant amplitude corresponding to the received current control signal DAC3. The modulation circuit 112131 can receive the drive control signal PWM3 corresponding to the third color light-emitting device 1113, and input the current IL3 generated by the constant current source circuit 112132 to the coupled output terminal O3 according to the effective level (e.g., high level) of the received drive control signal PWM3, so as to control the second positive signal line to form an electrical circuit at least sequentially through the third color light-emitting device 1113, the output terminal O3 of the drive element 112, and the reference voltage terminal O6 during the working period, so as to make the third color light-emitting device 1113 emit light. In other words, the effective duration of the drive control signal PWM3 can be considered as the working period of the third color light-emitting device 1113. Thus, the brightness and duration of the third color light-emitting device 1113 within the display sub-frame can be controlled by combining the drive control signal PWM3, the current control signal DAC3, and the current control signal DAC3.

[0142] In some embodiments of this disclosure, the potential compensation time can be stored in the processor 11221. To reduce the storage requirements of the processor 11221, the control circuit can, exemplarily, store the potential compensation time of the device group corresponding to each driving element 112 coupled thereto. For example, the system circuit stores the potential compensation time of the device group corresponding to each driving element 112 coupled thereto. Furthermore, when the electronic device is powered on, the system circuit sends the potential compensation time of the device group corresponding to each driving element 112 to each driving element 112. The driving element 112 can receive and store the potential compensation time sent by the system circuit when the electronic device is powered on, and clear the stored potential compensation time when the electronic device is powered off. Exemplarily, the system circuit can send the potential compensation time of the device group corresponding to each driving element 112 to each driving element 112 in the display frame F0, and the driving element 112 receives and stores the potential compensation time sent by the system circuit in the display frame F0.

[0143] In some embodiments of this disclosure, such as Figure 13As shown, each driving element 112 may further include at least one of the following: an interface circuit 1123, a reference voltage circuit 1124, a decoder circuit 1125, a voltage regulator circuit 1126, and an electrostatic discharge (ESD) protection circuit 1127. The reference voltage circuit 1124 can determine a fixed reference voltage. The ESD protection circuit 1127 can be coupled to the address signal terminal O5 and the reference voltage terminal O6 respectively, thus providing ESD protection for the supply voltage VCC input to the address signal terminal O5 and the reference voltage VSS input to the reference voltage terminal O6. The voltage regulator circuit 1126 can be coupled to the address signal terminal O5 and can regulate the supply voltage VCC input to the address signal terminal O5. The decoder circuit 1125 can identify the address carried in the driving data sent by the logic control circuit, and when the corresponding address is identified, outputs a data receiving signal to the interface circuit 1123 coupled to the driving signal terminal O4. After receiving a data receiving signal, interface circuit 1123 receives driving data, decodes the received driving data, and provides it to processing control circuit 1122, so that processing control circuit 1122 generates a light-emitting control signal based on the driving data. Driving element 112 can receive the supply voltage VCC through address signal terminal O5 and input the received supply voltage VCC into interface circuit 1123. Interface circuit 1123 can decode the received supply voltage and provide it to processing control circuit 1122 and data driving circuit 1121 to power them. Interface circuit 1123 can also decode the received supply voltage and provide it to reference voltage circuit. Reference voltage circuit can generate a reference voltage based on the received supply voltage. Furthermore, driving data can be decoded by interface circuit 1123 and provided to processor 11221 in processing control circuit 1122, so that processor 11221 generates driving control signal and current control signal based on the decoded driving data.

[0144] The following combination Figure 3 , Figures 8 to 11 ,as well as Figures 13 to 17 The working process of the electronic device in the embodiments of this disclosure will be described in detail. For example, the light emission period is taken as a display subframe.

[0145] When the electronic device is powered on, display frame F0 may not display any image, for example, a black screen. During display frame F0, stages t0, t1, and t2 are executed sequentially. The processes of stages t0 and t1 are as described above and will not be repeated here. In stage t2, the 16-bit reserved control instruction bits P2+P3 and / or 16-bit reserved control instruction bits P4+P5 in the current setting information Co can carry the potential compensation time corresponding to the first color light-emitting device 1111, the second color light-emitting device 1112, and the third color light-emitting device 1113, respectively. This allows the processor 11221 to store the received potential compensation time.

[0146] It should be noted that the aforementioned potential compensation time can be determined by testing before the electronic device leaves the factory. For example, a method for determining the potential compensation time can be as follows: control each light-emitting device in the display panel to present a specific grayscale (a pre-set grayscale, for example, a low grayscale). By taking pictures of the illuminated display panel with a camera, the original brightness data of various locations on the display panel can be collected. Furthermore, the original brightness of the same specific grayscale presented by each light-emitting device can be divided into multiple intervals, each interval having a mapping relationship with a potential compensation time. For a specific grayscale, the corresponding interval can be found based on the original brightness data of each light-emitting device, thereby determining the potential compensation time corresponding to each light-emitting device. For example, when displaying the same specific grayscale, the original brightness presented by each light-emitting device can be divided into 8 intervals: L0-L1, L1-L2, L2-L3, L3-L4, L4-L5, L5-L6, L6-L7, L7-L8. The brightness range L0-L1 corresponds to a potential compensation time of 0 ns, L1-L2 to 5 ns, L2-L3 to 10 ns, L3-L4 to 20 ns, L4-L5 to 40 ns, L5-L6 to 50 ns, L6-L7 to 60 ns, and L7-L8 to 70 ns. If the original brightness data of the light-emitting device when displaying a specific grayscale corresponds to a brightness within the L6-L7 range, then the potential compensation time for that light-emitting device when displaying that specific grayscale can be determined to be 60 ns. Accordingly, the determined potential compensation time for each light-emitting device when displaying a specific grayscale is stored, for example, in system circuit 300.

[0147] This disclosure also provides a display driving method, which can be applied to the aforementioned electronic device. The display driving method may include: controlling the positive signal line to form an electrical circuit with the reference voltage terminal of the driving element during a working period of one light-emitting cycle. Specifically, before the working period of the light-emitting cycle, the potential of the second terminal of the device group coupled to the driving element is adjusted. It should be noted that the working principle and specific implementation of this display driving method are basically the same as the working principle and specific implementation of the electronic device in the above embodiments. Therefore, the working method of this display driving method can be implemented by referring to the specific implementation of the electronic device in the above embodiments, and will not be repeated here.

[0148] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0149] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0150] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0151] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0152] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0153] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An electronic device, comprising: Multiple device groups and multiple driving elements; At least one of the plurality of device groups has its first terminal coupled to a positive signal line, and its second terminal is coupled to the output terminal of any one of the plurality of driving elements. The reference voltage terminal of any one of the plurality of driving elements is configured to be coupled to a reference signal line. Any one of the plurality of driving elements is configured to: control the positive signal line and its reference voltage terminal to form an electrical circuit during a working period of one light emission cycle; and, before the working period of the light emission cycle, adjust the potential of the second terminal of the device group coupled thereto, and control the second terminal of the device group coupled thereto to conduct with the reference voltage terminal for a first compensation time; and, during the working period, control the second terminal of the device group coupled thereto to conduct with the reference voltage terminal for a second compensation time. Wherein, for at least one of the plurality of device groups, the second compensation time corresponding to the device group is less than the first compensation time.

2. The electronic device as claimed in claim 1, wherein, Any one of the plurality of driving elements is further configured to: at the end of the first compensation time, control the positive signal line to form an electrical circuit at least sequentially via the device group coupled to the driving element, the output terminal of the driving element, and the reference voltage terminal.

3. The electronic device as claimed in claim 1, wherein, The first compensation time and the second compensation time are consecutive time periods.

4. The electronic device as claimed in claim 1, wherein, For at least one of the plurality of device groups, the second compensation time corresponding to the device group is less than half of the first compensation time.

5. The electronic device as claimed in claim 4, wherein, The at least one device group includes multiple devices; Each of the plurality of devices has its own corresponding first compensation time and second compensation time, and the second compensation time corresponding to each of the plurality of devices is less than half of the first compensation time.

6. The electronic device as claimed in claim 5, wherein, At least two of the plurality of devices correspond to different first compensation times; wherein the device with the larger first compensation time corresponds to a larger second compensation time.

7. The electronic device as claimed in claim 5, wherein, At least some of the plurality of devices have the same second compensation time.

8. The electronic device according to any one of claims 2-7, wherein, Any one of the plurality of driving elements is further configured to: control the second terminal of the device group coupled to it to conduct the potential compensation time with its reference voltage terminal according to the pre-stored potential compensation time corresponding to the device group coupled to it; wherein the potential compensation time is the first compensation time; or, the potential compensation time is the sum of the first compensation time and the second compensation time.

9. The electronic device as claimed in claim 8, wherein, Any one of the plurality of driving elements includes: a processing control circuit and a data driving circuit; the data driving circuit is coupled to the processing control circuit, the output terminal and the reference voltage terminal respectively. The processing control circuit is configured to generate a light emission control signal during the light emission cycle and send the light emission control signal to the data driving circuit; and to generate a potential adjustment control signal according to the potential compensation time and send the potential adjustment control signal to the data driving circuit. The data driving circuit is configured to, during the light emission cycle, control the positive signal line to sequentially form an electrical circuit via a device group coupled to the driving element, the output terminal of the driving element, and a reference voltage terminal according to the received light emission control signal; and control the second terminal of the corresponding device group to be connected to its reference voltage terminal according to the effective level of the received potential adjustment control signal; wherein the effective level duration of the potential adjustment control signal corresponding to the device group is the potential compensation time.

10. The electronic device of claim 9, wherein, The data driving circuit includes: at least one data driving sub-circuit; one of the data driving sub-circuits is coupled to one of the output terminals; The data driving sub-circuit is configured to receive a light emission control signal and a potential adjustment control signal corresponding to the coupled device group, and, in response to the light emission control signal, control the positive signal line to form an electrical loop sequentially via the device group coupled to the driving element, the output terminal of the driving element, and the reference voltage terminal; and, in response to the potential adjustment control signal, control the second terminal of the coupled device group to be connected to its reference voltage terminal.

11. The electronic device of claim 10, wherein, The light emission control signal includes a drive control signal and a current control signal; The data driving sub-circuit includes: a modulation circuit, a constant current source circuit, and a potential adjustment circuit; wherein, the constant current source circuit is coupled to the processing control circuit and the modulation circuit respectively, and the modulation circuit is coupled to the corresponding output terminal; the potential adjustment circuit is coupled to the processing control circuit and the corresponding output terminal respectively. The constant current source circuit is configured to receive the current control signal of the corresponding device group, and output a current with a constant amplitude corresponding to the received current control signal. The modulation circuit is configured to receive the drive control signal of the corresponding device group, and according to the effective level of the received drive control signal, to couple the current generated by the constant current source circuit to the output terminal, so as to control the positive signal line to form an electrical circuit at least sequentially through the device group coupled to the drive element, the output terminal of the drive element, and the reference voltage terminal during the working time period. The potential adjustment circuit is configured to receive a potential adjustment control signal for the corresponding device group, and control the second terminal of the coupled device group to be connected to its reference voltage terminal according to the received potential adjustment control signal.

12. The electronic device according to any one of claims 9-11, wherein, The electronic device further includes: a control circuit; the control circuit is coupled to the plurality of driving elements respectively; The control circuit is configured to store the potential compensation time of the device group corresponding to each of the coupled driving elements; and to send the potential compensation time of the device group corresponding to each of the driving elements to each driving element when the electronic device is powered on. The driving element is configured to receive and store the potential compensation time sent by the system circuit when the electronic device is powered on, and to clear the stored potential compensation time when the electronic device is powered off.

13. The electronic device of claim 12, wherein, The drive signal terminal of any one of the plurality of drive elements is configured to be coupled to the drive signal line; The control circuit is also configured to be coupled to the drive signal line and stores the addresses of each of the coupled drive elements; And transmit drive data carrying the address corresponding to the drive element to the drive signal line; The driving element is further configured to receive the driving data and generate the light emission control signal based on the driving data when the corresponding address in the driving data is identified.

14. The electronic device of claim 13, wherein, The addressing signal terminal of any one of the plurality of driving elements is configured to be coupled to the addressing signal line; The control circuit is also configured to be coupled to the address signal line and to input a power supply voltage to the address signal line; The driving element is also configured to receive the supply voltage via the addressing signal terminal.

15. A display driving method applied to an electronic device, the electronic device comprising a plurality of device groups and a plurality of driving elements; The display driving method includes: The control positive signal line and its reference voltage terminal form an electrical circuit within the working time period of one light-emitting cycle; Specifically, before the working time period of the light emission cycle, the potential of the second terminal of the device group coupled thereto is adjusted, and the second terminal of the device group coupled thereto is controlled to conduct with the reference voltage terminal for a first compensation time; and during the working time period, the second terminal of the device group coupled thereto is controlled to conduct with the reference voltage terminal for a second compensation time. Wherein, for at least one of the plurality of device groups, the second compensation time corresponding to the device group is less than the first compensation time.

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