A data readout module and design method for processing data with odd bit streams
By designing odd-number stream data segmentation and gating modules, the problems of large storage capacity and high circuit complexity of odd-number bit stream data readout modules were solved, achieving high-frequency data readout and hardware optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2023-10-12
- Publication Date
- 2026-07-03
AI Technical Summary
Existing technologies for designing odd bitstream data readout modules have large storage capacities, low processing frequencies, and high circuit complexity, making it difficult to achieve high-frequency data output.
By employing an odd-number stream data segmentation module and a gating module, data is stored in blocks through registers, and data filtering is performed using counters and state machines. A reasonable storage and data flow scheme is designed to reduce data stacking and logic circuit complexity.
It achieves high-frequency data readout, reduces hardware circuit area and power consumption, improves circuit operability and optimizes hardware performance.
Smart Images
Figure CN117420954B_ABST
Abstract
Description
Technical Field
[0001] This invention proposes a data readout module and design method for processing odd bit streams, belonging to the field of algorithms and digital circuits. Background Technology
[0002] The design of a data readout module with odd-bit streams currently involves two steps: data flow scheme design and hardware circuit design. Data flow scheme design typically involves determining the corresponding data storage and data flow allocation schemes based on the structure of the input data and the requirements of the output data. This is mainly divided into three aspects: module interface, module function, and module timing. From the module interface perspective, the interface includes input and output ports, representing the data bandwidth. From the module function perspective, this data readout module designs a corresponding number of register sets based on a clear understanding of the input and output data bit widths, outputting data according to the interface scheme. From the module timing perspective, the input data is generated into a two-dimensional array containing all data, which is then sequentially input into registers for data storage. Based on the output data requirements, the data is filtered and output sequentially.
[0003] The current mainstream design for odd-bit data readout modules involves stacking all the data into registers. This approach has some shortcomings in data block processing, although its advantage is the simplicity of the code implementation. However, from a macroscopic perspective, the amount of data stored in memory becomes enormous. Data processing requires iterating through each bit sequentially and performing a simple operation, significantly reducing the data processing frequency and increasing the complexity of the combinational logic circuit. This results in a poorly performing synthesized circuit and makes it difficult to achieve high-frequency data output. Summary of the Invention
[0004] To address the shortcomings of the existing technology, the present invention aims to provide a data readout module and design method for processing odd bit streams, used for data readout from a chip.
[0005] The technical solution adopted by the module of this invention is as follows:
[0006] A data readout module for processing odd-bit streams includes an odd-bit stream data segmentation module and an odd-bit stream data gating module. The odd-bit stream data segmentation module, during odd-bit stream data readout, designs a data storage scheme based on the number of input data bits and the output data, and reassembles and segments the data into blocks. The odd-bit stream data gating module, based on the segmented data output by the odd-bit stream data segmentation module, selects data links according to a data filtering method and outputs a data stream.
[0007] Furthermore, the odd-numbered stream data segmentation module is equipped with a register with a corresponding number of data bits as the input data to store the data. At the same time, it has a built-in first register rBitIndex and a second register rCounterIndex to count the data segments. The number of data bits in the first register rBitIndex is determined by the smallest unit of the data bit stream, and the number of data bits in the second register rCounterIndex is the ratio of the number of bits in a data segment to the smallest unit of the data bit stream.
[0008] Furthermore, the odd-number stream data gating module includes a counter and a state machine. The counter sets a counting period according to different data filtering modes. The working modes of the state machine include standby mode, frame header mode, data mode, and frame tail mode.
[0009] Furthermore, in data mode, the odd-stream data gating module determines the data filtering mode and starting point of the odd-stream data gating module based on three data filtering signals: the downsampling mode signal RG_SampleMode, the downsampling X-axis starting point signal RG_SampleSubParamX, and the downsampling Y-axis starting point signal RG_SampleSubParamY.
[0010] Furthermore, the data filtering modes include full sampling, 2x downsampling, 4x downsampling, and 8x downsampling.
[0011] The present invention utilizes the above-mentioned design method for a data reading module with an odd number of bit streams. The method includes the following steps: S1, designing a data storage scheme based on the number of input data bits and output data, and reorganizing and dividing the data into blocks; S2, selecting the data link and outputting the data stream based on the block data and data filtering method in step S1.
[0012] Furthermore, the specific steps of step S1 include:
[0013] S11, based on the number of bits of the input data stream and the output data stream, define the number of input data bits as l and the number of output data bits as n, set n as the number of data blocks required for the block, and set l / n as the number of data bits for each data block;
[0014] S12, based on the characteristics of the input data stream, the smallest unit of the data bit stream is defined as k. If k is an odd number, then the total number of counter bits in the data block is k. The ratio of the number of data bits l / n in each data block to k is defined as the number of counters required for each data block.
[0015] S13, group the counters in the data block Block, with j counters as a group, and divide them into l / (n*k*j) groups in total, and define i = l / (n*k*j).
[0016] Furthermore, the specific steps of step S2 include:
[0017] S21, based on the input data filtering signal, confirm the data filtering method and the number of bits for each data block;
[0018] S22, select to enter frame header mode or frame tail mode based on the frame header and frame tail signals at the current line's read position;
[0019] S23. Based on the filtering method confirmed in step S21 and the mode selected in step S22, the data in all data blocks is traversed and collected. When the counter accumulates to the value equal to the number of bits in each data block, the traversal ends.
[0020] S24, according to the data stream output requirements, output the collected data to the corresponding data interface according to the output mode requirements.
[0021] Furthermore, in step S22, when entering the frame header mode, the working state of this mode lasts only one clock cycle before switching to the data mode to start transmitting all lines of data until the current frame transmission ends; when entering the frame tail mode, frame tail information is output to distinguish frames.
[0022] Furthermore, the data mode specifically refers to: determining the data filtering mode and starting point of the module based on three data filtering signals: the downsampling mode signal RG_SampleMode, the downsampling X-axis starting point signal RG_SampleSubParamX, and the downsampling Y-axis starting point signal RG_SampleSubParamY.
[0023] In the sub-module design of the data readout module of this invention, data can be divided and reorganized into blocks according to the input and output data requirements, instead of directly generating a two-dimensional array containing all data, which would increase storage capacity. This allows for a more reasonable arrangement of registers to cache the data, facilitating subsequent high-frequency data stream selection. Blocking the data reduces data stacking, eliminates the need to handle massive amounts of data, reduces the complexity of combinational logic circuits, and makes hardware circuitry easier and more convenient to implement, increasing the operability of the circuit. Therefore, during data readout, this invention can formulate reasonable storage and data flow schemes for odd-numbered bit streams, enabling high-frequency data readout while implementing complex data flow processing in subsequent hardware circuitry. Furthermore, block division minimizes the area of the implemented hardware circuitry, significantly reducing hardware costs and achieving functional implementation and hardware optimization of the data readout module. Attached Figure Description
[0024] Figure 1 This is a diagram illustrating the storage scheme and data flow allocation scheme based on input and output data requirements in an embodiment of the present invention;
[0025] Figure 2 This is a block diagram of the data reading module for processing odd bit streams in an embodiment of the present invention;
[0026] Figure 3 This is a pseudocode flowchart of the odd stream data block segmentation module (GrayReorder_Block) in an embodiment of the present invention;
[0027] Figure 4 This is a pseudocode flowchart of the odd stream data gating module (GrayReorder) in an embodiment of the present invention;
[0028] Figure 5 This is a comprehensive simulation report of the hardware implementation area in the embodiments of the present invention. Detailed Implementation
[0029] This embodiment provides a data readout module for processing odd-numbered bitstreams, as shown in the module block diagram below. Figure 2As shown, it includes an odd-stream data blocking module (GrayReorder_Block) and an odd-stream data gating module (GrayReorder). To design a data readout module capable of real-time processing of large data bandwidth, the odd-stream data blocking unit is designed based on the module's input signal requirements and output requirements. It calculates the data storage scheme and data stream allocation scheme, and efficiently selects the data stream according to the given functional requirements. The odd-stream data gating unit is designed to achieve macroscopic data stream processing, relying on the data streams generated by the sub-modules and state machine sub-modules to package the data and output the data according to the defined interface scheme. This embodiment uses the following parameters and indicators as examples: the input data is 112640 bits, with each data unit being 11 bits. It needs to be transmitted out at a clock frequency of 100MHz, with 256 bits per clock cycle. The data filtering function includes downsampling data filtering, with four downsampling modes: 1x downsampling, 2x downsampling, 4x downsampling, and 8x downsampling. The output data requirement is four groups of 64-bit data, totaling 256 bits.
[0030] The specific block-splitting process is as follows:
[0031] First, given that the input data rData has a total of n*i*j*k = 112640 bits and the output data wData has a total of n = 256 bits, rData is divided into 256 data blocks, requiring 256 sub-modules GrayReorder_Block. Each GrayReorder_Block contains 112640 / 256 = 440 bits of data, meaning the bit width of the rGrayData data in the input data block is i*j*k = 440. Second, since the smallest unit of data is k = 11 bits and the highest downsampling mode is j = 8x downsampling, the data rGrayData in each data block is further divided into 8 intermediate blocks rBlock. Each rBlock is further divided into i = 5 sub-blocks sBlock, and each sBlock contains 11 bits of data, such as... Figure 1As shown. Therefore, the GrayReorder_Block module contains a 440-bit register for data storage. In addition, it includes the rBitIndex and rCounterIndex registers, which are used to count the blocks within a block. Each block consists of 440 bits, or 40 11-bit counters. To achieve an 8x downsampling rate, the 440 bits are divided into 5x8x11 bits. The number of bits in the rBitIndex register is determined by the smallest unit of the data bitstream. The 11 bits of data in each sub-block (sBlock) are sampled from the least significant bit to the most significant bit. The number of bits in the rCounterIndex register is the ratio of the number of bits in a data block to the smallest unit of the data bitstream. This process involves sampling 40 sets of data from the GrayReorder_Block. Taking full resolution as an example, rCounterIndex is iterated. When rCounterIndex finishes one cycle of counting, rBitIndex increments by 1, meaning it jumps from bit 0 to bit 1 of the 11-bit data set. The corresponding rCounterIndex and rBitIndex are passed into all blocks. The blocks will perform 440-bit data filtering based on the filtering index. Each block transmits 1 bit of data per clock cycle. The output data duration depends on the sampling function.
[0032] After the 256 sub-modules GrayReorder_Block are ready, they are imported into the odd-stream data gating module (GrayReorder). The odd-stream data gating module includes a counter rReorderCounter and a state machine FSM. The counter rReorderCounter can be set with a counting period according to different operating modes. For example, if full-resolution sampling is set, the counting period is the number of bits in one data block. The state machine has four operating modes: standby mode, frame header mode, data mode, and frame tail mode. First, the GrayReorder module needs to receive the frame header and frame tail signals Frame from the previous module as the basis for determining the current row's read position. When the Frame output is a frame header, the GrayReorder module will enter frame header mode from standby. The frame header mode lasts for only one clock cycle before jumping to data mode to start transmitting all rows of data. When the frame transmission is finished and the Frame data is a frame tail, the GrayReorder module will jump to frame tail mode and output frame tail information to distinguish the frame. The workflow in data mode is as follows: Based on the three data filtering signals RG_SampleMode (downsampling mode signal), RG_SampleSubParamX (downsampling X-axis start signal), and RG_SampleSubParamY (downsampling Y-axis start signal), the module's data filtering mode and start point are determined, and the value of the collected data packet Gray_Packet is also determined accordingly. Data filtering modes include full sampling, 2x downsampling, 4x downsampling, and 8x downsampling. The number of data bits required for each data block is determined according to the downsampling mode. Taking 4x downsampling as an example, the value of Gray_Packet is 440 / 4 = 110. Therefore, the final count value of the module's built-in counter rReorderCounter is also 110. The register rCounterIndex will begin traversing the data in the submodule GrayReorder_Block, starting from the first position of the first subblock sBlock out of 40 subblocks, with a step size of 4 to obtain the fifth... The first bit of each sub-block sBlock is traversed, and so on. After the register rCounterIndex counts from 1 to 40 in steps of 4, the traversal of the second bit of the data in the first sub-block sBlock is restarted. When rBitIndex = 11, rCounterIndex = 40, and rReorderCounter = 110, the traversal ends. When all 256 data blocks have completed data downsampling, 256 bits of grayscale data are sent to four 64-bit data interfaces through four 64-bit signals in each clock cycle. This completes all the functions of the data readout module in this example.
[0033] The comprehensive simulation report for this example is as follows: Figure 5 As shown, the total hardware area used by this module to achieve a clock frequency of 100MHz under the conditions of the XMC55 process library is 1,836,576 μm. 2 With a total power consumption of 135mW, compared with other data readout design methods, this invention not only greatly reduces the chip area, but also reduces power consumption and latency, and optimizes and improves the entire hardware implementation.
Claims
1. A data readout device for processing odd-numbered bit streams, characterized in that, The device includes an odd-stream data segmentation module and an odd-stream data gating module; The odd-number stream data segmentation module is used to design a data storage scheme and reassemble and segment the data when reading out odd-number bit stream data, based on the number of bits of input data and output data. The odd-number stream data gating module is used to select data links and output data streams based on the block data output by the odd-number stream data segmentation module and according to the data filtering method. The data readout device is designed through the following steps: S1. Based on the number of bits in the input data and the output data, design a data storage scheme and reorganize and divide the data into blocks; specific steps include: S11, Define the number of input data bits based on the number of bits in the input and output data streams. l The output data bits are n. Set n to the number of data blocks required for the desired data partitioning. l / n sets the number of bits of data per block; S12, Based on the characteristics of the input data stream, the smallest unit of the data bit stream is defined as k, where k is an odd number. Therefore, the total number of counter bits in a data block is k, and the number of data bits in each data block is k. l The ratio of / n to k is defined as the number of counters required for each data block; S13, group the counters in the data block, with j counters forming a group, for a total of... l Groups of / (n*k*j), defined i= l / (n*k*j); S2, based on the data block segmentation and data filtering method in step S1, selects the data link and outputs the data stream; specific steps include: S21, based on the input data filtering signal, confirm the data filtering method and the number of bits for each data block; S22, select to enter frame header mode or frame tail mode based on the frame header and frame tail signals at the current line's read position; S23. Based on the filtering method confirmed in step S21 and the mode selected in step S22, the data in all data blocks is traversed and collected. When the counter accumulates to the value equal to the number of bits in each data block, the traversal ends. S24, according to the data stream output requirements, output the collected data to the corresponding data interface according to the output mode requirements.
2. The data readout device for processing odd-numbered bit streams according to claim 1, characterized in that, The odd-numbered stream data segmentation module is equipped with a register with a corresponding number of bits for the input data to store the data. It also has a built-in first register rBitIndex and a second register rCounterIndex to count the data segments. The number of bits in the first register rBitIndex is determined by the smallest unit of the data bit stream, and the number of bits in the second register rCounterIndex is the ratio of the number of bits in a data segment to the smallest unit of the data bit stream.
3. The data readout device for processing odd-numbered bit streams according to claim 1, characterized in that, The odd-number stream data gating module includes a counter and a state machine. The counter sets the counting period according to different data filtering modes. The working modes of the state machine include standby mode, frame header mode, data mode, and frame tail mode.
4. The data readout device for processing odd-numbered bit streams according to claim 3, characterized in that, In data mode, the odd-stream data gating module determines the data filtering mode and starting point based on three data filtering signals: the downsampling mode signal RG_SampleMode, the downsampling X-axis starting point signal RG_SampleSubParamX, and the downsampling Y-axis starting point signal RG_SampleSubParamY.
5. The data readout device for processing odd-numbered bit streams according to claim 4, characterized in that, The data filtering modes include full sampling, 2x downsampling, 4x downsampling, and 8x downsampling.
6. The data readout device for processing odd-numbered bit streams according to claim 1, characterized in that, In step S22, when entering the frame header mode, the working state of this mode lasts only one clock cycle before switching to the data mode and starting to transmit all lines of data until the current frame transmission ends. When entering frame end mode, frame end information is output to distinguish frames.
7. The data readout device for processing odd-numbered bit streams according to claim 6, characterized in that, The data mode is specifically determined by three data filtering signals: the downsampling mode signal RG_SampleMode, the downsampling X-axis start signal RG_SampleSubParamX, and the downsampling Y-axis start signal RG_SampleSubParamY.