Display panel, driving method thereof and display device

Abstract

Embodiments of the present application disclose a display panel, a driving method thereof and a display device. The display panel comprises a plurality of pixel units, a data driver and a plurality of data lines. The data driver comprises a plurality of driving modules, and each driving module is connected with a data line. Each driving module comprises a digital-to-analog conversion unit and an output control unit. The digital-to-analog conversion unit is used for converting display data into display analog voltage. The output control unit is used for transmitting the display analog voltage to the corresponding data line in a first display mode, and transmitting the display analog voltage and a pixel-off voltage to the corresponding data line in a second display mode in time division, so that the pixel units in the same row and / or the same column are alternately turned on and off. According to the present application, the PPI of the display panel can be flexibly selected according to the display mode, and the display analog voltage and the pixel-off voltage are transmitted in time division by the driving module in the data driver, so that the PPI of the display panel is reduced, and the display power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel, its driving method, and a display device. Background Technology

[0002] With the continuous development of display technology, the display functions of display panels are becoming increasingly rich and diverse, and high PPI (Pixels Per Inch), high refresh rate and high brightness have become a trend.

[0003] The downside of optimizing the display function is that power consumption increases accordingly. Currently, the batteries of existing mobile devices cannot support the use of the device for a long time, resulting in short standby time and severely reducing the user experience. Summary of the Invention

[0004] This invention provides a display panel, its driving method, and a display device to reduce display power consumption.

[0005] According to one aspect of the present invention, a display panel is provided, comprising:

[0006] Multiple pixel units;

[0007] The data driver includes multiple data cables. The data driver consists of multiple driver modules, which are connected to the corresponding data cables.

[0008] The driving module includes a digital-to-analog converter unit and an output control unit. The digital-to-analog converter unit is connected to the output control unit. The digital-to-analog converter unit is used to convert display data into display analog voltage. The output control unit is used to transmit the display analog voltage to the corresponding data line in the first display mode, and to transmit the off pixel voltage and display analog voltage to the corresponding data line in a time-division manner in the second display mode, so that multiple pixel units in the same row and / or the same column alternately turn on and off.

[0009] Optionally, the output control unit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the pixel-killing voltage, the first terminal of the second transistor is connected to the output terminal of the digital-to-analog converter, and the second terminals of the first transistor and the second transistor are connected to the same data line. The gate of the first transistor in the odd-numbered output control unit is connected to the first control signal line, the gate of the second transistor in the odd-numbered output control unit is connected to the second control signal line, the gate of the first transistor in the even-numbered output control unit is connected to the third control signal line, and the gate of the second transistor in the even-numbered output control unit is connected to the fourth control signal line.

[0010] The first transistor and the second transistor are configured to be turned on alternately in the second display mode, and the first transistor is also configured to remain off in the first display mode;

[0011] Optionally, one of two adjacent pixel units is in a bright state and the other is in a dark state;

[0012] Optionally, the first transistor and the second transistor have the same channel type.

[0013] Optionally, the output control unit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the pixel-kill voltage, and the first terminal of the second transistor is connected to the output terminal of the digital-to-analog converter. The second terminals of the first transistor and the second transistor are connected to the same data line. In the odd-numbered output control units, the gates of the first transistor and the second transistor are both connected to the first control signal line, and in the even-numbered output control units, the gates of the first transistor and the second transistor are both connected to the second control signal line. The first transistor and the second transistor have different channel types.

[0014] Optionally, in the second display mode, both the first control signal transmitted on the first control signal line and the second control signal transmitted on the second control signal line are pulse signals.

[0015] Optionally, the time interval for the first transistor to switch from the on state to the off state is the row scan time.

[0016] Optionally, at least part of the display analog voltage is multiplexed as pixel-killing voltage.

[0017] Optionally, the selection precision of the pixel voltage is greater than or equal to 1 bit.

[0018] Optionally, the drive module also includes a multiplexer connected to the output control unit, which is used to select one output pixel voltage.

[0019] Optionally, the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The multiple data lines are divided into multiple data line groups. Each data line group includes a first data line, a second data line, and a third data line. The first data line, the second data line, and the third data line are arranged along a first direction and extend along a second direction. The first direction and the second direction intersect.

[0020] Optionally, the display panel also includes multiple pixel circuits, with each sub-pixel connected to a corresponding pixel circuit;

[0021] Optionally, in the same pixel unit, the first data line is connected to the pixel circuit corresponding to the first sub-pixel or the third sub-pixel, the second data line is connected to the pixel circuit corresponding to the second sub-pixel, and the third data line is connected to the pixel circuit corresponding to the third sub-pixel or the first sub-pixel; wherein the first data line and the third data line are connected to the pixel circuits corresponding to different sub-pixels.

[0022] Optionally, the first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors.

[0023] Optionally, the display panel also includes multiple scan lines, which are arranged along a second direction and extend along a first direction. The scan lines are used to control the write of the pixel-killing voltage or display analog voltage transmitted on the data line to the corresponding pixel circuit during the line scanning time.

[0024] According to another aspect of the present invention, a display device is provided, which includes a display panel provided in any embodiment of the present invention.

[0025] According to another aspect of the present invention, a driving method for a display panel is provided. The display panel includes: a plurality of pixel units, a data driver and a plurality of data lines. The plurality of pixel units are arranged in an array. The data driver includes a plurality of driving modules. The driving modules are connected to the data lines one by one. The driving modules include a digital-to-analog conversion unit and an output control unit. The digital-to-analog conversion unit is connected to the output control unit.

[0026] The driving methods for the display panel include:

[0027] In the first display mode, the control output control unit transmits the display analog voltage output by the digital-to-analog converter to the corresponding data line;

[0028] In the second display mode, the control output control unit transmits the pixel voltage and display analog voltage to the corresponding data lines in a time-division manner, so that multiple pixel units in the same row and / or the same column alternately turn on and off.

[0029] The technical solution provided in this invention includes a driving module comprising a digital-to-analog converter (DAC) and an output control unit. The DAC is connected to the output control unit. The DAC converts display data into display analog voltages. The output control unit transmits the display analog voltages to the corresponding data lines in a first display mode, and transmits the pixel-off voltage and the display analog voltages to the corresponding data lines in a time-division multiplexing manner in a second display mode, so that multiple pixel units in the same row and / or column alternately light up and turn off. This solution flexibly selects the PPI of the display panel according to the display mode. In the second display mode, the display analog voltage and pixel-off voltage are transmitted in a time-division multiplexing manner through the driving module in the data driver to reduce the PPI of the display panel, thereby reducing display power consumption and achieving power saving.

[0030] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the structure of a data driver provided in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0039] Figure 8 A driving waveform diagram in a second display mode is provided as an embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of the structure of a driver module provided in an embodiment of the present invention;

[0041] Figure 10 This is a schematic diagram of a pixel arrangement structure in a first display mode provided by an embodiment of the present invention;

[0042] Figure 11 This is a schematic diagram of a pixel arrangement structure in a second display mode provided by an embodiment of the present invention;

[0043] Figure 12 A schematic diagram of another pixel arrangement structure in a first display mode provided by an embodiment of the present invention;

[0044] Figure 13 A schematic diagram of a pixel arrangement structure in another second display mode provided by an embodiment of the present invention;

[0045] Figure 14 This is a flowchart of a driving method for a display panel provided in an embodiment of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] Currently, to overcome the short standby time of mobile devices, existing technologies typically employ LTPO (Low Temperature Poly-oxide) technology or eLEAP technology (where e stands for environment-positive; L for lithography with maskless deposition; E for extreme long life, low power, and high luminance; and AP for Any shape Patterning). These technologies achieve low refresh rates by reducing leakage current or increasing pixel aperture ratio, thereby reducing display power consumption. However, this method of reducing refresh rates affects the normal use of mobile devices and is only suitable for displaying low refresh rates or static scenarios, such as browsing e-books. In actual use, mobile devices (such as mobile phones) are mostly in dynamic scenes, such as WeChat chatting, web browsing, and video playback, which are not suitable for low refresh rate displays. Therefore, existing technologies cannot effectively improve the problem of high display power consumption.

[0049] To address the aforementioned problems, this invention provides a display panel that reduces display power consumption by switching resolutions. Generally, the resolution limit of the human retina is 300 PPI, and a display pixel density of 200-300 PPI is sufficient for normal display applications. In most scenarios, the human eye cannot distinguish the difference between high and low resolution displays on the same screen. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figures 1-3 The display panel provided in this embodiment includes:

[0050] Multiple pixel units PX are located in the display area AA, and the multiple pixel units PX are arranged in an array.

[0051] The system includes a data driver 10 and multiple data lines DL. The data driver 10 includes multiple driver modules 20, each connected to a corresponding data line DL. The multiple data lines DL are arranged along a first direction X and extend along a second direction Y, where the first direction X and the second direction Y intersect. The data driver 10 can be located in the non-display area NA.

[0052] The driving module 20 includes a digital-to-analog converter 201 and an output control unit 202. The digital-to-analog converter 201 is connected to the output control unit 202. The digital-to-analog converter 201 is used to convert display data Data into display analog voltage Vdata. The output control unit 202 is used to transmit the display analog voltage Vdata to the corresponding data line DL in non-low power display mode, and to transmit the off pixel voltage VE and display analog voltage Vdata to the corresponding data line DL in a time-division manner in low power display mode, so that multiple pixel units PX in the same row and / or the same column alternately turn on and off.

[0053] Specifically, each pixel unit PX includes multiple sub-pixels, such as red, green, and blue sub-pixels. Each sub-pixel includes a light-emitting unit and a pixel circuit. The light-emitting unit can be an organic light-emitting diode (OLED). The pixel circuit consists of multiple thin-film transistors (TFTs) and a storage capacitor. For example, the pixel circuit can be a 2T1C or 7T1C structure, where T represents a TFT and C represents a storage capacitor. The TFTs include driving transistors and switching transistors. The pixel circuit is connected to the data line DL via the switching transistors. When the switching transistors are turned on, they can transfer the data voltage (display analog voltage Vdata) on the data line DL to the storage capacitor. The storage capacitor stores the data voltage, enabling the driving transistors to generate a stable driving current based on the data voltage, thereby driving the OLED to emit light.

[0054] The data driver 10 includes multiple driver modules 20, which can be used to transmit the display analog voltage Vdata or the pixel-killing voltage VE to the data line DL.

[0055] In this embodiment, the display panel has two display modes: a first display mode and a second display mode. The second display mode can be a low-power display mode, and the first display mode can be a non-low-power display mode. In the first display mode, the output control unit 202 transmits the display analog voltage Vdata output by the digital-to-analog converter 201 to the data line DL. During the line-by-line scanning process of the pixel units PX, the display analog voltage Vdata on each data line DL can be transmitted to the pixel circuit of the corresponding pixel unit PX to drive the light-emitting unit to emit light. In the second display mode, all pixel units PX are in a bright state, and the display panel is in a high PPI mode, such as 500 PPI.

[0056] In this embodiment, low-power display refers to a display mode that does not require high PPI, such as low-definition display for WeChat chatting, simple web browsing, and displaying simple content. Displaying high-definition images, movies, or games is defined as a non-low-power display mode. In an optional implementation, 200-300 PPI can be considered low PPI, and above 300 PPI can be considered high PPI.

[0057] In the second display mode, the output control unit 202 transmits the pixel-off voltage VE and the display analog voltage Vdata to the corresponding data line DL in a time-division manner, so that the pixel unit PX corresponding to the same data line DL alternately turns on and off, thereby reducing PPI and thus reducing power consumption. For example, as... Figure 3 As shown, during the scanning of the first row of pixel units PX, the first output control unit 202 transmits the pixel-off voltage VE to the first data line DL1, so that the first pixel unit PX is in a dark state (black square). The second output control unit 202 transmits the display analog voltage Vdata to the second data line DL2, so that the second pixel unit PX is in a bright state (white square). The third output control unit 202 transmits the pixel-off voltage VE to the third data line DL3, so that the third pixel unit PX is in a dark state. And so on, the nth output control unit 202 transmits the display analog voltage Vdata to the nth data line DLn, so that the nth pixel unit PX is in a bright state. Therefore, the pixel units PX in the first row alternately turn on and off.

[0058] During the scanning of the second row of pixel units PX, the first output control unit 202 of the second row transmits the analog voltage Vdata to the first data line DL1 to make the first pixel unit PX bright. The second output control unit 202 transmits the pixel-off voltage VE to the second data line DL2 to make the second pixel unit PX dark. The third output control unit 202 transmits the analog voltage Vdata to the third data line DL3 to make the third pixel unit PX bright. And so on, the nth output control unit 202 transmits the pixel-off voltage VE to the nth data line DLn to make the nth pixel unit PX dark. Therefore, the pixel units PX in the second row alternately brighten and turn off.

[0059] The next row of pixel units PX repeats the driving method of the first row of pixel units PX until the last row, thereby reducing PPI, reducing power consumption, and achieving the purpose of saving power.

[0060] In summary, during the line scan time of the first row of pixel units PX, the voltage transmitted on each data line DL remains constant. During the line scan time of the second row of pixel units PX, the voltage transmitted on each data line DL changes, such as jumping from the display analog voltage Vdata to the pixel-off voltage VE, or jumping from the pixel-off voltage VE back to the display analog voltage Vdata. That is, the voltage transmitted on the same data line DL is different during different line scan times.

[0061] Of course, in other embodiments, the on / off state of each row of pixel units PX can be in other ways. The above is only an illustrative representation of a specific method and is not intended to limit the scope of the invention.

[0062] The technical solution provided in this embodiment of the invention includes a driving module 20 comprising a digital-to-analog converter 201 and an output control unit 202. The digital-to-analog converter 201 is connected to the output control unit 202. The digital-to-analog converter 201 is used to convert display data Data into display analog voltage Vdata. The output control unit 202 is used to transmit the display analog voltage Vdata to the corresponding data line DL in a first display mode, and to transmit the pixel-off voltage VE and the display analog voltage Vdata to the corresponding data line DL in a time-division multiplexing manner in a second display mode, so that multiple pixel units PX in the same row and / or the same column alternately turn on and off. This solution flexibly selects the PPI of the display panel according to the display mode. In the second display mode, the display analog voltage Vdata and the pixel-off voltage VE are transmitted in a time-division multiplexing manner through the driving module 20 in the data driver 10 to reduce the PPI of the display panel, thereby reducing display power consumption and achieving power saving.

[0063] Figure 4This is a schematic diagram of the structure of a data driver provided in an embodiment of the present invention, with reference to... Figure 4 Based on the above technical solution, optionally, the data driver 10 provided in this embodiment includes an n-bit shift register 101, a first latch 102, a second latch 103, and a level conversion circuit 104, as well as n analog-to-digital converters (DACs) 201, an output control unit 202, and a buffer 105. Each buffer 105 is connected to a corresponding data line DL (DL1, DL2, DL3...DLn-1, DLn). The shift register 101 is used to sequentially transmit the pulses of the synchronization signal Hsync from the input to the output according to the clock signal Hclock. The first latch 102 is used to write the display data Data corresponding to the nth scan line one by one and hold it. The second latch 103 is used to write the display data Data corresponding to the (n-1)th scan line one by one and hold it. The level conversion circuit 104 converts the level of the corresponding display data Data into the required level. The digital-to-analog converter 201 converts the level-converted display data Data into a display analog voltage. The output control unit 202 selects either the display analog voltage or the pixel-killing voltage VE for output. The voltage output by the output control unit 202 is applied as a driving voltage to all data lines DL. The voltage source for the digital-to-analog converter 201 is the voltage generated by the display analog gamma voltage series.

[0064] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 5 The display panel further includes a gate driver 30 and multiple scan lines GL. The scan lines GL are arranged along the second direction Y and extend along the first direction X. The gate driver 30 is used to transmit gate drive signals to the scan lines GL, so that the scan lines GL control the pixel kill voltage VE or display analog voltage Vdata transmitted on the data line DL to be written into the pixel circuit of the corresponding pixel unit PX during the line scan time. The line scan time is the time required for one line of pixel unit PX to be scanned.

[0065] Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, specifically illustrating the structure of the output control unit 202 as a device. Based on the above technical solution, referencing... Figure 6Optionally, the output control unit 202 includes a first transistor M1 and a second transistor M2. The first terminal of the first transistor M1 is connected to the pixel-off voltage VE, and the first terminal of the second transistor M2 is connected to the output terminal of the digital-to-analog converter unit 201. The second terminals of the first transistor M1 and the second transistor M2 are connected to the same data line DL. The gate of the first transistor M1 in the odd-numbered output control units 202 is connected to the first control signal line SC1, the gate of the second transistor M2 in the odd-numbered output control units 202 is connected to the second control signal line SC2, the gate of the first transistor M1 in the even-numbered output control units 202 is connected to the third control signal line SC3, and the gate of the second transistor M2 in the even-numbered output control units 202 is connected to the fourth control signal line SC4. The first transistor M1 and the second transistor M2 are configured to be alternately turned on in the second display mode.

[0066] Specifically, in the first display mode, the first transistor M1 remains off in response to the first control signal on the first control signal line SC1 and the third control signal on the third control signal line SC3, respectively, while the second transistor M2 remains on in response to the second control signal on the second control signal line SC2 and the fourth control signal on the fourth control signal line SC4, respectively. The digital-to-analog converter 201 converts the display data Data into a display analog voltage Vdata, which is then transmitted to the data line DL via the second transistor M2. During the row scanning time of each row pixel unit PX, the display analog voltage Vdata on each data line DL is transmitted to the corresponding pixel unit PX to achieve the display function.

[0067] In the second display mode, the first transistor M1 and the second transistor M2 are alternately turned on when the line scan time of two adjacent pixel units PX switches. That is, the first transistor M1 and the second transistor M2 are not turned on at the same time. For the same output control unit 202, the first transistor M1 can be turned on during the line scan time of the current pixel unit PX, and the second transistor M2 can be turned on during the line scan time of the next pixel unit PX. This allows the same data line DL to transmit different voltages during different line scan times, so that one of the light-emitting units in two adjacent pixel units PX is in a bright state and the other is in a dark state, thereby reducing the display PPI and saving display power consumption.

[0068] For example, during the row scanning time of the first row of pixel units PX, the first transistor M1 in the odd-numbered output control unit 202 turns on in response to the first control signal on the first control signal line SC1, and the second transistor M2 turns off in response to the second control signal on the second control signal line SC2. The first transistor M1 in the even-numbered output control unit 202 turns off in response to the third control signal on the third control signal line SC3, and the second transistor M2 turns on in response to the fourth control signal on the fourth control signal line SC2. This causes the odd-numbered output control unit 202 to output a pixel-off voltage VE, and the even-numbered output control unit 202 to output a display analog voltage Vdata. Consequently, the pixel units PX corresponding to the odd-numbered data lines DL (DL1, DL3…DLn-1) are in a dark state, and the pixel units PX corresponding to the even-numbered data lines DL (DL2…DLn) are in a bright state. Here, n is an even number. During the row scan time of the second row of pixel units PX, the first transistor M1 in the odd-numbered output control unit 202 turns off in response to the first control signal on the first control signal line SC1, and the second transistor M2 turns on in response to the second control signal on the second control signal line SC2. The first transistor M1 in the even-numbered output control unit 202 turns on in response to the third control signal on the third control signal line SC3, and the second transistor M2 turns off in response to the fourth control signal on the fourth control signal line SC2. This causes the even-numbered output control unit 202 to output a pixel-off voltage VE, and the odd-numbered output control unit 202 to output a display analog voltage Vdata. Consequently, the pixel units PX corresponding to the odd-numbered data lines DL (DL1, DL3…DLn-1) are in a bright state, and the pixel units PX corresponding to the even-numbered data lines DL (DL2…DLn) are in a dark state. During the row scan time of the third row of pixel units PX, the on / off states of the first transistor M1 and the second transistor M2 are the same as those during the row scan time of the first row of pixel units PX. This continues until the row scan time of the last row of pixel units PX.

[0069] Optionally, in Figure 6 In the structure shown, the channel types of the first transistor M1 and the second transistor M2 can be different. Of course, in Figure 6 In the structure shown, the channel types of the first transistor M1 and the second transistor M2 can also be the same to reduce the wiring space of the first transistor M1 and the second transistor M2.

[0070] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 7The first transistor M1 and the second transistor M2 have different channel types to reduce the number of control signal lines. Specifically, the output control unit 202 includes a first transistor M1 and a second transistor M2. The first terminal of the first transistor M1 is connected to the pixel-kill voltage VE, and the first terminal of the second transistor M2 is connected to the output terminal of the digital-to-analog converter unit 201. The second terminals of the first transistor M1 and the second transistor M2 are connected to the same data line DL. In the odd-numbered output control units 202, the gates of the first transistor M1 and the second transistor M2 are both connected to the first control signal line SC1, and in the even-numbered output control units 202, the gates of the first transistor M1 and the second transistor M2 are both connected to the second control signal line SC2. The first transistor M1 and the second transistor M2 in the same output control unit 202 have different channel types, one being a P-type transistor and the other an N-type transistor.

[0071] Figure 8 A driving waveform diagram in low-power display mode provided in this embodiment of the invention is applicable to... Figure 7 The structure shown, combined with Figure 7 and Figure 8 In low-power mode, both the first control signal transmitted on the first control signal line SC1 and the second control signal transmitted on the second control signal line SC2 are pulse signals. During the row scan time T1 of the first row pixel unit PX, the first transistor M1 in the odd-numbered output control unit 202 turns on in response to the high-level signal on the first control signal line SC1, transmitting the pixel-killing voltage VE to the corresponding data line DL, and the second transistor M2 turns off in response to the high-level signal on the first control signal line SC1. In the even-numbered output control unit 202, the first transistor M1 turns off in response to the high-level signal on the first control signal line SC1, and the second transistor M2 turns on in response to the high-level signal on the first control signal line SC1, transmitting the display analog voltage Vdata to the corresponding data line DL.

[0072] During the row scan time T2 of the second row pixel unit PX, in the odd-numbered output control unit 202, the first transistor M1 turns off in response to a low-level signal on the first control signal line SC1, and the second transistor M2 turns on in response to a low-level signal on the first control signal line SC1, transmitting the display analog voltage Vdata to the corresponding data line DL. In the even-numbered output control unit 202, the first transistor M1 turns on in response to a low-level signal on the first control signal line SC1, and the second transistor M2 turns off in response to a low-level signal on the first control signal line SC1, transmitting the pixel voltage VE to the corresponding data line DL.

[0073] During the row scan time T3 of the third row of pixel units PX, the steps during the row scan time T1 of the first row of pixel units PX are repeated. During the scanning process of two adjacent rows of pixel units PX, the first transistor M1 and the second transistor M2 in the same output control unit 202 are alternately turned on until the last row of pixel units PX is scanned, thus achieving the effect of saving power by reducing the display PPI.

[0074] In this embodiment, by connecting the first transistor M1 and the second transistor M2 in the unified output control unit 202 to the same control signal line, the synchronous switching of bright pixels and dark pixels can be achieved in low-power display mode, which is beneficial to improving the visual effect.

[0075] In the above technical solutions, the time interval between the switching of the first transistor M1 and the second transistor M2 from the on state to the off state is the line scan time. That is, during the line scan time of a row of pixel units PX, the on / off states of the first transistor M1 and the second transistor M2 in the same output control unit 202 remain unchanged until the line scan time of the next row of pixel units PX arrives, at which point the first transistor M1 and the second transistor M2 will switch on / off states.

[0076] Figure 9 This is a schematic diagram of a driver module provided in an embodiment of the present invention, with reference to... Figure 9 Based on the above technical solutions, the drive module 20 may optionally include a multiplexer 203, which is connected to the output control unit 202. The multiplexer 203 is used to select one output pixel voltage VE. The multiplexer 203 is a multi-to-one selector.

[0077] Optionally, the multiplexer 203 includes multiple transistors, each of which has a gate that can respond to different control signals.

[0078] Specifically, since different display screens have different process parameters, the pixel elimination voltage VE of different display screens is not exactly the same. Therefore, in this embodiment, the selection precision of the pixel elimination voltage VE is set to be greater than or equal to 1 bit, that is, the number of pixel elimination voltages VE is at least two (2^1 = 2).

[0079] Optionally, the selection precision of the pixel-killing voltage VE can be 8 bits, meaning the number of pixel-killing voltages VE is 256 (2^8 = 256). For example... Figure 9As shown, the timing controller can select one voltage from 256 voltages (V0...V254, V255) as the pixel-extinguishing voltage VE according to the type of display screen. This meets the requirements of large-size screens formed by splicing technology, ensuring the consistency of dark state levels among the screens in low-power display mode and guaranteeing good display effects. This solution allows for flexible selection of the pixel-extinguishing voltage VE through the multiplexer 203, improving controllability and compatibility.

[0080] Optionally, in this embodiment, at least a portion of the display analog voltage Vdata is reused as the pixel-killing voltage VE. Since the pixel-killing voltage VE can kill pixels, it can be the same as the display analog voltage Vdata, so that the display analog voltage Vdata that makes the pixel appear dark is used as the pixel-killing voltage VE, without the need for a separate voltage source.

[0081] Optionally, in the second display mode, since the PPI is lower, the display effect can be further optimized by using an image magnification algorithm.

[0082] Figure 10 This is a schematic diagram of a pixel arrangement structure in a first display mode provided by an embodiment of the present invention, with reference to... Figure 10 The pixel unit PX includes a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Multiple data lines DL are divided into multiple data line groups. Each data line group includes a first data line D1, a second data line D2, and a third data line D3. The first data line D1, the second data line D2, and the third data line D3 are arranged along a first direction X and extend along a second direction Y. The first direction X and the second direction Y intersect.

[0083] like Figure 10As shown, the first sub-pixel P1 can be a red sub-pixel, the second sub-pixel P2 can be a green sub-pixel, and the third sub-pixel P3 can be a blue sub-pixel. Within the same column of sub-pixels, the third sub-pixel P3 in the current pixel unit PX and the first sub-pixel P1 in the next pixel unit PX are connected to the same data line DL. For example, the first data line D1 connects the third sub-pixel P3 in odd-numbered row pixel units PX and the first sub-pixel P1 in even-numbered row pixel units PX, and the second data line D2 connects the second sub-pixel P2. Specifically, the first data line D1-1, the first second data line D2-1, and the first third data line D3-1 together form the first data line group; the second data line D1-2, the second second data line D2-2, and the second third data line D3-2 together form the second data line group; the third data line D1-3, the third second data line D2-3, and the third third data line D3-3 together form the third data line group; the fourth data line D1-4, the fourth second data line D2-4, and the fourth third data line D3-4 together form the fourth data line group, and so on.

[0084] Figure 11 This is a schematic diagram of a pixel arrangement structure in a second display mode provided by an embodiment of the present invention, in conjunction with... Figure 2 and Figure 11 In the second display mode, during progressive scanning, odd-numbered and even-numbered data line groups alternately output the pixel-killing voltage VE and the display analog voltage Vdata to the pixel circuit corresponding to each sub-pixel. This ensures that half of the pixel units PX in each row are in a dark state, thereby reducing the display PPI and saving power. The first data line D1, the second data line D2, and the third data line D3 corresponding to each pixel unit PX transmit the same voltage.

[0085] Figure 12 This is a schematic diagram of another pixel arrangement structure in a first display mode provided by an embodiment of the present invention, and... Figure 10 The difference in the pixel arrangement structure shown is that... Figure 12 In the pixel unit PX shown, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged sequentially in the first direction X, and the emission color of multiple sub-pixels in the same column is the same. In the same pixel unit PX, the first data line D1 is connected to the pixel circuit corresponding to the first sub-pixel P1, the second data line D2 is connected to the pixel circuit corresponding to the second sub-pixel P2, and the third data line D3 is connected to the pixel circuit corresponding to the third sub-pixel P3. The driving method of the display panel with this pixel arrangement structure is similar to... Figure 10 The driving method for the display panel shown is the same, so it will not be described again.

[0086] Figure 13This is a schematic diagram of another pixel arrangement structure in a second display mode provided by an embodiment of the present invention. Figure 13 The driving method for the display panel with the pixel arrangement structure shown can be found in [reference]. Figure 11 The driving method for the display panel shown will not be described in detail here, but it has the same beneficial effects as the above-mentioned technical solutions.

[0087] Optionally, this embodiment of the invention also provides a display device, which includes the display panel provided in any of the above embodiments. Therefore, the display device provided in this embodiment also possesses the beneficial effects described in any of the above embodiments. In this embodiment, the display device can be a mobile phone or any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on these categories.

[0088] Optionally, embodiments of the present invention also provide a driving method for a display panel, which can be used to drive the display panel provided in any of the above embodiments. Figure 14 A flowchart of a display panel driving method provided in an embodiment of the present invention is shown below. Figure 14 The driving method includes:

[0089] S110. In the first display mode, the control output control unit transmits the display analog voltage output by the digital-to-analog converter to the corresponding data line.

[0090] S120 In the second display mode, the control output control unit transmits the pixel voltage and display analog voltage to the corresponding data lines in a time-division manner, so that multiple pixel units in the same row and / or the same column alternately turn on and off.

[0091] The driving method provided in this embodiment of the invention can flexibly select the PPI of the display panel according to the display mode. In the second display mode, the display analog voltage and pixel-killing voltage are transmitted in a time-division manner through the driving module in the data driver to reduce the PPI of the display panel, thereby reducing display power consumption and achieving power saving.

[0092] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0093] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Multiple pixel units; A data driver and multiple data lines, wherein the data driver includes multiple driver modules, and the driver modules are connected to the data lines respectively; The driving module includes a digital-to-analog converter (DAC) unit and an output control unit. The DAC unit is connected to one input terminal of the output control unit, and the other input terminal of the output control unit is connected to the pixel-off voltage. The output terminal of the output control unit is connected to the corresponding data line. The DAC unit is used to convert display data into display analog voltage. The output control unit is used to transmit the display analog voltage to the corresponding data line in a first display mode, and in a second display mode to time-division select the pixel-off voltage and the display analog voltage, and transmit the pixel-off voltage and the display analog voltage to the corresponding data line in a time-division manner, so that multiple pixel units in the same row and / or the same column alternately light up and turn off.

2. The display panel according to claim 1, characterized in that, The output control unit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the pixel-killing voltage, and the first terminal of the second transistor is connected to the output terminal of the digital-to-analog converter. The second terminals of the first transistor and the second transistor are connected to the same data line. The gate of the first transistor in the odd-numbered output control units is connected to a first control signal line, the gate of the second transistor in the odd-numbered output control units is connected to a second control signal line, the gate of the first transistor in the even-numbered output control units is connected to a third control signal line, and the gate of the second transistor in the even-numbered output control units is connected to a fourth control signal line. The first transistor and the second transistor are configured to alternately turn on in the second display mode, and the first transistor is also configured to remain off in the first display mode.

3. The display panel according to claim 2, characterized in that, One of two adjacent pixel units is in a bright state and the other is in a dark state.

4. The display panel according to claim 2, characterized in that, The first transistor and the second transistor have the same channel type.

5. The display panel according to claim 1, characterized in that, The output control unit includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the pixel-killing voltage, and the first terminal of the second transistor is connected to the output terminal of the digital-to-analog converter. The second terminals of the first transistor and the second transistor are connected to the same data line. The gates of the first transistor and the second transistor in the odd-numbered output control units are both connected to the first control signal line, and the gates of the first transistor and the second transistor in the even-numbered output control units are both connected to the second control signal line. The first transistor and the second transistor have different channel types.

6. The display panel according to claim 5, characterized in that, In the second display mode, both the first control signal transmitted on the first control signal line and the second control signal transmitted on the second control signal line are pulse signals.

7. The display panel according to claim 2, characterized in that, The time interval between the first transistor switching from the on state to the off state is the row scan time.

8. The display panel according to claim 1, characterized in that, At least a portion of the display analog voltage is multiplexed as the pixel-killing voltage.

9. The display panel according to claim 1, characterized in that, The selection precision of the pixel elimination voltage is greater than or equal to 1 bit.

10. The display panel according to claim 1, characterized in that, The driving module also includes a multiplexer connected to the output control unit, which is used to select one of the pixel-killing voltages for output.

11. The display panel according to claim 1, characterized in that, The pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The multiple data lines are divided into multiple data line groups. Each data line group includes a first data line, a second data line, and a third data line. The first data line, the second data line, and the third data line are arranged along a first direction and extend along a second direction. The first direction and the second direction intersect.

12. The display panel according to claim 11, characterized in that, The display panel also includes multiple pixel circuits, and each sub-pixel is connected to one of the pixel circuits. In the same pixel unit, the first data line is connected to the pixel circuit corresponding to the first sub-pixel or the third sub-pixel, the second data line is connected to the pixel circuit corresponding to the second sub-pixel, and the third data line is connected to the pixel circuit corresponding to the third sub-pixel or the first sub-pixel; wherein the first data line and the third data line are connected to the pixel circuits corresponding to different sub-pixels.

13. The display panel according to claim 12, characterized in that, The first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors.

14. The display panel according to claim 12, characterized in that, The display panel also includes multiple scan lines, which are arranged along a second direction and extend along a first direction. The scan lines are used to control the writing of the pixel-killing voltage or the display analog voltage transmitted on the data line to the corresponding pixel circuit during the row scanning time.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1-14.

16. A driving method for a display panel, characterized in that, The display panel includes: multiple pixel units, a data driver, and multiple data lines. The data driver includes multiple driving modules, each driving module being connected to a corresponding data line. Each driving module includes a digital-to-analog converter and an output control unit. The digital-to-analog converter is connected to one input terminal of the output control unit, and the other input terminal of the output control unit is connected to a pixel-killing voltage. The output terminal of the output control unit is connected to the corresponding data line. The driving method for the display panel includes: In the first display mode, the output control unit is controlled to transmit the display analog voltage output by the digital-to-analog converter to the corresponding data line; In the second display mode, the output control unit is controlled to select the pixel-off voltage and the display analog voltage in a time-division manner, and transmit the pixel-off voltage and the display analog voltage to the corresponding data line in a time-division manner, so that multiple pixel units in the same row and / or the same column alternately turn on and off.

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