Memory systems, memory devices, and methods of operating memory devices

Abstract

The present application relates to memory systems, memory devices, and methods of operating memory devices. A memory device includes a plurality of memory cells and a control circuit. Each memory cell is capable of storing multi-bit data corresponding to an erase state and a plurality of program states. The control circuit is configured to divide a plurality of program loops to be performed to store the multi-bit data in the plurality of memory cells into a plurality of program groups and apply different program pulses corresponding to each of the plurality of program groups to the plurality of memory cells.

Description

Technical Field

[0001] One or more embodiments of this disclosure described herein relate to memory devices, and more specifically, to an apparatus and method for programming data entries in a non-volatile memory device. Background Technology

[0002] Data processing systems include memory systems or data storage devices. Data processing systems can be developed to store larger volumes of data in data storage devices, store data in data storage devices faster, and retrieve data stored in data storage devices faster. Memory systems or data storage devices may include non-volatile memory cells and / or volatile memory cells for storing data. Summary of the Invention

[0003] The embodiments described herein provide a data processing system and a method for operating the data processing system. The data processing system includes components and resources such as a memory system and a host, and is capable of dynamically allocating multiple data paths for data communication between components based on the use of the components and resources.

[0004] Embodiments of this disclosure may provide an apparatus and method capable of improving the data input / output speed of a memory device.

[0005] Additionally, embodiments of this disclosure may provide an apparatus and method for performing data programming operations, which can reduce or avoid programming disturbances or errors that occur in a non-volatile memory device during data programming operations.

[0006] In one embodiment, a memory device may include: a plurality of memory cells, each memory cell capable of storing multi-bit data corresponding to an erase state and a plurality of programming states; and control circuitry configured to divide a plurality of programming cycles to be executed to store multi-bit data in the plurality of memory cells into a plurality of programming groups and to apply different programming pulses corresponding to each of the plurality of programming groups to the plurality of memory cells.

[0007] The memory device may also include a voltage supply circuit configured to apply programming pulses to multiple memory cells during each of a plurality of programming cycles.

[0008] Each of the plurality of programming cycles may include: a first operation that controls bit lines connected to a plurality of memory cells; a second operation that applies a programming pulse corresponding to one of a plurality of programming states to the plurality of memory cells; and a third operation that verifies the programming state of the plurality of memory cells corresponding to the programming pulse.

[0009] The control circuit can be configured to execute multiple programming loops as one or more odd programming loops and one or more even programming loops.

[0010] The control circuit can also be configured to apply programming pulses to a plurality of memory cells with respect to a first programming state group, which includes the programming state closest to the erase state among a plurality of programming states, during one or more odd programming cycles, and to apply another programming pulse to a plurality of memory cells with respect to a second programming state group, which includes the programming state furthest from the erase state among a plurality of programming states, during one or more even programming cycles.

[0011] The first programming state group and the second programming state group can be mutually exclusive.

[0012] A programming pulse configured to program the programming state corresponding to LSB data "1" in multi-bit data can be applied to multiple memory cells during one or more odd-numbered programming cycles. Another programming pulse configured to program the programming state corresponding to LSB data "0" in multi-bit data can be applied to multiple memory cells during one or more even-numbered programming cycles.

[0013] The control circuit can also be configured to: divide a plurality of memory cells into a first memory cell group and a second memory cell group before dividing the plurality of programming cycles into a plurality of programming groups, wherein the first memory cell group includes memory cells having a threshold voltage in an erase state, and the second memory cell group includes memory cells having a threshold voltage in one of a plurality of programming states; and apply a common programming pulse corresponding to the programming state closest to the erase state among the plurality of programming states to the second memory cell group.

[0014] The control circuit is also configured to: perform verification of the common programming pulse after it is applied to the second memory cell group; and determine whether the second memory cell group is defective based on the verification result.

[0015] The number of programming states corresponding to the programming pulses applied during each period of multiple programming groups divided into multiple programming loops can be the same.

[0016] In another embodiment, a memory system may include: a controller configured to determine a physical address corresponding to a write data entry and transfer the write data entry to the location corresponding to the physical address; and a memory device configured to be executed to divide a plurality of programming cycles into a plurality of programming groups for storing multi-bit data included in the write data entry in a plurality of memory cells, and to apply different programming pulses corresponding to each of the plurality of programming groups to the plurality of memory cells.

[0017] The memory device can also be configured to send a completion notification to the controller after multiple bits of data have been fully programmed into multiple memory cells. The controller can also be configured to generate mapping data entries that associate the logical address and physical address of the written data.

[0018] Each of the plurality of programming cycles may include: a first operation that controls bit lines connected to a plurality of memory cells; a second operation that applies a programming pulse corresponding to one of a plurality of programming states to the plurality of memory cells; and a third operation that verifies the programming state of the plurality of memory cells, the programming state corresponding to the programming pulse.

[0019] The memory device can be configured to execute multiple programming loops as one or more odd programming loops and one or more even programming loops.

[0020] The memory device may also be configured to apply programming pulses to a plurality of memory cells with respect to a first programming state group comprising a plurality of programming states that is closest to the erase state during one or more odd programming cycles, and to apply another programming pulse to a plurality of memory cells with respect to a second programming state group comprising a plurality of programming states that is furthest from the erase state during one or more even programming cycles.

[0021] The first programming state group and the second programming state group can be mutually exclusive.

[0022] A programming pulse configured to program the programming state corresponding to LSB data "1" in multi-bit data can be applied to multiple memory cells during one or more odd-numbered programming cycles. Another programming pulse configured to program the programming state corresponding to LSB data "0" in multi-bit data can be applied to multiple memory cells during one or more even-numbered programming cycles.

[0023] The memory device may also be configured to: divide a plurality of memory cells into a first memory cell group and a second memory cell group before dividing a plurality of programming cycles into a plurality of programming groups, wherein the first memory cell group includes memory cells having a threshold voltage in an erase state, and the second memory cell group includes memory cells having a threshold voltage in one of a plurality of programming states; and apply a common programming pulse corresponding to the programming state closest to the erase state among the plurality of programming states to the second memory cell group.

[0024] The memory device can also be configured to: perform verification of the common programming pulse after it is applied to the second memory cell group; and determine whether the second memory cell group is defective based on the verification result.

[0025] In another embodiment, a method of operating a memory device may include the following steps: dividing a plurality of memory cells configured to store multi-bit data corresponding to an erase state and a plurality of programming states into a first memory cell group and a second memory cell group, wherein the first memory cell group includes memory cells having a threshold voltage corresponding to an erase state, and the second memory cell group includes memory cells having a threshold voltage corresponding to one of a plurality of programming states; applying a common programming pulse to the second memory cell group; dividing a plurality of programming cycles to be executed to store multi-bit data in the second memory cell group into a plurality of programming groups; applying a different programming pulse corresponding to each of the plurality of programming groups to the second memory cell group; and terminating the programming operation with respect to the multi-bit data after successful verification in the plurality of programming groups.

[0026] In another embodiment, a method of performing programming operations in a memory device may include the steps of: applying a common programming pulse to a group of memory cells configured to be programmed into a plurality of programming states; and alternately executing odd programming cycles and even programming cycles by applying different programming pulses. The odd programming cycle corresponds to a first programming group of the plurality of programming states, and the even programming cycle corresponds to a second programming group of the plurality of programming states.

[0027] Alternating between odd and even programming cycles may involve applying a high-potential programming pulse during odd programming cycles and a low-potential programming pulse during even programming cycles.

[0028] Alternating between odd and even programming cycles may involve applying long programming pulses during odd programming cycles and short programming pulses during even programming cycles. Attached Figure Description

[0029] The description in this article refers to the accompanying drawings, in which the same reference numerals are used throughout the drawings to denote the same parts.

[0030] Figure 1 A memory device according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A data processing system according to an embodiment of the present disclosure is shown.

[0032] Figure 3A and Figure 3B A first example of incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is shown.

[0033] Figure 4 A method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is shown.

[0034] Figure 5 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is shown.

[0035] Figure 6 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is shown.

[0036] Figure 7 The programming and verification operations of an incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure are shown.

[0037] Figure 8 A second example of incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is shown.

[0038] Figure 9 A third example of incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is shown.

[0039] Figure 10 A first example of programming operations according to an embodiment of this disclosure is shown.

[0040] Figure 11 Shown in Figure 10 The cell threshold voltage distribution changes during the programming operation shown.

[0041] Figure 12 A second example of programming operations according to an embodiment of this disclosure is shown.

[0042] Figure 13 Shown in Figure 12 The cell threshold voltage distribution changes during the programming operation shown. Detailed Implementation

[0043] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0044] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any of these features are included in one or more embodiments of this disclosure, but may not necessarily be combined in the same embodiment.

[0045] In this disclosure, the terms “comprising” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the said element but do not exclude the presence or addition of one or more other elements. Terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0046] In this disclosure, various units, circuits, or other components may be described or declared as "configured to" perform a task. In such a context, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component may be said to be configured to perform a task even when the specified block / unit / circuit / component is currently inoperable (e.g., not turned on or not enabled). Blocks / units / circuits / components used with the language "configured to" include hardware (e.g., circuits), memory storing program instructions executable to perform operations, etc. Additionally, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., FPGAs or general-purpose processors executing software) to operate in a manner capable of performing the relevant tasks. "Configured to" may also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0047] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a hardware circuit implementation only (e.g., an implementation in analog and / or digital circuits only); and (b) a combination of circuitry and software (and / or firmware), such as (applicable to): (i) a combination of processors or (ii) a portion of processor / software (including digital signal processors), memory, and software working together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit such as a microprocessor or a portion of a microprocessor that requires software or firmware to operate, even if the software or firmware does not actually exist. This definition of “circuit” or “logic” applies to all uses of the term in this application (including in any claim). As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations of processors (or processors) or portions of processors and their accompanying software and / or firmware only. The terms “circuit” or “logic” also cover (e.g., and if applicable to elements of a particular claim) integrated circuits for storage devices.

[0048] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns preceding them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must precede the second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another that would otherwise have the same or similar names. For example, a first circuit can be distinguished from a second circuit.

[0049] Furthermore, the term "based on" is used to describe factors influencing a determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on those factors or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, this phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0050] In this document, a data item or data entry can be a sequence of bits. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to one embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a transmission packet between two different components.

[0051] Embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements.

[0052] Figure 1 A memory device 150 comprising a memory cell array circuit formed in a memory die is shown according to an embodiment of the present disclosure.

[0053] Reference Figure 1The memory device 150 may include at least one memory bank 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of non-volatile memory cells MC0 to MCn-1 connected to corresponding bit lines of a plurality of bit lines BL0 to BLm-1. The cell strings 340 are arranged in corresponding columns of the memory bank 330, and each cell string 340 may include at least one drain select transistor DST and at least one source select transistor SST. The non-volatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor DST and the source select transistor SST. Each of the non-volatile memory cells MC0 to MCn-1 may be configured to store a multi-level cell (MLC) of data items having a plurality of bits per cell. The cell string 340 may be electrically connected to corresponding bit lines of the bit lines BL0 to BLm-1.

[0054] In one embodiment, memory group 330 may include NAND flash memory cells MC0 to MCn-1. In another embodiment, memory group 330 may be implemented as NOR flash memory, hybrid flash memory in which at least two different types of memory cells are mixed or combined, or monolithic NAND flash memory in which the controller is embedded in a single memory chip. In another embodiment, memory group 330 may include flash memory cells, each flash memory cell including a charge trap flash (CTF) layer, the CTF layer including a conductive floating gate or an insulating layer.

[0055] Figure 2 A memory system 110 is illustrated, which may include a memory device 150 according to an embodiment of the present disclosure. In this embodiment, a memory group 330 in the memory device 150 may include one or more memory blocks 152, 154, 156. According to the embodiment, the memory device 150 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 may be implemented as a 3D structure (e.g., a vertical structure). Each of the memory blocks 152, 154, 156 may have a three-dimensional structure extending along a first to a third direction (e.g., the x-axis direction, the y-axis direction, and the z-axis direction).

[0056] A memory bank 330, comprising multiple memory blocks 152, 154, and 156, can be connected to multiple bit lines BL, multiple string select lines SSL, multiple drain select lines DSL, multiple word lines WL, multiple dummy word lines DWL, and multiple common source lines CSL. In one embodiment, the memory bank 330 may include multiple NAND strings NS, which may, for example, correspond to cell strings 340. Each NAND string NS may include multiple memory cells MC and may be connected to a corresponding bit line in the bit line BL. Additionally, the string select transistor SST of each NAND string NS may be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS may be connected to the corresponding bit line BL. In each NAND string NS, the memory cell MC may be arranged between the string select transistor SST and the drain select transistor DST.

[0057] Reference Figure 1 and Figure 2 The memory device 150 may include a voltage supply circuit 170, which may supply word line voltages (e.g., one or more predetermined voltages such as programming voltages), read voltages, and pass voltages to corresponding word lines in the word lines according to an operating mode, or may supply voltages to the body (e.g., a well region) forming various memory blocks including memory cells MC. In this case, the voltage generation operation of the voltage supply circuit 170 may be performed under the control of the control circuit 180. Additionally, the voltage supply circuit 170 may generate multiple variable read voltages with different levels to distinguish multiple data items from each other.

[0058] In response to control by control circuitry 180, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied individually to the selected word line and the unselected word line. Voltage supply circuitry 170 may include voltage generating circuitry for generating target voltages with various levels (e.g., see reference 170). Figures 4 to 8 ).

[0059] In one embodiment, the voltage supply circuit 170 may be coupled to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device) and a second pin or pad that receives a second power supply voltage VPP applied from an external source. The second power supply voltage VPP may have a voltage level greater than that of the first power supply voltage VCC (e.g., twice or more). For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V.

[0060] According to one embodiment, the voltage supply circuit 170 may include a voltage generating circuit for more rapidly generating target voltages of various levels used in the memory bank 330. The voltage generating circuit may use a second supply voltage VPP to generate a target voltage that may have a higher voltage level than the second supply voltage VPP.

[0061] The memory device 150 may further include a read / write circuit 320 controlled by the control circuit 180. The read / write circuit 320 may operate as a sense amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 may operate as a sense amplifier for reading data items from the memory cell array. In programming operations, the read / write circuit 320 may operate as a write driver for controlling the potential of bit lines based on the data items to be stored in the memory cell array. The read / write circuit 320 may receive data items to be programmed into the cell array from a page buffer during programming operations. The read / write circuit 320 may drive bit lines based on the input data items. For this purpose, the read / write circuit 320 may include a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to a column or bit line, or a column pair or bit line pair. According to an embodiment, a plurality of latches may be included in each of the page buffers 322, 324, 326.

[0062] Page buffers 322, 324, and 326 can be connected to data input / output devices (e.g., serialization circuits or serializers) via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, the latency that may occur in data transmission from page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transmission without waiting time.

[0063] According to an embodiment, the memory device 150 may receive a write command, write data, and information about the location where the write data is to be stored (e.g., a physical address). The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., for a programming operation performed in response to the write command. The control circuit 180 may also cause the voltage supply circuit 170 to generate one or more voltages for a verification operation performed after the programming operation.

[0064] When multi-bit data items are programmed into non-volatile memory cells included in memory bank 330, the error rate may be higher than when single-bit data items are stored in non-volatile memory cells. For example, errors in non-volatile memory cells may occur due to inter-cell interference (CCI). To reduce errors in non-volatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the stored data items between non-volatile memory cells should be reduced.

[0065] To this end, the memory device 150 can perform incremental step pulse programming (ISPP) operations to effectively form a narrow threshold voltage distribution for the non-volatile memory cells. In an embodiment, the memory device 150 can use ISPP operations to perform multi-step programming operations. For example, the memory device 150 can divide the programming operations into least significant bit (LSB) programming operations and most significant bit (MSB) programming operations according to a predetermined order between non-volatile memory cells or pages.

[0066] According to embodiments, an apparatus and method can be provided that reduces the time spent discharging bit lines or channels between programming pulse applications during data programming operations performed by applying multiple programming pulses to memory cells in a memory device. When the discharge time is reduced, the speed of programming operations on the memory device can be increased. For example, to discharge bit lines or channels in the memory device, the memory device can control or adjust the voltage level of the bit line select line or drain select line (DSL) to prevent transistors from becoming floating when controlled by the bit line select line or drain select line (DSL). When transistors are floating, bit lines or channels may not discharge properly.

[0067] In one embodiment, during a single programming operation of a non-volatile memory cell in a memory device, the memory device can adjust and change the setting time for the potential of the adjustment bit line after the programming pulse is applied. As a result, an apparatus and method capable of increasing the speed of programming operations and / or improving the efficiency of programming operations can be provided.

[0068] For example, during the operation of applying multiple programming pulses to a non-volatile memory cell in a memory device (in order to program the non-volatile memory cell using multi-bit data), the memory device may perform a unit programming operation in one of a variety of modes, applying a second programming pulse after the first programming pulse has been applied.

[0069] The programming operation modes may include a first programming mode, a second programming mode, and a third programming mode. In the first programming mode, the degree to which data is programmed in response to a second programming pulse (e.g., a change or shift in the threshold voltage of a non-volatile memory cell when the second programming pulse is applied) is similar to or greater than the degree to which data is programmed in response to a first programming pulse. In the second programming mode, the degree to which data is programmed in response to a second programming pulse is less than the degree to which data is programmed in response to a first programming pulse. In the third programming mode, there is no programming in response to a second programming pulse; for example, even when the second programming pulse is applied, there is no change or shift in the threshold voltage of the non-volatile memory cell. This mode can be implemented based on the potential of the bit line connected to the target memory cell when the programming pulse is applied. If the discharge time can be reduced, the memory device can improve the efficiency or speed of the data programming operation by adjusting and changing the setting time for changing or discharging the potential of the bit line.

[0070] According to an embodiment, the memory device can change or adjust the control voltage applied via the bit line select line or drain select line (DSL) during data programming operations in response to the programming operation environment (e.g., temperature and level or magnitude) or with respect to the number of programming pulses applied to the non-volatile memory cells. Therefore, the memory device can reduce the operating margin corresponding to each programming pulse during data programming operations. This can be achieved by applying multiple programming pulses to the non-volatile memory cells. As a result, the time spent performing the data programming operation can be reduced.

[0071] Refer to Figure 2 The memory device 150 is shown as being included in the data processing system 100. According to an embodiment, the data processing system 100 may include a host 102 that is coupled to or connected to a memory system (e.g., memory system 110). For example, the host 102 and the memory system 110 may be connected to each other via a data bus, host cable, etc., to perform data communication.

[0072] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 may be considered as physically separate components or elements. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a path.

[0073] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented on a single chip or multiple chips. The controller 130 may perform data input / output operations in response to requests input from external devices. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0074] In addition, Figure 2 In this configuration, memory device 150 may include one or more memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells in which data is erased together by a single erase operation. Memory blocks 152, 154, and 156 may include at least one page, for example, a group of non-volatile memory cells that store data together during a single programming operation and / or output data together during a single read operation. For example, a memory block may include multiple pages.

[0075] In one embodiment, the memory device 150 may include a plurality of memory planes or one or more memory dies. According to one embodiment, a memory plane may be considered as a logical or physical partition including at least one memory block, drive circuitry capable of controlling an array of multiple non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells.

[0076] According to an embodiment, each memory die may include at least one memory plane and can be understood as a collection of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 via a data path and may include an interface for exchanging data items and signals with the controller 130.

[0077] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. The memory device 150 (e.g., Figure 1 The internal configuration of (shown) may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to those shown. Figure 2 The internal configuration shown.

[0078] exist Figure 2 In this context, memory device 150 includes a voltage supply circuit 170 capable of supplying one or more voltages to memory blocks 152, 154, and 156. (See reference...) Figures 4 to 8As described, for example, voltage supply circuit 170 may include voltage generating circuitry for generating target voltages for storage blocks 152, 154, 156.

[0079] In this implementation, the voltage supply circuit 170 may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the programming voltage Vprog to the selected non-volatile memory cell. During a read or programming operation performed on the selected non-volatile memory cell, the voltage supply circuit 170 may supply the pass voltage Vpass to a non-selected non-volatile memory cell. During an erase operation for erasing data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the erase voltage Vers to the memory block.

[0080] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on its operation. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multi-bit data, multiple levels of read voltages Vrd can be used to identify or read multi-bit data items. Memory device 150 may include a table corresponding to the multi-bit data items, the table having information indicating multiple levels of read voltages Vrd. For example, the table may include bias values ​​stored in registers, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​of read voltage Vrd used for read operations may be limited to a preset range. Additionally, in embodiments, the bias values ​​may be quantized.

[0081] The host device 102 may include portable electronic devices (e.g., mobile phones, MP3 players, laptops, etc.) or non-portable electronic devices (e.g., desktop computers, game consoles, televisions, projectors, etc.). According to an embodiment, the host device 102 may include the central processing unit (CPU) included in both portable and non-portable electronic devices.

[0082] Host 102 may include at least one operating system (OS) that controls the functions and operations performed within host 102. The OS provides interoperability between host 102, which is operatively coupled to memory system 110, and a user intended to store data in memory system 110. The OS may support functions and operations corresponding to user requests. By way of example and not limitation, OS may be classified as a general operating system and a mobile operating system based on the mobility of host 102. General operating systems may be classified as personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems may be dedicated to ensuring and supporting high-performance computing.

[0083] The mobile operating system may allow support for services or functions for mobility (e.g., power-saving features). Host 102 may include multiple operating systems and, in response to a user's request, may execute multiple operating systems linked to memory system 110. Host 102 may send multiple commands corresponding to a user's request to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0084] The controller 130 can control the memory device 150 in response to requests or commands from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (e.g., a programming operation) to store data input from the host 102 into the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0085] According to an implementation, the controller 130 may include a host interface (I / F) 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144. Figure 2 The components in the controller 130 shown may vary depending on the structure, function, and operational performance of the memory system 110.

[0086] For example, memory system 110 may be implemented using any of a variety of storage devices electrically connected to host 102, depending on the host interface protocol. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Components may be added to or omitted from controller 130 depending on the implementation of memory system 110.

[0087] Each of the host 102 and the memory system 110 may include an interface or controller for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 may include devices capable of sending signals, data, etc. to or receiving signals, data, etc. from the host 102.

[0088] Host interface 132 can receive signals, commands (or requests), and / or data input from host 102. For example, host 102 and memory system 110 can use predetermined protocols to send and receive data between them. Examples of communication standards or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to embodiments, host interface 132 is a layer for exchanging data with host 102 and is implemented or driven by firmware called the Host Interface Layer (HIL).

[0089] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and cables, for example, can be used comprising a predetermined number (e.g., 40) leads connected in parallel to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be divided into master and slave devices using the positions or DIP switches to which the multiple memory systems 110 are connected. The memory system 110 set as the master device can be used as the master memory device. IDE (ATA) may include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0090] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronic Devices (IDE) devices. The 40 pins in an IDE interface can be reduced to 6 pins in a SATA interface. For example, the 40 parallel signals of IDE can be converted to the 6 serial signals of a SATA interface. The SATA interface is widely used in host 102 for data transmission and reception due to its faster data transmission and reception rates and lower resource consumption. The SATA interface can connect up to 30 external devices to a single transceiver included in host 102. Furthermore, the SATA interface supports hot-plugging, allowing external devices to be attached to or detached from host 102 even while data communication between host 102 and another device is in progress. Therefore, even when host 102 is powered on, memory system 110 can be connected or disconnected as an attachment device, similar to devices supported by Universal Serial Bus (USB). For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102, similar to an external hard drive.

[0091] Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI offers high transfer speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and the various peripheral devices can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from the host 102. SCSI can support up to 15 other devices connected to a single transceiver included in the host 102.

[0092] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed according to a serial data communication scheme. Furthermore, SAS supports connections between the host 102 and peripheral devices via serial cables instead of parallel cables, making it easier to manage devices and enhance or improve operational reliability and communication performance. Additionally, SAS can support up to eight external devices connected to a single transceiver included in the host 102.

[0093] High-speed non-volatile memory (NVMe) is an interface based at least on high-speed peripheral component interconnect (PCIe) designed to increase the performance and design flexibility of a host 102, server, computing device, etc., equipped with a non-volatile memory system 110. PCIe uses slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18-pin, 32-pin, 49-pin, or 82-pin) and at least one lead (e.g., x1, x4, x8, or x16) to achieve high-speed data communication exceeding several hundred MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). Depending on the implementation, PCIe schemes can achieve bandwidths from tens to hundreds of gigabits per second. NVMe can support operating speeds of non-volatile memory systems 110 such as SSDs, which are faster than hard drives.

[0094] According to one implementation, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides cost-effective standard connectivity between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video cameras, etc. Multiple peripheral devices, such as memory system 110, can be connected to a single transceiver included in host 102.

[0095] Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction coding on data to be programmed into memory device 150 to generate encoded data with added parity bits. The encoded data may be stored in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether the error correction decoding was successful and outputs a command signal (e.g., a correction success signal or a correction failure signal) based on the result of the error correction decoding. Error correction circuit 138 may use parity bits generated during ECC encoding processing of data stored in memory device 150 to correct erroneous bits in the read data. When the number of erroneous bits is greater than or equal to the number of correctable erroneous bits, error correction circuit 138 may not correct the erroneous bits but instead output a correction failure signal indicating that the correction of erroneous bits failed.

[0096] According to an implementation, the error correction circuit 138 may perform error correction operations based on coded modulation. Examples include low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the above codes. In an implementation, the error correction circuit 138 may include... Figure 1 At least some of the components in the controller 130 shown.

[0097] The ECC decoder can perform either hard decision decoding or soft decision decoding on data sent from memory device 150. Hard decision decoding can be understood as one of two broadly categorized methods for error correction. Hard decision decoding may include, for example, correcting erroneous bits by reading digital data "0" or "1" from non-volatile memory cells in memory device 150. Because hard decision decoding processes binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster than soft decision decoding.

[0098] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 using two or more quantization values ​​(e.g., multi-bit data, approximations, analog values, etc.) to correct erroneous bits based on the two or more quantization values. Controller 130 can receive two or more letters or quantization values ​​from a plurality of non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantization values ​​as a combination of information such as conditional probabilities or likelihoods.

[0099] According to the implementation, the ECC decoder can use Low-Density Parity-Generator Matrix (LDPC-GM) codes, which are designed for soft-decision decoding. Low-Density Parity-Generator (LDPC) codes use an algorithm that reads several bits of data value from memory device 150 based on reliability, rather than simply data 1 or 0 as in hard-decision decoding, and iteratively repeats this process through message exchange to improve the reliability of the value. These values ​​are then ultimately determined to be data 1 or 0. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from a non-volatile memory cell is decoded as 0 or 1.

[0100] Compared to hard decision decoding, soft decision decoding can determine the value stored in a non-volatile memory cell based on random information. Regarding bit flips that can be considered errors that may occur in memory device 150, soft decision decoding improves the probability of correcting errors and recovering data, and provides the reliability and stability of the corrected data. LDPC-GM codes can have an internal low-density generator matrix (LDGM) code that can be cascaded with high-speed LDPC codes.

[0101] According to the implementation, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can correspond to schemes that use linear-time coding and pipelined decoding based on variable block lengths and shift registers.

[0102] According to implementation methods, the ECC decoder may use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft decision decoding. The log-likelihood ratio (LLR) can be calculated as a nonlinear function of the distance between a sampled value and an ideal value. Alternatively, the Turbo code (TC) may include a simple two-dimensional or three-dimensional code (e.g., Hamming code) and be repeatedly decoded in both row and column directions to improve the reliability of the values.

[0103] The power management unit (PMU) 140 controls the power supplied to the controller 130. The PMU 140 monitors the power supplied to the memory system 110 (e.g., the voltage supplied to the controller 130) and supplies power to components included in the controller 130. The PMU 140 not only detects power on or off, but also generates a trigger signal when the power supply to the memory system 110 is unstable, enabling the memory system 110 to perform an emergency backup of its current state. According to embodiments, the PMU 140 may include means or components capable of accumulating power available for use in emergency situations.

[0104] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, so that the controller 130 can control the memory device 150 in response to commands or requests input from the host 102. When the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0105] For example, when the memory device 150 includes NAND flash memory, the memory interface 142 includes a NAND flash memory controller (NFC). The memory interface 142 provides an interface for processing commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 may be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0106] According to the implementation, the memory interface 142 may support an Open NAND Flash Interface (ONFi), switching modes, etc., for data input / output with the memory device 150. For example, ONFi may use a data path (e.g., channel, path, etc.) including at least one signal line capable of bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0107] Memory 144 can be used as working memory for memory system 110 or controller 130, while temporarily storing transaction data of operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store read data output from memory device 150 in response to a read request from host 102 before the read data is output to host 102.

[0108] Additionally, the controller 130 may temporarily store write data input from the host 102 in the memory 144 before programming the write data into the memory device 150. When the controller 130 controls the operation of the memory device 150 (e.g., data read operation, data write or programming operation, data erase operation, etc.), data transmitted between the controller 130 of the memory system 110 and the memory device 150 may be temporarily stored in the memory 144.

[0109] In addition to reading or writing data, memory 144 may store information (e.g., mapped data, read requests, programming requests, etc.) for inputting or outputting data between host 102 and memory device 150. According to embodiments, memory 144 may include one or more of a command queue, program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data undergoing programming operations.

[0110] In implementations, memory 144 may be implemented using volatile memory. For example, memory 144 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 The memory 144 is shown to be located within the controller 130, but the implementation is not limited thereto. The memory 144 may be located within or outside the controller 130. For example, the memory 144 may be specifically implemented as an external volatile memory having a memory interface for transferring data and / or signals between the memory 144 and the controller 130.

[0111] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to a write or read request input from host 102. According to an embodiment, processor 134 can execute firmware to control programming or reading operations in memory system 110. The firmware may be, for example, a flash translation layer (FTL). According to an embodiment, processor 134 may be implemented using a microprocessor, a central processing unit (CPU), or another processing device.

[0112] According to one implementation, the memory system 110 may be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores (considered as different processing regions). For example, the data input / output speed or performance of the memory system 110 can be improved when multiple cores in the multi-core processor independently drive or execute multiple flash translation layers (FTLs). According to another implementation, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0113] The processor 134 in controller 130 can perform operations corresponding to requests or commands input from host 102. Furthermore, memory system 110 can perform operations independently of commands or requests input from host 102. In one case, operations performed by controller 130 in response to requests or commands input from host 102 can be considered foreground operations, while operations performed by controller 130 independently of requests or commands input from host 102 can be considered background operations. Controller 130 can perform foreground or background operations for reading, writing, or erasing data in memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands sent from host 102 can be considered foreground operations. Examples of background operations that can be performed by controller 130 without commands sent from host 102 include garbage collection (GC), wear leveling (WL), bad block management (identifying and handling bad blocks), etc.

[0114] According to the implementation, substantially similar operations can be performed as both foreground and background operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection independently of the host 102 (e.g., automatic GC).

[0115] When the memory device 150 includes multiple dies or chips, each comprising a plurality of non-volatile memory cells, the controller 130 can perform parallel processing on multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands may be divided into multiple groups, including at least some of the multiple planes, dies, or chips included in the memory device 150. The multiple groups of requests or commands are processed individually or in parallel within each plane, die, or chip.

[0116] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data across multiple dies via the respective channels or paths in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be executed simultaneously or in parallel across multiple dies or planes. This processing method or scheme can be considered an interleaving method. Since the data input / output speed of memory system 110 is increased by operating in an interleaving manner, the data I / O performance of memory system 110 can be improved.

[0117] As an example and not a limitation, controller 130 may identify the status of multiple channels (or pathways) associated with multiple dies included in memory device 150. Controller 130 may determine the status of each channel or pathway as one of a busy state, a ready state, an active state, an idle state, a normal state, or an abnormal state. The determination of which channel or pathway the controller 130 uses to transmit instructions and / or data may be associated with a physical block address. Controller 130 may reference descriptors transmitted from memory device 150. Descriptors may include blocks or pages describing parameters about certain contents of memory device 150. Descriptors may have a predetermined format or structure. For example, descriptors may include device descriptors, configuration descriptors, cell descriptors, etc. Controller 130 may refer to or use descriptors to determine which channel(s) ...

[0118] As described above, the memory device 150 in the memory system 110 may include one or more memory blocks 152, 154, and 156. Each of the memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, the memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, and 156 may include a plurality of pages as a group of non-volatile memory cells that are read or programmed together.

[0119] In this implementation, for high integration, each memory block 152, 154, 156 may have a three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including memory blocks 152, 154, 156. The configuration of the memory device 150 may be varied depending on the performance of the memory system 110.

[0120] exist Figure 2 In this embodiment, memory device 150 includes memory blocks 152, 154, and 156. Based on the number of bits that can be stored in a single memory cell, memory blocks 152, 154, and 156 can be any of single-level cell (SLC) memory blocks, multi-level cell (MLC) memory blocks, etc. An SLC memory block comprises multiple pages implemented from memory cells, each memory cell storing one bit of data. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented from memory cells, each memory cell storing multiple bits of data (e.g., two or more bits of data). Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. Considering storage capacity, MLC memory blocks can be highly integrated.

[0121] In one embodiment, the memory device 150 may be implemented using MLC memory blocks such as two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, or combinations thereof. A DLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 2 bits of data. A TLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 3 bits of data. A QLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 4 bits of data. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented from memory cells, each memory cell capable of storing 5 bits or more of data.

[0122] According to one implementation, the controller 130 can use an MLC (Multi-Level Cell) memory block included in the memory device 150 as an SLC (Simplified Level Cell) memory block that stores one bit of data in a memory cell. The data input / output speed of a Multi-Level Cell (MLC) memory block can be slower than that of an SLC memory block. For example, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 can use the MLC memory block as an SLC buffer to temporarily store data, because the buffer can use a high data input / output speed to improve the performance of the memory system 110.

[0123] According to one embodiment, the controller 130 can program data into the MLC multiple times without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data overwriting. However, the controller 130 can use the feature of the MLC capable of storing multiple bits of data to program 1 bit of data into the MLC multiple times. For an MLC overwrite operation, the controller 130 can store the number of programming operations as separate operation information when 1 bit of data is programmed into the MLC. According to one embodiment, an operation to evenly level the threshold voltage of the MLC can be performed before another 1 bit of data is programmed into the same MLC where another bit of data is stored.

[0124] In one embodiment, the memory device 150 is specifically implemented as a non-volatile memory such as flash memory, e.g., NAND flash memory, NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), spin-torque magnetic random access memory (STT-MRAM), etc.

[0125] Figure 3A and Figure 3B Incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is shown.

[0126] Reference Figure 3AData can be programmed into non-volatile memory cells in an erased state. When a programming pulse is supplied to a word line connected to a non-volatile memory cell, the threshold voltage distribution of the non-volatile memory cell can shift to the right (e.g., in the direction of increasing threshold voltage) from the erased state. If programming pulses are continuously supplied to the non-volatile memory cells, the threshold voltage distribution of the non-volatile memory cells can be continuously shifted to the right. Programming pulses can be supplied until a majority (e.g., a predetermined number) of the multiple non-volatile memory cells in the threshold voltage distribution have a value higher than a target voltage V. TARG Threshold voltage.

[0127] exist Figure 3B In operation 212, when programming begins, memory device 150 may apply programming pulses to a plurality of non-volatile memory cells to be programmed with data (operation 214). After applying the programming pulses, memory device 150 may verify whether a majority (e.g., a predetermined number) of the plurality of non-volatile memory cells have a voltage higher than a target voltage V. TARG Threshold voltage V TH (Operation 216). When the verification result "failed" and it is determined that most of the multiple non-volatile memory cells do not have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, memory device 150 applies another programming pulse to the corresponding non-volatile memory cell (operation 214). When, according to another verification result "pass", most of the plurality of non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, the memory device 150 may end the programming operation (operation 218).

[0128] To narrow the threshold voltage distribution of multiple non-volatile memory cells, when applying a single programming pulse, it is advantageous to slightly shift the threshold voltage distribution of the multiple non-volatile memory cells to the right (e.g., by a first amount), rather than shifting them drastically to the right (e.g., by a second amount greater than the first amount). On the other hand, when the threshold voltage distribution of the multiple non-volatile memory cells is slightly shifted to the right, the number of programming pulses applied can be increased.

[0129] According to the implementation, three times or more of the number of data bits can be stored in the non-volatile memory cell. For example, when 2 bits of data can be stored in the non-volatile memory cell, the non-volatile memory cell can have four programming states corresponding to the 2 bits of data (e.g., "00", "01", "10", and "11"). To form a denser threshold voltage distribution (e.g., a narrower distribution), the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts to the right in response to a single programming pulse can be less than the difference between two adjacent programming states. For example, when two or more programming pulses are applied, it can be designed to shift the difference between two adjacent programming states. In this case, the number of programming pulses applied can be eight or more (more than four times the number of data bits).

[0130] According to the implementation method, the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts when a single programming pulse is applied can be understood as the target level. For Figure 6 An example of the implementation method is described in more detail below for the target level.

[0131] Figure 4 A method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is shown. Figure 4 The method may include programming operations performed in a memory device 150 comprising non-volatile memory cells capable of storing 3 bits of data.

[0132] Data stored in non-volatile memory cells can be based on the threshold voltage V of the corresponding memory cell. TH The threshold voltage V of the memory cell is used to distinguish them. TH The threshold voltage (VTH) can vary depending on the amount of electrons or charge injected into the floating gate of the corresponding memory cell. A single-level cell (SLC) can be divided into two threshold voltage ranges (VTH) to store one bit of data, "0" or "1". A three-level cell (TLC) in memory device 150 can have eight threshold voltage ranges.

[0133] Reference Figure 4 To reduce the number of programming pulses applied in Incremental Step Pulse Programming (ISPP) operations, the application of programming pulses to the Level 3 Cell (TLC) in response to data bits stored in the TLC can be controlled differently. The data stored in the TLC can be divided into LSB data, CSB data, and MSB data. The number of programming pulses applied can be minimized when programming LSB data, and the number of programming pulses applied can be greater when programming CSB data than when programming LSB data. The number of programming pulses applied can be maximized when programming MSB data.

[0134] In a three-level cell (TLC) memory device, each physical page can be divided into three logical pages: the LSB page, the CSB page, and the MSB page. The programming pulses applied to each page can be different. For example, different positive threshold voltages (V) can be induced during the programming of the LSB, CSB, and MSB data. TH The distribution shifts. In the implementation, during the programming of LSB pages, the threshold voltage V of multiple non-volatile memory cells... TH The maximum movable threshold voltage V of multiple non-volatile memory cells during MSB page programming is [not specified]. TH Minimal mobility is achieved. According to the implementation, the latency and power consumption are minimized when the number of programming pulses applied during LSB page programming is minimized. On the other hand, the number of programming pulses applied during MSB page programming can be increased, thereby increasing both latency and power consumption.

[0135] Figure 5 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is shown. Figure 5 The programming operation performed by a memory device 150, which includes a non-volatile memory cell capable of storing 3 bits of data, will be described as an example.

[0136] Reference Figure 5 The memory device 150 may not sequentially divide the operation of storing 3 bits of data in the non-volatile memory cell into LSB, CSB, and MSB programming operations. In order to store the 3 bits of data without separation in the non-volatile memory cell, the code values ​​of the LSB, CSB, and MSB corresponding to the eight programming states may differ from... Figure 4 The 3-bit data corresponding to the 8 programming states can be identified as Gray code, and the code values ​​of LSB, CSB, and MSB can be set differently. In this paper, Gray code can be a code whose value changes by only one bit (1 bit) between adjacent data when the data changes. For example, it can be understood that the data for the erase state is "111" and the data for the lowest programming state is "011". The data for the second lowest programming state adjacent to the lowest programming state data "011" can be "001".

[0137] Reference Figure 4 and Figure 5 The code values ​​of LSB, CSB, and MSB can differ depending on how multi-bit data is stored in non-volatile memory cells. For example, with... Figure 4 The code value corresponding to the MSB of the eight programming states shown can be "10101010", while Figure 5The MSB code value for the eight programming states shown can be "11100001". According to the implementation method, Figure 4 and Figure 5 The code values ​​of the LSB and MSB described herein may vary depending on the implementation method.

[0138] Figure 6 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is shown. Figure 6 As an example, programming performed in a memory device 150 that includes a non-volatile memory cell capable of storing 3 bits of data will be described.

[0139] Reference Figure 6 The memory device 150 can perform a data programming operation that stores 3 bits of data in non-volatile memory cells in three stages. The data programming operation can be divided into three steps. First, the plurality of non-volatile memory cells included in the memory device 150 can be divided into two groups: one group remains in an erased state (e.g., corresponding to data "111", E0) with all LSB, CSB, and MSB set to "1" after the data programming operation; the other group is in any of the programming states PV1 to PV7. In this document, the other group including the memory cells to be programmed by the programming pulse may include memory cells corresponding to 3 bits of data (e.g., 3 bits of data other than data "111") whose "0" is included in at least one of the LSB, CSB, and MSB.

[0140] According to the implementation, dividing a non-volatile memory cell into two groups, an erase state E0 and programming states PV1 to PV7, during the first programming operation can be used as a method to check the operating state of the non-volatile memory cell. For example, when a defect occurs in a particular non-volatile memory cell, its threshold voltage VTH often does not change even when a programming pulse is applied to the non-volatile memory cell. During the first programming operation, pulses can be applied together to multiple non-volatile memory cells to be programmed using programming states PV1 to PV7, which correspond to seven 3-bit data including "0"s in at least one of the LSB, CSB, and MSB. This can be performed to shift its threshold voltage VTH from the erase state (e.g., corresponding to data "111", E0) or to the closest programming state (e.g., corresponding to data "011", PV1). If, after a common programming pulse is applied, the threshold voltage of a specific non-volatile memory cell having one of the programming states PV1 to PV7 does not change or shift (e.g., from erase state E0 corresponding to data "111" to the closest programming state PV1 corresponding to data "011"), then the reliability of the data stored in the corresponding non-volatile memory cell can be ensured or guaranteed. Whether a non-volatile memory cell is defective can be determined by the commonly applied programming pulse. According to an implementation, if some target non-volatile memory cells are determined to be defective, the memory device 150 or memory system 110 may change the physical address assigned to the 3-bit data (e.g., the location where the 3-bit data is stored may be changed to include another page or another memory block in the memory device 150).

[0141] After the first programming operation of programming multiple non-volatile memory cells (each having one of the seven 3-bit data programming states, from the erase state E0 corresponding to data "111" to the closest programming state PV1 corresponding to data "011"), LSB data can be programmed into the multiple non-volatile memory cells. The programming states PV1 to PV7 corresponding to the seven 3-bit data can be divided into two programming groups based on the LSB data. In the first programming group (from the first programming state PV1 to the fourth programming state PV4) within the first programming states PV1 to the seventh programming states PV7, the LSB data is "0". On the other hand, in the second programming group (from the fifth programming state PV5 to the seventh programming state PV7) within the first programming states PV1 to the seventh programming states PV7, the LSB data is "1". Therefore, during the second programming operation of programming the LSB data, programming pulses are selectively applied to the non-volatile memory cells included in the second programming group from the fifth programming state PV5 to the seventh programming state PV7 to shift or change the threshold voltage distribution from the first programming state PV1 to the fifth programming state PV5.

[0142] Subsequently, the memory device 150 can program 2 bits of data corresponding to the CSB and MSB into a non-volatile memory cell. For example, the memory device 150 can selectively apply a programming pulse to a non-volatile memory cell having a first programming state PV1 to shift or change the threshold voltage VTH of the non-volatile memory cell. The threshold voltage VTH may belong to one of the threshold voltage distributions corresponding to the first programming state PV1 to the fourth programming state PV4. Additionally, the memory device 150 can selectively apply a programming pulse to a non-volatile memory cell having a fifth programming state PV5 to shift or change the threshold voltage VTH of the non-volatile memory cell. The threshold voltage VTH may belong to one of the threshold voltage distributions corresponding to the fifth programming state PV5 to the seventh programming state PV7.

[0143] Figure 7 The programming voltage application operation and verification operation of ISPP operation according to an embodiment of the present disclosure are shown.

[0144] Reference Figure 7 After the programming voltage application operation Pgm is performed during ISPP operation, the memory device 150 performs the verification operation Ver corresponding to the programming voltage application operation Pgm. Each programming voltage application operation Pgm can increase the threshold voltage V of the non-volatile memory cell. TH For example, the operation Pgm, which applies the programming voltage to each non-volatile memory cell, will change the threshold voltage V. TH Increase the first potential difference ΔV.

[0145] After performing the programming voltage application operation Pgm, the threshold voltage V of the non-volatile memory cell can be applied during the verification operation. TH Compare with the verification voltage. When the threshold voltage V of the non-volatile memory cell... TH If the voltage drops below the verification voltage, the next programming voltage application operation Pgm can be performed again to add more electrons to the floating gate of the non-volatile memory cell. Thereafter, in response to the corresponding programming voltage application operation Pgm, the verification operation Ver is performed. Repeated programming voltage application operations Pgm can be performed until the threshold voltage V of the non-volatile memory cell is reached. TH Change to the verification voltage or higher.

[0146] According to the implementation, the number of repetitions of the programming voltage application operation Pgm and the verification operation Ver can vary depending on standby time or delay time, power consumption, accuracy, etc. The threshold voltage V of the non-volatile memory cell is finely increased through the programming voltage application operation Pgm. TH At this rate, the accuracy of the programming voltage application operation can be increased. However, with a larger number of programming voltage application operations, the latency can be longer and the power consumption can be greater. On the other hand, when the threshold voltage V of the non-volatile memory cell is significantly increased by each programming voltage application operation Pgm, TH At this time, the power consumption of the programming voltage application operation Pgm can be increased and the operation time can be shortened. The operation time Δt of the programming voltage application operation Pgm and the verification operation Ver can be adjusted according to the target of each programming voltage application operation Pgm (e.g., threshold voltage V). TH (Changes)

[0147] Reference Figures 4 to 6 In a memory device comprising a three-level nonvolatile memory cell (TLC), the programming voltage application operation Pgm and the verification operation Ver can be performed differently based on the purpose and process of programming data into the least significant bit (LSB), center significant bit (CSB), and most significant bit (MSB) of the memory cell. Figure 4 The example described above is a memory device including a three-level non-volatile memory cell (TLC), but the above programming operations can also be applied to memory devices including a four-level non-volatile memory cell (QLC) that stores 4 bits of data or a non-volatile memory cell that can store 5 bits or more of data.

[0148] According to the implementation, for each programming cycle during ISPP operation, the voltage level of the programming pulse applied to the non-volatile memory cell in the programming voltage application operation Pgm can be gradually increased according to a preset voltage ΔV. However, the voltage level of the verification pulse applied to the non-volatile memory cell in the verification operation Ver corresponding to the programming voltage application operation Pgm can be substantially the same (e.g., unchanged). In the verification operation Ver of each programming cycle, substantially the same verification pulse is applied to the non-volatile memory cell, but the time Δt for applying the verification pulse can vary. When the verification operation is performed by reflecting noise generated according to the operating characteristics of the memory device 150, the memory device 150 can change or adjust the voltage level of the verification pulse.

[0149] Figure 8 A second example of incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is shown.

[0150] Reference Figure 8 The memory device 150 can execute multiple programming loops Loop0 to LoopN to program data in non-volatile memory cells. At least some of the programming loops can be executed repeatedly. Each of the multiple programming loops Loop0 to LoopN may include controlling the bit line (BL control) before applying the programming pulse PGM to the non-volatile memory cell and performing a verification operation after applying the programming pulse PGM to the non-volatile memory cell.

[0151] Reference Figures 4 to 7 The level of the programming pulse PGM applied to the non-volatile memory cell can vary in response to the data programmed into the non-volatile memory cell. The memory device 150 can sequentially apply programming pulses corresponding to the first programming state PV1 through the seventh programming state PV7 to the non-volatile memory cell. For example, different programming pulses corresponding to the first programming state PV1 through the seventh programming state PV7 can be sequentially applied to the non-volatile memory cell during a data programming operation. After a verification operation on a specific programming state confirms that the programming operation for the corresponding programming state (applying the programming pulse corresponding to the programming state to the non-volatile memory cell) is successful, a programming operation for the next programming state can be performed on the non-volatile memory cell.

[0152] Reference Figures 4 to 6 as well as Figure 8The memory device 150 can sequentially apply programming pulses (PGMs) to a plurality of non-volatile memory cells. The sequentially applied programming pulses (PGMs) can correspond to seven programming states (e.g., first programming state PV1 to seventh programming state PV7). The plurality of non-volatile memory cells can be selectively programmed via bit line control. When the memory device 150 sequentially applies programming pulses (PGMs) in response to a target programming state of the plurality of non-volatile memory cells, whether to execute a programming cycle using a specific programming pulse can be determined based on whether there is a memory cell among the plurality of non-volatile memory cells that needs to be programmed to a programming state corresponding to the specific programming pulse.

[0153] Multiple non-volatile memory cells are included in memory groups 330 or memory blocks 152, 154, 156 of memory device 150. As integration density increases, the distance or spacing between adjacent non-volatile memory cells becomes closer. Therefore, programming disturbances are more likely to occur during data programming operations. For example, when programming pulses PGM corresponding to the first programming states PV1 through the seventh programming states PV7 are sequentially applied to non-volatile memory cells, at least some non-volatile memory cells will be repeatedly stressed by the sequentially applied programming pulses PGM. Such data programming operations may degrade the durability of non-volatile memory cells and lead to defects.

[0154] Figure 9 A third example of incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is shown.

[0155] Reference Figure 9 The memory device 150 can repeat multiple programming loops Loop0 to Loop4 to program multi-bit data in non-volatile memory cells. Each of the programming loops Loop0 to Loop4 may include controlling the bit line (BL control) before applying the programming pulse PGM and performing a verification operation after applying the programming pulse PGM.

[0156] Reference Figure 6 and Figure 9The memory device 150 can divide a plurality of non-volatile memory cells into two groups of cells. The first group of cells includes memory cells among the plurality of non-volatile memory cells to be programmed using one of the first programming states PV1 to the seventh programming states PV7. The second group of cells includes non-volatile memory cells that remain in the erase state E0 after a programming pulse PGM is applied. The memory device 150 can apply a common programming pulse to the first group of cells including the non-volatile memory cells to be programmed using one of the first programming states PV1 to the seventh programming states PV7 to execute the zeroth programming loop Loop0 of a plurality of programming loops Loop0 to Loop4. According to an embodiment, the zeroth programming loop Loop0 may include a verification operation of the first programming state PV1 performed after the programming pulse PGM is applied.

[0157] According to the implementation, the memory device 150 can classify a plurality of programming loops Loop1 to Loop4 into multiple groups. For example, the plurality of programming loops Loop1 to Loop4 can be divided into two programming groups. For example, odd-numbered programming loops Loop1 and Loop3 can belong to the first programming group, and even-numbered programming loops Loop2 and Loop4 can belong to the second programming group. The memory device 150 can use the first programming group to program a first non-volatile memory cell, each memory cell being programmed using one of the first programming states PV1 to the fourth programming states PV4. The memory device 150 can use the second programming group to program a second non-volatile memory cell, each memory cell being programmed using one of the fifth programming states PV5 to the seventh programming states PV7. In the first programming group including odd-numbered programming loops Loop1 and Loop3, the memory device 150 can apply programming pulses PGM corresponding to the first programming states PV1 to the fourth programming states PV4 to the first non-volatile memory cell. In the second programming group, which includes even-numbered programming loops Loop2 and Loop4, the memory device may apply programming pulses PGM corresponding to the fifth programming state PV5 to the seventh programming state PV7 to the second non-volatile memory cell. The programming pulses PGM applied in the first programming group may differ from those applied in the second programming group because the target programming states of the first and second programming groups are different from each other.

[0158] Reference Figure 4 and Figure 9 The multiple non-volatile memory cells can be divided into two groups based on LSB data stored in the multiple non-volatile memory cells. In this embodiment, the memory device 150 can divide multiple repeating programming cycles into two programming groups and use each programming group to program multi-bit data in each of the two group of cells divided based on LSB data.

[0159] although Figure 9The diagram shows multiple programming cycles divided into two groups, but according to an embodiment, the multiple programming cycles can be divided into different numbers of groups (e.g., four or more groups). When the number of data bits programmed into the non-volatile memory cells of memory device 150 is 4 bits or more, the multiple programming cycles can be divided into four or more groups. Additionally, refer to... Figure 4 and Figure 6 When the operation of applying programming pulses to non-volatile memory cells storing multi-bit data can be divided into multi-step programming operations, the memory device 150 can divide the programming loops included in each programming step into multi-step programming groups. In each programming group, the memory device 150 can apply different programming pulses PGM corresponding to different programming states to the memory group 330 or memory blocks 152, 154, 156.

[0160] During data programming operations, when programming pulses PGM may be sequentially applied to memory banks 330 or memory blocks 152, 154, 156, programming disturbances may occur due to the significant differences in the threshold voltages VTH of non-volatile memory cells programmed while maintained in erase state E0 and programmed using high-level programming states (e.g., the sixth programming state P6 and the seventh programming state P7, which are among the programming states furthest from erase state E0). In embodiments, multiple programming cycles may be divided into multiple programming groups to prevent programming pulses (for high-level programming states) from being sequentially applied to memory banks 330 or memory blocks 152, 154, 156. For example, memory device 150 may apply low-potential (or short-duration) programming pulses PGM to multiple non-volatile memory cells during odd-numbered programming cycles for shifting or forming a low-level threshold voltage (VTH) distribution, and apply high-potential (or long-duration) programming pulses PGM to multiple non-volatile memory cells during even-numbered programming cycles for shifting or forming a high-level threshold voltage (VTH) distribution. According to another embodiment, the memory device 150 may alternately apply a high-level (or long-duration) programming pulse PGM during odd-numbered programming cycles and a low-level (or short-duration) programming pulse PGM during even-numbered programming cycles. When programming non-volatile memory cells included in memory groups 330 or memory blocks 152, 154, 156 using a high-level programming state, the memory device 150 may reduce the stress applied to adjacent non-volatile memory cells surrounding the corresponding non-volatile memory cell.

[0161] Figure 10 A first example of programming operations according to an embodiment of this disclosure is shown.

[0162] Reference Figure 10 The data programming operation performed by the memory device 150 may include setting the programming cycle number to an odd number "1" (operation 802).

[0163] The memory device 150 can check the programming cycle number to determine whether it is even or odd (operation 810). If the programming cycle number is odd, a programming pulse set for an odd programming cycle can be applied. The memory device 150 can then check and determine whether the programming operation based on the applied programming pulse passes or fails (operation 812).

[0164] After the threshold voltage distribution of the memory cell moves or shifts as expected in response to the applied programming pulse ("pass" in operation 812), the memory device 150 may check whether the result of the previous programming cycle (e.g., an even-numbered programming cycle) was successful or failed (operation 820). If the result of the previous programming cycle was successful ("pass" in operation 820), the memory device 150 may terminate the data programming operation (operation 822). According to an embodiment, the memory device 150 may include storage space (e.g., registers, etc.) for recording the results (e.g., success / failure) of at least two programming cycles. If the result of the previous programming cycle was failed ("fail" in operation 820), the memory device 150 may increment the number of the programming cycle by 1 (operation 824). The memory device 150 checks the value of the programming cycle that has been incremented by 1 (e.g., since it is an even-numbered "2" because it is incremented from an odd number "1"), the memory device 150 may apply a programming pulse set for an even-numbered programming cycle, and check whether the programming operation according to the applied programming pulse passed or failed (operation 832).

[0165] In response to a programming pulse applied in an odd-numbered programming loop, if the threshold voltage distribution of the memory cell does not shift or move as expected (a "failure" in operation 812), the memory device 150 may reapply the programming pulse (operation 814). According to an embodiment, the level of the programming pulse is determined by multiplying the increment (ISPP) for each programming loop by a quotient obtained by dividing the programming loop number by 2, and then adding the multiplied value to the level of the programming pulse applied for the first programming state (PV1) (e.g., PV1 initial pulse + ISPP × (Loop / 2)). The memory device 150 may verify the programming state corresponding to the applied programming pulse (e.g., one of the first programming states PV1 to the fourth programming state PV4) (operation 816). The memory device 150 may determine whether the programming operation with respect to the target programming state corresponding to the applied programming pulse was successful or failed and store the result in memory (operation 818). Thereafter, the memory device 150 may increment the programming loop number by 1 (operation 824).

[0166] If the memory device 150 identifies that the programming cycle number is even, the memory device 150 may apply a programming pulse set for the even-numbered programming cycle and check whether the programming operation succeeded or failed (operation 832). If the threshold voltage distribution of the memory cell moves or shifts as expected in response to the applied programming pulse ("pass" in operation 832), the memory device 150 may check whether the result of the previous programming cycle (e.g., the odd-numbered programming cycle) succeeded or failed (operation 840). If the result of the previous programming cycle was successful ("pass" in operation 840), the memory device 150 may terminate the data programming operation (operation 842). If the result of the previous programming cycle was a failure ("fail" in operation 840), the memory device 150 may increment the programming cycle number by 1 (operation 844). The memory device 150 checks the number of the programming cycle that is incremented by 1 (e.g., since it is an odd number "3" because it is incremented by 1 from the previous even number "2"). The memory device 150 may apply a programming pulse set for the odd programming cycle to the memory cell and check whether the programming operation based on the applied programming pulse passes or fails (operation 812).

[0167] In response to a programming pulse applied in an even-numbered programming loop, if the threshold voltage distribution of the memory cell does not shift or move as expected (a "failure" in operation 832), the memory device 150 may reapply the programming pulse (operation 834). According to an embodiment, the level of the programming pulse is obtained by multiplying the increment (ISPP) for each programming loop by the quotient obtained by dividing the programming loop number by 2, minus 1, and then adding the multiplied value to the level of the programming pulse applied for the first programming state PV1 (e.g., PV1 initial pulse + ISPP * (Loop / 2 - 1)). The memory device 150 may verify the programming state corresponding to the applied programming pulse (e.g., one of the fifth programming state PV5 to the seventh programming state PV7) (operation 836). The memory device 150 may determine whether the programming operation with respect to the target programming state corresponding to the applied programming pulse was successful or failed (operation 838). Thereafter, the memory device 150 may increment the programming loop number by 1 (operation 844).

[0168] Reference Figure 10 The memory device 150 can divide multiple programming cycles into two groups (e.g., odd-numbered programming cycles and even-numbered programming cycles), apply different programming pulses corresponding to each group, and perform verification operations corresponding to the applied programming pulses. Furthermore, to determine whether the data programming operation has terminated, if the odd-numbered programming cycle is successful, the memory device 150 can check whether the previously executed even-numbered programming cycle was successful; or if the even-numbered programming cycle is successful, the memory device 150 can check whether the previously executed odd-numbered programming cycle was successful.

[0169] Figure 11 Shown in Figure 10 The cell threshold voltage distribution changes during the programming operation shown.

[0170] Reference Figure 10 and Figure 11 The first programming cycle is an odd-numbered programming cycle. When the first programming cycle is executed, the threshold voltage distribution of the memory cell to be programmed using one of the first programming states PV1 to the fourth programming state PV4 is shifted to the right from the erase state ERA. On the other hand, after the first programming cycle has been executed, the other threshold voltage distributions of the memory cell to be programmed using one of the fifth programming states PV5 to the seventh programming state PV7 can be maintained in the erase state ERA.

[0171] The second programming cycle is an even-numbered programming cycle. When the second programming cycle is executed, the threshold voltage distribution of the memory cell to be programmed using one of the first programming states PV1 to the fourth programming state PV4 remains unchanged, but the other threshold voltage distributions of the memory cell to be programmed using one of the fifth programming states PV5 to the seventh programming state PV7 can be shifted to the right from the erase state ERA to approach the fifth programming state PV5.

[0172] The third programming cycle is an odd-numbered programming cycle. When the third programming cycle is executed, programming pulses are applied to some memory cells that are to be programmed using the first programming state PV1, which are to be programmed using one of the first programming states PV1 to the fourth programming state PV4. Therefore, a threshold voltage distribution corresponding to the first programming state PV1 can be generated and shifted. On the other hand, the threshold voltage distribution for other memory cells to be programmed using one of the second programming states PV2 to the fourth programming states PV4 does not change. Furthermore, in the current state approaching the fifth programming state PV5, the threshold voltage distribution for other memory cells to be programmed using one of the fifth programming states PV5 to the seventh programming state PV7 may not change.

[0173] The fourth programming cycle is an even-numbered programming cycle. When the fourth programming cycle is executed, the threshold voltage distribution of the memory cells to be programmed using one of the first programming states PV1 to the fourth programming state PV4 remains unchanged. However, programming pulses can be applied to some memory cells to be programmed into the fifth programming state PV5, which are shifted to the right from the erase state ERA and are to be programmed using one of the fifth programming states PV5 to the seventh programming state PV7. Therefore, a threshold voltage distribution corresponding to the fifth programming state PV5 can be generated. On the other hand, the other threshold voltage distributions for other memory cells to be programmed using one of the sixth programming states PV6 to the seventh programming state PV7 remain unchanged.

[0174] Reference Figure 10 and Figure 11 For programming operations, the memory device 150 can apply different programming pulses to the memory cells according to odd-numbered and even-numbered programming cycles. According to an embodiment, coarse programming operations (coarse PGM) and fine programming operations (fine PGM) can be performed alternately in each of the odd-numbered and even-numbered programming cycles. Even when fine programming operations (fine PGM) and coarse programming operations (coarse PGM) are performed to program the same data, the width of the threshold voltage distribution generated by the fine programming operation (fine PGM) can be narrower than the width of the threshold voltage distribution generated by the coarse programming operation (coarse PGM). For example, a coarse programming operation (coarse PGM) can be performed to shift or deflect the threshold voltage distribution closer to different programming states, and a fine programming operation (fine PGM) can be performed after a coarse programming operation (coarse PGM) to narrow the width of the threshold voltage distribution.

[0175] Figure 12 A second example of programming operations according to an embodiment of this disclosure is shown.

[0176] Reference Figure 12 The data programming operation performed by the memory device 150 may include setting the programming cycle number to an odd number "1" (operation 902). The memory device 150 may apply a programming pulse corresponding to a first programming state PV1 to some of the non-volatile memory cells to be programmed using one of multiple programming states (e.g., PV1 to PV7), excluding other memory cells that remain in an erased state after the data programming operation (operation 912). In this document, the multiple programming states may vary depending on the number of data bits that can be stored in each non-volatile memory cell. For example, refer to... Figures 4 to 6 The 3-bit data can be stored in a non-volatile memory cell. In these cases, the multiple programming states may include a first programming state PV1 to a seventh programming state PV7. Here, the first programming state PV1 may correspond to the threshold voltage distribution of the multiple programming states (e.g., PV1 to PV7) closest to the erase state E0. After applying a programming pulse corresponding to the first programming state PV1 to some memory cells (operation 904), the memory device 150 may perform a verification operation corresponding to the applied programming pulse (operation 906). Thereafter, the memory device 150 may increment the programming cycle number by 1 (operation 908).

[0177] The memory device 150 may check the programming cycle number to determine whether it is even or odd (operation 910). If the memory device 150 identifies the programming cycle number (e.g., 2, 4, 6, etc.) as even, the memory device 150 may apply a programming pulse set for an even-numbered programming cycle and check whether the programming operation succeeded or failed (operation 932). If the threshold voltage distribution of the memory cell moves or shifts as expected in response to the applied programming pulse ("pass" in operation 932), the memory device 150 may check whether the result of the previous programming cycle (e.g., an odd-numbered programming cycle) succeeded or failed (operation 940). If the result of the previous programming cycle was successful ("pass" in operation 940), the memory device 150 may terminate the data programming operation (operation 942). If the result of the previous programming cycle was a failure ("fail" in operation 940), the memory device 150 may increment the programming cycle number by 1 (operation 944). The memory device 150 checks the number of the programming cycle that is incremented by 1 (e.g., since it is an odd number "3" because it is incremented by 1 from the previous even number "2"). The memory device 150 may apply a programming pulse set for the odd programming cycle to the memory cell and check whether the programming operation based on the applied programming pulse passes or fails (operation 912).

[0178] In response to a programming pulse applied in an even-numbered programming cycle, if the threshold voltage distribution of the memory cell does not shift or move as expected (a "failure" in operation 932), the memory device 150 may reapply the programming pulse (operation 934). The memory device 150 may verify the programming state corresponding to the applied programming pulse (e.g., one of the fifth programming state PV5 to the seventh programming state PV7) (operation 936). The memory device 150 may determine whether the programming operation with respect to the target programming state corresponding to the applied programming pulse was successful or failed (operation 938). Thereafter, the memory device 150 may increment the programming cycle number by 1 (operation 944).

[0179] If the programming cycle number (e.g., 3, 5, 7, etc.) is odd, a programming pulse set for the odd programming cycle can be applied. The memory device 150 can then check and determine whether the programming operation based on the applied programming pulse succeeds or fails (operation 912).

[0180] After the threshold voltage distribution of the memory cell moves or shifts as expected in response to the applied programming pulse ("pass" in operation 912), the memory device 150 may check whether the result of the previous programming cycle (e.g., an even-numbered programming cycle) was successful or failed (operation 920). If the result of the previous programming cycle was successful ("pass" in operation 920), the memory device 150 may terminate the data programming operation (operation 922). If the result of the previous programming cycle was unsuccessful ("fail" in operation 920), the memory device 150 may increment the programming cycle number by 1 (operation 924). The memory device 150 checks the value of the incremented programming cycle (e.g., since it is an even-numbered "2" because it is incremented from an odd number "1"), the memory device 150 may apply a programming pulse set for the even-numbered programming cycle, and check whether the programming operation according to the applied programming pulse passed or failed (operation 932).

[0181] In response to a programming pulse applied in an odd-numbered programming cycle, if the threshold voltage distribution of the memory cell does not move or shift as expected (a "failure" in operation 912), the memory device 150 may reapply the programming pulse (operation 914). The memory device 150 may verify the programming state corresponding to the applied programming pulse (e.g., one of the first programming states PV1 to the fourth programming states PV4) (operation 916). The memory device 150 may determine whether the programming operation with respect to the target programming state corresponding to the applied programming pulse was successful or failed and store the result in the memory space (operation 918). Thereafter, the memory device 150 may increment the programming cycle number by 1 (operation 924).

[0182] Reference Figure 12 Similar to Figure 10 In the illustrated embodiment, the memory device 150 can divide multiple programming cycles into two programming groups (e.g., odd-numbered programming cycles and even-numbered programming cycles), apply different programming pulses corresponding to each group, and perform verification operations corresponding to the applied programming pulses. Furthermore, to determine whether the data programming operation has terminated, if the odd-numbered programming cycle is successful, the memory device 150 can check whether the previously executed even-numbered programming cycle was successful; or if the even-numbered programming cycle is successful, the memory device 150 can check whether the previously executed odd-numbered programming cycle was successful.

[0183] Additionally, refer to Figure 6 and Figure 12The memory device 150 may apply programming pulses together to some memory cells to be programmed using multiple programming states (e.g., PV1 to PV7) (operation 904) such that a threshold voltage distribution with respect to the corresponding memory cell is generated or shifted corresponding to the first programming state PV1 closest to the erase state E0. For example, if at least one of the memory cells to be programmed using a particular programming state (e.g., one of PV1 to PV7) is not programmed using the first programming state (PV1) by the jointly applied programming pulses, the memory device 150 may determine that the page pair including said at least one memory cell in which multi-bit data is stored is defective. Thus, even before all multi-bit data is programmed into the memory cell, the memory device 150 can more quickly check or determine whether the memory cell to which multi-bit data is stored is defective.

[0184] Additionally, refer to Figure 6 and Figure 12 The memory device 150 can apply a programming pulse to the memory cells regarding a first programming state PV1 among a plurality of programming states (e.g., PV1 to PV7), and then divide the plurality of programming cycles into two programming groups. The same number of programming states (e.g., three programming states, PV2 to PV4 and PV5 to PV7) can belong to each of the two programming groups. As a result, excessive load on a particular programming group between the two programming groups, including the divided programming cycles, can be avoided.

[0185] Figure 13 Shown in Figure 12 The implementation of changing the cell threshold voltage distribution during the programming operation is shown.

[0186] Reference Figure 12 and Figure 13 The first programming cycle is an odd-numbered programming cycle. When the first programming cycle is executed, the threshold voltage distribution of the memory cells to be programmed using the first programming states PV1 to the seventh programming states PV7, except for the other memory cells that remain in the erase state ERA after the data programming operation, is shifted to the right from the erase state ERA. According to an embodiment, during the first programming cycle, the memory device 150 may apply a programming pulse (coarse PGM) for a coarse programming operation with respect to the first programming state PV1.

[0187] The second programming cycle is an even-numbered programming cycle. When the second programming cycle is executed, the threshold voltage distribution of the memory cells to be programmed using one of the first programming states PV1 to the fourth programming state PV4 remains unchanged. However, the other threshold voltage distributions of the memory cells to be programmed using one of the fifth programming states PV5 to the seventh programming state PV7 can be shifted to the right from the erase state ERA to approach the fifth programming state PV5. According to an embodiment, during the second programming cycle, the memory device 150 can apply programming pulses (coarse PGMs) for coarse programming operations with respect to the fifth programming state PV5.

[0188] The third programming cycle is an odd-numbered programming cycle. When the third programming cycle is executed, programming pulses are applied to some memory cells that are to be programmed using the first programming state PV1, among those memory cells to be programmed using one of the first programming states PV1 to the fourth programming state PV4. According to the embodiment, during the third programming cycle, the memory device 150 may apply programming pulses (fine PGM) for fine programming operations with respect to the first programming state PV1. Therefore, a threshold voltage distribution corresponding to the first programming state PV1 can be generated and shifted. On the other hand, the threshold voltage distribution for other memory cells to be programmed using one of the second programming states PV2 to the fourth programming states PV4 does not change. Furthermore, in the current state approaching the fifth programming state PV5, the threshold voltage distribution for other memory cells to be programmed using one of the fifth programming states PV5 to the seventh programming state PV7 may not change.

[0189] The fourth programming cycle is an even-numbered programming cycle. When the fourth programming cycle is executed, the threshold voltage distribution of the memory cells to be programmed using one of the first programming states PV1 to the fourth programming state PV4 remains unchanged. However, programming pulses can be applied to some memory cells to be programmed to the fifth programming state PV5, which are memory cells that have been shifted to the right from the erase state ERA and are to be programmed using one of the fifth programming states PV5 to the seventh programming state PV7. For example, during the fourth programming cycle, the memory device 150 can apply programming pulses (fine PGM) for fine programming operations with respect to the fifth programming state PV5. Therefore, a threshold voltage distribution corresponding to the fifth programming state PV5 can be generated. On the other hand, the other threshold voltage distributions for other memory cells to be programmed using one of the sixth programming states PV6 to the seventh programming state PV7 remain unchanged.

[0190] Reference Figure 12 and Figure 13During data programming operations, the memory device 150 may apply a common programming pulse in the initial programming cycle to separate some memory cells to be programmed using one of the first programming states PV1 to the seventh programming states PV7 from other memory cells to be maintained in the erase state ERA. Then, different programming pulses are applied to the memory cells according to odd and even programming cycles. According to embodiments, coarse programming operations (coarse PGM) and fine programming operations (fine PGM) may be performed alternately in each of the odd and even programming cycles. Even when fine programming operations (fine PGM) and coarse programming operations (coarse PGM) are performed to program the same data, the width of the threshold voltage distribution generated by the fine programming operation (fine PGM) may be narrower than the width of the threshold voltage distribution generated by the coarse programming operation (coarse PGM). For example, a coarse programming operation (coarse PGM) may be performed to shift or deflect the threshold voltage distribution closer to different programming states, and a fine programming operation (fine PGM) may be performed after the coarse programming operation (coarse PGM) to narrow the width of the threshold voltage distribution.

[0191] According to the above embodiments, a memory device or memory system is provided, wherein multiple programming cycles are divided into multiple programming groups, and different programming pulses corresponding to different programming states are applied to memory cells in each programming group. Furthermore, since the programming pulses set for each programming group are applied alternately to the memory cells, continuous strong stress on neighboring memory cells located around a specific memory cell to be programmed according to the programming pulses can be avoided or reduced. During data programming operations, the memory device or memory system can suppress or reduce programming disturbances.

[0192] Furthermore, embodiments of this disclosure may provide a memory system, a memory device, and a method of operating the same, in order to improve the performance of data programming operations.

[0193] Furthermore, memory devices or memory systems can improve the reliability of data programming operations on specific data entries that are susceptible to programming disturbances.

[0194] The methods, processes, and / or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or other elements besides those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a general-purpose processor for performing the methods herein.

[0195] Alternatively, another implementation may include a computer-readable medium (e.g., a non-transitory computer-readable medium) for storing the aforementioned code or instructions. The computer-readable medium may be volatile or non-volatile memory or other storage devices that may be removably or permanently coupled to a computer, processor, controller, or other signal processing device that executes the code or instructions for performing the operations of the method or apparatus implementations described herein.

[0196] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features disclosed herein may be implemented, for example, in non-transitory logic, which may include hardware, software, or both. When at least partially implemented in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, system-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0197] When at least partially implemented in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or other elements besides those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a general-purpose processor for performing the methods described herein.

[0198] Although this teaching has been shown and described with reference to specific embodiments, it will be apparent to those skilled in the art from this disclosure that various changes and modifications may be made without departing from the spirit and scope of this disclosure as defined in the following claims. Furthermore, these embodiments may be combined to form additional embodiments.

[0199] Cross-references to related applications

[0200] This patent application claims the benefit of Korean Patent Application No. 10-2022-0090175, filed on July 21, 2022, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory cells, each of which is capable of storing multi-bit data corresponding to erase states and multiple programming states; as well as A control circuit is executed to divide the multi-bit data stored in the plurality of memory cells into a plurality of programming loops into a plurality of programming groups, and to apply a different programming pulse to the plurality of memory cells corresponding to each of the plurality of programming groups, wherein the control circuit executes the plurality of programming loops in one or more odd programming loops and one or more even programming loops.

2. The memory device according to claim 1, further comprising: A voltage supply circuit that applies programming pulses to the plurality of memory cells during each of the plurality of programming cycles.

3. The memory device according to claim 1, wherein, Each of the plurality of programming loops includes: The first operation controls the bit lines connected to the plurality of memory cells; The second operation involves applying a programming pulse corresponding to one of the plurality of programming states to the plurality of memory cells; and The third operation verifies the programming status of the plurality of memory cells, the programming status corresponding to the programming pulse.

4. The memory device according to claim 1, wherein, The control circuit also includes: During one or more odd-numbered programming cycles, programming pulses are applied to the plurality of memory cells relating to a first group of programming states, including the programming state closest to the erase state among the plurality of programming states. During one or more even-numbered programming cycles, another programming pulse is applied to the plurality of memory cells relating to a second programming state group, which includes the programming state furthest from the erase state among the plurality of programming states.

5. The memory device according to claim 4, wherein, The first programming state group and the second programming state group are mutually exclusive.

6. The memory device according to claim 1, in, During the one or more odd-numbered programming cycles, programming pulses configured to program the programming state corresponding to LSB data 1 in the multi-bit data are applied to the plurality of memory cells, and During one or more even-numbered programming cycles, another programming pulse, configured to program the programming state corresponding to LSB data 0 in the multi-bit data, is applied to the plurality of memory cells.

7. The memory device according to claim 1, wherein, The control circuit also includes: Before dividing the plurality of programming cycles into the plurality of programming groups, the plurality of memory cells are divided into a first memory cell group and a second memory cell group, wherein the first memory cell group includes memory cells having a threshold voltage to be in the erase state, and wherein the second memory cell group includes memory cells having a threshold voltage to be in one of the plurality of programming states; and A common programming pulse corresponding to the programming state that is closest to the erase state among the plurality of programming states is applied to the second memory cell group.

8. The memory device according to claim 7, wherein, The control circuit also includes: After the common programming pulse is applied to the second memory cell group, verification of the common programming pulse is performed; and Based on the results of the verification, it is determined whether the second memory cell group is defective.

9. The memory device according to claim 1, wherein, The number of programming states is the same as the number of programming pulses applied during each of the plurality of programming groups that divide the plurality of programming cycles.

10. A memory system comprising: A controller that determines the physical address corresponding to a write data entry and transmits the write data entry to the location corresponding to the physical address; as well as A memory device is configured to divide a plurality of programming cycles into a plurality of programming groups to store multi-bit data included in the write data entry into a plurality of memory cells, and to apply a different programming pulse corresponding to each of the plurality of programming groups to the plurality of memory cells, wherein the memory device executes the plurality of programming cycles in one or more odd programming cycles and one or more even programming cycles.

11. The memory system according to claim 10, in, The memory device also sends a completion notification to the controller after the multi-bit data has been fully programmed into the plurality of memory cells, and The controller also generates a mapping data entry that associates the logical address of the write data entry with the physical address.

12. The memory system according to claim 10, wherein, Each of the plurality of programming loops includes: The first operation controls the bit lines connected to the plurality of memory cells; The second operation involves applying a programming pulse corresponding to one of a plurality of programming states to the plurality of memory cells; and The third operation verifies the programming status of the plurality of memory cells, the programming status corresponding to the programming pulse.

13. The memory system according to claim 10, wherein, The memory device also includes: During one or more odd-numbered programming cycles, programming pulses are applied to the plurality of memory cells relating to a first programming state group, which includes a plurality of programming states and is closest to the erase state. During one or more even-numbered programming cycles, another programming pulse is applied to the plurality of memory cells relating to a second programming state group, which includes the programming state furthest from the erase state among the plurality of programming states.

14. The memory system according to claim 13, wherein, The first programming state group and the second programming state group are mutually exclusive.

15. The memory system according to claim 10, in, During the one or more odd-numbered programming cycles, programming pulses configured to program the programming state corresponding to LSB data 1 in the multi-bit data are applied to the plurality of memory cells, and During one or more even-numbered programming cycles, another programming pulse, configured to program the programming state corresponding to LSB data 0 in the multi-bit data, is applied to the plurality of memory cells.

16. The memory system of claim 10, wherein, The memory device also includes: Before dividing the plurality of programming cycles into the plurality of programming groups, the plurality of memory cells are divided into a first memory cell group and a second memory cell group, wherein the first memory cell group includes memory cells having a threshold voltage to be in an erase state, and wherein the second memory cell group includes memory cells having a threshold voltage to be in one of a plurality of programming states; and A common programming pulse corresponding to the programming state that is closest to the erase state among the plurality of programming states is applied to the second memory cell group.

17. The memory system according to claim 16, wherein, The memory device also includes: After the common programming pulse is applied to the second memory cell group, verification of the common programming pulse is performed; and Based on the results of the verification, it is determined whether the second memory cell group is defective.

18. A method of operating a memory device, the method comprising the steps of: Multiple memory cells storing multi-bit data corresponding to erase states and multiple programming states are divided into a first memory cell group and a second memory cell group. The first memory cell group includes memory cells having a threshold voltage corresponding to the erase state, and the second memory cell group includes memory cells having a threshold voltage corresponding to one of the multiple programming states. Apply a common programming pulse to the second memory cell group; The multiple programming loops to be executed to store the multi-bit data in the second memory cell group will be divided into multiple programming groups; Apply different programming pulses corresponding to each of the plurality of programming groups to the second memory cell group; and After successful verification in the multiple programming groups, the programming operation on the multi-bit data is terminated.

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