Analog-to-digital conversion circuits and equipment

Abstract

The present application relates to an analog-to-digital conversion circuit and device. The analog-to-digital conversion circuit includes: a loop filter, a quantizer, a single-frequency jitter generation module and a digital extraction filter. The above-mentioned analog-to-digital conversion circuit generates a single-frequency digital signal with a known frequency, and modulates the single-frequency digital signal into a 1-bit digital signal. The 1-bit digital signal is used to replace the pseudo-random jitter signal in the traditional technology. When the digital extraction filter is filtered, the 1-bit digital signal can be accurately filtered out to obtain a pure signal, that is, the second digital signal. Therefore, the analog-to-digital conversion circuit can disrupt the periodic output of the ∑‑Δ analog-to-digital converter, eliminate idle tones, and the digital extraction filter carried by the analog-to-digital conversion circuit can accurately filter out frequency components higher than the first digital signal and the 1-bit digital signal, thereby improving the spurious-free dynamic range of the analog-to-digital converter and the performance parameters such as the signal-to-noise and distortion ratio, and also improving the reliability of the output signal of the analog-to-digital conversion circuit.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital conversion, and in particular to an analog-to-digital conversion circuit and device. Background Art

[0002] ∑-Δ (Sigma-Delta) ADC is a commonly used high-precision ADC that uses oversampling and noise shaping technology to achieve high resolution and dynamic range. It has the advantages of low power consumption and high precision, and is widely used in consumer smart electronics, sensors, biomedicine and other fields. However, when a ∑-Δ ADC inputs a DC signal or a very slowly changing signal, a periodic sequence will appear in the output signal, and the energy at a certain frequency is very high, which appears as an idle tone, thereby reducing the spurious-free dynamic range and signal-to-noise and distortion ratio of the ∑-Δ ADC.

[0003] In traditional technology, a pseudo-random jitter signal is mainly superimposed on the input end of the ∑-Δ ADC to disrupt the periodic output of the ∑-Δ ADC, thereby eliminating idle tones. However, the pseudo-random jitter signal is difficult to eliminate, so the output signal of the ∑-Δ ADC will increase the background noise. Summary of the invention

[0004] Based on this, it is necessary to provide an analog-to-digital conversion circuit and device that can suppress idle tones in order to solve the above technical problems.

[0005] In a first aspect, an analog-to-digital conversion circuit is provided, comprising:

[0006] A loop filter, wherein the input end of the loop filter is used to receive an analog input signal;

[0007] A quantizer, an input end of the quantizer is connected to an output end of the loop filter, and the quantizer is used to convert an analog input signal into a first digital signal;

[0008] A single-frequency jitter generation module is used to generate a single-frequency digital signal and modulate it into a 1-bit digital signal. The frequency of the single-frequency digital signal is outside the bandwidth of the input analog signal.

[0009] A digital decimation filter, wherein the input end of the digital decimation filter is connected to the output end of the quantizer, and the digital decimation filter is used to filter out frequency components higher than the first digital signal and the 1-bit digital signal, and output a second digital signal.

[0010] In the above analog-to-digital conversion circuit, since the frequency of the single-frequency digital signal generated by the single-frequency jitter generation module is known, the frequency of the 1-bit digital signal modulated according to the single-frequency digital signal is also known, and its frequency is outside the bandwidth of the input analog signal, the 1-bit digital signal is used to replace the pseudo-random jitter signal in the traditional technology, and the 1-bit digital signal can be accurately filtered out when the digital extraction filter is filtered out, and a pure signal, i.e., the second digital signal, is obtained. Therefore, the traditional pseudo-random jitter signal is replaced by a 1-bit digital signal whose frequency is known and outside the bandwidth of the input analog signal, disrupting the periodic output of the ∑-Δ analog-to-digital converter, and eliminating idle tones. The digital extraction filter carried by the analog-to-digital conversion circuit can accurately filter out the frequency components higher than the first digital signal and the 1-bit digital signal, thereby improving the spurious-free dynamic range of the analog-to-digital converter and the performance parameters such as the signal-to-noise and distortion ratio, and also improving the reliability of the output signal of the analog-to-digital conversion circuit.

[0011] In one embodiment, the single frequency jitter generation module includes:

[0012] A periodic signal generator for generating a single-frequency digital signal;

[0013] The auxiliary modulator is connected to the periodic signal generator and is used for receiving the single-frequency digital signal and generating a 1-bit digital signal according to the single-frequency digital signal.

[0014] In one embodiment, a first input terminal of the quantizer is connected to an output terminal of the loop filter, and a second input terminal of the quantizer is connected to an output terminal of the single-frequency jitter generating module.

[0015] In one embodiment, the circuit further comprises:

[0016] A digital-to-analog converter, wherein the input end of the digital-to-analog converter is connected to the output end of the quantizer, the output end of the digital-to-analog converter is connected to the input end of the loop filter, and the digital-to-analog converter is used to convert the first digital signal into a feedback analog signal.

[0017] In one embodiment, a first input terminal of the digital-to-analog converter is connected to an output terminal of the quantizer, and a second input terminal of the digital-to-analog converter is connected to an output terminal of the single-frequency jitter generating module.

[0018] In one embodiment, the quantizer comprises:

[0019] A plurality of first switches, wherein a first input end of the first switch is used to access a first reference voltage, and a second input end of the first switch is used to access a second reference voltage;

[0020] A plurality of first capacitors, wherein input ends of the plurality of first capacitors are respectively connected to output ends of the plurality of first switches correspondingly;

[0021] a second switch, wherein an input end of the second switch is connected to an output end of the loop filter;

[0022] A comparator, wherein a first input terminal of the comparator is respectively connected to an output terminal of the first capacitor and an output terminal of the second switch, and a second input terminal of the comparator is used to access a third reference voltage;

[0023] A control circuit, wherein an input end of the control circuit is connected to an output end of the comparator, a plurality of control ends of the control circuit are respectively connected to controlled ends of a plurality of first switches, and an output end of the control circuit is connected to an input end of a digital decimation filter;

[0024] A second capacitor, wherein an output terminal of the second capacitor is connected to the first input terminal of the comparator;

[0025] The third switch, the first input end of the third switch is used to connect to the first reference voltage, the second input end of the third switch is used to connect to the second reference voltage, the output end of the third switch is connected to the input end of the second capacitor, the controlled end of the third switch is connected to the output end of the single-frequency jitter generation module, and the third switch is used to alternately connect the first reference voltage and the second reference voltage to the first input end of the comparator under the drive of the single-frequency digital signal, so as to trigger the control circuit to adjust the conduction state of multiple first switches and output the first digital signal.

[0026] In one embodiment, the digital-to-analog converter comprises:

[0027] A fourth switch, wherein an input end of the fourth switch is used to connect to an external power supply, and a controlled end of the fourth switch is connected to an output end of the single-frequency jitter generating module;

[0028] a fifth switch, wherein an input end of the fifth switch is connected to an output end of the fourth switch, and a controlled end of the fifth switch is connected to an output end of the single-frequency jitter generating module;

[0029] an amplifier, wherein a first input terminal of the amplifier is connected to a common connection terminal of the fourth switch and the fifth switch, a second input terminal of the amplifier is used to access a fourth reference voltage, and an output terminal of the amplifier is connected to an input terminal of the loop filter;

[0030] A plurality of sixth switches, wherein an input end of each sixth switch is used to connect to an external power supply, a controlled end of each sixth switch is connected to an output end of the quantizer, and an output end of each sixth switch is connected to an input end of the amplifier;

[0031] A plurality of seventh switches, wherein the input end of each seventh switch is respectively connected to the output end of each sixth switch, the controlled end of each seventh switch is connected to the output end of the quantizer, and the output end of each seventh switch is grounded;

[0032] A plurality of first current sources, each of which is connected in series between the external power source and the input end of the fourth switch, and between the input end of the sixth switch;

[0033] A plurality of second current sources, each second current source being connected in series between the ground and the output terminal of the fifth switch, and between the ground and the output terminal of the seventh switch;

[0034] Among them, the fourth switch and the sixth switch are both turned on when a high level signal is connected, and are turned off when a low level signal is connected, and the fifth switch and the seventh switch are both turned off when a high level signal is connected, and are turned on when a low level signal is connected.

[0035] In one embodiment, the periodic signal generator is used to generate a single-frequency multi-bit width sinusoidal wave signal.

[0036] In one embodiment, the frequency range of the analog input signal is 20 Hz to 20 kHz.

[0037] In a second aspect, a device is provided, comprising an analog-to-digital conversion circuit of the above circuit.

[0038] A device equipped with the above analog-to-digital conversion circuit can further improve the reliability of device signal processing based on the improvement of the reliability of the output signal of the analog-to-digital conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 One of the structural schematic diagrams of an analog-to-digital conversion circuit in an embodiment;

[0041] Figure 2 It is a structural schematic diagram of a single-frequency jitter generating module in one embodiment;

[0042] Figure 3 The second structural diagram of the analog-to-digital conversion circuit in one embodiment;

[0043] Figure 4 is a schematic diagram of the structure of a quantizer in one embodiment;

[0044] Figure 5 FIG. 4 is a schematic diagram of the structure of a digital-to-analog converter in an embodiment. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0048] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0049] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, components, parts or combinations thereof.

[0050] In one embodiment, Figure 1 As shown, an analog-to-digital conversion circuit is provided, including: a loop filter 102 , a quantizer 104 , a single-frequency jitter generation module 106 , and a digital decimation filter 108 .

[0051] Among them, the input end of the loop filter 102 is used to access the analog input signal. The loop filter 102 is used to selectively filter the analog input signal to obtain the output signal expected by the user. The selection of the loop filter 102 can be determined based on the desired output signal characteristics, for example, it can be determined based on the frequency band of the output signal expected by the user, by selectively processing the signal within a specific frequency range, suppressing interference signals or noise, and retaining the signal components of interest to ensure the effective transmission and processing of the required signal, thereby improving the signal data reliability of the digital-to-analog conversion circuit. Optionally, the loop filter 102 can perform weighted summation on the analog input signal and other signals received at its input end to obtain a processed analog input signal.

[0052] The input end of the quantizer 104 is connected to the output end of the loop filter 102, and the quantizer 104 is used to convert the analog input signal into a first digital signal. The quantizer 104 quantizes the amplitude of the analog input signal received at its input end and converts it into a discrete first digital signal. The quantizer 104 can be used to convert the analog signal into a digital signal, thereby reducing the influence of noise and distortion in the subsequent signal processing or transmission process. At the same time, the digital signal can be compressed, which can reduce the space and bandwidth required for storage and transmission, and improve the efficiency of data processing and transmission.

[0053] The single-frequency jitter generating module 106 is used to generate a single-frequency digital signal and modulate it into a 1-bit digital signal. The frequency of the single-frequency digital signal is outside the bandwidth of the input analog signal.

[0054] The single-frequency jitter generation module 106 can generate a single-frequency digital signal with a known frequency, and modulate the single-frequency digital signal into a 1-bit digital signal. The frequency of the single-frequency digital signal is outside the bandwidth of the input analog signal. On the one hand, it can prevent the injected jitter signal from interfering with the original input analog signal during transmission. On the other hand, in the subsequent signal processing part, the different frequencies of the single-frequency digital signal and the input analog signal can be processed in a targeted manner. For example, the single-frequency digital signal can be simply filtered out in the filtering part to ensure that a pure signal can be obtained.

[0055] The input end of the digital decimation filter 108 is connected to the output end of the quantizer 104. The digital decimation filter 108 is used to filter out frequency components higher than the first digital signal and the 1-bit digital signal, and output a second digital signal.

[0056] The digital decimation filter 108 performs filtering processing on the signal received at its input end to filter out the frequency components higher than the first digital signal and the 1-bit digital signal to obtain a pure second digital signal. In addition, the digital decimation filter 108 can also perform timing filtering and reconstruction on the signal in the time domain to eliminate the influence of noise and distortion on the signal in the time domain.

[0057] In the above analog-to-digital conversion circuit, since the frequency of the single-frequency digital signal generated by the single-frequency jitter generation module 106 is known, the frequency of the 1-bit digital signal modulated according to the single-frequency digital signal is also known, and its frequency is outside the bandwidth of the input analog signal, the 1-bit digital signal is used to replace the pseudo-random jitter signal in the traditional technology, and when the digital extraction filter 108 is filtered, the 1-bit digital signal can be accurately filtered out to obtain a pure signal, that is, the second digital signal. Therefore, the 1-bit digital signal whose frequency is known and outside the bandwidth of the input analog signal is used to replace the traditional pseudo-random jitter signal, disrupting the periodic output of the ∑-Δ analog-to-digital converter, and eliminating the idle tone. The digital extraction filter 108 carried by the analog-to-digital conversion circuit can accurately filter out the frequency components higher than the first digital signal and the 1-bit digital signal, thereby improving the spurious-free dynamic range of the analog-to-digital converter and the performance parameters such as the signal-to-noise and distortion ratio, and also improving the reliability of the output signal of the analog-to-digital conversion circuit.

[0058] In one embodiment, Figure 2 As shown, the single-frequency jitter generating module 106 includes: a periodic signal generator 1062 and an auxiliary modulator 1064 .

[0059] The periodic signal generator 1062 is used to generate a single-frequency digital signal. The frequency of the single-frequency digital signal is known, and the frequency is outside the bandwidth of the analog input signal frequency. For example, when the frequency of the analog input signal is 20KHz, the frequency of the single-frequency digital signal can be 60KHz. When the single-frequency digital signal is injected, it will not have a negative impact on the original signal, and it can be used to simply and quickly separate and extract the analog input signal and the single-frequency digital signal when the signal is subsequently processed. In addition, the single-frequency digital signal only includes one frequency component, and is relatively stable and has a strong anti-interference ability. Therefore, when the single-frequency digital signal is subsequently processed or transmitted, the complexity of the analog-to-digital conversion circuit can be reduced, and the fault tolerance of the analog-to-digital conversion circuit can be improved.

[0060] Of course, the above examples do not limit the frequencies of the analog input signal and the single-frequency digital signal, which will not be elaborated here.

[0061] The auxiliary modulator 1064 is connected to the periodic signal generator 1062 and is used to receive the single-frequency digital signal and generate a 1-bit digital signal according to the single-frequency digital signal.

[0062] The method of generating a 1-bit digital signal from a single-frequency digital signal varies in different application scenarios. Taking the field of audio coding as an example, in audio coding, a quantization algorithm can be used to convert a single-frequency multi-bit width signal into a 1-bit digital signal to achieve audio data compression. Of course, in other application scenarios, other more appropriate processing methods can be used to convert a single-frequency multi-bit width signal into a 1-bit digital signal to meet different application requirements, which will not be repeated here.

[0063] In one embodiment, Figure 1 As shown, a first input end of the quantizer 104 is connected to an output end of the loop filter 102 , and a second input end of the quantizer 104 is connected to an output end of the single-frequency jitter generating module 106 .

[0064] The first input end of the quantizer 104 is connected to the output end of the loop filter 102, and is used to receive the analog input signal output from the output end of the loop filter 102. The second input end of the quantizer 104 is connected to the output end of the single-frequency jitter generation module 106, and is used to receive the 1-bit digital signal output from the output end of the single-frequency jitter generation module 106. At this time, the 1-bit digital signal is injected from the input end of the quantizer 104 and superimposed with the analog input signal at the first input end of the quantizer 104, so as to disrupt the periodic output of the quantizer 104, and then disrupt the periodic output of the analog-to-digital conversion circuit, thereby eliminating the idle tone.

[0065] In one embodiment, Figure 3 As shown, the analog-to-digital conversion circuit further includes: a digital-to-analog converter 110. The input end of the digital-to-analog converter 110 is connected to the output end of the quantizer 104, and the output end of the digital-to-analog converter 110 is connected to the input end of the loop filter 102. The digital-to-analog converter 110 is used to convert the first digital signal into a feedback analog signal.

[0066] The input end of the digital-to-analog converter 110 is connected to the output end of the quantizer 104, and is used to receive the first digital signal output by the output end of the quantizer 104, and convert the first digital signal into a feedback analog signal, complete the conversion of the digital quantity signal to the analog quantity signal, and transmit the feedback analog signal to the input end of the loop filter 102, and complete the feedback of the analog-to-digital conversion circuit. The digital-to-analog converter 110 adds a feedback circuit part of the analog-to-digital conversion circuit. The feedback circuit can improve the accuracy, stability and reliability of the circuit. The feedback circuit can adjust and correct the circuit characteristics, reduce the nonlinear distortion of the circuit, and make it closer to a linear response. This is very important in application fields such as the audio field and the radio field, and can improve the accuracy of the signal. Therefore, the digital-to-analog converter 110 and the feedback circuit composed of it can improve the accuracy, stability and reliability of the analog-to-digital conversion circuit.

[0067] In one embodiment, Figure 3 As shown, a first input end of the digital-to-analog converter 110 is connected to an output end of the quantizer 104 , and a second input end of the digital-to-analog converter 110 is connected to an output end of the single-frequency jitter generating module 106 .

[0068] The first input end of the digital-to-analog converter 110 is connected to the output end of the quantizer 104, and is used to receive the first digital signal output from the output end of the quantizer 104. The second input end of the digital-to-analog converter 110 is connected to the output end of the single-frequency jitter generation module 106, and is used to receive the 1-bit digital signal output from the output end of the single-frequency jitter generation module 106. At this time, the 1-bit digital signal is injected from the input end of the digital-to-analog converter 110, and is superimposed with the first digital signal at the first input end of the digital-to-analog converter 110, and after being processed by the digital-to-analog converter 110, a feedback analog signal is obtained, and then injected into the input end of the loop filter 102 in the form of a feedback analog signal, so as to disrupt the periodic output of the loop filter 102, and then disrupt the periodic output of the analog-to-digital conversion circuit, thereby eliminating the idle tone.

[0069] In one embodiment, Figure 4 As shown, the quantizer 104 includes: a plurality of first switches 1041 (A1-A M ), a plurality of first capacitors 1042 (C*2-C*2 M ), a second switch 1043 (SW0 in the figure), a comparator 1044, a control circuit 1045, a second capacitor 1046 (C1 in the figure) and a third switch 1047 (S1 in the figure).

[0070] The first input terminal of the first switch 1041 is used to access the first reference voltage VREFP, and the second input terminal of the first switch 1041 is used to access the second reference voltage VREFN.

[0071] The quantizer 104 has multiple first switches 1041. The first input end of the first switch 1041 is used to access the first reference voltage VREFP, which can be a high-level voltage or a low-level voltage; the second input end of the first switch 1041 is used to access the second reference voltage VREFN, which is set corresponding to the first reference voltage VREFP and can be a low-level voltage or a high-level voltage.

[0072] Input terminals of the plurality of first capacitors 1042 are connected to output terminals of the plurality of first switches 1041 , respectively.

[0073] The first capacitor 1042 is connected to the first reference voltage VREFP or the second reference voltage VREFN and is controlled by the corresponding first switch 1041. In addition, the capacitance value of the first capacitor 1042 can be configured according to requirements. Setting multiple first capacitors 1042 can achieve refined charge separation and more accurate voltage measurement, thereby improving the performance of the quantizer 104.

[0074] An input end of the second switch 1043 is connected to an output end of the loop filter 102 .

[0075] When the input terminal of the quantizer 104 receives the analog input signal VIP, the second switch 1043 is closed, otherwise it is opened.

[0076] A first input terminal of the comparator 1044 is connected to the output terminal of the first capacitor 1042 and the output terminal of the second switch 1043 respectively, and a second input terminal of the comparator 1044 is used to access a third reference voltage.

[0077] The comparator 1044 is used to control the access of the high level voltage or the low level voltage of the quantizer 104. The on and off of the high level voltage and the low level voltage can be judged by comparing the analog input signal VIP of the quantizer 104 with the third reference voltage of the quantizer 104. Taking the first reference voltage VREFP as a high level voltage and the second reference voltage VREFN as a low level voltage as an example, when the voltage of the analog input signal VIP received at the input end of the quantizer 104 is higher than the third reference voltage set by the quantizer 104, the quantizer 104 determines the analog input signal VIP at this time as a high level voltage signal. At this time, the first switch 1041 is connected to the first reference voltage VREFP, that is, the first switch 1041 is connected to its first input end; conversely, the first switch 1041 is connected to its second input end; the amplitude of the analog signal can be judged by connecting the first reference voltage VREFP or the second reference voltage VREFN, and the corresponding digital code is output according to the comparison result to convert the analog signal into a digital signal.

[0078] Among them, the third reference voltage of the quantizer 104 can be obtained according to the actual needs of the application environment, such as an environmental reference voltage source, an internal circuit reference voltage source and an external circuit reference voltage source. These reference voltage sources can be fixed-value voltage sources or programmable voltage sources, which are mainly used to provide a stable third reference voltage for the quantizer 104.

[0079] In addition to being directly compared with the third reference voltage set by the quantizer 104, the voltage of the analog input signal VIP received by the input end of the quantizer 104 can also be compared after setting a corresponding correspondence. The commonly used comparison relationship is: when the voltage of the input signal received by the input end of the quantizer 104 is higher than half of the third reference voltage set by the quantizer 104, the input signal at this time is determined to be a high-level voltage. Of course, in addition to the above-mentioned correspondence, other correspondences can be used between the input signal of the quantizer 104 and the third reference voltage of the quantizer 104. The specific correspondence can be set according to the actual needs of the application scenario, which is only used as an example here.

[0080] The input end of the control circuit 1045 is connected to the output end of the comparator 1044, the multiple control ends of the control circuit 1045 are respectively connected to the controlled ends of the multiple first switches 1041, and the output end of the control circuit 1045 is connected to the input end of the digital extraction filter 108. Figure 4 As shown, the M control terminals of the control circuit 1045 are respectively connected to the M first switches 1041 (A1-A M )’s controlled end corresponding connection.

[0081] The control circuit 1045 is set to obtain a digital signal that is closer to the analog input signal VIP. By successive approximation, the analog input signal VIP is as close as possible, and at the same time, the mismatch of multiple first capacitors 1042 can be shaped in the first order. The mismatch of the above-mentioned multiple first capacitors 1042 refers to: when using multiple first capacitors 1042, there are slight differences between different first capacitors 1042. The appearance of this mismatch will cause the performance of the quantizer 104 to degrade, which is specifically manifested as the increase of quantization error and the decrease of linearity of the quantizer 104. In order to solve the capacitor mismatch problem, multiple control terminals of the control circuit 1045 can be connected to the controlled terminals of multiple first switches 1041, and then the mismatch of the capacitor is shaped in the first order, and the harmonic energy generated by the mismatch is dispersed to the noise energy of each frequency point of the entire signal bandwidth in the spectrum, reducing the nonlinear distortion of the signal, improving the performance and accuracy of the quantizer 104, and then improving the linearity and spurious-free dynamic range indicators of the analog-to-digital converter, making the analog-to-digital converter more stable and reliable.

[0082] The capacitor mismatch problem can also be solved by other methods and measures, such as adding a calibration circuit to adjust the capacitance value or channel gain of the first capacitor 1042; or using a digital algorithm to compensate for the nonlinear error caused by the capacitor mismatch. Of course, the above methods and measures are only examples and do not limit the specific means of solving the capacitor mismatch problem.

[0083] An output terminal of the second capacitor 1046 is connected to a first input terminal of the comparator 1044 .

[0084] The digital signal is converted into an analog signal after passing through the second capacitor 1046 , and the analog signal is transmitted to the first input terminal of the comparator 1044 as an input signal of the comparator 1044 .

[0085] The first input end of the third switch 1047 is used to connect to the first reference voltage VREFP, the second input end of the third switch 1047 is used to connect to the second reference voltage VREFN, the output end of the third switch 1047 is connected to the input end of the second capacitor 1046, the controlled end of the third switch 1047 is connected to the output end of the single-frequency jitter generation module 106, and the third switch 1047 is used to alternately connect the first reference voltage VREFP and the second reference voltage VREFN to the first input end of the comparator 1044 under the drive of the single-frequency digital signal to trigger the control circuit 1045 to adjust the conduction state of the multiple first switches 1041 and output the first digital signal.

[0086] The single-frequency jitter generation module 106 controls the third switch 1047, controls the third switch 1047 to access the first reference voltage VREFP or the second reference voltage VREFN, and injects the single-frequency jitter generation module 106 to generate a single-frequency digital signal, which can be modulated into a 1-bit digital signal. After the single-frequency digital signal flows through the second capacitor 1046, it is converted into a corresponding analog signal according to the single-frequency digital signal, and then input into the first input terminal of the comparator 1044, completing the injection of the single-frequency digital signal to replace the pseudo-random jitter signal in the traditional technology, so as to disrupt the periodic output of the ∑-Δ analog-to-digital converter, thereby eliminating the idle tone.

[0087] The third switch 1047 is used to alternately connect the first reference voltage VREFP and the second reference voltage VREFN to the first input terminal of the comparator 1044 under the drive of the single-frequency digital signal. After the signal received by the first input terminal of the comparator 1044 changes, the control circuit 1045 is triggered to adjust the conduction state of the plurality of first switches 1041 and output the first digital signal Dout. [N：0] .

[0088] The quantizer 104 may be a successive approximation analog-to-digital converter, which is a low-power analog-to-digital converter that uses the successive approximation method to perform analog-to-digital conversion. The successive approximation analog-to-digital converter is suitable for applications with high accuracy requirements and slow conversion speed.

[0089] Therefore, the quantizer 104 in this solution can also be a flash analog-to-digital converter, which can replace the above-mentioned successive approximation digital-to-analog converter 110 to convert analog signals into digital signals. The flash analog-to-digital converter is a high-speed analog-to-digital converter that performs analog-to-digital conversion by comparing the magnitude of the analog input voltage with a series of reference voltages. Specifically, the flash analog-to-digital converter divides the analog input signal into a plurality of small intervals, and uses a plurality of comparators 1044 to determine which interval the input signal falls into. Each interval corresponds to an output bit of a comparator 1044, and these bits are processed by an encoder to form the final digital output. The main advantage of the flash analog-to-digital converter is that it is fast and can achieve high-speed analog-to-digital conversion. However, it requires a large number of comparators 1044 and encoders, so it is costly and consumes a lot of power.

[0090] Of course, the quantizer 104 may also use other types of analog-to-digital converters. The selection of the device can be made according to the requirements of the actual application scenario, and will not be repeated here.

[0091] In one embodiment, Figure 5 As shown, the digital-to-analog converter 110 includes: a fourth switch 1101 , a fifth switch 1102 , an amplifier 1103 , a plurality of sixth switches 1104 , a plurality of seventh switches 1105 , a plurality of first current sources 1106 , and a plurality of second current sources 1107 .

[0092] The input end of the fourth switch 1101 is used to connect to an external power source, and the controlled end of the fourth switch 1101 is connected to the output end of the single-frequency jitter generating module 106 .

[0093] The controlled end of the fourth switch 1101 is connected to the output end of the single-frequency jitter generation module 106, and the output signal of the single-frequency jitter generation module 106, that is, the 1-bit digital signal, controls the opening and closing of the fourth switch 1101. Specifically, when the 1-bit digital signal of the single-frequency jitter generation module 106 is a high level "1", the fourth switch 1101 is closed; when the 1-bit digital signal of the single-frequency jitter generation module 106 is a low level "0", the fourth switch 1101 is opened.

[0094] The input end of the fifth switch 1102 is connected to the output end of the fourth switch 1101, and the controlled end of the fifth switch 1102 is connected to the output end of the single-frequency jitter generation module 106. The controlled end of the fifth switch 1102 is connected to the output end of the single-frequency jitter generation module 106, and the output signal of the single-frequency jitter generation module 106, that is, the 1-bit digital signal, controls the opening and closing of the fifth switch 1102. Specifically, when the 1-bit digital signal of the single-frequency jitter generation module 106 is a high level "1", the fifth switch 1102 is opened; when the 1-bit digital signal of the single-frequency jitter generation module 106 is a low level "0", the fifth switch 1102 is closed.

[0095] The first input end of the amplifier 1103 is connected to the common connection end of the fourth switch 1101 and the fifth switch 1102, the second input end of the amplifier 1103 is used to access the fourth reference voltage, and the output end of the amplifier 1103 is connected to the input end of the loop filter 102. When the digital-to-analog converter 110 converts the analog signal into a digital signal, it is necessary to amplify the analog signal to a certain range to ensure conversion precision and accuracy. In this process, the amplifier 1103 is responsible for amplifying the input analog signal to an appropriate range for digital-to-analog conversion. The range is determined by the fourth reference voltage connected to the second input end of the amplifier 1103, and the fourth reference voltage can be determined according to the amplitude range and accuracy of the analog signal to be converted, that is, according to the amplitude range and accuracy of the feedback analog signal, and can be specifically set and adjusted by the external circuit or internal register of the digital-to-analog converter 110. Generally, the fourth reference voltage is slightly larger than the maximum amplitude of the feedback analog signal to ensure that saturation does not occur during the conversion process.

[0096] By properly setting the fourth reference voltage, the accuracy and precision of the digital-to-analog conversion can be improved, and the first digital signal can be converted within an appropriate range. At the same time, attention should also be paid to the stability and noise level of the fourth reference voltage to avoid adverse effects on the conversion result.

[0097] In addition, the amplifier 1103 can also improve the signal-to-noise ratio of the signal, that is, the ratio of the signal to the noise. The amplifier 1103 increases the signal strength by increasing the voltage or current of the signal, and relatively reduces the influence of the noise on the signal, thereby improving the signal-to-noise ratio.

[0098] The input end of each sixth switch 1104 is used to connect to an external power supply, the controlled end of each sixth switch 1104 is connected to the output end of the quantizer 104, and the output end of each sixth switch 1104 is connected to the input end of the amplifier 1103. The external power supply provides the required working voltage for the digital-to-analog converter 110, and is connected to the digital-to-analog converter 110 through multiple sixth switches 1104. Each sixth switch 1104 is controlled by the output of the quantizer 104. Specifically, when the first digital signal outputted from the output end of the quantizer 104 is at a high level, each sixth switch 1104 is controlled to be closed; otherwise, each sixth switch 1104 is controlled to be open.

[0099] The input ends of the seventh switches 1105 are respectively connected to the output ends of the sixth switches 1104, the controlled ends of the seventh switches 1105 are connected to the output ends of the quantizer 104, and the output ends of the seventh switches 1105 are grounded. The seventh switches 1105 are controlled by the output of the quantizer 104. Specifically, when the first digital signal outputted from the output end of the quantizer 104 is at a low level, the seventh switches 1105 are controlled to be closed; otherwise, the seventh switches 1105 are controlled to be opened.

[0100] Each first current source 1106 is connected in series between the external power supply and the input end of the fourth switch 1101, and between the input end of the sixth switch 1104. The first current source 1106 can provide a current matching the first digital signal. The matching current can convert the first digital signal into a current range suitable for processing by the digital-to-analog converter 110, so as to improve the anti-interference ability and dynamic range of the converter.

[0101] Each second current source 1107 is connected in series one by one between the ground and the output terminal of the fifth switch 1102, and between the ground and the output terminal of the seventh switch 1105. Similar to the first current source 1106, the second current source 1107 can provide a current that matches the first digital signal. The matching current can convert the first digital signal into a current range suitable for processing by the digital-to-analog converter 110, so as to improve the anti-interference ability and dynamic range of the converter.

[0102] The matching current provided by the first current source 1106 processes the positive voltage portion of the first digital signal, and the matching current provided by the second current source 1107 processes the negative voltage portion of the first digital signal. By adjusting the size and polarity of the two current sources, it can be ensured that the input signal does not exceed the range of the converter during the conversion process, thereby ensuring the accuracy and precision of the conversion.

[0103] Among them, the fourth switch 1101 and the sixth switch 1104 are both turned on when a high level signal is connected, and turned off when a low level signal is connected, and the fifth switch 1102 and the seventh switch 1105 are both turned off when a high level signal is connected, and turned on when a low level signal is connected.

[0104] In one embodiment, the periodic signal generator 1062 is used to generate a single-frequency multi-bit-width sinusoidal wave signal.

[0105] The single-frequency digital signal generated by the periodic signal generator 1062 can be a multi-bit width sine wave signal. The single-frequency digital signal can also be a single-frequency multi-bit width signal such as a sine wave signal, a square wave signal, a sawtooth wave signal, such as a 16-bit multi-bit width sine wave signal and a 24-bit multi-bit width square wave signal. This single-frequency multi-bit width signal is commonly used in the audio and music fields to achieve high-fidelity audio playback and synthesis. In audio coding, the use of a single-frequency multi-bit width signal can provide a higher dynamic range and lower distortion. At the same time, a higher bit width means that the amplitude of the single-frequency multi-bit width signal can be more finely represented and adjusted. Of course, the above examples do not limit the specific form of the single-frequency digital signal, and will not be repeated here.

[0106] In one embodiment, the frequency range of the analog input signal is 20 Hz to 20 kHz. The analog input signal with a frequency in the range of 20 Hz to 20 kHz can be converted to digital using the analog-to-digital conversion circuit to eliminate the idle tone.

[0107] In one embodiment, a device is provided, comprising the analog-to-digital conversion circuit of any one of the above embodiments.

[0108] A device equipped with the above analog-to-digital conversion circuit can further improve the reliability of device signal processing based on the improvement of the reliability of the output signal of the analog-to-digital conversion circuit.

[0109] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0110] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An analog-to-digital conversion circuit, characterized in that: include: A loop filter, wherein an input end of the loop filter is used to receive an analog input signal; A quantizer, wherein an input end of the quantizer is connected to an output end of the loop filter, and the quantizer is used to convert the analog input signal into a first digital signal; A single-frequency jitter generation module, used to generate a single-frequency digital signal and modulate it into a 1-bit digital signal, wherein the frequency of the single-frequency digital signal is outside the bandwidth of the input analog signal; A digital decimation filter, wherein an input end of the digital decimation filter is connected to an output end of the quantizer, and the digital decimation filter is used to filter out frequency components higher than the first digital signal and the 1-bit digital signal, and output a second digital signal; Wherein, the quantizer comprises: A plurality of first switches, wherein a first input end of the first switch is used to access a first reference voltage, and a second input end of the first switch is used to access a second reference voltage; A plurality of first capacitors, wherein input ends of the plurality of first capacitors are respectively connected to output ends of the plurality of first switches correspondingly; a second switch, wherein an input end of the second switch is connected to an output end of the loop filter; a comparator, wherein a first input terminal of the comparator is respectively connected to an output terminal of the first capacitor and an output terminal of the second switch, and a second input terminal of the comparator is used to access a third reference voltage; A control circuit, wherein an input end of the control circuit is connected to an output end of the comparator, a plurality of control ends of the control circuit are respectively connected to controlled ends of the plurality of first switches, and an output end of the control circuit is connected to an input end of the digital decimation filter; a second capacitor, wherein an output terminal of the second capacitor is connected to the first input terminal of the comparator; A third switch, wherein the first input end of the third switch is used to connect to a first reference voltage, the second input end of the third switch is used to connect to a second reference voltage, the output end of the third switch is connected to the input end of the second capacitor, the controlled end of the third switch is connected to the output end of the single-frequency jitter generation module, and the third switch is used to alternately connect the first reference voltage and the second reference voltage to the first input end of the comparator under the drive of the single-frequency digital signal, so as to trigger the control circuit to adjust the conduction state of the multiple first switches and output the first digital signal.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The single-frequency jitter generation module comprises: A periodic signal generator for generating a single-frequency digital signal; The auxiliary modulator is connected to the periodic signal generator and is used for receiving the single-frequency digital signal and generating a 1-bit digital signal according to the single-frequency digital signal.

3. The analog-to-digital conversion circuit according to claim 1, characterized in that: The first input end of the quantizer is connected to the output end of the loop filter, and the second input end of the quantizer is connected to the output end of the single-frequency jitter generating module.

4. The analog-to-digital conversion circuit according to claim 1, characterized in that: The circuit further comprises: A digital-to-analog converter, wherein the input end of the digital-to-analog converter is connected to the output end of the quantizer, the output end of the digital-to-analog converter is connected to the input end of the loop filter, and the digital-to-analog converter is used to convert the first digital signal into a feedback analog signal.

5. The analog-to-digital conversion circuit according to claim 4, characterized in that: The first input end of the digital-to-analog converter is connected to the output end of the quantizer, and the second input end of the digital-to-analog converter is connected to the output end of the single-frequency jitter generating module.

6. The analog-to-digital conversion circuit according to claim 5, characterized in that: The digital-to-analog converter comprises: a fourth switch, wherein an input end of the fourth switch is used to connect to an external power supply, and a controlled end of the fourth switch is connected to an output end of the single-frequency jitter generating module; a fifth switch, wherein an input end of the fifth switch is connected to an output end of the fourth switch, and a controlled end of the fifth switch is connected to an output end of the single-frequency jitter generating module; an amplifier, wherein a first input end of the amplifier is connected to a common connection end of the fourth switch and the fifth switch, a second input end of the amplifier is used to access a fourth reference voltage, and an output end of the amplifier is connected to an input end of the loop filter; A plurality of sixth switches, wherein an input end of each of the sixth switches is used to connect to the external power supply, a controlled end of each of the sixth switches is connected to an output end of the quantizer, and an output end of each of the sixth switches is connected to an input end of the amplifier; A plurality of seventh switches, wherein an input end of each of the seventh switches is respectively connected to an output end of each of the sixth switches, a controlled end of each of the seventh switches is connected to an output end of the quantizer, and an output end of each of the seventh switches is grounded; a plurality of first current sources, each of the first current sources being connected in series between the external power source and the input end of the fourth switch, and between the first current sources and the input end of the sixth switch; a plurality of second current sources, each of the second current sources being connected in series between the ground and the output terminal of the fifth switch, and between the ground and the output terminal of the seventh switch; The fourth switch and the sixth switch are both turned on when a high level signal is connected, and are turned off when a low level signal is connected. The fifth switch and the seventh switch are both turned off when a high level signal is connected, and are turned on when a low level signal is connected.

7. The analog-to-digital conversion circuit according to claim 2, characterized in that: The periodic signal generator is used to generate a single-frequency multi-bit width sinusoidal wave signal.

8. The analog-to-digital conversion circuit according to claim 1, characterized in that: The frequency range of the analog input signal is 20 Hz to 20 kHz.

9. An analog-to-digital conversion device, characterized in that: The method comprises an analog-to-digital conversion circuit as described in any one of claims 1 to 8.

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