Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a plurality of data lines, a plurality of first scan lines intersecting the data lines, and a plurality of sub-pixels, each of which comprises a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit, the pixel driving circuit is located in the main non-opening area and is electrically connected to the corresponding data line and the corresponding first scan line, and the pixel electrode is at least partially located in the opening area; wherein the display panel further comprises a plurality of polar plates, at least one of which is located in the main non-opening area of the corresponding sub-pixel area, between the corresponding data line and the adjacent data line electrically connected to the pixel driving circuit in the main non-opening area, and is electrically connected to the adjacent data line; the polar plate and the pixel electrode in the opening area of the corresponding sub-pixel area form a first capacitor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel and a display device. Background Technology

[0002] The development of LCD panels has pushed bezel widths closer to their limits, making narrow bezels a major trend in the future market. In terms of design, narrow bezels are achieved by moving the GOA (Gatedriver on Array) from the left and right sides of the LCD panel to the source driver side. However, this design involves more vertical traces, which create significant parasitic capacitance with the pixel electrodes. Related technologies use dummy datalines on the opposite side of the sub-pixel to balance the parasitic capacitance. These dummy datalines form a balancing capacitance with the pixel electrodes, thus balancing the parasitic capacitance on both sides of the sub-pixel. However, dummy datalines reduce the aperture ratio. Summary of the Invention

[0003] This invention provides a display panel and a display device that can improve the technical problem that virtual data lines reduce the aperture ratio.

[0004] An embodiment of the present invention provides a display panel including a display area, the display area including a plurality of sub-pixel areas, each sub-pixel area including an opening area and a non-opening area, the non-opening area including a main non-opening area located on one side of the opening area, the display panel including: a plurality of data lines extending along a first direction, a plurality of first scan lines extending along a second direction intersecting the first direction; and a plurality of sub-pixels, each sub-pixel located within a corresponding sub-pixel area and including a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit, the pixel driving circuit being located within the main non-opening area and electrically connected to the corresponding data line and the corresponding first scan line, the pixel electrode being at least partially located within the opening area; wherein, the display panel further includes a plurality of electrode plates, at least one electrode plate being located within the main non-opening area of ​​the corresponding sub-pixel area, located between the corresponding data line electrically connected to the pixel driving circuit within the main non-opening area and an adjacent data line, and electrically connected to the adjacent data line; the electrode plate and the pixel electrode within the opening area of ​​the corresponding sub-pixel area form a first capacitor.

[0005] In some embodiments, at least one of the pixel electrodes includes an extension located within a corresponding main non-aperture region, and at least one electrode plate overlaps with the corresponding extension in a top-view perspective.

[0006] In some embodiments, at least one of the pixel electrodes includes a main electrode and a plurality of branch electrodes connected to the main electrode, and at least one of the branch electrodes includes the extension portion.

[0007] In some embodiments, the width of at least one of the electrode plates is greater than the width of the corresponding data line.

[0008] In some embodiments, the display panel further includes a plurality of second scan lines extending along the first direction, each second scan line being electrically connected to a corresponding first scan line and located on a different layer from the corresponding first scan line.

[0009] In some embodiments, each of the electrode plates is electrically connected to an adjacent data line via a bridging portion that crosses the corresponding second scan line.

[0010] In some embodiments, the display panel includes a first conductive layer, a first insulating layer located on the first metal layer, and a second conductive layer located on the first insulating layer. The first conductive layer includes a plurality of first scan lines and a plurality of bridging portions. The second conductive layer includes a plurality of second scan lines, a plurality of data lines, and a plurality of electrode plates. Each bridging portion is electrically connected between a corresponding electrode plate and an adjacent data line through a via in the first insulating layer.

[0011] In some embodiments, the first conductive layer further includes a gate portion of each pixel driving circuit, the gate portion extending from one side of the corresponding first scan line, and the area of ​​the gate portion being smaller than the area of ​​the corresponding electrode plate.

[0012] In some embodiments, the corresponding data line overlaps with the pixel electrode in a top-view perspective, forming a second capacitor.

[0013] Embodiments of the present invention also provide a display device, including the display panel described above.

[0014] In the display panel and display device provided in the embodiments of the present invention, by adding an electrode plate electrically connected to the adjacent data line in the original main opening area, the electrode plate can form a first capacitor with the pixel electrode, thereby balancing the parasitic capacitance between the data line and the pixel electrode while ensuring the aperture ratio. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the planar structure of the display panel according to an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the sub-pixel structure of the display panel according to an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the structure of two adjacent sub-pixels of the display panel according to an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the film layer structure of the display panel according to an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0021] like Figure 1 As shown, an embodiment of the present invention provides a display panel 100, which may be an LCD (liquid crystal display) panel.

[0022] The display panel 100 includes a display area DA and a non-display area NDA.

[0023] The display area DA can be an area used to set the sub-pixel SPX of the displayed image.

[0024] The non-display area NDA may be a driving unit, such as a gate driving circuit, that provides driving signals to the pixel driving circuit for setting up a sub-pixel SPX, and an area containing lines, such as power lines, connecting the driving unit. No sub-pixel SPX may be set within the non-display area NDA. The non-display area NDA may be located on at least one side of the display area DA. The non-display area NDA may at least partially surround the display area DA.

[0025] Please see Figure 2The display area DA includes multiple sub-pixel areas SPA. Each sub-pixel area SPA includes an aperture area OA and a non-aperture area NOA, wherein the non-aperture area NOA includes a main non-aperture area MNA located on one side of the aperture area OA.

[0026] Please refer to the following: Figure 2 and Figure 3 The display panel 100 includes multiple data lines 11, multiple first scan lines 21, multiple second scan lines 22, multiple sub-pixels SPX, and multiple electrode plates 13.

[0027] The plurality of data lines 11 are arranged substantially parallel to each other and extend along a first direction Y. Each data line 11 passes through the corresponding opening region OA and is used to transmit the source driver data voltage to the corresponding sub-pixel SPX. The data lines 11 overlap with the corresponding pixel electrodes 31 in a top-view perspective to form parasitic capacitance (i.e., a second capacitance). It can be understood that when the data lines 11 are offset from the pixel electrodes 31, lateral parasitic capacitance (i.e., a second capacitance) is also formed.

[0028] A plurality of first scan lines 21 are arranged substantially parallel to each other and extend along a second direction X intersecting the first direction Y. Each first scan line 21 is located within the main non-aperture region (MNA) of the corresponding row's sub-pixel region SPX, and is used to transmit a scan signal to the corresponding sub-pixel SPX. Exemplarily, the first direction Y is perpendicular to the second direction X.

[0029] Multiple second scan lines 22 are arranged substantially parallel to each other and extend along the first direction Y. Each second scan line 22 is located between two adjacent sub-pixel regions SPA and is electrically connected between the corresponding first scan line 21 and the gate driver to transmit a scan signal from the gate driver to the first scan line 21. Each second scan line 22 and the corresponding first scan line 21 are located on different layers. In this way, the gate driver and the source driver can be located on the same side of the display panel 100, for example, the lower bezel of the display panel 100. As a result, the width of the side bezel of the display panel 100 can be reduced.

[0030] Each of the sub-pixels SPX is located within the corresponding sub-pixel region SPA and includes a pixel driving circuit 30 and a pixel electrode 31 electrically connected to the pixel driving circuit 30.

[0031] The pixel driving circuit 30 is located within the main non-aperture region (MNA) and electrically connected to the corresponding data line 11 and the corresponding first scan line 21. Each pixel driving circuit 30 includes a plurality of thin-film transistors for driving the corresponding pixel electrode 31. The gate portion 33 of each pixel driving circuit 30 extends from one side of the corresponding first scan line 21 and is generally rectangular. Exemplarily, the gate portion 33 is used to form the gates of at least two thin-film transistors.

[0032] The pixel electrode 31 is at least partially located within the opening region OA. Specifically, at least one pixel electrode 31 includes a main electrode and a plurality of branch electrodes connected to the main electrode. The main electrode is generally cross-shaped. At least one branch electrode forms an angle with the main electrode, and the at least one branch electrode also includes a main body portion and an extension portion 36 connected to the main body portion and located within the corresponding main non-opening region MNA, wherein the area of ​​the extension portion 36 is smaller than the area of ​​the main body portion. In this way, the design of the parasitic capacitance between the electrode plate 13 and the pixel electrode 31 can be controlled.

[0033] At least one of the electrode plates 13 is located within the main non-aperture region (MNA) of the corresponding sub-pixel region SPA, between the corresponding data line 11 and the adjacent data line 11 (i.e., two adjacent data lines 11) which are electrically connected to the pixel driving circuit 30 within the main non-aperture region (MNA), and is electrically connected to the adjacent data line 11.

[0034] The electrode plate 13 overlaps with the extension 36 of the pixel electrode 31 within the opening region OA of the corresponding sub-pixel region SPA to form a first capacitor. It can be understood that the electrode plate 13 can also be offset from the pixel electrode 31 to form a lateral first capacitor. Thus, by adding an electrode plate 13 electrically connected to the adjacent data line 11 within the existing main opening region OA, the electrode plate 13 can form a first capacitor with the pixel electrode 31, thereby balancing the parasitic capacitance (i.e., the second capacitance) between the data line 11 and the pixel electrode 31 while maintaining the aperture ratio.

[0035] Since the length of the electrode plate 13 is less than the length of the corresponding data line 11, in order to ensure the matching degree between the first capacitor and the second capacitor, the electrode plate 13 can be designed to be approximately rectangular, and the width of the electrode plate 13 can be designed to be greater than the width of the corresponding data line 11. In actual design, in order to ensure the capacitance value of the first capacitor, the area of ​​the electrode plate 13 can be designed to be greater than the area of ​​the corresponding gate portion 33.

[0036] Please see Figure 4The display panel 100 includes a substrate SUB, a first conductive layer M1 on the substrate SUB, a gate insulating layer GI on the first conductive layer M1, an active layer ACT on the gate insulating layer GI, a first insulating layer ILD on the active layer, and a second conductive layer M2 on the first insulating layer ILD.

[0037] The substrate SUB may comprise a single-layer insulating material such as glass, quartz, and polymer resin, or a multi-layer insulating material such as a double-layer polymer resin. The substrate SUB may be a rigid substrate SUB or a flexible substrate SUB. The substrate SUB supports a film layer disposed thereon.

[0038] The first conductive layer M1 includes a plurality of first scan lines 21 ( Figure 4 (Not shown), multiple bridging portions BG, and a gate portion 33 of each of the pixel driving circuits 30. The first conductive layer M1 may be constructed using a low-resistance material. The first conductive layer M1 may include, but is not limited to, one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0039] The gate insulating layer GI serves as a gate insulating film that insulates the active layer ACT from the gate portion 33. The gate insulating layer GI may include silicon compounds, metal oxides, etc. For example, the gate insulating layer GI may include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These substances may be used individually or in combination.

[0040] The active layer ACT may include silicon-containing semiconductor materials such as amorphous silicon, polycrystalline silicon, or oxide semiconductor materials. In this case, the oxide semiconductor material may include any one of oxides or composite oxides of titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In).

[0041] The first insulating layer ILD is disposed on the active layer ACT. The first insulating layer ILD may include silicon compounds, metal oxides, etc. For example, the second insulating layer may include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials may be used alone or in combination with each other.

[0042] The second conductive layer M2 includes a plurality of second scan lines 22, a plurality of data lines 11, and a plurality of electrode plates 13. The second conductive layer M2 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer M2 may be a single-layer film or a multilayer film. For example, the second conductive layer M2 may be formed as a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0043] Each bridging portion BG is electrically connected between the corresponding electrode plate 13 and the adjacent data line 11 through a via of the first insulating layer ILD and the gate insulating layer GI, thereby enabling the electrode plate 13 to be electrically connected to the adjacent data line 11 through the bridging portion BG that crosses the corresponding second scan line 22.

[0044] The table below compares the characteristics of display panels in related technologies and embodiments of the present invention. It can be seen that the pixel design of the present invention can achieve a rough balance of parasitic capacitances on the left and right sides of the sub-pixel SPX, with little difference in capacitance values ​​in other parts. However, the aperture ratio of the display panel of the present invention increases by 6%.

[0045] Item Pixel A Pixel B Cpd_Left / fF 44.72 44.59 Cpd_Right / fF 44.66 44.53 Ctotal / fF 1486.86 1550.70 Cpd / Ctotal 0.03 0.029 Cv-gate / fF 296152 288023 Cdata / fF 549296 5133814 AR 68.42％ 72.45％

[0046] Embodiments of the present invention also provide a display device, including the display panel described above. The display device can be a fixed terminal, such as a television or desktop computer; a mobile terminal, such as a laptop or smartphone; or a wearable device, such as VR, AR, or a smartwatch.

[0047] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area, which includes multiple sub-pixel areas. Each sub-pixel area includes an opening area and a non-opening area. The non-opening area includes a main non-opening area located on one side of the opening area. Multiple data lines extend along the first direction; Multiple first scan lines extend along a second direction intersecting the first direction; and Multiple sub-pixels, each sub-pixel being located within a corresponding sub-pixel region, and including a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit, the pixel driving circuit being located within the main non-aperture region and electrically connected to the corresponding data line and the corresponding first scan line, the pixel electrode being at least partially located within the aperture region; The display panel further includes multiple electrode plates, at least one of which is located within the main non-aperture area of ​​the corresponding sub-pixel region, between the corresponding data line and the adjacent data line electrically connected to the pixel driving circuit within the main non-aperture area, and electrically connected to the adjacent data line; the electrode plate and the pixel electrode within the opening area of ​​the corresponding sub-pixel region form a first capacitor; at least one pixel electrode includes an extension located within the corresponding main non-aperture area, and at least one electrode plate and the corresponding extension overlap in a top-view perspective.

2. The display panel as described in claim 1, characterized in that, At least one of the pixel electrodes includes a main electrode and a plurality of branch electrodes connected to the main electrode, and at least one of the branch electrodes includes the extension portion.

3. The display panel as described in claim 1, characterized in that, At least one of the electrode plates has a width greater than the width of the corresponding data line.

4. The display panel as described in claim 1, characterized in that, It also includes a plurality of second scan lines extending along the first direction, each of the second scan lines being electrically connected to a corresponding first scan line and located in a different layer from the corresponding first scan line.

5. The display panel as described in claim 4, characterized in that, Each of the electrodes is electrically connected to the adjacent data line via a bridging portion that crosses the corresponding second scan line.

6. The display panel as described in claim 5, characterized in that, The display panel includes a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer. The first conductive layer includes a plurality of first scan lines and a plurality of bridging portions. The second conductive layer includes a plurality of second scan lines, a plurality of data lines, and a plurality of electrode plates. Each bridging portion is electrically connected to the corresponding electrode plate and the adjacent data line through a via in the first insulating layer.

7. The display panel as described in claim 6, characterized in that, The first conductive layer further includes a gate portion of each pixel driving circuit, the gate portion extending from one side of the corresponding first scan line, and the area of ​​the gate portion being smaller than the area of ​​the corresponding electrode plate.

8. The display panel as described in claim 1, characterized in that, The corresponding data line overlaps with the pixel electrode from a top-down view, forming a second capacitor.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8.

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