Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving units. The Nth gate driving unit comprises a pull-up transistor, a touch transistor and a potential holding unit. In a touch stage, the potential holding unit is turned on, and a high potential signal transmitted in a high potential line is output to a pull-up node. The high potential signal can be continuously injected into the pull-up node, and the pull-up node can maintain a high potential in the touch stage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and display panel. BACKGROUND

[0002] The gate driving circuit is used for providing corresponding scanning signals to each scanning line, and includes a plurality of gate driving units. The pull-up node of each gate driving unit needs a corresponding potential in different stages to achieve the required function. SUMMARY

[0003] The present application provides a gate driving circuit and display panel to alleviate the technical problem of unstable potential of the pull-up node in the touch stage.

[0004] In a first aspect, the present application provides a gate driving circuit, which includes a plurality of cascaded gate driving units. The Nth gate driving unit includes a pull-up transistor, a touch transistor and a potential holding unit. The first electrode of the pull-up transistor is connected with a clock line, the second electrode of the pull-up transistor is connected with an Nth scanning line, and the gate of the pull-up transistor is connected with a pull-up node. The first electrode of the touch transistor is connected with the Nth scanning line, the second electrode of the touch transistor is connected with a first low potential line, and the gate of the touch transistor is connected with a touch line. The input end of the potential holding unit is connected with a high potential line, the first control end of the potential holding unit is connected with the touch line, the second control end of the potential holding unit is connected with the pull-up node, and the output end of the potential holding unit is connected with the pull-up node.

[0005] In some embodiments, the potential holding unit includes a first transistor and a second transistor. The first electrode of the first transistor is connected with the gate of the first transistor and the pull-up node. The first electrode of the second transistor is connected with the second electrode of the first transistor, the second electrode of the second transistor is connected with the high potential line, and the gate of the second transistor is connected with the touch line.

[0006] In some embodiments, the potential holding unit is used for maintaining the potential of the pull-up node in the touch stage.

[0007] In some embodiments, the channel type of the touch transistor is the same as the channel type of the second transistor, and the first transistor is an N-channel thin film transistor.

[0008] In some embodiments, the touch line is used for transmitting a touch signal. In the touch stage, the potential of the touch signal and the potential of the pull-up node are both high potentials.

[0009] In some embodiments, the Nth-stage gate driving unit further comprises a pull-up maintaining transistor, a first electrode of the pull-up maintaining transistor is connected with the high potential line, a second electrode of the pull-up maintaining transistor is connected with the pull-up node, and a gate electrode of the pull-up maintaining transistor is connected with the first control line.

[0010] In some embodiments, the Nth-stage gate driving unit further comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, a first electrode of the third transistor is connected with a gate electrode of the third transistor and the high potential line; a first electrode of the fourth transistor is connected with a second electrode of the third transistor, a second electrode of the fourth transistor is connected with the second low potential line, and a gate electrode of the fourth transistor is connected with the pull-up node; a first electrode of the fifth transistor is connected with the high potential line, and a second electrode of the fifth transistor is connected with the first electrode of the fourth transistor; a first electrode of the sixth transistor is connected with the second electrode of the fifth transistor, a second electrode of the sixth transistor is connected with the second low potential line, and a gate electrode of the sixth transistor is connected with the gate electrode of the fourth transistor; a gate electrode of the seventh transistor is connected with the first electrode of the sixth transistor, a first electrode of the seventh transistor is connected with the pull-up node, and a second electrode of the seventh transistor is connected with the first low potential line.

[0011] In some embodiments, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are N-channel thin film transistors; the first low potential line is used for transmitting a first low potential signal, and the second low potential line is used for transmitting a second low potential signal, and a potential of the second low potential signal is smaller than a potential of the first low potential signal.

[0012] In some embodiments, the Nth-stage gate driving unit further comprises an eighth transistor, a first electrode of the eighth transistor is connected with the Nth-stage scanning line, a second electrode of the eighth transistor is connected with the first low potential line, a gate electrode of the eighth transistor is connected with the gate electrode of the seventh transistor, and the eighth transistor is an N-channel thin film transistor.

[0013] In a second aspect, the present application provides a display panel, which comprises a common voltage line and the gate driving circuit in the at least one embodiment, the common voltage line is used for transmitting a common voltage signal, the clock line is used for transmitting a clock signal, a frequency of the clock signal in a touch stage is greater than a frequency of the clock signal in a display stage, and a waveform of the clock signal in the touch stage is the same as a waveform of the common voltage signal.

[0014] The gate driving circuit and the display panel provided by the present application can output the high potential signal transmitted in the high potential line to the pull-up node by turning on the potential maintaining unit in the touch stage, can continuously inject the high potential signal to the pull-up node, and can ensure that the pull-up node maintains the high potential in the touch stage.

[0015] Furthermore, the first control terminal of the potential holding unit and the gate of the touch transistor can share the same touch line, which can save the number of traces required for the gate drive circuit, thereby reducing the bezel space and making it easier to achieve a narrow bezel. Attached Figure Description

[0016] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of the gate drive circuit in related technologies.

[0018] Figure 2 for Figure 1 The timing diagram of key signals in the gate drive circuit shown is illustrated.

[0019] Figure 3 This is a schematic diagram of the gate drive circuit provided in an embodiment of this application.

[0020] Figure 4 This is a schematic diagram of the operating mode of the gate drive circuit in the related technology.

[0021] Figure 5 This is a timing comparison diagram of the display panel provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0024] Figure 1 This is a schematic diagram of the gate drive circuit in the related technology. Figure 2 for Figure 1 The timing diagram of key signals in the gate drive circuit shown is as follows. Figure 1 The gate drive circuit shown has the following problems:

[0025] 1. In Figure 2As shown in the touch phase P1, because there is a long time (for example, 300 microseconds) between the two adjacent display phases P2, at this time, the clock signal CK and the Nth stage scanning signal G(N) are all at low potential, and the potential of the pull-up node Q(N) continues to drop with the extension of the touch phase P1.

[0026] 2, one pole of the pull-up maintaining transistor T11 is connected with the N-1th stage scanning line for transmitting the N-1th stage scanning signal G(N-1), in the case that the potential of the pull-up node Q(N) is higher than the potential of the N-1th stage scanning signal G(N-1), the charge of the pull-up node Q(N) is easy to leak to the N-1th stage scanning line through the pull-up maintaining transistor T11, which also causes the potential of the pull-up node Q(N) difficult to stabilize.

[0027] 3, when the potential of the pull-up node Q(N) is high, the sixth transistor T54 is turned on, and the gate potential of the seventh transistor T42 and the source potential of the seventh transistor T42 are both at the potential of the first low potential signal VSS, which easily causes the seventh transistor T42 not to be completely closed, and the charge of the pull-up node Q(N) is easy to leak to the first low potential line through the seventh transistor T42, which also causes the potential of the pull-up node Q(N) difficult to stabilize.

[0028] In view of the above-mentioned technical problem of the unstable potential of the pull-up node Q(N) in the touch phase P1, the embodiment provides a gate driving circuit, please refer to Figures 3 to 5 , as shown in the figure, Figure 1 , Figure 3 The gate driving circuit includes a plurality of cascaded gate driving units, wherein the Nth gate driving unit includes a pull-up transistor T21, a touch transistor Ttp and a potential holding unit 10, the first pole of the pull-up transistor T21 is connected with the clock line, the second pole of the pull-up transistor T21 is connected with the Nth stage scanning line, and the gate of the pull-up transistor T21 is connected with the pull-up node Q(N); the first pole of the touch transistor Ttp is connected with the Nth stage scanning line, the second pole of the touch transistor Ttp is connected with the first low potential line, and the gate of the touch transistor Ttp is connected with the touch line; the input end of the potential holding unit 10 is connected with the high potential line, the first control end of the potential holding unit 10 is connected with the touch line, the second control end of the potential holding unit 10 is connected with the pull-up node Q(N), and the output end of the potential holding unit 10 is connected with the pull-up node Q(N).

[0029] It can be understood that the gate drive circuit provided by the embodiment can output the high potential signal VGH transmitted in the high potential line to the pull-up node Q(N) through the potential maintaining unit 10 in the touch stage P1, can continuously inject the high potential signal VGH to the pull-up node Q(N), and further can ensure that the pull-up node Q(N) maintains the high potential in the touch stage P1.

[0030] In addition, the first control end of the potential maintaining unit 10 and the gate of the touch transistor Ttp can share the same touch line, the number of lines required by the gate drive circuit can be saved, the frame space is reduced, and narrow frame is beneficial to be realized.

[0031] It should be noted that the potential maintaining unit 10 is used to maintain the potential of the pull-up node Q(N) in the touch stage P1. The touch line is used to transmit a touch signal TP, and the potential state of the touch signal TP is used to indicate the arrival of the touch stage P1. For example, when the touch signal TP is high potential, it means that the current is the touch stage P1. That is, in the touch stage P1, the potential of the touch signal TP and the potential of the pull-up node Q(N) are both high.

[0032] The first pole is one of the source or the drain, and the second pole is the other of the source or the drain. For example, when the first pole is the source, the second pole is the drain; or when the first pole is the drain, the second pole is the source.

[0033] In one of the embodiments, the potential maintaining unit 10 includes a first transistor T12 and a second transistor T13. The first pole of the first transistor T12 is connected with the gate of the first transistor T12 and the pull-up node Q(N). The first pole of the second transistor T13 is connected with the second pole of the first transistor T12. The second pole of the second transistor T13 is connected with the high potential line. The gate of the second transistor T13 is connected with the touch line.

[0034] It should be noted that since the channel type of the touch transistor Ttp is the same as the channel type of the second transistor T13, and the first transistor T12 is an N-channel thin film transistor, when the touch signal TP transmitted in the touch line is high potential, the touch transistor Ttp and the second transistor T13 are synchronously turned on. At this time, since the potential of the pull-up node Q(N) is also high potential, the first transistor T12 is also in the on state. In this case, the high potential signal VGH transmitted in the high potential line is written to the pull-up node Q(N), and the pull-up node Q(N) is continuously charged to maintain the high potential in the touch stage P1.

[0035] In one of the embodiments, the Nth gate driving unit further comprises a pull-up maintaining transistor T11, a first electrode of the pull-up maintaining transistor T11 is connected with the high potential line, a second electrode of the pull-up maintaining transistor T11 is connected with the pull-up node Q(N), and a gate of the pull-up maintaining transistor T11 is connected with the first control line.

[0036] It should be noted that, in the touch phase P1, the pull-up maintaining transistor T11 is in the off state, compared with Figure 1 the first electrode of the pull-up maintaining transistor T11 is connected with the N-1th scanning signal G(N-1), and the potential of the high potential signal VGH in the high potential line is greater than or equal to the potential of the pull-up node Q(N), which can prevent the charge of the pull-up node Q(N) from leaking through the pull-up maintaining transistor T11, thereby further stabilizing the potential of the pull-up node Q(N).

[0037] The first control line can be used to transmit Figure 1 the clock signal CK(N-1) shown in FIG. 4B, or Figure 2 the N-1th scanning signal G(N-1) shown in FIG. 4C.

[0038] In one of the embodiments, the Nth gate driving unit further comprises a third transistor T51, a fourth transistor T52, a fifth transistor T53, a sixth transistor T54, and a seventh transistor T42, a first electrode of the third transistor T51 is connected with a gate of the third transistor T51 and the high potential line; a first electrode of the fourth transistor T52 is connected with a second electrode of the third transistor T51, a second electrode of the fourth transistor T52 is connected with the second low potential line, and a gate of the fourth transistor T52 is connected with the pull-up node Q(N); a first electrode of the fifth transistor T53 is connected with the high potential line, and a second electrode of the fifth transistor T53 is connected with the first electrode of the fourth transistor T52; a first electrode of the sixth transistor T54 is connected with a second electrode of the fifth transistor T53, a second electrode of the sixth transistor T54 is connected with the second low potential line, and a gate of the sixth transistor T54 is connected with the gate of the fourth transistor T52; a gate of the seventh transistor T42 is connected with the first electrode of the sixth transistor T54, a first electrode of the seventh transistor T42 is connected with the pull-up node Q(N), and a second electrode of the seventh transistor T42 is connected with the first low potential line.

[0039] It should be noted that the third transistor T51, the fourth transistor T52, the fifth transistor T53, and the sixth transistor T54 can constitute an inverter, the node K is an output terminal of the inverter, when the pull-up node Q(N) is at a high potential, the node K is at a low potential; and when the pull-up node Q(N) is at a low potential, the node K is at a high potential.

[0040] Wherein, the high potential is a potential that can turn on the N-channel transistor or turn off the P-channel transistor, and the low potential is a potential that can turn off the N-channel transistor or turn on the P-channel transistor.

[0041] Since the third transistor T51, the fourth transistor T52, the fifth transistor T53, the sixth transistor T54 and the seventh transistor T42 are all N-channel thin film transistors, the first low potential line is used to transmit the first low potential signal VSS, the second low potential line is used to transmit the second low potential signal VSSK, the potential of the second low potential signal VSSK is less than the potential of the first low potential signal VSS, when the pull-up node Q(N) is at a high potential, the sixth transistor T54 is turned on, the gate potential of the seventh transistor T42 is the potential of the second low potential signal VSSK, the source potential of the seventh transistor T42 is the potential of the first low potential signal VSS, at this time, the gate-source potential difference (Vgs) of the seventh transistor T42 is less than 0, which can more thoroughly turn off the seventh transistor T42, prevent the pull-up node Q(N) from leaking through the seventh transistor T42, and further stabilize the potential of the pull-up node Q(N).

[0042] In one of the embodiments, the Nth-stage gate driving unit further comprises an eighth transistor T32, the first pole of the eighth transistor T32 is connected with the Nth-stage scan line, the second pole of the eighth transistor T32 is connected with the first low potential line, the gate of the eighth transistor T32 is connected with the gate of the seventh transistor T42, and the eighth transistor T32 is an N-channel thin film transistor.

[0043] It needs to be noted that when the pull-up node Q(N) is at a high potential, the sixth transistor T54 is turned on, the gate potential of the eighth transistor T32 is the potential of the second low potential signal VSSK, the source potential of the eighth transistor T32 is the potential of the first low potential signal VSS, at this time, the gate-source potential difference (Vgs) of the eighth transistor T32 is less than 0, which can more thoroughly turn off the eighth transistor T32, prevent the Nth-stage scan line from leaking through the seventh transistor T42, and further stabilize the potential of the Nth-stage scan signal G(N).

[0044] In one of the embodiments, the Nth-stage gate driving unit further comprises a bootstrap capacitor Cbt, one end of the bootstrap capacitor Cbt is connected with the pull-up node Q(N), and the other end of the bootstrap capacitor Cbt is connected with the Nth-stage scan line.

[0045] In one of the embodiments, the Nth-stage gate driving unit further comprises a transistor T41, the first pole of the transistor T41 is connected with the pull-up node Q(N), the second pole of the transistor T41 is connected with the first low potential line, and the gate of the transistor T41 is connected with the N+1th-stage scan line. In one of the embodiments, the Nth-stage gate driving unit further comprises a transistor T41, the first pole of the transistor T41 is connected with the pull-up node Q(N), the second pole of the transistor T41 is connected with the first low potential line, and the gate of the transistor T41 is connected with the N+1th-stage scan line.

[0046] The (N+1)th scan line is used to transmit the (N+1)th scan signal.

[0047] In one embodiment, the Nth-level gate drive unit further includes a transistor TrQ, the first terminal of which is connected to the pull-up node Q(N), the second terminal of which is connected to the first low-potential line, and the gate of which is connected to the reset line.

[0048] The reset line is used to transmit the reset signal Reset.

[0049] In one embodiment, the Nth-level gate driving unit further includes a transistor TrG, the first terminal of which is connected to the Nth-level scan line, the second terminal of which is connected to the first low-potential line, and the gate of which is connected to the reset line.

[0050] It should be noted that the gate of transistor TrQ and the gate of transistor TrG can share the same reset line, which can save the number of traces required for the gate drive circuit, thereby reducing the bezel space and making it easier to achieve a narrow bezel.

[0051] All of the transistors mentioned above can be N-channel thin-film transistors. Using thin-film transistors of the same channel type in the same gate drive circuit can simplify the manufacturing process and improve manufacturing efficiency.

[0052] Figure 4 This diagram illustrates the operating modes of the gate drive circuit in related technologies. The "Normal" row represents the normal operating mode, which includes only a display phase P2 and a blank phase in one frame. The "One Block" row represents the time-division simplex operating mode, which includes one display phase P2, one touch phase P1, and a blank phase in one frame. The "Multi Block" row represents the time-division multiplexing operating mode, which includes multiple sequentially alternating display phases P2, touch phases P1, and a final blank phase in one frame.

[0053] Preferably, the gate driving circuit provided in this application operates in a time-division multiplexing mode, which can respond to touch operations more promptly, thereby improving the touch response speed.

[0054] Figure 5 This is a timing comparison diagram of the display panel provided in the embodiments of this application. In this time-division multiplexing working mode, which includes multiple sequentially alternating display stages P2 and touch stages P1 in one frame,... Figure 5As shown in the middle right graph, the clock signal CK, the clock signal XCK, the N-1 level pull-up node Q(N-1), the pull-up node Q(N), the N+1 level pull-up node Q(N+1), the N+2 level pull-up node Q(N+2), the N-1 level scanning signal G(N-1), the N level scanning signal G(N), the N+1 level scanning signal G(N+1) and the N+2 level scanning signal G(N+2) maintain fixed potentials in the touch stage P1 and do not change with the potential change of the common voltage signal, which is easy to increase the coupling capacitance between the scanning line and the common voltage line, thereby affecting the touch effect.

[0055] Therefore, in the touch stage P1, the potential of the pull-up node Q(N) is maintained at a high potential, the pull-up transistor T21 is in an on state, and the clock signal CK or the clock signal XCK adopts the same waveform as the common voltage signal as shown in the middle right graph, thereby generating the scanning signals with the same waveform as the common voltage signal, which can reduce the capacitive coupling effect between the scanning line and the common voltage line. Figure 5

[0056] In one of the embodiments, the display panel comprises a common voltage line for transmitting a common voltage signal and the gate drive circuit in at least one of the above embodiments, a clock line for transmitting a clock signal CK, the frequency of the clock signal CK in the touch stage P1 is greater than that in the display stage P2, and the waveform of the clock signal CK in the touch stage P1 is the same as that of the common voltage signal.

[0057] It can be understood that the display panel provided by the embodiment can also output the high potential signal VGH transmitted in the high potential line to the pull-up node Q(N) by turning on the potential maintaining unit 10 in the touch stage P1, can continuously inject the high potential signal VGH to the pull-up node Q(N), and can ensure that the pull-up node Q(N) maintains a high potential in the touch stage P1 due to the gate drive circuit in at least one of the above embodiments.

[0058] In addition, the first control end of the potential maintaining unit 10 and the gate of the touch transistor Ttp can share the same touch line, which can save the number of lines required by the gate drive circuit, thereby reducing the frame space and being conducive to realizing narrow frame.

[0059] It should be noted that the display panel described above can be but is not limited to a liquid crystal display panel, and can also be other display panels, such as a self-luminous display panel.

[0060] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0061] ​The above describes the gate drive circuit and the display panel provided by the embodiments of the present application in detail. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. Those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and the modification or replacement does not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes multiple cascaded gate driving units, wherein the Nth gate driving unit includes: A pull-up transistor, wherein the first terminal of the pull-up transistor is connected to the clock line, the second terminal of the pull-up transistor is connected to the Nth scan line, and the gate of the pull-up transistor is connected to the pull-up node; A touch transistor, wherein the first terminal of the touch transistor is connected to the Nth scan line, the second terminal of the touch transistor is connected to the first low potential line, and the gate of the touch transistor is connected to the touch line; A potential holding unit, wherein the input terminal of the potential holding unit is connected to the high potential line, the first control terminal of the potential holding unit is connected to the touch line, the second control terminal of the potential holding unit is connected to the pull-up node, and the output terminal of the potential holding unit is connected to the pull-up node; The third transistor, wherein the first terminal of the third transistor is connected to the gate of the third transistor and the high potential line; The fourth transistor has its first terminal connected to the second terminal of the third transistor, its second terminal connected to the second low-potential line, and its gate connected to the pull-up node. The fifth transistor has its first terminal connected to the high-potential line and its gate connected to the first terminal of the fourth transistor. The sixth transistor has its first terminal connected to the second terminal of the fifth transistor, its second terminal connected to the second low-potential line, and its gate connected to the gate of the fourth transistor. The seventh transistor has its gate connected to the first terminal of the sixth transistor, the first terminal of the seventh transistor connected to the pull-up node, and the second terminal of the seventh transistor connected to the first low-potential line.

2. The gate driving circuit according to claim 1, characterized in that, The potential holding unit includes: The first transistor, wherein the first terminal of the first transistor is connected to the gate of the first transistor and the pull-up node; The second transistor has its first terminal connected to the second terminal of the first transistor, its second terminal connected to the high-potential line, and its gate connected to the touch line.

3. The gate driving circuit according to claim 2, characterized in that, The potential holding unit is used to maintain the potential of the pull-up node during the touch phase.

4. The gate driving circuit according to claim 3, characterized in that, The channel type of the touch transistor is the same as that of the second transistor, and the first transistor is an N-channel thin-film transistor.

5. The gate driving circuit according to claim 4, characterized in that, The touch line is used to transmit touch signals. During the touch phase, the potential of the touch signal and the potential of the pull-up node are both high potentials.

6. The gate driving circuit according to claim 1, characterized in that, The Nth-level gate drive unit further includes a pull-up sustaining transistor, the first terminal of which is connected to the high-potential line, the second terminal of which is connected to the pull-up node, and the gate of which is connected to the first control line.

7. The gate driving circuit according to claim 1, characterized in that, The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all N-channel thin-film transistors; The first low-potential line is used to transmit a first low-potential signal, and the second low-potential line is used to transmit a second low-potential signal, wherein the potential of the second low-potential signal is less than the potential of the first low-potential signal.

8. The gate driving circuit according to claim 7, characterized in that, The Nth-level gate driving unit further includes an eighth transistor, the first terminal of which is connected to the Nth-level scan line, the second terminal of which is connected to the first low-potential line, and the gate of which is connected to the gate of the seventh transistor. The eighth transistor is an N-channel thin-film transistor.

9. A display panel, characterized in that, The display panel includes a common voltage line and a gate driving circuit as described in any one of claims 1-8, wherein the common voltage line is used to transmit a common voltage signal, the clock line is used to transmit a clock signal, the frequency of the clock signal in the touch phase is greater than the frequency in the display phase, and the waveform of the clock signal in the touch phase is the same as the waveform of the common voltage signal.

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