A method for obtaining nanometer scale lines using a laser
By forming regular grain boundaries through laser crystallization and damascus processing, combined with chemical mechanical polishing and etching treatment, the problem of high cost and high complexity in the fabrication of nanoscale optical lines in existing technologies has been solved, enabling low-cost nanoscale line arrays to be used in integrated circuit fabrication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-11-09
- Publication Date
- 2026-05-22
AI Technical Summary
The existing industry processes for obtaining high-density nanoscale optical lines are cumbersome and extremely costly.
A partial crystallization of an amorphous silicon layer is achieved by irradiating a photomask with a laser, forming regular grain boundaries. The grain boundaries are then removed through planarization and etching to form trenches. These grain boundary trenches are used to obtain nanoscale lines on the substrate. The process combines damascus etching and chemical mechanical polishing, using silicon nitride and silicon dioxide as materials.
It enables the low-cost acquisition of nanoscale line arrays, suitable for integrated circuit fabrication processes below 5 nanometers, reducing dependence on photolithography machines, and the grain boundary trenches can be used as hard mask materials, with the thickness not decreasing as the linewidth decreases.
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Figure CN117457480B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for obtaining nanoscale lines using lasers. Background Technology
[0002] Integrated circuit linewidth refers to the minimum size that can be lithographically reproduced, determined by a specific process. It can generally be understood as the minimum line width in the fabricated circuit pattern. There is a corresponding relationship between integration density and linewidth; that is, the higher the integration density, the smaller the linewidth. Therefore, linewidth is often used to indicate the level of integrated circuit manufacturing technology.
[0003] As integrated circuit dimensions continue to shrink, advanced photolithography is needed to obtain fine lines. The industry uses multiple exposures or expensive extreme ultraviolet (EUV) lithography to obtain high-density nanoscale optical lines. This process is complicated and extremely costly. Summary of the Invention
[0004] Based on the above analysis, the present invention aims to provide a method for obtaining nanoscale lines using lasers, in order to solve the problem that the existing industry processes for obtaining high-density nanoscale optical lines are cumbersome and extremely costly.
[0005] This invention provides a method for obtaining nanoscale lines using lasers, comprising the following steps:
[0006] A dielectric layer and an amorphous silicon layer are sequentially formed on top of the substrate;
[0007] A laser is used to irradiate a mask to crystallize silicon in a portion of the amorphous silicon layer. The grain boundaries of the polycrystalline silicon formed after the crystallization of the portion of the amorphous silicon layer are determined by the spacing of the orifices with regular shapes on the mask.
[0008] The grain boundaries of the polycrystalline silicon in the amorphous silicon layer are planarized.
[0009] The grain boundaries are removed using an etchant to form grain boundary trenches; and
[0010] Nanoscale lines are obtained on the substrate using the grain boundary trenches.
[0011] Based on a further improvement of the above method, the material of the dielectric layer is silicon nitride.
[0012] The beneficial effects of the above-mentioned further improvement plan are:
[0013] Silicon nitride materials have good silicon wettability, which can reduce the nucleation rate during the crystallization process and promote lateral growth.
[0014] Based on a further improvement of the above method, the substrate material is silicon or silicon dioxide.
[0015] Based on a further improvement to the above method, the planarization treatment of the grain boundaries of the polycrystalline silicon in the amorphous silicon layer includes:
[0016] Silicon dioxide is deposited on the amorphous silicon layer;
[0017] The silicon dioxide on the polycrystalline silicon is removed using a chemical mechanical polishing process; and
[0018] The remaining surface silica on the amorphous silicon layer is removed using an acidic etching solution.
[0019] The beneficial effects of the above-mentioned further improvement plan are:
[0020] Remove grain boundary protrusions formed during laser crystallization to obtain smoother and more regular grain boundaries.
[0021] Based on a further improvement of the above method, obtaining nanoscale lines on the substrate using the grain boundary trenches includes:
[0022] A silicon dioxide film is filled over the polycrystalline silicon to cover the grain boundary trenches;
[0023] The surface silicon dioxide on the polycrystalline silicon is removed by chemical mechanical polishing or reverse etching.
[0024] The polycrystalline silicon is removed using an alkaline silicon etching solution, leaving the silicon dioxide filling the grain boundary trenches;
[0025] Using silicon dioxide within the grain boundary trenches as a hard mask, the dielectric layer is etched and the etching stops at the substrate surface; and
[0026] Using the silicon dioxide in the grain boundary trench and the etched dielectric layer as a hard mask, nanoscale lines are etched on the substrate.
[0027] Based on a further improvement of the above method, the step of filling the grain boundary trench with a silicon dioxide thin film over the polycrystalline silicon includes:
[0028] The grain boundary trenches are covered by a silicon dioxide film filled over the polycrystalline silicon using an atomic layer deposition (ALD) process.
[0029] Based on a further improvement of the above method, the alkaline silicon etching solution is a tetramethylammonium hydroxide solution or a potassium hydroxide solution.
[0030] Based on further improvements to the above method, the width of the nanoscale lines is less than 10 nanometers.
[0031] Based on a further improvement of the above method, the etchant is a Secco etchant.
[0032] Based on further improvements to the above method, the energy density of the laser is 100 millijoules per square centimeter to 2 joules per square centimeter.
[0033] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0034] 1. By utilizing laser crystallization to form regular grain boundaries and damascus processing, low-cost nanoscale line arrays can be obtained, which, after integration, can be used in integrated circuit fabrication processes below 5 nanometers.
[0035] 2. Damascus structures were previously mainly used in metal interconnect processes, resulting in relatively large dimensions and a high dependence on lithography machines. The above-mentioned technical solution utilizes damascus structures to obtain hard mask materials with fine lines. The trenches in the damascus structure are obtained by etching to remove grain boundaries, and their dimensions can be as small as 20 nanometers or less, comparable to extreme ultraviolet lithography machines.
[0036] 3. After filling the grain boundary trench, it can be used as a hard mask material for subsequent pattern transfer. Its thickness is mainly determined by the film thickness, unlike photolithography, where the photoresist thickness decreases as the linewidth decreases.
[0037] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0038] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0039] Figure 1 This is a schematic flowchart of a method for obtaining nanoscale lines using lasers according to an embodiment of the present invention.
[0040] Figure 2 This is a process flow for a method of obtaining nanoscale lines using lasers according to an embodiment of the present invention.
[0041] Figure 3-1 An example of a grain boundary of polycrystalline silicon formed according to an embodiment of the present invention is shown.
[0042] Figure 3-2Another example of a grain boundary of polycrystalline silicon formed according to an embodiment of the present invention is shown.
[0043] Figure 3-3 A conceptual structural diagram of silicon dioxide deposited on an amorphous silicon layer 30 according to an embodiment of the present invention is shown.
[0044] Figure 3-4 A conceptual structural schematic diagram of silicon dioxide removal on polycrystalline silicon 70 using a chemical mechanical polishing process according to an embodiment of the present invention is shown.
[0045] Figure 4 An example of a planarized polycrystalline silicon grain boundary is shown according to an embodiment of the present invention.
[0046] Figure 5 An example of nanoscale lines obtained on a substrate according to this embodiment is shown.
[0047] Figure 6 A conceptual structural diagram is shown after filling a silicon dioxide thin film over polycrystalline silicon 70 to cover grain boundary trenches according to this embodiment.
[0048] Figure 7 A conceptual structural diagram is shown after removing the surface silicon dioxide on the polycrystalline silicon 70 using a chemical mechanical polishing process or reverse etching according to this embodiment.
[0049] Figure 8 A conceptual structural diagram of polycrystalline silicon 70 after removal using an alkaline silicon etching solution according to this embodiment is shown.
[0050] Figure 9 A conceptual structural diagram of the dielectric layer 20 after etching with silicon dioxide in the grain boundary trench as a hard mask according to this embodiment is shown.
[0051] Figure 10 This diagram illustrates a conceptual structure after nanoscale lines are etched onto a substrate 10 using silicon dioxide in grain boundary trenches and the etched dielectric layer 20 as hard masks, according to this embodiment.
[0052] Figure 11 A process flow for obtaining nanoscale lines using lasers according to an embodiment of the present invention is shown.
[0053] Figure label:
[0054] 10 - Substrate; 20 - Dielectric layer; 30 - Amorphous silicon layer; 40 - Mask; 50 - Circular hole; 60 - Crystalline silicon; 70 - Polycrystalline silicon; 80 - Fine line. Detailed Implementation
[0055] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0056] Figure 1 This is a schematic flowchart of a method for obtaining nanoscale lines using lasers according to an embodiment of the present invention.
[0057] The following is combined Figure 1 An embodiment of the present invention will be described.
[0058] like Figure 1 As shown, the method for obtaining nanoscale lines using lasers includes:
[0059] Step 101: A dielectric layer and an amorphous silicon layer are sequentially formed on top of the substrate.
[0060] In this embodiment, the substrate material can be silicon or silicon dioxide; a dielectric layer can be grown on the substrate using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The dielectric layer material can be silicon nitride, which has good silicon wettability, can reduce the nucleation rate during crystallization, and promote lateral growth.
[0061] In this embodiment, an amorphous silicon layer can be grown over the dielectric layer using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or reduced-pressure chemical vapor deposition (RPCVD).
[0062] In some embodiments, a thickness of 10 to 1000 Å (angstroms) for the dielectric layer and the amorphous silicon layer is advantageous.
[0063] Step 102: Use a laser to irradiate the mask to crystallize silicon in a portion of the amorphous silicon layer, wherein the grain boundaries of the polycrystalline silicon formed after the partial crystallization of the amorphous silicon layer are determined by the spacing of the orifices with regular shapes on the mask. Figure 2 A schematic diagram of a laser-irradiated mask according to this embodiment is shown. Figure 2As shown, the photomask 40 may have multiple circular holes 50. When the photomask 40 is irradiated with a laser, a portion of the amorphous silicon 60 on the amorphous silicon layer 30 is in a near-molten state. When the amorphous silicon 60 solidifies in the near-molten state, it undergoes lateral growth to form grain boundaries of polycrystalline silicon. The width of the grain boundaries is determined by the spacing of the circular holes 50 on the photomask 40.
[0064] It should be noted that since the apertures on the photomask 40 are circular, the near-molten amorphous silicon 60 under laser irradiation is also circular. Therefore, the amorphous silicon 60 can grow uniformly in all directions. When these growing amorphous silicon particles touch, they stop growing and form grain boundaries between polycrystalline silicon particles. Because the amorphous silicon 60 grows uniformly in all directions, when the circular apertures on the photomask are regularly distributed, the resulting polycrystalline silicon grain boundaries will be regular rectangles. Therefore, both a regular shape of the apertures on the photomask and a regular distribution between the apertures are advantageous.
[0065] In some embodiments, it is advantageous that the energy density of laser melting crystallization is between 100 millijoules per square centimeter and 2 joules per square centimeter, which can be achieved by adjusting the laser power.
[0066] Step 103: Planarize the grain boundaries of the polycrystalline silicon in the amorphous silicon layer.
[0067] Figure 3-1 An example of a grain boundary of polycrystalline silicon formed in step 102 according to this embodiment is shown, by Figure 3-1 As can be seen, protrusions may appear at the grain boundaries of polycrystalline silicon. In order to make the surface of the crystallized film smoother, the grain boundaries of polycrystalline silicon need to be planarized in step 103.
[0068] In some preferred embodiments, the planarization of the grain boundaries of polycrystalline silicon can be performed using the following process:
[0069] Silicon dioxide is deposited on the amorphous silicon layer 30;
[0070] The silicon dioxide on the polycrystalline silicon is removed using a chemical mechanical polishing process; and
[0071] The remaining surface silica on the amorphous silicon layer 30 is removed using an acidic etching solution.
[0072] In the above embodiments, a silicon dioxide layer with a thickness of 10–100 nm can be deposited on the amorphous silicon layer 30. Subsequently, the surface of the crystalline film is planarized using a chemical mechanical polishing process. Finally, the surface silicon dioxide on the amorphous silicon layer 30 is etched using an acidic etchant such as hydrofluoric acid.
[0073] The following is combined with Figures 3-2 to 3-4 The preferred embodiments described above will be explained.
[0074] Figure 3-2 Another example of a grain boundary of polycrystalline silicon formed according to step 102 of this embodiment is shown. For example... Figure 3-2 As shown, during the lateral growth of molten silicon, collisions occur with silicon growing from adjacent directions, causing the lateral growth to terminate and forming grain boundaries. The crystallized surface is not completely flat; at the grain boundaries, collisions from growth in opposite directions create a series of protrusions, thus requiring planarization treatment of the polycrystalline silicon grain boundaries. Figures 3-3 to 3-4 It shows the Figure 3-2 The process flow for planarizing the grain boundaries in the grain.
[0075] Figure 3-3 A conceptual structural diagram is shown after silicon dioxide is deposited on the amorphous silicon layer 30. Figure 3-3 The thickness of the deposited silica can be 10–100 nm.
[0076] Figure 3-4 A conceptual structural diagram is shown illustrating the removal of silicon dioxide from polycrystalline silicon 70 using a chemical mechanical polishing (CMP) process. CMP removes protrusions and smooths the surface.
[0077] Because in Figure 3-3 In the process shown, silicon dioxide will also be deposited on the remaining portion of the amorphous silicon layer 30 (i.e., the surface area outside the polycrystalline silicon 70), so the following process will be performed: using an acidic etching solution to remove the surface silicon dioxide on the remaining portion of the amorphous silicon layer 30.
[0078] Step 104: Use an etchant to remove the grain boundaries to form grain boundary trenches.
[0079] In this embodiment, Secco etching solution (a mixture of potassium dichromate, hydrofluoric acid and water) can be used for grain boundary etching.
[0080] It should be noted that Secco etching solution can etch amorphous silicon. Since the crystal orientation in the grain boundary is not uniform, the grain boundary is also a type of amorphous silicon. When Secco etching solution is used for grain boundary etching, the amorphous silicon layer 30 is also etched away, leaving polycrystalline silicon 70.
[0081] Figure 4 An example of a planarized polycrystalline silicon grain boundary is shown according to the preferred embodiment described above. By removing the grain boundary protrusions formed during laser crystallization, the resulting grain boundaries can be made smoother and more regular.
[0082] Step 105: Using the grain boundary trenches, obtain nanoscale lines on the substrate.
[0083] In this embodiment, the damascus-structured trenches are obtained by etching away grain boundaries, and their size can be as small as nanometers.
[0084] Figure 5 An example of nanoscale lines obtained on a substrate according to this embodiment is shown. Figure 5 As shown, the material of the fine lines 80 is the same as that of the substrate 10, and the width of the fine lines 80 is determined by the width of the grain boundary trenches of the polysilicon.
[0085] Compared with existing technologies, the method for obtaining nanoscale lines using lasers provided in this embodiment can obtain low-cost nanoscale line arrays by using laser crystallization to form regular grain boundaries and damascus processes. After integration, it can be used in integrated circuit fabrication processes below 5 nanometers.
[0086] In some embodiments, the dielectric layer in step 101 may be made of silicon nitride. Silicon nitride has good silicon wettability, which can reduce the nucleation rate during crystallization and promote lateral growth.
[0087] In some embodiments, the substrate material in step 101 can be silicon or silicon dioxide. Damascus structures were previously mainly used in metal interconnect processes, resulting in relatively large dimensions and heavy reliance on photolithography machines. The above technical solution utilizes damascus structures to obtain hard mask materials with fine lines. The trenches in the damascus structure are obtained by etching to remove grain boundaries, and their dimensions can be as small as less than 20 nanometers, comparable to extreme ultraviolet lithography machines.
[0088] In some embodiments, step 105 may include the following steps:
[0089] S10: Fill the grain boundary trench with a silicon dioxide film above the polysilicon 70. Deposit silicon dioxide above the polysilicon 70 to fill the entire grain boundary trench.
[0090] In this embodiment, silicon dioxide can be deposited over the polysilicon 70 to fill the entire grain boundary trench. Figure 6 A conceptual structural diagram is shown after filling a grain boundary trench with a silicon dioxide film over polycrystalline silicon 70. In some embodiments, an atomic layer deposition (ALD) process can be used to fill the grain boundary trench with silicon dioxide, the silicon dioxide extending above the trench and forming a silicon dioxide film on the polycrystalline silicon. It should be noted that since the grain boundary trenches of the polycrystalline silicon 70 can reach the nanometer scale, using an ALD process to fill the silicon dioxide is advantageous.
[0091] S20: Remove surface silicon dioxide from polysilicon 70 using chemical mechanical polishing or reverse etching.
[0092] In this embodiment, chemical mechanical polishing or reverse etching can be used to remove the silicon dioxide film on the top layer of polysilicon 70, exposing the top of the polysilicon.
[0093] Figure 7 A conceptual structural diagram is shown after removing the surface silicon dioxide on polycrystalline silicon 70 using a chemical mechanical polishing process or reverse etching.
[0094] S30: Use an alkaline silicon etching solution to remove polysilicon 70, leaving silicon dioxide filling the grain boundary trenches.
[0095] Figure 8 A conceptual structural diagram of polycrystalline silicon 70 after removal using an alkaline silicon etchant is shown. In some embodiments, the alkaline silicon etchant may be a tetramethylammonium hydroxide solution or a potassium hydroxide solution.
[0096] S40: Using silicon dioxide in the grain boundary trench as a hard mask, etch the dielectric layer 20 and stop at the surface of the substrate 10.
[0097] In this embodiment, silicon dioxide within the grain boundary trench can be used as a hard mask to etch the dielectric layer 20, exposing the substrate 10.
[0098] Figure 9 A conceptual structural diagram is shown after etching the dielectric layer 20 using silicon dioxide within the grain boundary trench as a hard mask.
[0099] S50: Using silicon dioxide in the grain boundary trench and the etched dielectric layer 20 as hard masks, nanoscale lines are etched on the substrate 10.
[0100] In this embodiment, silicon dioxide in the grain boundary trench and the dielectric material located below the silicon dioxide can be used as hard masks to etch nanoscale lines on the substrate 10, while retaining a portion of the substrate height.
[0101] Figure 10 A conceptual structural diagram is shown after nanoscale lines are etched on the substrate 10 using silicon dioxide in the grain boundary trenches and the etched dielectric layer 20 as hard masks.
[0102] In the embodiments described above in conjunction with steps S10-S50, the grain boundary trenches, after being filled, can be used as hard mask materials for subsequent pattern transfer. Their thickness is mainly determined by the thickness of the polycrystalline silicon thin film, unlike the photolithography process, where the photoresist thickness decreases as the linewidth decreases.
[0103] Figure 11 A process flow for obtaining nanoscale lines using lasers according to an embodiment of the present invention is shown below. Figure 11 Please provide an explanation.
[0104] like Figure 11 As shown, in step 1101, silicon nitride is grown to a thickness between 10 and 1000 Å. In step 1102, amorphous silicon is grown to a thickness between 10 and 1000 Å, using methods such as PECVD, LPCVD, and RPCVD. In step 1103, laser melting crystallization is performed using a laser irradiation mask, with the laser energy density ranging from 100 millijoules per square centimeter to 2 joules per square centimeter. In step 1104, silicon dioxide is deposited and removed using a chemical mechanical polishing (CMP) process. In step 1105, the surface silicon dioxide is etched using an acidic etchant. In step 1106, grain boundary etching is performed using a Secco etchant. In step 1107, silicon dioxide is filled into the grain boundaries and the surface silicon dioxide is removed using a CMP process or reverse etching. In step 1108, polycrystalline silicon is removed using an alkaline silicon etchant. In step 1109, a silicon nitride thin film is etched using silicon dioxide as a hard mask material. In step 1110, silicon lines are etched using silicon dioxide and silicon nitride as mask materials.
[0105] The above text combined Figure 11 The described embodiments have at least the following beneficial technical effects:
[0106] 1. By utilizing laser crystallization to form regular grain boundaries and damascus processing, low-cost nanoscale line arrays can be obtained, which, after integration, can be used in integrated circuit fabrication processes below 5 nanometers.
[0107] 2. Damascus structures were previously mainly used in metal interconnect processes, resulting in relatively large dimensions and a high dependence on lithography machines. The above-mentioned technical solution utilizes damascus structures to obtain hard mask materials with fine lines. The trenches in the damascus structure are obtained by etching to remove grain boundaries, and their dimensions can be as small as 20 nanometers or less, comparable to extreme ultraviolet lithography machines.
[0108] 3. After filling the grain boundary trench, it can be used as a hard mask material for subsequent pattern transfer. Its thickness is mainly determined by the film thickness, unlike photolithography, where the photoresist thickness decreases as the linewidth decreases.
[0109] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for obtaining nanoscale lines using lasers, characterized in that, Includes the following steps: A dielectric layer and an amorphous silicon layer are sequentially formed on top of the substrate; A laser is used to irradiate a mask to crystallize silicon in a portion of the amorphous silicon layer. The grain boundaries of the polycrystalline silicon formed after the crystallization of the portion of the amorphous silicon layer are determined by the spacing of the orifices with regular shapes on the mask. The grain boundaries of the polycrystalline silicon in the amorphous silicon layer are planarized. The grain boundaries are removed using an etchant to form grain boundary trenches; and Nanoscale lines are obtained on the substrate using the grain boundary trenches.
2. The method for obtaining nanoscale lines using lasers according to claim 1, wherein the material of the dielectric layer is silicon nitride.
3. The method for obtaining nanoscale lines using lasers according to claim 1, wherein the substrate material is silicon or silicon dioxide.
4. The method for obtaining nanoscale lines using lasers according to claim 1, wherein the planarization treatment of the grain boundaries of the polycrystalline silicon in the amorphous silicon layer comprises: Silicon dioxide is deposited on the amorphous silicon layer; The silicon dioxide on the polycrystalline silicon is removed using a chemical mechanical polishing process; as well as The remaining surface silica on the amorphous silicon layer is removed using an acidic etching solution.
5. The method for obtaining nanoscale lines using lasers according to claim 1, wherein obtaining nanoscale lines on the substrate using the grain boundary trenches comprises: A silicon dioxide film is filled over the polycrystalline silicon to cover the grain boundary trenches; The surface silicon dioxide on the polycrystalline silicon is removed by chemical mechanical polishing or reverse etching. The polycrystalline silicon is removed using an alkaline silicon etching solution, leaving the silicon dioxide filling the grain boundary trenches; Using silicon dioxide within the grain boundary trench as a hard mask, the dielectric layer is etched and the etching stops on the substrate surface; as well as Using the silicon dioxide in the grain boundary trench and the etched dielectric layer as a hard mask, nanoscale lines are etched on the substrate.
6. The method for obtaining nanoscale lines using lasers according to claim 5, wherein filling the grain boundary trenches with a silicon dioxide thin film over the polycrystalline silicon comprises: The grain boundary trenches are covered by a silicon dioxide film filled over the polycrystalline silicon using an atomic layer deposition (ALD) process.
7. The method for obtaining nanoscale lines using laser according to claim 5, wherein the alkaline silicon etching solution is a tetramethylammonium hydroxide solution or a potassium hydroxide solution.
8. The method for obtaining nanoscale lines using laser according to claim 1 or 5, wherein the width of the nanoscale lines is less than 10 nanometers.
9. The method for obtaining nanoscale lines using laser according to claim 1 or 5, wherein the etching solution is Secco etching solution.
10. The method for obtaining nanoscale lines using a laser according to claim 1 or 5, wherein the energy density of the laser is from 100 millijoules per square centimeter to 2 joules per square centimeter.