Time conversion circuit and chip based on differential delay chain

Abstract

This invention provides a time conversion circuit and chip based on a differential delay chain. The differential delay chain-based time conversion circuit includes: a coarse delay chain, a first delay chain, a first trigger chain, a high-order encoder counter, a first low-order encoder, and a decoder. The differential delay chain-based time conversion circuit and time measurement method of this invention, employing a differential delay chain system architecture and corresponding internal testing and calibration methods, significantly improves time measurement accuracy.

Description

Technical Field

[0001] This invention relates to the field of time-to-digital converter circuit technology, and more specifically to a time conversion circuit and chip based on a differential delay chain. Background Technology

[0002] A time-to-digital converter (TDC) is a device that measures time intervals and converts them into digital signals. It is widely used in high-energy physics, particle physics, positron emission tomography (PET), automated testing equipment, laser and ultrasonic measurements, and many other fields. There are two main technological approaches to achieving high-precision time-of-flight measurement:

[0003] (1) High-speed, high-precision ADC (analog-to-digital converter) oversampling, and peak finding through relevant algorithms;

[0004] (2) Delay chain technology, including single-ended, cursor, ring, pipeline, Flash and other architectures, latches and accumulates the number of logic units through which the signal passes.

[0005] The first method requires the ADC's sampling throughput to be 1-2 orders of magnitude higher than the signal frequency, likely at the GHz level or higher. This method presents two problems: extremely high power consumption (tens to hundreds of times) and extremely high cost (hundreds to thousands of RMB), making it impractical for most applications.

[0006] The second method, regardless of whether it's a vernier, ring, pipeline, or Flash architecture, is based on a single-ended delay chain at its core. Influenced by local process variations (differences in time propagation characteristics between delay cells at different locations on the same die) and global process variations (differences in time propagation characteristics between delay cells at different locations on the same wafer), its time resolution and accuracy are largely determined by the consistency of the delay cells, conforming to a normal distribution. Taking the currently very mature 180-110nm process node as an example, the time propagation characteristic (delay resolution) of each delay cell is approximately 100ps, simplified here to an accuracy of ±100ps. Assuming the delay chain contains n delay cells, and each measurement requires traversing all cells, the overall cumulative accuracy of the system (according to the extreme value method) is approximately ±100ps*n, a level of several hundred to several thousand picoseconds, which is clearly far from sufficient in practical applications.

[0007] To address the aforementioned issues and improve delay chain accuracy, a screening method is currently employed. The positive and negative deviations of delay units have a certain probability of canceling each other out. Through screening, the chip's timing accuracy can be categorized (following a normal distribution). Clearly, the probability of achieving tens of picoseconds of accuracy is quite low, possibly even less than 5%, thus high-precision chips are expensive and difficult to apply in practice. Summary of the Invention

[0008] The purpose of this invention is to provide a time conversion circuit and chip based on differential delay chain. By adopting a differential delay chain system architecture and with corresponding internal testing and calibration methods, the accuracy of time measurement can be greatly improved without significantly increasing the system power consumption and cost.

[0009] To achieve the above objectives, this invention proposes a time conversion circuit based on a differential delay chain, comprising: a coarse delay chain, a first delay chain, a first flip-flop chain, a data selector, a high-order bit encoding counter, a first low-order bit encoder, and a decoder.

[0010] The coarse delay chain includes N coarse delay units connected in series. The starting end of the coarse delay chain receives a start signal START. The N coarse delay units are used to process the received START signal with N levels of first delay τ1, where N is an integer not less than 2.

[0011] The first delay chain includes N first delay units connected in series. The starting end of the first delay chain receives a first end signal STOP1. The N first delay units are used to process the received STOP1 with N levels of second delay τ2.

[0012] The first trigger chain includes N first triggers, the first input terminals of the N first triggers are respectively connected to the output terminals of the N coarse delay units, and the second input terminals of the N first triggers are respectively connected to the output terminals of the N first delay units.

[0013] The input of the data selector is connected to the output of the p-th and q-th coarse delay units of the coarse delay chain, respectively. The output of the data selector is fed back to the starting end of the coarse delay chain, Ring_In, to form a ring oscillator, where q≠p.

[0014] The input of the high-order bit code counter is connected to the output of the data selector and is used to record the number of cycles of the START signal in the ring oscillator;

[0015] The first low-order encoder, each input terminal of the first low-order encoder is connected to the output terminals of the N first flip-flops of the first flip-flop chain;

[0016] The decoder's input is connected to the output of the high-bit encoder counter and the first low-bit encoder, and decodes the data input from the high-bit encoder counter and the first low-bit encoder into a time count.

[0017] Furthermore, where τ2 < τ1, and the data input terminals of the N first flip-flops are respectively connected to the output terminals of the N coarse delay units, and the clock terminals of the N first flip-flops are respectively connected to the output terminals of the aforementioned N first delay units.

[0018] Furthermore, in the coarse delay chain, the first-level coarse delay unit is a NAND gate, the remaining coarse delay units are NOT gates, and the outputs of the odd-numbered coarse delay units are connected to the data input terminals of the first flip-flops through a NOT gate, while the outputs of the even-numbered coarse delay units are directly connected to the data input terminals of the first flip-flops.

[0019] Furthermore, in the first delay chain, the N-stage first delay unit is an NOT gate, and the odd-numbered stage first delay units are connected to the clock terminal of the corresponding first flip-flop through an additional NOT gate, while the output of the even-numbered stage first delay units is directly connected to the clock terminal of the corresponding first flip-flop.

[0020] Furthermore, it also includes a second delay chain, a second trigger chain, and a second low-order encoder. The second delay chain includes N stages of second delay units connected in series. The N stages of second delay units are the same as the first delay unit mentioned above, with a delay time of τ2. The output of the data selector is connected to the start end of the second delay chain. The data input terminals of the N second triggers of the second trigger chain are respectively connected to the outputs of the N coarse delay units. The clock terminals of the second triggers are respectively connected to the outputs of the N second delay units. Each input terminal of the second low-order encoder is correspondingly connected to the output terminals of the N second triggers of the second trigger chain.

[0021] Furthermore, in the coarse delay chain, the first coarse delay unit is a NAND gate, the remaining coarse delay units are NOT gates, and the outputs of the odd-numbered coarse delay units are connected to the data input terminals of the N second flip-flops in the second flip-flop chain, while the outputs of the even-numbered coarse delay units are connected to the data input terminals of the N second flip-flops through a NOT gate.

[0022] Furthermore, the N-stage second delay unit of the second delay chain is a NOT gate, the output of the odd-numbered stage second delay unit is directly connected to the clock terminal of the corresponding second flip-flop, and the even-numbered stage second delay unit is connected to the clock terminal of the corresponding second flip-flop through an additional NOT gate.

[0023] Furthermore, it also includes a third delay chain, a third trigger chain, and a third low-order encoder. The third delay chain includes N-stage third delay units connected in series. The N-stage third delay units are exactly the same as the aforementioned second delay units, with a delay time of τ2. The starting end of the third delay chain receives the second end signal STOP2. The N third delay units are used to process the received second end signal STOP2 with N second delays τ2. The data input terminals of the N third triggers of the third trigger chain are respectively connected to the outputs of the N coarse delay units. The clock terminals of the N third triggers of the third trigger chain are respectively connected to the outputs of the aforementioned N third delay units. Each input terminal of the third low-order encoder is correspondingly connected to the output terminals of the N third triggers of the third trigger chain.

[0024] Furthermore, in the coarse delay chain, the first coarse delay unit is a NAND gate, the remaining coarse delay units are NOT gates, and the outputs of the odd-numbered coarse delay units are connected to the data input terminals of each third flip-flop through a NOT gate, while the outputs of the even-numbered coarse delay units are directly connected to the data input terminals of each third flip-flop.

[0025] Furthermore, the N-stage third delay unit of the third delay chain is an NOT gate. The odd-numbered third delay units are connected to the clock terminal of the corresponding third flip-flop through an additional NOT gate, and the output of the even-numbered third delay units is directly connected to the clock terminal of the corresponding third flip-flop.

[0026] Furthermore, the number of delay units in the coarse delay chain, the first delay chain, the second delay chain, and the third delay chain is 128, and p and q are odd numbers.

[0027] The present invention also proposes a time conversion chip based on a differential delay chain, including the aforementioned time conversion circuit based on a differential delay chain.

[0028] The time conversion circuit and chip of the present invention adopt a differential delay chain system architecture, and with the corresponding internal testing and calibration methods, the measurement accuracy can be greatly improved to the tens of picosecond level.

[0029] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below may be considered part of the inventive subject matter of this disclosure, provided that such concepts do not contradict each other. Furthermore, all combinations of the claimed subject matter are considered part of the inventive subject matter of this disclosure.

[0030] The foregoing and other aspects, embodiments, and features of the teachings of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description

[0031] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the invention will now be described by way of example and with reference to the accompanying drawings, wherein:

[0032] Figure 1 This is a general block diagram of the time conversion circuit based on the differential delay chain according to an embodiment of the present invention.

[0033] Figure 2 As shown Figure 1 The circuit diagram of the coarse-fine chain mutual calibration part of the time conversion circuit based on differential delay chain.

[0034] Figure 3 As shown Figure 1 The circuit diagram of the time measurement section of the time conversion circuit based on the differential delay chain. Detailed Implementation

[0035] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0036] Various aspects of the invention are described in this disclosure with reference to the accompanying drawings, which illustrate numerous illustrative embodiments. The embodiments of this disclosure are not necessarily intended to encompass all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0037] like Figure 1 As shown, the time conversion circuit based on differential delay chains includes: a coarse delay chain 110, a flip-flop chain module 120, a fine delay chain module 130, a data selector 140, a high-order encoder counter 150, a first low-order encoder 161, a second low-order encoder 162, a third low-order encoder 163, and a decoder 170. The three flip-flop chains in the flip-flop chain module 120 are identical, and all the flip-flops in it are D flip-flops. Similarly, the three delay chains in the fine delay chain module 130 are also identical.

[0038] In this embodiment, the time conversion circuit based on the differential delay chain also includes a coarse-fine chain cross-calibration process and a resolution calibration process before the measurement time. To more clearly illustrate the time conversion circuit based on the differential delay chain, the circuit during measurement and the circuit during coarse calibration are described separately.

[0039] Coarse-fine chain cross-calibration: Calculates the relationship between the high-order and low-order codes. The high-order code is based on the delay of the coarse delay chain (110), and the low-order code is based on the delay difference between the coarse and fine delay chains. Calibration is necessary to ensure that the low-order and high-order codes of the LSB are 2-1. n This calibration procedure also reduces the differential nonlinearity (DNL) of the TDC. Preferably, calibration is performed after each power-on reset and before measurement initiation.

[0040] Circuits such as Figure 2 As shown, the coarse delay chain 110 includes 128 coarse delay units connected in series. The start end of the coarse delay chain 110 receives a start signal START. The START signal is sequentially delayed in the 128 coarse delay units. The delay time of the coarse delay unit is τ1. In this embodiment, τ1 = 100 ps. The first coarse delay unit of the coarse delay chain 110 is a NAND gate, and the remaining coarse delay units are NOT gates.

[0041] The second delay chain 132 (fine delay chain) used for calibration includes 128 second delay units connected in series. The second delay chain 132 receives the end signal STOP0, and STOP0 is sequentially delayed within the 128 second delay units. The delay time of each second delay unit is τ2, which in this embodiment is 80 ps. In this embodiment, the 128 delay units of the second delay chain 132 are NOT gates.

[0042] The second flip-flop chain 122 includes 128 D flip-flops. The data input terminals D of the 128 D flip-flops are connected one-to-one to the output terminals of the 128 coarse delay units, and the clock terminal CLK is connected one-to-one to the output terminals of the 128 second delay units of the second delay chain 132.

[0043] In this embodiment, the first-stage coarse delay unit of the coarse delay chain 110 is a NAND gate, and the remaining coarse delay units are NOT gates. The outputs of the odd-numbered coarse delay units are connected to the data inputs of the 128 second flip-flops in the second flip-flop chain, and the outputs of the even-numbered coarse delay units are connected to the data inputs of the 128 second flip-flops through a NOT gate. The 128-stage second delay units of the second delay chain 132 are NOT gates. The outputs of the odd-numbered second delay units are directly connected to the clock inputs of the corresponding second flip-flops in the second flip-flop chain 122, and the even-numbered second delay units are connected to the clock inputs of the corresponding second flip-flops through an additional NOT gate.

[0044] The time conversion circuit based on the differential delay chain also includes a data selector 140. The input of the data selector 140 is connected to the output of the p-th coarse delay unit and the q-th coarse delay unit of the coarse delay chain, respectively. The data selector 140 is used to select whether the output of the p-th or q-th coarse delay unit is fed back to the high-order code counter 150 and the starting terminal Ring_In of the coarse delay chain, where q≠p. This forms a ring oscillator with an adjustable frequency. In this embodiment, p and q satisfy the following conditions: p and q are odd numbers, and p*100≤128*(100-80), that is, p and q are less than or equal to 128*(100-80). The odd number. In this example, the data selector 140 selects the output of the 7th coarse delay unit of the coarse delay chain 110 and feeds it back to the starting end Ring_In of the coarse delay chain 110. Together with START, it is used as the input of the NAND gate to form a ring oscillator with a period of 7*100*2ps.

[0045] The high-order encoder counter 150 is connected to the output of the 7th coarse delay unit and is used to record the number of cycles of the START signal in the first 7 coarse delay units of the coarse delay chain 110. The input of the second low-order encoder 162 is connected to the output of 128 D flip-flops. The input of the decoder 170 is connected to the output of the high-order encoder counter 150 and the second low-order encoder 162, decoding the data input from the high-order encoder counter 150 and the second low-order encoder 162 into a time count.

[0046] Each new rising edge of START resets TDC, including resetting the initial states of the high-order code counter 150, the second flip-flop chain 122, and the coarse delay chain 110.

[0047] During coarse-to-fine chain cross-calibration, the number of delay units in the ring oscillator needs to be calibrated. First, initialization is performed with the START input low. All high-order encoder counters 150, the second low-order encoder 162, and the decoder 170 are reset to zero. At this time, the coarse delay units of the coarse delay chain 110 sequentially output 101010…1010. Since the feedback from the ring oscillator is obtained from the outputs of an odd number of coarse delay units, the upper input of the NAND gate, Ring_In, is 1. Next, the rising edge of the START signal arrives, and the lower input of the NAND gate is 1. The D inputs of the 128 D flip-flops sequentially receive 1, with a time interval of 100ps between each D input receiving 1. The output of the 7th coarse delay unit is 0, and in this embodiment, the 0 output of the 7th coarse delay unit is also fed back to the second delay chain 132 as STOP0.

[0048] In this embodiment, the first-stage coarse delay unit in the coarse delay chain 110 is a NAND gate, and the remaining coarse delay units are NOT gates. The outputs of the odd-numbered coarse delay units are connected to the data inputs of the N second flip-flops in the second flip-flop chain 122, and the outputs of the even-numbered coarse delay units are connected to the data inputs of the N second flip-flops through a NOT gate. The N-stage second delay units in the second delay chain 132 are NOT gates. The outputs of the odd-numbered second delay units are directly connected to the clock inputs of the N second flip-flops in the corresponding second flip-flop chain 122, and the even-numbered second delay units are connected to the clock inputs of the corresponding second flip-flops through an additional NOT gate. When STOP0 receives a low-level signal, the clock inputs of all 128 D flip-flops receive a value of 1, and the high-level signal interval received by the clock input of each D flip-flop is 80 ps. In this embodiment, the 0 output of the 7th coarse delay unit is fed back to the second delay chain 132. At this time, the time interval between the STOP0 signal and the START signal is 700ps. Theoretically, the STOP0 signal catches up with the START signal at 3500ps. The STOP0 signal latches data through D flip-flops. The output of the first 34 D flip-flops is 0, and from the 35th D flip-flop onwards, the data latched by the D flip-flops is 1. Therefore, theoretically, the code received by the second low-order encoder 162 is 00000000 00000000 00000000000000000111111……. However, due to certain errors in the manufacturing process of the delay unit, the encoded value received by the second encoder may be: 00000000 00000000 00000000 0000000001111111……. Based on this encoded value, the time interval between the STOP0 signal and the SART signal is coded as 34. Therefore, the received time needs to be calibrated. The calibration coefficient is 34-35=-1, and the result of dividing by 8 is 0. Therefore, the number of delay units in the ring oscillator remains unchanged.

[0049] To perform resolution calibration, the quartz oscillator's signal output is sent to START, and simultaneously, this signal is inverted and output to STOP1. The time interval between the first and second rising edges is measured and written to a register. An external processor reads this data and performs a subtraction calculation of two 16-bit data points, dividing the actual period time by the measurement code. For example, a 12.5MHz quartz oscillator with a period of 80ns corresponds to the following theoretical count value:

[0050] 80ns / 20ps = 4000

[0051] In actual measurement, the count value obtained through decoding was 4096. This corresponds to the actual resolution (delay) of the time conversion circuit not being 20 ps, ​​but rather:

[0052] 80ns / 4096=19.5312ps

[0053] The external processor reads the corresponding count value and calculates the error coefficient by dividing the actual count value by the theoretical count value. In this embodiment, the error coefficient is 4096 / 4000 = 0.9765625. Next, the external processor multiplies the measured count value for each time interval by the error coefficient. For example, if a time count value of 8192 is measured, the calibration result after multiplying it by the error coefficient 0.9765625 is 8000.

[0054] The circuit used for measurement is as follows Figure 3 As shown, in this embodiment, the coarse delay chain 110 includes 128 coarse delay units connected in series. The start end of the coarse delay chain 110 receives the start signal START. The START signal is sequentially delayed in the 128 coarse delay units. The delay time of the coarse delay unit is τ1. In this embodiment, τ1 = 100ps.

[0055] The first delay chain 131 includes 128 first delay units connected in series. The first delay chain 131 receives a first end signal STOP1. STOP1 is sequentially delayed in the 128 first delay units. The delay time of the first delay unit is τ2. In this embodiment, τ2 = 80ps.

[0056] The first flip-flop chain 121 includes 128 D flip-flops. The data input terminals D of the 128 D flip-flops are connected one-to-one to the output terminals of the 128 coarse delay units, and the clock terminal CLK is connected one-to-one to the output terminals of the 128 first delay units of the first delay chain 131.

[0057] In this embodiment, the first coarse delay unit of the coarse delay chain 110 is a NAND gate, and the remaining coarse delay units are NOT gates. The outputs of the odd-numbered coarse delay units are connected to the data inputs of the 128 first flip-flops through a NOT gate, and the outputs of the even-numbered coarse delay units are connected to the data inputs of the 128 first flip-flops of the first flip-flop chain. The 128 first delay units of the first delay chain 131 are NOT gates. The odd-numbered first delay units are connected to the clock terminals of the corresponding flip-flops through an additional NOT gate, and the outputs of the even-numbered first delay units are directly connected to the clock terminals of the corresponding first flip-flops of the first flip-flop chain 121.

[0058] Each new rising edge of START resets TDC, including resetting the initial state of the high-order code counter, the latch flip-flops of the first flip-flop chain 121, and the coarse delay chain 110. In this example, the data selector 140 selects the output of the 7th coarse delay unit of the coarse delay chain 110 and feeds it back to the Ring_In terminal of the coarse delay chain 110. Together with START, it serves as the input of a NAND gate, forming a ring oscillator with a period of 7*100*2ps.

[0059] The high-order encoder counter 150 is connected to the output of the 7th coarse delay unit and is used to record the number of cycles of the START signal in the first 7 coarse delay units of the coarse delay chain 110. The input of the first low-order encoder 161 is connected to the output of 128 D flip-flops. The input of the decoder 170 is connected to the outputs of the high-order encoder counter 150 and the first low-order encoder 161, decoding the data input to the high-order encoder counter 150 and the first low-order encoder 161 into a time count.

[0060] During time measurement, initialization begins with the START input being low. This resets all data in the high-order encoder counter 150, the first low-order encoder 161, and the decoder 170 to zero. At this point, the upper input of the NAND gate in the coarse delay chain 110 is 1. Next, the rising edge of the START signal arrives, and the lower input of the NAND gate becomes 1. The inputs of the D flip-flops then sequentially receive 1s. After a time interval ΔT, the rising edge of the STOP1 signal arrives. This rising edge latches the waveform of the coarse delay chain sequentially through each D flip-flop and outputs the data to the first low-order encoder 161.

[0061] The decoder 170 decodes the time count value between STOP1 and START based on the information input from the high-order encoder counter 150 and the first low-order encoder 161, and finally calculates ΔT.

[0062] For example, the high-order encoder counter has a count value of Z. When calculating the time count according to the first low-order encoder 161, the initial state of Ring_In is 1 during the first half-cycle of the ring oscillator; after half a cycle, the output 0 of the multiplexer is fed back to the Ring_In terminal of the coarse delay chain, and the input of Ring_In changes from 1 to 0. Therefore, there are two cases for the waveform of the coarse delay chain latched by each D flip-flop in the flip-flop chain. When it is in the first half-cycle of the ring oscillator, the corresponding D flip-flop receives a high-level signal of 1, and the number of D flip-flops latched to the high level is X. Then the time calculation formula is: (Z*2*7*100+X*20ps)*0.9765625; when it is in the second half-cycle of the ring oscillator, the data output by the coarse delay chain to the corresponding D flip-flop is a low-level 0, and the number of D flip-flops latched to 0 is Y. At this time, the time is (Z*2*7*100+7*100+Y*20)*0.9765625.

[0063] In this embodiment, the fine delay chain module 130 further includes a third delay chain. The calibration process of the third delay chain is exactly the same as that of the first delay chain, and will not be described again here. The time conversion circuit of this embodiment can simultaneously calculate the time of two end signals STOP1 and STOP2. However, in other embodiments, the time conversion circuit based on the differential delay chain may only include the first delay chain 131, which can be used to calculate the time of one end signal. This invention is not limited to this.

[0064] The time conversion circuit and time measurement method of this invention employ a differential delay chain system architecture, coupled with corresponding internal testing and calibration methods, which can significantly improve time measurement accuracy without noticeably increasing system power consumption and cost. Furthermore, the time conversion circuit of this invention includes a ring oscillator for calibrating the coarse and fine delay chains, and the number of delay units in the ring oscillator can be selected via a data selector, allowing adjustment of the ring oscillator's frequency.

[0065] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A time conversion circuit based on a differential delay chain, characterized in that, include: Coarse delay chains, including those cascaded end-to-end. N A coarse delay unit, the start end of the coarse delay chain receives the start signal START, the... N One coarse delay unit is used to process the received START signal. N Level 1 delay τ 1. Processing, in which, N It is an integer not less than 2; The first delay chain includes chains that are connected end-to-end. N A first delay unit, wherein the start end of the first delay chain receives a first end signal STOP1. N The first delay unit is used to process the received STOP1. N Level 2 delay τ 2. Processing; The first trigger chain includes N A first trigger, the N The first input terminals of each of the first flip-flops are respectively connected to... N The output of a coarse delay unit N The second input terminals of each of the first flip-flops are respectively connected to... N The output of the first delay unit; A data selector, the inputs of which are respectively connected to the first coarse delay chain. p Level coarse delay unit and the first q The output of the first-stage coarse delay unit, and the output feedback of the data selector, are connected to the starting end of the coarse delay chain, Ring_In, to form a ring oscillator. p ≠ q ; A high-order code counter, the input of which is connected to the output of the data selector, is used to record the number of cycles of the START signal in the ring oscillator; The first low-order encoder, each input terminal of which is correspondingly connected to the first trigger chain. N The output of the first flip-flop; A decoder, the input of which is connected to the output of the high-bit encoder counter and the first low-bit encoder, decodes the data input to the high-bit encoder counter and the first low-bit encoder into a time count; in, τ 2< τ 1, and the stated N The data input terminals of each of the first flip-flops are connected to a corresponding one-to-one connection N The output of the coarse delay unit, the N The clock terminals of each of the first flip-flops are connected to the corresponding terminals. N The output of the first delay unit; The first coarse delay unit in the coarse delay chain is a NAND gate, and the remaining coarse delay units are NOT gates. The outputs of the odd-numbered coarse delay units are connected to the data input terminals of the first flip-flops through a NOT gate, and the outputs of the even-numbered coarse delay units are directly connected to the data input terminals of the first flip-flops. The first delay chain N The first delay unit of each stage is an NOT gate, and the output of the odd-numbered first delay units is connected to the clock terminal of the corresponding first flip-flop through an additional NOT gate, while the output of the even-numbered first delay units is directly connected to the clock terminal of the corresponding first flip-flop.

2. The time conversion circuit based on differential delay chain according to claim 1, characterized in that, in, It also includes a second delay chain, a second trigger chain, and a second low-order encoder. The second delay chain includes a series connection at both ends. N Second delay unit of stage, N The second delay unit is the same as the first delay unit, with a delay time of [missing information]. τ 2. The output of the data selector is connected to the start of the second delay chain, and the second trigger chain... N The data input terminals of each of the second flip-flops are connected to a corresponding one-to-one connection. N The outputs of each coarse delay unit are connected one-to-one with the clock terminals of the second flip-flops. N The outputs of the second delay units are connected to the inputs of the second low-order encoder, respectively, which are connected to the second flip-flop chain. N The output of the second flip-flop.

3. The time conversion circuit based on differential delay chain according to claim 2, characterized in that, The first coarse delay unit in the coarse delay chain is a NAND gate, the remaining coarse delay units are NOT gates, and the outputs of the odd-numbered coarse delay units are connected to the second flip-flop chain. N The data input terminal of the second flip-flop, and the output of the even-numbered coarse delay unit are connected to a corresponding NOT gate. N The data input terminal of the second flip-flop.

4. The time conversion circuit based on differential delay chain according to claim 3, characterized in that, The second delay chain N The second delay unit of the stage is an NOT gate. The output of the odd-numbered stage second delay unit is directly connected to the clock terminal of the corresponding second flip-flop, while the output of the even-numbered stage second delay unit is connected to the clock terminal of the corresponding second flip-flop through an additional NOT gate.

5. The time conversion circuit based on differential delay chain according to claim 2, characterized in that, in, It also includes a third delay chain, a third trigger chain, and a third low-order encoder. The third delay chain includes a series-connected third delay unit. N The third delay unit is exactly the same as the second delay unit, with a delay time of [missing information]. τ 2. The start of the third delay chain receives the second end signal STOP2. N A third delay unit is used to process the received second end signal STOP2. N The second delay τ 2. Processing the third trigger chain N The data input terminals of each third flip-flop are connected to a corresponding one-to-one connection. N The output of the coarse delay unit, the third flip-flop chain N The clock terminals of each of the third flip-flops are connected to the corresponding terminals. N The output of the third delay unit, and the input terminals of the third low-order encoder are respectively connected to the third trigger chain. N The output of the third flip-flop.

6. The time conversion circuit based on differential delay chain according to claim 5, characterized in that, in, In the coarse delay chain, the first coarse delay unit is a NAND gate, and the remaining coarse delay units are NOT gates. The outputs of the odd-numbered coarse delay units are connected to the data inputs of each third flip-flop through a NOT gate, while the outputs of the even-numbered coarse delay units are directly connected to the data inputs of each third flip-flop.

7. The time conversion circuit based on differential delay chain according to claim 6, characterized in that, Third delay chain N The third delay unit of the stage is an NOT gate. The output of the odd-numbered third delay units is connected to the clock terminal of the corresponding third flip-flop through an additional NOT gate, while the output of the even-numbered third delay units is directly connected to the clock terminal of the corresponding third flip-flop.

8. The time conversion circuit based on differential delay chain according to any one of claims 5-7, characterized in that, The number of delay units in the coarse delay chain, the first delay chain, the second delay chain, and the third delay chain is 128 each, and p , q It is an odd number.

9. A time conversion chip based on a differential delay chain, characterized in that, Includes the time conversion circuit described in any one of claims 1-8.

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