Ramp compensation circuit for a buck switching regulator and switching regulator

Abstract

The application provides a slope compensation circuit and a switching voltage regulator for a step-down switching voltage regulator, which comprises a current sampling compensation module and a comparator module; the current sampling compensation module is connected with a bias current and a gate control signal respectively, and is electrically connected with a positive input end of the comparator module and a source electrode of a power switching tube respectively, and an inverting input end of the comparator module is connected with an EA output signal; the current sampling compensation module samples the gate control signal to generate a sampling current, and superimposes the bias current and the sampling current to generate a slope compensation current; the comparator module compares the slope compensation current with the EA output signal and generates a pulse width modulation signal according to a comparison result, so that a duty cycle of an output voltage / output current of the step-down switching voltage regulator converges. The application reduces a peak value of the output voltage (or the output current) when the output voltage (or the output current) of the step-down switching voltage regulator is disturbed, so that the duty cycle of the pulse width modulation has convergence.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a slope compensation circuit for a buck switching regulator and a switching regulator. Background Technology

[0002] Figure 1 This diagram illustrates a typical wide-input-range, high-efficiency, high-frequency DC-DC buck switching regulator capable of providing up to 0.6A of output current. At a fixed switching frequency of 1.6MHz, the current-mode PWM (Pulse Width Modulation) controlled converter allows the use of small external components such as ceramic input / output capacitors and small inductors. This configuration includes cold-start and dual-supply jump-start capabilities, with a minimum input voltage as low as 4.5V and a maximum of 45V, and even higher transient voltages. Due to the high input voltage, the converter may overheat when the supply current is increased.

[0003] VIN provides the power supply voltage to the IC (integrated circuit). EN, via EN_Detector, turns on the regulator, activating various protection circuits, soft-start circuits, and the oscillator. The internal driver controls the gate of the NMOS power switch, periodically turning it on and off. The VGS (gate-source voltage) of the power switch is fixed at 4.8V, periodically charging and discharging the inductor L to maintain a stable output voltage. The output enters the error amplifier (EA) module through the feedback terminal (FB), which generates the EAOUT signal. However, due to insufficient charging and discharging of the inductor during this process, the ripple of the output current becomes increasingly large, ultimately causing significant fluctuations in the output voltage VOUT. After voltage division feedback, this causes the switching duty cycle of the power switch to deviate significantly from the expected value, thus affecting the magnitude of the output voltage VOUT. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defect in the prior art that the switching duty cycle of the power switch tube deviates significantly from the expected value due to insufficient charging and discharging of the inductor, thereby affecting the output voltage. The present invention provides a slope compensation circuit and a switching regulator for a buck switching regulator.

[0005] The present invention solves the above-mentioned technical problems through the following technical solution:

[0006] In a first aspect, the present invention provides a slope compensation circuit for a step-down switching regulator, the slope compensation circuit comprising: a current sampling compensation module and a comparator module;

[0007] The first input terminal of the current sampling compensation module is connected to the bias current, the second input terminal of the current sampling compensation module is electrically connected to the gate of the power switch in the buck switching regulator to receive the gate control signal, the first output terminal of the current sampling compensation module is electrically connected to the non-inverting input terminal of the comparator module, the second output terminal of the current sampling compensation module is electrically connected to the source of the power switch, and the inverting input terminal of the comparator module is connected to the EA output signal of the error amplifier module in the buck switching regulator.

[0008] The current sampling compensation module is used to sample the gate control signal to generate a sampling current, and to superimpose the bias current and the sampling current to generate a ramp compensation current and output it through the third output terminal;

[0009] The comparator module is used to compare the ramp compensation current with the EA output signal and generate a pulse width modulation signal based on the comparison result to make the duty cycle of the output voltage / output current of the buck switching regulator converge.

[0010] Optionally, the current sampling compensation module includes: a current sampling compensation unit and a bias unit;

[0011] The first input terminal, the second input terminal, the first output terminal, and the second output terminal of the current sampling compensation unit are respectively used as the first input terminal, the second input terminal, the first output terminal, and the second output terminal of the current sampling compensation module;

[0012] The third input terminal of the current sampling compensation unit is electrically connected to the first output terminal of the bias unit, the fourth input terminal of the current sampling compensation unit is electrically connected to the second output terminal of the bias unit, the fifth input terminal of the current sampling compensation unit is electrically connected to the third output terminal of the bias unit, the sixth input terminal of the current sampling compensation unit is electrically connected to the fourth output terminal of the bias unit, and the control terminal of the bias unit is connected to an enable control signal.

[0013] The bias unit is used to provide the module's internal bias voltage for the current sampling compensation unit.

[0014] Optionally, the current sampling compensation unit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first diode, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a compensation capacitor network composed of several NMOS transistors;

[0015] The eleventh MOS transistor is a PMOS transistor, and the twelfth and thirteenth MOS transistors are both NMOS transistors;

[0016] The first terminals of the second resistor and the third resistor are both connected to the input voltage. The second terminal of the second resistor is electrically connected to the drain of the thirteenth MOSFET and the first terminal of the fourth resistor, respectively. The second terminal of the third resistor is electrically connected to the first terminal of the fifth resistor and the source of the eleventh MOSFET, respectively. The second terminal of the fifth resistor is electrically connected to the output terminal of the first diode. The input terminal of the first diode is electrically connected to the gate of the eleventh MOSFET. The drain of the eleventh MOSFET is electrically connected to the drain of the twelfth MOSFET. The source of the twelfth MOSFET is electrically connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor is electrically connected to the first terminal of the first resistor and the first terminal of the compensation capacitor network, respectively. The second terminal of the first resistor is grounded. The second terminal of the compensation capacitor network is electrically connected to the first input terminal and the third output terminal of the current sampling compensation unit, respectively.

[0017] The gate of the thirteenth MOS transistor is used as the second input terminal of the current sampling compensation unit, the source of the thirteenth MOS transistor is used as the second output terminal of the current sampling compensation unit, the second terminal of the third resistor is used as the third input terminal of the current sampling compensation unit, the second terminal of the fourth resistor is used as the fourth input terminal of the current sampling compensation unit, the input terminal of the first diode is used as the fifth input terminal of the current sampling compensation unit, and the gate of the twelfth MOS transistor is used as the sixth input terminal of the current sampling compensation unit.

[0018] Optionally, the compensation capacitor network includes: a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, and a seventeenth MOS transistor;

[0019] The first end of the compensation capacitor network is electrically connected to the source and drain of the fourteenth MOS transistor, the source and drain of the fifteenth MOS transistor, the source and drain of the sixteenth MOS transistor, and the source and drain of the seventeenth MOS transistor, respectively.

[0020] The second end of the compensation capacitor network is electrically connected to the gate of the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, the gate of the sixteenth MOS transistor, and the gate of the seventeenth MOS transistor, respectively.

[0021] Optionally, the bias unit includes: a first current source, a zeroth MOS transistor, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, a second diode, a seventh resistor, and a NOT gate;

[0022] The output terminal of the first current source is electrically connected to the gate and drain of the first MOS transistor, the drain of the zeroth MOS transistor, and the gate of the second MOS transistor. The ground terminal of the first current source is grounded. The source of the zeroth MOS transistor, the source of the first MOS transistor, and the source of the second MOS transistor are all connected to the power supply voltage. The gate of the zeroth MOS transistor and the input terminal of the NOT gate are both connected to the enable control signal. The drain of the second MOS transistor is electrically connected to the drain of the third MOS transistor. The gate of the third MOS transistor is electrically connected to the gate of the fourth MOS transistor, the drain of the fifth MOS transistor, and the gate of the sixth MOS transistor.

[0023] The drain of the fourth MOS transistor is electrically connected to the source of the seventh MOS transistor. The drain of the seventh MOS transistor is electrically connected to the input terminal of the second diode, the drain and gate of the ninth MOS transistor, and the gate of the tenth MOS transistor. The gate of the seventh MOS transistor is connected to the input bias voltage. The gate of the seventh MOS transistor is also electrically connected to the gate of the eighth MOS transistor.

[0024] The source of the ninth MOS transistor is electrically connected to the first terminal of the seventh resistor, the second terminal of the seventh resistor is electrically connected to the output terminal of the second diode, the source of the eighth MOS transistor is electrically connected to the drain of the sixth MOS transistor, the drain of the eighth MOS transistor is electrically connected to the drain of the tenth MOS transistor, and the gate of the fifth MOS transistor is electrically connected to the output terminal of the NOT gate.

[0025] The sources of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all grounded;

[0026] The source of the ninth MOS transistor is used as the first output terminal of the bias unit, the source of the tenth MOS transistor is used as the second output terminal of the bias unit, the drain of the tenth MOS transistor is used as the third output terminal of the bias unit, and the gate of the eighth MOS transistor is used as the fourth output terminal of the bias unit.

[0027] Optionally, the zeroth MOS transistor, the first MOS transistor, the second MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are all PMOS transistors;

[0028] The third, fourth, fifth, sixth, seventh, and eighth MOS transistors are all NMOS transistors.

[0029] Optionally, the thirteenth MOS transistor is a sampling transistor, and the width-to-length ratio of the thirteenth MOS transistor is 1 / K times the width-to-length ratio of the power switching transistor, where K is a positive integer.

[0030] Optionally, the resistance value of the third resistor is the same as that of the fourth resistor.

[0031] In a second aspect, the present invention provides a switching regulator, the switching regulator comprising: a buck switching regulator and the aforementioned slope compensation circuit for the buck switching regulator;

[0032] The buck switching regulator includes: a bandgap reference module, a power switch, and an error amplifier module;

[0033] The slope compensation circuit includes: a current sampling compensation module and a comparator module;

[0034] The bandgap reference module outputs a bias current, and the error amplifier module outputs an EA output signal.

[0035] The first input terminal of the current sampling compensation module is connected to the bias current, the second input terminal of the current sampling compensation module is electrically connected to the gate of the power switch to receive the gate control signal, the second output terminal of the current sampling compensation module is electrically connected to the source of the power switch, and the inverting input terminal of the comparator module is connected to the EA output signal.

[0036] The ramp compensation circuit is used to sample the gate control signal to generate a sampling current, and to superimpose the bias current and the sampling current to generate a ramp compensation current. The ramp compensation current is compared with the EA output signal, and a pulse width modulation signal is generated according to the comparison result to make the duty cycle of the output voltage / output current of the buck switching regulator converge.

[0037] Optionally, the buck switching regulator further includes: a voltage regulator;

[0038] The voltage regulator is connected to the input voltage, and the voltage regulator outputs the power supply voltage to the bandgap reference module;

[0039] The bandgap reference module also outputs an input bias voltage;

[0040] And / or,

[0041] The step-down switching regulator also includes: an enable control module;

[0042] The first terminal of the first resistor in the slope compensation circuit outputs a peak current to the peak current detection unit in the enable control module, so that the slope compensation circuit is shut down when the peak current exceeds the rated value.

[0043] The positive and progressive effects of this invention are as follows: by using a slope compensation circuit, the peak value of the output voltage (or output current) of the buck switching regulator is reduced when there is a disturbance, so that the peak value when there is no disturbance and when there is a disturbance forms a descending slope. Thus, when the DC-DC circuit is working, whether in current mode or voltage mode, when pulse width modulation (PWM) occurs, the duty cycle of the output can automatically return to the ideal value when there is a small fluctuation in the output. The duty cycle of PWM modulation has convergence. Attached Figure Description

[0044] Figure 1 This is an example of a step-down switching regulator structure in the prior art.

[0045] Figure 2 This is a schematic diagram of the ramp compensation circuit for a step-down switching regulator according to Embodiment 1 of the present invention.

[0046] Figure 3 This is a schematic diagram of the output current of the slope compensation circuit for a step-down switching regulator in Embodiment 1 of the present invention without slope compensation.

[0047] Figure 4 This is a schematic diagram of the output current with added slope compensation in the slope compensation circuit for a step-down switching regulator according to Embodiment 1 of the present invention.

[0048] Figure 5 This is a schematic diagram of the slope compensation principle of the slope compensation circuit for a step-down switching regulator according to Embodiment 1 of the present invention.

[0049] Figure 6 This is a structural diagram of the slope compensation circuit for a step-down switching regulator according to Embodiment 1 of the present invention.

[0050] Figure 7 The simulation results of Isample for the slope compensation circuit of the step-down switching regulator in Embodiment 1 of the present invention are shown.

[0051] Figure 8 This is a structural diagram of the switching regulator of Embodiment 2 of the present invention. Detailed Implementation

[0052] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.

[0053] Example 1

[0054] This embodiment provides a slope compensation circuit for a buck switching regulator, referencing... Figure 2The slope compensation circuit includes a current sampling compensation module (ISENSE_and_OCP) and a comparator module (PWM_COMP).

[0055] The first input terminal of the current sampling compensation module (ISENSE_and_OCP) is connected to the bias current (Ibias). The second input terminal of the current sampling compensation module (ISENSE_and_OCP) is electrically connected to the gate of the power switch (NMOS) in the buck switching regulator to receive the gate control signal (CTL_DRI). The first output terminal of the current sampling compensation module (ISENSE_and_OCP) is electrically connected to the non-inverting input terminal of the comparator module (PWM_COMP). The second output terminal of the current sampling compensation module (ISENSE_and_OCP) is electrically connected to the source of the power switch (NMOS). The inverting input terminal of the comparator module (PWM_COMP) is connected to the EA output signal (EAOUT) of the error amplifier module in the buck switching regulator.

[0056] The current sampling compensation module (ISENSE_and_OCP) is used to sample the gate control signal (CTL_DRI) to generate a sampling current (Isample), and to superimpose the bias current (Ibias) and the sampling current (Isample) to generate a ramp compensation current (V_ISENSE), which is then output through the third output terminal.

[0057] The comparator module (PWM_COMP) compares the ramp compensation current (V_ISENSE) with the EA output signal (EAOUT) and generates a pulse width modulation signal (PWM_logic) based on the comparison result to bring the duty cycle of the output voltage / output current of the buck switching regulator to converge.

[0058] Without slope compensation, the output current is divergent. If there is a small disturbance in the output current, the output current in current mode will be as follows: Figure 3 The changes shown.

[0059] Figure 3 The diagram illustrates the subsequent changes in the output current when an error occurs. The horizontal dashed line represents Icomp (or the equivalent current value of the EAOUT output). Over a short period of several cycles, Icomp can be considered a constant current, compared to a current value proportional to the output current. Assuming ml and m2 are the rates of increase and decrease of the output current, respectively, then:

[0060] That is to say

[0061] And by Figure 3 It can be seen that the absolute value of the time difference Δt between the current rising stage and the current falling stage in each period is equal (comparison between with current disturbance and without current disturbance), and the directions are opposite, that is, Δt = Δt 1up = -Δt 1down Therefore

[0062] Or, within equal time intervals, the relationship between the current change amount and the slope is calculated, and the connection between each period is that the time is equal. Also, for a BUCK (buck converter circuit),

[0063] where L is the inductance value.

[0064] Therefore: Therefore Also at this time, the duty cycle d > 0.5, VIN - VOUT < VOUT, so ΔI1 < ΔI2. By generalization, we have ΔIn < ΔIn+1. That is, the output current is divergent and cannot be stabilized. Refer to Figure 4 , after adding slope compensation, assume the slope of the slope compensation is -Ma.

[0065] Figure 5 In, AD = BF = CG = ΔI1, GI = ΔI2' (the current falling slope without slope compensation),

[0066] FE = ΔI2 (the current falling slope after adding slope compensation), GH = Ma * Δt

[0067] Therefore

[0068] We have:

[0069] To ensure convergence, the absolute value of α needs to be less than l. That is Therefore, when m2 > Ma, m2 - Ma < m1 + Ma,

[0070] That is:

[0071] And since for a BUCK So

[0072]

[0073] That is

[0074] That is

[0075] Continue to derive:

[0076] (d is the duty cycle, d + d' = 1)

[0077] To ensure the current loop remains stable at the maximum duty cycle, assuming the duty cycle reaches the ideal value of 100%, at which point d' = 0, therefore... Need to ensure That is, 1-

[0078]

[0079] final

[0080] To obtain a sufficient slope compensation value, the compensation current must be set according to the slope of the inductor current drop. The problem is that the slope m2 of the output current drop is proportional to the output voltage. Therefore, the slope current should ideally be proportional to the output voltage. If the slope compensation current is fixed, it must be determined based on the maximum output voltage (because m2 is at its maximum and m1 is at its minimum when the output voltage is at its maximum). Note: The units of the slope variables ml, m2, and Ma above are all A / s (amperes per second). Generally, the value is taken around ma = 0.75 * m2.

[0081] In this embodiment, a slope compensation circuit reduces the peak value of the output voltage (or output current) of the buck switching regulator when there is a disturbance. This creates a descending slope between the peak values ​​when there is no disturbance and when there is a disturbance. As a result, when the DC-DC circuit is in operation, whether in current mode or voltage mode, the duty cycle of the output can automatically return to the ideal value when there is a small fluctuation in the output during pulse width modulation (PWM). The duty cycle of PWM modulation has convergence.

[0082] In one embodiment, refer to Figure 6 The current sampling compensation module (ISENSE_and_OCP) includes: a current sampling compensation unit 11 and a bias unit 12.

[0083] The first input terminal, the second input terminal, the first output terminal, and the second output terminal of the current sampling compensation unit 11 are respectively used as the first input terminal, the second input terminal, the first output terminal, and the second output terminal of the current sampling compensation module (ISENSE_and_OCP).

[0084] The third input terminal of the current sampling compensation unit 11 is electrically connected to the first output terminal of the bias unit 12, the fourth input terminal of the current sampling compensation unit 11 is electrically connected to the second output terminal of the bias unit 12, the fifth input terminal of the current sampling compensation unit 11 is electrically connected to the third output terminal of the bias unit 12, the sixth input terminal of the current sampling compensation unit 11 is electrically connected to the fourth output terminal of the bias unit 12, and the control terminal of the bias unit 12 is connected to an enable control signal (OTP_n).

[0085] The bias unit 12 is used to provide the module internal bias voltage for the current sampling compensation unit 11.

[0086] In one embodiment, the current sampling compensation unit 11 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first diode D1, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, and a compensation capacitor network composed of several NMOS transistors.

[0087] The eleventh MOSFET M11 is a PMOS transistor, while the twelfth MOSFET M12 and the thirteenth MOSFET M13 are both NMOS transistors.

[0088] The first terminals of the second resistor R2 and the third resistor R3 are both connected to the input voltage (VIN). The second terminal of the second resistor R2 is electrically connected to the drain of the thirteenth MOSFET M13 and the first terminal of the fourth resistor R4, respectively. The second terminal of the third resistor R3 is electrically connected to the first terminal of the fifth resistor R5 and the source of the eleventh MOSFET M11, respectively. The second terminal of the fifth resistor R5 is electrically connected to the output terminal of the first diode D1. The input terminal of the first diode D1 is electrically connected to the gate of the eleventh MOSFET M11. The drain of the eleventh MOSFET M11 is electrically connected to the drain of the twelfth MOSFET M12. The source of the twelfth MOSFET M12 is electrically connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the compensation capacitor network (Ccompensation), respectively. The second terminal of the first resistor R1 is grounded. The second terminal of the compensation capacitor network (Ccompensation) is electrically connected to the first input terminal and the third output terminal of the current sampling compensation unit 11, respectively.

[0089] The gate of the thirteenth MOSFET M13 is used as the second input terminal of the current sampling compensation unit 11, the source of the thirteenth MOSFET M13 is used as the second output terminal of the current sampling compensation unit 11, the second terminal of the third resistor R3 is used as the third input terminal of the current sampling compensation unit 11, the second terminal of the fourth resistor R4 is used as the fourth input terminal of the current sampling compensation unit 11, the input terminal of the first diode D1 is used as the fifth input terminal of the current sampling compensation unit 11, and the gate of the twelfth MOSFET M12 is used as the sixth input terminal of the current sampling compensation unit 11 (the bias voltage VBE is input through the sixth input terminal).

[0090] In one embodiment, refer to Figure 6The compensation capacitor network includes: the fourteenth MOSFET M14, the fifteenth MOSFET M15, the sixteenth MOSFET M16, and the seventeenth MOSFET M17.

[0091] The first terminal of the compensation capacitor network is electrically connected to the source and drain of the fourteenth MOSFET M14, the source and drain of the fifteenth MOSFET M15, the source and drain of the sixteenth MOSFET M16, and the source and drain of the seventeenth MOSFET M17, respectively.

[0092] The second terminal of the compensation capacitor network is electrically connected to the gates of the fourteenth MOSFET M14, the fifteenth MOSFET M15, the sixteenth MOSFET M16, and the seventeenth MOSFET M17, respectively.

[0093] In one embodiment, refer to Figure 6 The bias unit 12 includes: a first current source I1, a zeroth MOSFET M0, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, a second diode D2, a seventh resistor R7, and a NOT gate NO.

[0094] The output terminal of the first current source I1 is electrically connected to the gate and drain of the first MOSFET M1, the drain of the zeroth MOSFET M0, and the gate of the second MOSFET M2. The ground terminal of the first current source I1 is grounded. The source of the zeroth MOSFET M0, the source of the first MOSFET M1, and the source of the second MOSFET M2 are all connected to the power supply voltage (VCC). The gate of the zeroth MOSFET M0 and the input terminal of the NOT gate NO are all connected to the enable control signal (OTP_n). The drain of the second MOSFET M2 is electrically connected to the drain of the third MOSFET M3. The gate of the third MOSFET M3 is electrically connected to the gate of the fourth MOSFET M4, the drain of the fifth MOSFET M5, and the gate of the sixth MOSFET M6.

[0095] The drain of the fourth MOSFET M4 is electrically connected to the source of the seventh MOSFET M7. The drain of the seventh MOSFET M7 is electrically connected to the input terminal of the second diode D2, the drain and gate of the ninth MOSFET M9, and the gate of the tenth MOSFET M10. The gate of the seventh MOSFET M7 is connected to the input bias voltage (VBE). The gate of the seventh MOSFET M7 is also electrically connected to the gate of the eighth MOSFET M8.

[0096] The source of the ninth MOSFET M9 is electrically connected to the first terminal of the seventh resistor R7, and the second terminal of the seventh resistor R7 is electrically connected to the output terminal of the second diode D2. The source of the eighth MOSFET M8 is electrically connected to the drain of the sixth MOSFET M6, and the drain of the eighth MOSFET M8 is electrically connected to the drain of the tenth MOSFET M10. The gate of the fifth MOSFET M5 is electrically connected to the output terminal of the NOT gate NO.

[0097] The sources of the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 are all grounded.

[0098] The source of the ninth MOSFET M9 is used as the first output terminal of the bias unit 12, the source of the tenth MOSFET M10 is used as the second output terminal of the bias unit 12, the drain of the tenth MOSFET M10 is used as the third output terminal of the bias unit 12, and the gate of the eighth MOSFET M8 is used as the fourth output terminal of the bias unit 12.

[0099] In one embodiment, the zeroth MOS transistor M0, the first MOS transistor M1, the second MOS transistor M2, the ninth MOS transistor M9, and the tenth MOS transistor M10 are all PMOS transistors.

[0100] The third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, and the eighth MOSFET M8 are all NMOS transistors.

[0101] In one embodiment, the thirteenth MOS transistor M13 is a sampling transistor, and the width-to-length ratio of the thirteenth MOS transistor M13 is 1 / K times the width-to-length ratio of the power switching transistor (NMOS), where K is a positive integer.

[0102] In one embodiment, the resistance value of the third resistor R3 is the same as that of the fourth resistor R4.

[0103] The circuit diagram of the current sampling compensation module is as follows: Figure 6 As shown, due to the large range of inductance variation (2.2uH-47uH) and the large output voltage range (0.8V-54V (=0.9*VIN)), fixed slope compensation is difficult to cover a wide range of applications.

[0104] The compensation slope needs to cover a range that varies by tens of times. If designed according to the maximum compensation slope, the peak current will be too large.

[0105] Compensation slope requires trim, and the trim range needs to be large enough to meet all application scenarios.

[0106] In the slope compensation circuit, CTL_DRI is the gate control signal, and M13 is the sampling transistor. The aspect ratio of M13 is 1 / K times that of the power switch transistor. Therefore, the sampling current multiple is 1 / K. After sampling, the current gains through the resistor network composed of R2 and R3 are R3 / R2. Isample is converted into a voltage signal through resistor R1 (within the dashed box below). The Bandgap input bias current signal Ibias passes through the compensation capacitor network Ccompensation composed of NMOS transistors to generate a voltage with compensation signal.

[0107] Set the system's slope compensation gradient to a typical application scenario: Ma = 0.7 * 12 / 47uH = 1.787M.

[0108]

[0109] Therefore

[0110] Therefore, the slope of the slope compensation

[0111] Therefore

[0112] Assuming the bias current Ibias providing slope compensation is 2.5uA, the sampling current multiple K is 1937.5, and since R3 = R4, the current gain of Isample is R3 / R2 = 15, and R1 is 12.94Komh, then Ccompensation = 3.142pF is obtained.

[0113] Therefore, the EA output signal with current compensation information is:

[0114] The compensation process is now complete.

[0115] The current mirror includes I1, M0, M1, M2, M3, M4, M7, and M9. The enable control signal OTP_n ​​controls the current mirror's on / off state. When OTP_n ​​is high, M0 and M5 are off, and the current mirror operates normally, replicating the reference current I1 proportionally to M4 and M5. R5, R7, and the diode group (D1 and D2) form a protection circuit. The gate control signal CTR_DRI is a duty cycle controlled switching signal that controls the conduction of the sampling transistor M13, thereby obtaining the sampling current. The LX signal is connected to the source of the power switch NMOS, causing the sampling current to flow into the inductor L. The input bias voltage VBE can be provided by the bandgap reference module in the buck switching regulator.

[0116] The peak current VSENSE_OCP is a peak current detection signal that can be connected to the peak current detection unit in a buck switching regulator. When the peak current VSENSE_OCP exceeds the rated value, the slope compensation circuit will be shut down.

[0117] The following are the simulation results of the conversion of the output power transistor's current Iswitch to the sampling current Isample under different process angles. Different process angles have almost no effect on Isample. When Iswitch = 1A, the simulated Isample is 39uA, and the calculated gain from Iswitch to Isample is 1 / 24863. Since R3 / R2 = 15, K = 1657. When Iswitch = 600m, Isample = 23.3uA, so gain = 1 / 25751, K = 1716, which matches the design requirements.

[0118] VSENSE_OCP = Isample * RI. This signal monitors whether the peak current of the power transistor exceeds 1A. When Iswitch ≥ 1A, the VSENSE_OCP signal will cause the OCP (peak current detection) output to go high. At 600mA, the power consumption is 9.601W, and at 1A, the power consumption is 16W.

[0119] Figure 7 The simulation results for Isample corresponding to different Iswitch are shown.

[0120] Example 2

[0121] This invention provides a switching regulator, with reference to... Figure 8 The switching regulator includes: a buck switching regulator and a slope compensation circuit 1 for the buck switching regulator in Embodiment 1. Figure 8 All parts except for the slope compensation circuit 1 belong to the step-down switching regulator.

[0122] A step-down switching regulator includes: a bandgap reference module, a power switch (NMOS), and an error amplifier module (EA).

[0123] The slope compensation circuit 1 includes a current sampling compensation module (ISENSE_and_OCP) and a comparator module (PWM_COMP).

[0124] The bandgap reference module outputs the bias current, and the error amplifier module (EA) outputs the EA output signal.

[0125] The first input terminal of the current sampling compensation module (ISENSE_and_OCP) is connected to the bias current (Ibias). The second input terminal of the current sampling compensation module (ISENSE_and_OCP) is electrically connected to the gate of the power switch (NMOS) to receive the gate control signal. The second output terminal of the current sampling compensation module (ISENSE_and_OCP) is electrically connected to the source of the power switch (NMOS). The inverting input terminal of the comparator module (PWM_COMP) is connected to the EA output signal (EAOUT).

[0126] The slope compensation circuit 1 is used to sample the gate control signal (CTL_DRI) to generate a sampling current, and to superimpose the bias current (Ibias) and the sampling current (Isample) to generate a slope compensation current. The slope compensation current (V_ISENSE) is compared with the EA output signal (EAOUT), and a pulse width modulation signal is generated based on the comparison result to make the duty cycle of the output voltage / output current of the buck switching regulator converge.

[0127] Wherein, NMOS_sample is the sampling tube (i.e. Figure 6 The sampling transistor M13 generates a sampling current Isample. The sampling current is added to the compensation current and passed through a resistor to obtain the ramp compensation current V_ISENSE, which is then output. In addition, a comparator (PWM_COMP) is added to compare V_ISENSE with EAOUT for further pulse width modulation.

[0128] The switching regulator in this embodiment is an improved step-down switching regulator. Through the slope compensation circuit, the duty cycle of the output voltage VOUT can automatically return to the ideal value, and the duty cycle of the PWM modulation has convergence.

[0129] In this embodiment, a slope compensation circuit reduces the peak value of the output voltage (or output current) of the buck switching regulator when there is a disturbance. This creates a descending slope between the peak values ​​when there is no disturbance and when there is a disturbance. As a result, when the DC-DC circuit is in operation, whether in current mode or voltage mode, the duty cycle of the output can automatically return to the ideal value when there is a small fluctuation in the output during pulse width modulation (PWM). The duty cycle of PWM modulation has convergence.

[0130] In one embodiment, the buck switching regulator further includes a voltage regulator (REG).

[0131] The voltage regulator (REG) is connected to the input voltage (VIN), and the voltage regulator (REG) outputs the power supply voltage (VCC) to the bandgap reference module.

[0132] The bandgap reference module also outputs the input bias voltage (VBE).

[0133] In one embodiment, the buck switching regulator further includes an enable control module (EN_Detector).

[0134] The first terminal of the first resistor in the slope compensation circuit 1 outputs a peak current (VSENSE_OCP) to the peak current (VSENSE_OCP) detection unit in the enable control module, so that the slope compensation circuit 1 is shut down when the peak current (VSENSE_OCP) exceeds the rated value.

[0135] In one embodiment, the buck switching regulator may further include an oscillator module (OSC) for generating a clock signal (CLK_OSC).

[0136] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. A slope compensation circuit for a step-down switching regulator, characterized in that, The slope compensation circuit includes: a current sampling compensation module and a comparator module; The first input terminal of the current sampling compensation module is connected to the bias current, the second input terminal of the current sampling compensation module is electrically connected to the gate of the power switch in the buck switching regulator to receive the gate control signal, the first output terminal of the current sampling compensation module is electrically connected to the non-inverting input terminal of the comparator module, the second output terminal of the current sampling compensation module is electrically connected to the source of the power switch, and the inverting input terminal of the comparator module is connected to the EA output signal of the error amplifier module in the buck switching regulator. The current sampling compensation module is used to sample the gate control signal to generate a sampling current, and to superimpose the bias current and the sampling current to generate a ramp compensation current and output it through the first output terminal; The comparator module is used to compare the ramp compensation current with the EA output signal and generate a pulse width modulation signal based on the comparison result to make the duty cycle of the output voltage / output current of the buck switching regulator converge. The current sampling compensation module includes: a current sampling compensation unit and a bias unit; The first input terminal, the second input terminal, the first output terminal, and the second output terminal of the current sampling compensation unit are respectively used as the first input terminal, the second input terminal, the first output terminal, and the second output terminal of the current sampling compensation module; The third input terminal of the current sampling compensation unit is electrically connected to the first output terminal of the bias unit, the fourth input terminal of the current sampling compensation unit is electrically connected to the second output terminal of the bias unit, the fifth input terminal of the current sampling compensation unit is electrically connected to the third output terminal of the bias unit, the sixth input terminal of the current sampling compensation unit is electrically connected to the fourth output terminal of the bias unit, and the control terminal of the bias unit is connected to an enable control signal. The bias unit is used to provide the internal bias voltage for the current sampling compensation unit. The current sampling compensation unit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first diode, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a compensation capacitor network composed of several NMOS transistors; The eleventh MOS transistor is a PMOS transistor, and the twelfth and thirteenth MOS transistors are both NMOS transistors; The first terminals of the second resistor and the third resistor are both connected to the input voltage. The second terminal of the second resistor is electrically connected to the drain of the thirteenth MOSFET and the first terminal of the fourth resistor, respectively. The second terminal of the third resistor is electrically connected to the first terminal of the fifth resistor and the source of the eleventh MOSFET, respectively. The second terminal of the fifth resistor is electrically connected to the output terminal of the first diode. The input terminal of the first diode is electrically connected to the gate of the eleventh MOSFET. The drain of the eleventh MOSFET is electrically connected to the drain of the twelfth MOSFET. The source of the twelfth MOSFET is electrically connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor is electrically connected to the first terminal of the first resistor and the first terminal of the compensation capacitor network, respectively. The second terminal of the first resistor is grounded. The second terminal of the compensation capacitor network is electrically connected to the first input terminal and the first output terminal of the current sampling compensation unit, respectively. The gate of the thirteenth MOS transistor is used as the second input terminal of the current sampling compensation unit, the source of the thirteenth MOS transistor is used as the second output terminal of the current sampling compensation unit, the second terminal of the third resistor is used as the third input terminal of the current sampling compensation unit, the second terminal of the fourth resistor is used as the fourth input terminal of the current sampling compensation unit, the input terminal of the first diode is used as the fifth input terminal of the current sampling compensation unit, and the gate of the twelfth MOS transistor is used as the sixth input terminal of the current sampling compensation unit.

2. The slope compensation circuit for a step-down switching regulator as described in claim 1, characterized in that, The compensation capacitor network includes: the fourteenth MOSFET, the fifteenth MOSFET, the sixteenth MOSFET, and the seventeenth MOSFET; The first end of the compensation capacitor network is electrically connected to the source and drain of the fourteenth MOS transistor, the source and drain of the fifteenth MOS transistor, the source and drain of the sixteenth MOS transistor, and the source and drain of the seventeenth MOS transistor, respectively. The second end of the compensation capacitor network is electrically connected to the gate of the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, the gate of the sixteenth MOS transistor, and the gate of the seventeenth MOS transistor, respectively.

3. The slope compensation circuit for a step-down switching regulator as described in claim 1, characterized in that, The bias unit includes: a first current source, a zeroth MOSFET, a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, a second diode, a seventh resistor, and a NOT gate; The output terminal of the first current source is electrically connected to the gate and drain of the first MOS transistor, the drain of the zeroth MOS transistor, and the gate of the second MOS transistor. The ground terminal of the first current source is grounded. The source of the zeroth MOS transistor, the source of the first MOS transistor, and the source of the second MOS transistor are all connected to the power supply voltage. The gate of the zeroth MOS transistor and the input terminal of the NOT gate are both connected to the enable control signal. The drain of the second MOS transistor is electrically connected to the drain of the third MOS transistor. The gate of the third MOS transistor is electrically connected to the gate of the fourth MOS transistor, the drain of the fifth MOS transistor, and the gate of the sixth MOS transistor. The drain of the fourth MOS transistor is electrically connected to the source of the seventh MOS transistor. The drain of the seventh MOS transistor is electrically connected to the input terminal of the second diode, the drain and gate of the ninth MOS transistor, and the gate of the tenth MOS transistor. The gate of the seventh MOS transistor is connected to the input bias voltage. The gate of the seventh MOS transistor is also electrically connected to the gate of the eighth MOS transistor. The source of the ninth MOS transistor is electrically connected to the first terminal of the seventh resistor, the second terminal of the seventh resistor is electrically connected to the output terminal of the second diode, the source of the eighth MOS transistor is electrically connected to the drain of the sixth MOS transistor, the drain of the eighth MOS transistor is electrically connected to the drain of the tenth MOS transistor, and the gate of the fifth MOS transistor is electrically connected to the output terminal of the NOT gate. The sources of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all grounded; The source of the ninth MOS transistor is used as the first output terminal of the bias unit, the source of the tenth MOS transistor is used as the second output terminal of the bias unit, the drain of the tenth MOS transistor is used as the third output terminal of the bias unit, and the gate of the eighth MOS transistor is used as the fourth output terminal of the bias unit.

4. The slope compensation circuit for a step-down switching regulator as described in claim 3, characterized in that, The zeroth MOS transistor, the first MOS transistor, the second MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are all PMOS transistors; The third, fourth, fifth, sixth, seventh, and eighth MOS transistors are all NMOS transistors.

5. The slope compensation circuit for a step-down switching regulator as described in claim 1, characterized in that, The thirteenth MOS transistor is a sampling transistor, and the width-to-length ratio of the thirteenth MOS transistor is 1 / K times the width-to-length ratio of the power switching transistor, where K is a positive integer.

6. The slope compensation circuit for a step-down switching regulator as described in claim 1, characterized in that, The resistance value of the third resistor is the same as that of the fourth resistor.

7. A switching regulator, characterized in that, The switching regulator includes: a buck switching regulator and a slope compensation circuit for the buck switching regulator as described in any one of claims 1-6; The buck switching regulator includes: a bandgap reference module, a power switching transistor, and an error amplifier module; The slope compensation circuit includes: a current sampling compensation module and a comparator module; The bandgap reference module outputs a bias current, and the error amplifier module outputs an EA output signal. The first input terminal of the current sampling compensation module is connected to the bias current, the second input terminal of the current sampling compensation module is electrically connected to the gate of the power switch to receive the gate control signal, the second output terminal of the current sampling compensation module is electrically connected to the source of the power switch, and the inverting input terminal of the comparator module is connected to the EA output signal. The ramp compensation circuit is used to sample the gate control signal to generate a sampling current, and to superimpose the bias current and the sampling current to generate a ramp compensation current. The ramp compensation current is compared with the EA output signal, and a pulse width modulation signal is generated according to the comparison result to make the duty cycle of the output voltage / output current of the buck switching regulator converge.

8. The switching regulator as described in claim 7, characterized in that, The step-down switching regulator also includes: a voltage regulator; The voltage regulator is connected to the input voltage, and the voltage regulator outputs the power supply voltage to the bandgap reference module; The bandgap reference module also outputs an input bias voltage; And / or, The step-down switching regulator also includes: an enable control module; The first terminal of the first resistor in the slope compensation circuit outputs a peak current to the peak current detection unit in the enable control module, so that the slope compensation circuit is shut down when the peak current exceeds the rated value.

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