Chip test pattern generation method

Abstract

The present invention provides a method for generating a chip test pattern, comprising: obtaining test data associated with a first chip, wherein the first chip includes a plurality of first dies arranged in sequence, each first die belonging to one of a plurality of test numbers; assigning different preset color codes to the plurality of test numbers respectively; and assigning the color code of each first die to a corresponding preset color code according to the test number to which each first die belongs, so as to generate a general chip test pattern of the first chip.

Description

Technical Field

[0001] This invention relates to a method for generating chip test information, and more particularly to a method for generating chip test patterns. Background Technology

[0002] Engineers will examine the chip probing wafer map (CP map) of a specific wafer for different purposes. Common types of CP maps include single map, composite map, and bin-grouping map.

[0003] In a single-chip test diagram corresponding to a specific chip, the die belonging to a designated test number (Bin number) will be displayed in a user-specified color. Additionally, in a chip test number group diagram corresponding to a specific chip, dies belonging to different test numbers can be displayed in different colors.

[0004] Furthermore, different chips can generate corresponding single-chip test patterns for the same specified test number, and the single-chip test patterns of different chips can be superimposed into a composite chip test pattern.

[0005] Since different products have different definitions for the test number color (Bin color), it is known that it is common practice to pre-generate CP diagrams according to requirements and store them in a database.

[0006] Specifically, when implementing the above method, users can set the required test number colors in the system interface for drawing CP diagrams, and then generate the required CP diagrams through scheduling. If users set parameters for multiple sets of chip test number group diagrams at the same time, each corresponding chip test number group diagram needs to be stored on a server / database, thus occupying a large amount of storage space.

[0007] Furthermore, if the CP diagram is drawn using the aforementioned scheduling method, then when a user wants to change the color of the test number used, the system needs to redraw all CP diagrams already stored on the server / database. Moreover, if new single-chip test diagrams and / or composite chip test diagrams need to be generated, the system cannot generate these CP diagrams by processing existing ones; they must be redrawn entirely.

[0008] Furthermore, while there are known methods for real-time CP graph generation, these methods take a considerable amount of time to produce the final CP graph. Specifically, in this approach, the system accesses the raw CP data in the database in real time and uses it to generate the CP graph. However, if a user wants to view a large number of CP graphs simultaneously, the system will consume significant resources accessing the raw CP data in the database, thus substantially increasing the user's waiting time. Summary of the Invention

[0009] In view of this, the present invention provides a method for generating chip test patterns, which can be used to solve the above-mentioned technical problems.

[0010] The present invention provides a method for generating a chip test pattern, comprising: obtaining test data associated with a first chip, wherein the first chip includes a plurality of first dies arranged in sequence, each first die belonging to one of a plurality of test numbers; assigning different preset color codes to the plurality of test numbers respectively; and assigning the color code of each first die to a corresponding preset color code according to the test number to which each first die belongs, so as to generate a general chip test pattern of the first chip. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a chip test pattern generation apparatus according to an embodiment of the present invention.

[0012] Figure 2 This is a flowchart illustrating a chip test pattern generation method according to an embodiment of the present invention.

[0013] Figure 3 This is a flowchart illustrating the generation of a specified chip test pattern according to an embodiment of the present invention.

[0014] Figure 4 This is an application scenario diagram drawn according to the first embodiment of the present invention.

[0015] Figure 5 This is a chip test number group diagram illustrated according to the second embodiment of the present invention.

[0016] Figure 6 This is a flowchart illustrating the generation of a composite chip test pattern according to the third embodiment of the present invention.

[0017] Figure 7 This is a schematic diagram illustrating a composite chip test pattern according to an embodiment of the present invention.

[0018] [Symbol Explanation]

[0019] 100: Chip test pattern generation device

[0020] 102: Storage Circuit

[0021] 104: Processor

[0022] 410: General-purpose chip test diagram

[0023] 421: First Data Structure

[0024] 422: Second Data Structure

[0025] 422a, 422b: Areas

[0026] 430: Test diagram of the first designated chip

[0027] 500: Chip Test Number Group Diagram

[0028] 700: Composite Chip Test Diagram

[0029] S210~S230, S310~S350, S610~S650: Steps Detailed Implementation

[0030] Please refer to Figure 1 This is a schematic diagram of a chip test pattern generating apparatus according to an embodiment of the present invention. In different embodiments, the chip test pattern generating apparatus 100 may be implemented as various intelligent devices and / or computer devices, but is not limited thereto.

[0031] exist Figure 1 In the chip test pattern generation device 100, there are storage circuits 102 and processors 104. The storage circuit 102 is, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk or other similar devices or combinations thereof, and can be used to record multiple program codes or modules.

[0032] Processor 104 is coupled to storage circuit 102 and may be a general purpose processor, special purpose processor, conventional processor, digital signal processor, multiple microprocessors, one or more microprocessors incorporating a digital signal processor core, controller, microcontroller, application specific integrated circuit (ASIC), field programmable gate array (FPGA), any other type of integrated circuit, state machine, processor based on advanced RISC machine (ARM), and the like.

[0033] In an embodiment of the present invention, the processor 104 can access the modules and program code recorded in the storage circuit 102 to implement the chip test pattern generation method proposed in the present invention, the details of which are described below.

[0034] Please refer to Figure 2 This is a flowchart illustrating a chip test pattern generation method according to an embodiment of the present invention. The method of this embodiment can be derived from... Figure 1 The chip test pattern generation device 100 performs the following steps: Figure 1 Component description shown Figure 2 Details of each step.

[0035] In step S210, the processor 104 acquires test data associated with the first chip. In embodiments of the present invention, the first chip is, for example, any chip to generate a CP diagram, and this first chip may include, for example, a plurality of dies arranged in sequence (hereinafter referred to as first dies).

[0036] In one embodiment, the test data of the first chip may indicate the test number corresponding to each first die. For example, a portion of the first dies may correspond to test number 1 (represented by Bin1), another portion of the first dies may correspond to test number 3 (represented by Bin3), and so on.

[0037] In embodiments of the present invention, each first die belongs to one of a plurality of test numbers. For example, assuming there are K test numbers under consideration (represented by Bin1 to BinK, where K is a positive integer), any first die will belong to one of Bin1 to BinK, but this is not limited to this.

[0038] In step S220, the processor 104 assigns different preset color codes to the plurality of test numbers respectively.

[0039] In one embodiment, the processor 104 can arbitrarily assign different preset color codes to each test number according to the designer's needs. For example, if there are K test numbers under consideration, the processor 104 can arbitrarily assign K different preset color codes to the K test numbers respectively.

[0040] In one embodiment, the processor 104 may also determine the preset color code corresponding to each test number according to a specific principle. For ease of explanation, it is assumed that K is 256, but the implementation of the present invention is not limited to this. In this case, for the Xth test number (represented by BinX) among the K test numbers, the processor 104 may determine the preset color code according to "BinX:f(#RRGGBB)=(256 2 The formula ×int(BB)+256×int(GG)+int(RR))-1 is used to determine the corresponding preset color code.

[0041] In this case, the preset color codes corresponding to the 256 test numbers can be illustrated in Table 1 below.

[0042]

[0043] Table 1

[0044] In Table 1, the preset color code for Bin1 is, for example, "#010000"; the preset color code for Bin2 is, for example, "#020000"; the preset color code for Bin255 is, for example, "#FF0000"; and the preset color code for Bin256 is, for example, "#000100". For ease of explanation, it will be assumed below that the processor 104 determines / assigns the preset color code corresponding to each test number based on the contents of Table 1, but this is only an example and is not intended to limit the possible implementations of the present invention.

[0045] In step S230, the processor 104 assigns the color code of each first chip to a corresponding preset color code according to the test number to which each first chip belongs, so as to generate a general chip test pattern of the first chip.

[0046] For example, if a first die A belongs to Bin 1, the processor 104 can assign the color code of this first die A to a preset color code corresponding to Bin 1, such as #010000 in Table 1. If a first die B belongs to Bin 2, the processor 104 can assign the color code of this first die B to a preset color code corresponding to Bin 2, such as #020000 in Table 1. If a first die C belongs to Bin 255, the processor 104 can assign the color code of this first die C to a preset color code corresponding to Bin 255, such as #FF0000 in Table 1. If a first die D belongs to Bin 256, the processor 104 can assign the color code of this first die D to a preset color code corresponding to Bin 256, such as #000100 in Table 1.

[0047] Based on this, a general chip test pattern for the first chip can be generated accordingly. In the general chip test pattern of the first chip (its file format is, for example, JPG, PNF, or other commonly used image file formats), the color of each pixel located within the image area will be presented according to the color code of the corresponding first die.

[0048] For example, the color of pixel A in the image region corresponding to the first die A (which belongs to Bin1) can be represented by color code #010000. The color of pixel B in the image region corresponding to the first die B (which belongs to Bin2) can be represented by color code #020000. The color of pixel C in the image region corresponding to the first die C (which belongs to Bin255) can be represented by color code #FF0000. The color of a pixel in the image region located in the first die D (which belongs to Bin256) can be represented by color code #000100.

[0049] It should be understood that although the pixels corresponding to different test numbers (of the first chip) are presented as different colors in the general chip test pattern of the first chip, in the scenario illustrated in Table 1, since the preset color codes corresponding to different test numbers are not significantly different, the general chip test pattern of the first chip generated based on Table 1 may appear almost completely black to the human eye.

[0050] In other embodiments, if the preset color codes corresponding to different test numbers are designed to have significantly different appearances, the human eye can also distinguish the color differences between pixels corresponding to different test numbers (first chips) in the generated general chip test diagram of the first chip, but it is not limited to this.

[0051] In embodiments of the present invention, after generating a general chip test pattern for the first chip, the processor 104 may store it on a server / database. Since the general chip test pattern for the first chip can be easily stored on the server / database in a common image file format (e.g., JPG), it will occupy less storage space compared to known methods. Furthermore, since the process of generating the general chip test pattern for the first chip is relatively simple, it can also be completed with less computational resources.

[0052] In one embodiment, when a user wants to obtain a single-chip test pattern, a composite chip test pattern, and / or a chip test number group pattern associated with the first chip, the processor 104 only needs to perform simple processing on the general chip test pattern of the first chip to generate the CP pattern required by the user. Different embodiments will be described below.

[0053] Please refer to Figure 3 This is a flowchart illustrating the generation of a specified chip test pattern according to an embodiment of the present invention. In the first embodiment, assuming that a user wants to obtain a single-chip test pattern of a first chip for a certain test number, the processor 104 can correspondingly execute steps S310 to S350 to generate the corresponding single-chip test pattern as the first specified chip test pattern of the first chip.

[0054] In addition, in order to make Figure 3The concept is easier to understand, and will be supplemented below. Figure 4 For example, in which Figure 4 This is an application scenario diagram drawn according to the first embodiment of the present invention.

[0055] Specifically, in step S310, the processor 104 converts the color code of each first die in the general chip test diagram of the first chip back to the corresponding test number.

[0056] For example, processor 104 can convert the color code (e.g., #010000) of the first pixel A corresponding to pixel A into test number Bin1 according to Table 1. Additionally, processor 104 can convert the color code (e.g., #020000) of the first pixel B corresponding to pixel B into test number Bin2 according to Table 1. Furthermore, processor 104 can convert the color code (e.g., #FF0000) of the first pixel C corresponding to pixel C into test number Bin255 according to Table 1. Moreover, processor 104 can convert the color code (e.g., #000100) of the first pixel D corresponding to pixel D into test number Bin256 according to Table 1.

[0057] exist Figure 4 In this scenario, assuming the general chip test pattern of the first chip under consideration is general chip test pattern 410, the processor 104 can obtain the content shown in the first data structure 421. Figure 4 The first data structure 421 shown here corresponds only to a portion of the general chip test diagram 410.

[0058] In the first data structure 421, the horizontal axis (e.g., V100 to V105) corresponds to the horizontal coordinate in the general chip test pattern 410, and the vertical axis (e.g., H180 to H190) corresponds to the vertical coordinate in the general chip test pattern 410. In the first data structure 421, (Hx, Vy) represents the pixel at coordinates (x, y) in the general chip test pattern 410, and corresponds to each first die. The color code of (Hx, Vy) is, for example, derived from the color conversion of the pixel at coordinates (x, y) in the general chip test pattern 410.

[0059] For example, the color code (H180, V100) (i.e., #070000) is derived from the pixel color at coordinates (180, 100) in the general chip test diagram 410. The color code (H182, V101) (i.e., #1A0000) is derived from the pixel color at coordinates (182, 101) in the general chip test diagram 410. The color code (H186, V103) (i.e., #070000) is derived from the pixel color at coordinates (186, 103) in the general chip test diagram 410. The determination method for the color codes at other positions in the first data structure 421 can be deduced from the above description and will not be repeated here.

[0060] Subsequently, the processor 104 can convert the color codes in the first data structure 421 into corresponding test numbers to generate the second data structure 422. In the first embodiment, assuming that color codes #070000 and #1A0000 correspond to Bin6 and Bin25 respectively, the processor 104 can convert #070000 and #1A0000 in the first data structure 421 into 6 and 25 respectively, thereby generating the second data structure 422.

[0061] Next, in step S320, the processor 104 obtains a specified test number from the plurality of test numbers and obtains a specified color code corresponding to the specified test number.

[0062] In the first embodiment, assuming that the user wants to obtain a single-chip test pattern of the first chip for Bin1, and wants to mark the first die belonging to Bin1 with a certain specified color (e.g., dark brown) in this single-chip test pattern, the processor 104 can regard Bin1 as the specified test number and obtain the color code corresponding to the specified color as the specified color code.

[0063] In another embodiment, suppose a user wants to obtain a single-chip test pattern of the first chip for Bin256 and wants to mark the first die belonging to Bin256 with a specified color (e.g., dark brown) in this single-chip test pattern, then the processor 104 can regard Bin256 as the specified test number and obtain the color code corresponding to the specified color as the specified color code, but it is not limited to this.

[0064] In step S330, the processor 104 identifies a plurality of first designated dies belonging to a designated test number within the first die. Furthermore, in step S340, the processor 104 identifies a plurality of first other dies that do not belong to the designated test number within the first die.

[0065] For example, if the designated test number under consideration is Bin0, the processor 104 can identify the die belonging to Bin0 in the first die as the plurality of first designated dies, and consider all dies not belonging to Bin0 as the plurality of first other dies. As another example, if the designated test number under consideration is Bin256, the processor 104 can identify the die belonging to Bin256 in the first die as the plurality of first designated dies, and consider all dies not belonging to Bin256 as the plurality of first other dies, but this is not limited to these methods.

[0066] In one embodiment, the processor 104 can determine the plurality of first designated dies by finding the pixels corresponding to designated test numbers in the second data structure 420. For example, suppose that only region 422a in the second data structure 422 corresponds to Bin25 and only region 422b corresponds to Bin6.

[0067] In this case, if the designated test number under consideration is Bin25, the processor 104 may consider all the chips belonging to the pixels corresponding to region 422a as the first designated chip, and all the chips belonging to the pixels in other regions (e.g., region 422b) as the first other chips. As another example, if the designated test number under consideration is Bin6, the processor 104 may consider all the chips belonging to the pixels corresponding to region 422b as the first designated chip, and all the chips belonging to the pixels in other regions (e.g., region 422a) as the first other chips, but this is not a limitation.

[0068] Subsequently, in step S350, the processor 104 replaces the color code of each first designated die with a designated color code and replaces the color code of each first other die with a reference color code, so as to convert the general chip test pattern of the first chip into the first designated chip test pattern 430 of the first chip.

[0069] In one embodiment, assuming the designated test number under consideration is Bin25, the designated color code is a color code corresponding to dark brown, and the reference color code is a color code corresponding to light brown, the processor 104 may, for example, set the color code of each pixel in region 422a to a color code corresponding to dark brown, and set the color code of each pixel in other regions (e.g., region 422b) to a color code corresponding to light brown, to generate the corresponding first designated chip test pattern 430.

[0070] In another embodiment, assuming the designated test number under consideration is Bin6, the designated color code is a color code corresponding to dark brown, and the reference color code is a color code corresponding to light brown, the processor 104 may, for example, set the color code of each pixel in region 422b to a color code corresponding to dark brown, and set the color code of each pixel in other regions (e.g., region 422a) to a color code corresponding to light brown, to generate the corresponding first designated chip test pattern 430.

[0071] In an embodiment of the present invention, Figure 4 The first designated chip test diagram 430 shown is merely an illustrative representation of possible single-chip test patterns and is not intended to limit possible implementations of the present invention.

[0072] As can be seen from the above, the method of this embodiment of the invention can generate corresponding single-chip test patterns according to user needs through simple conversion. Therefore, the efficiency of generating single-chip test patterns can be improved without occupying excessive storage space.

[0073] In the second embodiment, if the user wants to obtain a chip test number group map of the first chip for multiple test numbers, the processor 104 can also execute steps S310 to S350 accordingly to generate a corresponding chip test number group map as the first designated chip test map of the first chip.

[0074] Specifically, in the second embodiment, the processor 104 may first execute step S310 to convert the color code of each first die in the general chip test diagram 410 of the first chip back to the corresponding test number. Details of step S310 can be found in the relevant description in the first embodiment, and will not be repeated here.

[0075] Subsequently, in step S320, the processor 104 obtains a specified test number from the plurality of test numbers and obtains a specified color code corresponding to the specified test number.

[0076] In the second embodiment, suppose a user wants to obtain a chip test number group diagram for Bin25 and Bin6 of the first chip, and wants to mark the first chips belonging to Bin25 and Bin6 in this chip test number group diagram with a first designated color (e.g., dark brown) and a second designated color (e.g., blue), respectively. In this case, the processor 104 can regard Bin25 and Bin6 as the first designated test number and the second designated test number, respectively, and obtain the color codes corresponding to the first designated color and the second designated color as the first designated color code and the second designated color code, respectively.

[0077] In step S330, the processor 104 identifies multiple first designated dies belonging to a specified test number within the first die. In step S340, the processor 104 identifies multiple first other dies that do not belong to the specified test number within the first die.

[0078] Continuing with the previous example, the processor 104 can identify the first die belonging to Bin25 and Bin6 in the first die as the first designated die under consideration, and the first die not belonging to Bin25 and Bin6 as the first other die under consideration, but it is not limited to this.

[0079] Subsequently, in step S350, the processor 104 replaces the color code of each first designated die with a designated color code and replaces the color code of each first other die with a reference color code, so as to convert the general chip test pattern 410 of the first chip into the first designated chip test pattern of the first chip.

[0080] In the second embodiment, the processor 104 may replace the color code of each first designated die belonging to the first designated test number with the first designated color code, and replace the color code of each first designated die belonging to the second designated test number with the second designated color code, wherein the first designated color code, the second designated color code, and the reference color code are all different from each other.

[0081] Continuing with the previous example, processor 104 can, for instance, replace the color code of the first designated die belonging to Bin 25 with a first designated color code (e.g., a color code corresponding to dark brown), and replace the color code of the first designated die belonging to Bin 6 with a second designated color code (e.g., a color code corresponding to blue). Furthermore, processor 104 can replace the color codes of each of the other first dies with reference color codes (e.g., a color code corresponding to light brown). Based on this, processor 104 can correspondingly convert the general chip test pattern 410 of the first chip into a first designated chip test pattern of the first chip, wherein this first designated chip test pattern is, for example, a group diagram of chip test numbers marked with dark brown for the first die corresponding to Bin 25, blue for the first die corresponding to Bin 6, and light brown for the first dies not belonging to Bin 25 and Bin 6, but is not limited to this.

[0082] In other embodiments, the user may specify more test numbers as the designated test numbers to be considered, and the processor 104 may generate a corresponding chip test number group map based on the mechanism described in the second embodiment.

[0083] Please refer to Figure 5 This is a chip test number group diagram illustrated according to the second embodiment of the present invention. Figure 5In this scenario, assuming the user specifies several test numbers as the designated test numbers and assigns a corresponding color code to each designated test number, the processor 104 can, for example, generate a corresponding chip test number group diagram 500 for the user's reference. In the chip test number group diagram 500, the first die corresponding to a certain designated test number will be marked with the corresponding designated color. This allows the user to observe the distribution of the first dies belonging to different designated test numbers.

[0084] As can be seen from the above, the method of this embodiment of the invention only requires a simple conversion to generate the corresponding chip test number group diagram according to the user's needs. Therefore, the efficiency of generating chip test number group diagrams can be improved without occupying too much storage space.

[0085] Please refer to Figure 6 This is a flowchart illustrating the generation of a composite chip test pattern according to a third embodiment of the present invention. In the third embodiment, assuming a user wants to obtain a composite chip test pattern of a first chip and a second chip for a specified test number, the processor 104 can execute accordingly. Figure 6 The method.

[0086] In the third embodiment, the processor 104 may execute steps S310 to S350 based on the teaching of the first embodiment to obtain the first designated chip test pattern of the first chip, and the relevant details can be referred to the description of the first embodiment, which will not be repeated here.

[0087] For ease of explanation, it is assumed below that the designated test number considered in the third embodiment is Bin25, but this is only used as an example and is not intended to limit the possible implementation of the present invention.

[0088] In this case, the first designated chip test pattern of the first chip can be understood as a single-chip test pattern corresponding to Bin25. In this single-chip test pattern, the first die corresponding to Bin25 will be marked with a designated color, while other first dies not corresponding to Bin25 will be marked with a reference color. For ease of explanation, it is assumed below that the designated color and the reference color used in the third embodiment are dark brown and light brown, respectively, but it is not limited to this. In this case, in the first designated chip test pattern of the first chip, the first die corresponding to Bin25 will be marked with dark brown, while other first dies not corresponding to Bin25 will be marked with light brown.

[0089] In addition, in the third embodiment, the processor 104 may further execute steps S610 to S650 to obtain the first designated chip test pattern of the second chip.

[0090] Specifically, in step S610, the processor 104 can obtain a general chip test pattern of the second chip. In the third embodiment, the processor 104 can pre-generate a general chip test pattern of the first chip based on the method used to generate the general chip test pattern (i.e., Figure 2 The method shown generates a general chip test pattern for the second chip and stores it on a server / database.

[0091] For example, the processor 104 may first obtain test data associated with the second chip (corresponding to step S210), wherein the second chip is, for example, any chip to generate a CP diagram, and the second chip may include, for example, a plurality of dies arranged in sequence (hereinafter referred to as second dies).

[0092] In one embodiment, the test data of the second chip may indicate the test number corresponding to each second die. For example, a portion of the second dies may correspond to test number 1 (represented by Bin1), another portion of the second dies may correspond to test number 3 (represented by Bin3), and so on.

[0093] Subsequently, the processor 104 can assign the color code of each second die to a corresponding preset color code according to the test number to which each second die belongs, so as to generate a general chip test pattern for the second chip (corresponding to step S230). For related details, please refer to... Figure 2 The description of the embodiments will not be repeated here.

[0094] Subsequently, when the user wants to generate a CP diagram associated with the second chip, the processor 104 can obtain a general chip test diagram of the second chip from the server / database in step S610, but it is not limited to this.

[0095] In step S620, the processor 104 can convert the color code of each second die in the general chip test pattern of the second chip back to the corresponding test number.

[0096] For example, the processor 104 can convert the color code of each second chip into a corresponding test number according to Table 1. In this case, the processor 104 can accordingly obtain the test number of each pixel in the image area corresponding to each second chip.

[0097] Based on this, processor 104 can generate similar outputs to the second chip. Figure 4 Another second data structure in the second data structure 422.

[0098] In step S630, the processor 104 can identify a plurality of second specified dies belonging to a specified test number from the plurality of second dies, and identify a plurality of second other dies that do not belong to the specified test number from the plurality of second dies.

[0099] Continuing with the previous example, if the specified test number is assumed to be Bin25, the processor 104 can identify the grains belonging to Bin25 from the second grains as the plurality of second specified grains, and regard all grains not belonging to Bin25 as the plurality of second other grains.

[0100] In one embodiment, the processor 104 can determine the plurality of second designated dies by finding the pixel corresponding to the designated test number in a second data structure corresponding to the second die.

[0101] For ease of explanation, the following assumption is made that the second data structure corresponding to the second grain also has Figure 4 The state of the second data structure 422. In this case, if the designated test number under consideration is Bin25, the processor 104 can regard the chips to which the pixels corresponding to region 422a belong as the second designated chips, and regard the chips to which the pixels of other regions (e.g., region 422b) belong as the second other chips.

[0102] Subsequently, in step S640, the processor 104 may replace the color code of each second specified die belonging to the specified test number with the specified color code, and replace the color code of each second other die not belonging to the specified test number with the reference color code, so as to convert the general chip test pattern of the second chip into the first specified chip test pattern of the second chip.

[0103] In the third embodiment, since the specified color and the reference color are assumed to be dark brown and light brown respectively, the specified color code can be a color code corresponding to dark brown, and the reference color code can be a color code corresponding to light brown. Based on this, the processor 104 can, for example, set the color code of each pixel in region 422a of the second data structure corresponding to the second chip to a color code corresponding to dark brown, and set the color code of each pixel in other regions (e.g., region 422b) to a color code corresponding to light brown, to generate the first specified chip test pattern of the second chip.

[0104] In this context, the first designated chip test pattern for the second chip can be understood as a single-chip test pattern corresponding to Bin25. In this single-chip test pattern, the second die corresponding to Bin25 will be marked with a designated color, while other second dies not corresponding to Bin25 will be marked with a reference color. For example, in the first designated chip test pattern for the second chip, the second die corresponding to Bin25 will be marked dark brown, while other second dies not corresponding to Bin25 will be marked light brown, but this is not a limitation.

[0105] Subsequently, in step S650, the processor 104 can superimpose the first designated chip test pattern of the first chip and the first designated chip test pattern of the second chip into a composite chip test pattern.

[0106] As can be seen from the above, the method of this embodiment only needs to generate single-chip test patterns for different chips according to the user-specified test number (e.g., Bin25), and then superimpose the single-chip test patterns of different chips to form the required composite chip test pattern. Therefore, the efficiency of generating composite chip test patterns can be improved without occupying too much storage space.

[0107] In other embodiments, besides overlaying the single-chip test patterns of the first and second chips into a composite chip test pattern, the processor 104 can also generate single-chip test patterns corresponding to specified test numbers (e.g., Bin 25) for other chips as needed by the user, and overlay the single-chip test patterns corresponding to each chip into a composite chip test pattern. In this composite chip test pattern, the user can observe the color changes to see which locations on these chips have a higher failure rate for the dies belonging to the specified test numbers, but this is not limited to this.

[0108] Please refer to Figure 7 This is a schematic diagram illustrating a composite chip test pattern according to an embodiment of the present invention. Figure 7 In this context, the processor 104 can, for example, first generate corresponding single-chip test patterns for multiple chips based on a specified test number, and then overlay the single-chip test patterns of each chip into a composite image. Figure 7 The composite chip test diagram shown is 700.

[0109] In the composite chip test diagram 700, some darker-colored chips can be seen in the dashed area. Based on this, the user can determine that the chip with the specified test number is more prone to failure at the location corresponding to the dashed area, but this is not an isolated case.

[0110] In summary, the embodiments of the present invention can generate a corresponding general chip test pattern after obtaining the chip's test data. Since this general chip test pattern can be easily stored on a server / database in a common image file format (e.g., JPG), it will temporarily use less storage space compared to known methods. Furthermore, since the process of generating the general chip test pattern is relatively simple, it can also be completed with less computational resources.

[0111] Furthermore, embodiments of the present invention can generate single-chip test patterns and / or chip test number group diagrams corresponding to the chip according to the user's needs through simple conversion. Therefore, the efficiency of generating single-chip test patterns and / or chip test number group diagrams can be improved without occupying excessive storage space.

[0112] Furthermore, embodiments of the present invention can also easily obtain single-chip test patterns of multiple chips corresponding to specified test numbers, and then overlay these single-chip test patterns into a composite chip test pattern corresponding to the specified test number. This improves the efficiency of generating composite chip test patterns.

[0113] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A method for generating a chip test pattern, comprising: Obtain test data associated with a first chip, wherein the first chip comprises a plurality of first dies arranged in sequence, and each first die belongs to one of a plurality of test numbers; Each of these test numbers is assigned a different set of preset color codes; Based on the test number to which each first die belongs, the color code of each first die is assigned to the corresponding preset color code to generate a general chip test pattern for the first chip; Convert the color code of each first die in the general chip test diagram of the first chip back to the corresponding test number; Obtain at least one specified test number from these test numbers, and obtain at least one specified color code corresponding to the at least one specified test number; Identify among these first grains a plurality of first specified grains belonging to the at least one specified test number; Identify, among these first grains, multiple first other grains that do not belong to the at least one specified test number; as well as The color code of each of the first designated chips is replaced with the at least one designated color code, and the color code of each of the first other chips is replaced with a reference color code, so as to convert the general chip test pattern of the first chip into the first designated chip test pattern of the first chip.

2. The method of claim 1, wherein the at least one designated test number includes a first designated test number, the at least one designated color code is a first designated color code corresponding to the first designated test number, and the step of replacing the color code of each of the first designated wafers with the at least one designated color code includes: The color code of each of the first specified grains is replaced with the first specified color code, wherein the first specified color code is different from the reference color code.

3. The method of claim 1, wherein the at least one designated test number includes a first designated test number and a second designated test number, the at least one designated color code includes a first designated color code and a second designated color code, the first designated color code corresponds to the first designated test number, the second designated color code corresponds to the second designated test number, and the step of replacing the preset color code of each of the first designated chips with the at least one designated color code includes: Replace the color code of each of the first specified grains belonging to the first specified test number with the first specified color code; as well as The color code of each of the first specified chips belonging to the second specified test number is replaced with the second specified color code, wherein the first specified color code, the second specified color code, and the reference color code are all different from each other.

4. The method of claim 2, further comprising: Obtain a general chip test pattern for the second chip, which includes multiple second dies arranged in sequence, each of the second dies belonging to one of these test numbers, and the color code of each second die corresponding to the preset color code of the test number to which it belongs; The color code of each second die in the general chip test diagram of the second chip is converted back to the corresponding test number; From these second grains, identify a plurality of second designated grains that belong to the first designated test number, and from these second grains, identify a plurality of second other grains that do not belong to the first designated test number; The color code of each of the second specified chips belonging to the first specified test number is replaced with the first specified color code, and the color code of each of the other second chips that do not belong to the first specified test number is replaced with the reference color code, so as to convert the general chip test pattern of the second chip into the first specified chip test pattern of the second chip. as well as The first designated chip test pattern of the first chip and the first designated chip test pattern of the second chip are superimposed to form a composite chip test pattern.

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