A gate driving circuit and a display panel

Abstract

The application discloses a kind of gate drive circuit and display panel.Gate drive circuit includes first control module, output pull-up module, output pull-down module and second control module;In reset stage, clock signal is low potential, starting signal keeps high potential, sensing output signal keeps low potential;In the output stage after reset stage, clock signal becomes high potential, starting signal keeps high potential, sensing output signal changes from low potential to high potential;In the maintenance stage after output stage, clock signal turns to low potential, starting signal changes to low potential, sensing output signal maintains high potential.Through the application, only one group of clock signal is needed to reduce signal wiring and reduce the frame of display panel;And based on clock signal, the control step length of starting signal and sensing output signal is only two pulse widths of clock signal, to reduce the control step length of sensing output signal, which is beneficial to compensate the compensation effect of accurate control circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display panel. Background Technology

[0002] In the internal compensation circuit of some pixels of the display panel, due to the requirement of compensation accuracy, the gate drive circuit is required to output a pulse signal with adjustable width in order to achieve the purpose of compensation and adjustment of the display panel.

[0003] Currently, methods for achieving adjustable pulse width mainly utilize two types of control signals. Since the control signals must have a step-by-step transmission capability, two sets of clock signals are needed to generate two sets of cascading control signals. This results in numerous signal traces, leading to an increase in the bezel size of the display panel. On the other hand, the adjustable step size of the output pulse signal is relatively large, which is not conducive to precise control of the compensation effect. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a gate driving circuit and display panel that only requires one set of clock signals, which can reduce signal traces, reduce the bezel of the display panel, and reduce the control step size of the sensing output signal, which is conducive to the compensation circuit to accurately control the compensation effect.

[0005] To achieve the above objectives, the present invention first provides a gate driving circuit, comprising:

[0006] The first control module is connected to the first node and receives a clock signal, a start signal, and a first low-potential signal to control the potential of the first node.

[0007] The output pull-up module is connected to the first node and connected to a high-potential signal. It is used to output and pull up the potential of the sensing output signal. The starting signal is the previous level signal of the sensing output signal. Both the starting signal and the sensing output signal are pulse signals.

[0008] The output pull-down module is connected to the first control module and the second node, and is connected to the second low-potential signal to pull down the potential of the sensing output signal;

[0009] The second control module is connected to the first and second nodes and receives a high-potential signal, a transmission signal, and a start signal to maintain the low potential of the second node.

[0010] During the reset phase, the clock signal is at a low level, the start signal remains at a high level, the first node is at a low level, the second node is at a high level, and the sensing output signal remains at a low level.

[0011] In the output phase after the reset phase, the clock signal goes high, the start signal remains high, the second node goes low, the first node goes high, and the sensing output signal changes from low to high.

[0012] In the maintenance phase following the output phase, the clock signal goes low, the start signal goes low, the first node remains high, the second node remains low, and the sensing output signal remains high, so as to realize the step-by-step transmission of the start signal and the sensing output signal. The control step size of the step-by-step transmission is two pulse widths of the clock signal.

[0013] Optionally, the second control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first storage capacitor; the gate and first electrode of the first transistor, and the gate of the second transistor are all connected to a transmission signal; the first electrode of the second transistor and the second electrode of the first transistor are connected to a third node, and the second electrode of the second transistor and the gate of the third transistor are connected to a fourth node; the first electrode of the third transistor is connected to a high-potential signal, and the second electrode is connected to the third node; one end of the first storage capacitor is connected to the fourth node, and the other end is connected to a high-potential signal; the gate of the fourth transistor is connected to the fourth node, the first electrode is connected to a high-potential signal, and the second electrode is connected to the second node; the gate of the fifth transistor is connected to the first node, the first electrode is connected to a first low-potential signal, and the second electrode is connected to the second node; the gates of the sixth transistor and the seventh transistor are simultaneously connected to a start signal, the first electrode of the sixth transistor is connected to the fourth node, the second electrode of the sixth transistor and the first electrode of the seventh transistor are connected to the third node, and the second electrode of the seventh transistor is connected to the first low-potential signal.

[0014] Optionally, the second control module further includes an eighth transistor, the gate of which is connected to the gates of the sixth transistor and the seventh transistor and is simultaneously connected to a start signal. The first electrode of the eighth transistor is connected to a first low-potential signal, and the second electrode is connected to a second node.

[0015] Optionally, the second control module further includes a ninth transistor and a tenth transistor; the gate of the ninth transistor is connected to a clock signal, the first electrode is connected to the gates of the sixth transistor and the seventh transistor, and is simultaneously connected to a start signal, and the second electrode is connected to the gate of the tenth transistor; the first electrode of the tenth transistor is connected to a first low-potential signal, and the second electrode is connected to the second node.

[0016] Optionally, the first control module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second storage capacitor; the gate of the eleventh transistor is connected to a clock signal, the first electrode is connected to a start signal, and the second electrode is connected to a first node; the gates of the twelfth and thirteenth transistors are simultaneously connected to a second node, the first electrode of the twelfth transistor is connected to the first node, the second electrode and the first electrode of the thirteenth transistor are connected to a third node, and the second electrode of the thirteenth transistor is connected to a first low-potential signal; the gate of the fourteenth transistor is connected to the first node, the first electrode is connected to a high-potential signal, and the second electrode is connected to the third node; one end of the second storage capacitor is connected to the first node, and the other end is connected to a sensing output signal.

[0017] Optionally, the output pull-up module includes a fifteenth transistor, the gate of which is connected to the first node, the first electrode is connected to a high-potential signal, and the second electrode is connected to a sensing output signal.

[0018] Optionally, the output pull-down module includes a sixteenth transistor, the gate of which is connected to a second node, the first electrode is connected to a second low-potential signal, and the second electrode is connected to a sensing output signal.

[0019] Optionally, in the termination phase after the maintenance phase, the starting signal is at a low potential, the potential of the first node is pulled low, the transmission signal is at a high potential, the potential of the second node is pulled high, the output pull-down module is turned on, and the sensing output signal becomes low.

[0020] Optionally, the clock signal includes a positive clock signal or an inverted clock signal, wherein the positive clock signal and the inverted clock signal have opposite potentials, and the duty cycle of the clock signal is 40% to 60%.

[0021] The present invention also provides a display panel, including an array substrate and the aforementioned gate driving circuit, wherein the gate driving circuit is connected to the array substrate.

[0022] Compared with the prior art, the beneficial effects of the present invention include: the gate drive circuit of the present invention includes a first control module, an output pull-up module, an output pull-down module, and a second control module; in the reset phase, the clock signal is at a low potential, the start signal remains at a high potential, the first node is at a low potential, the second node is at a high potential, and the sensed output signal remains at a low potential; in the output phase after the reset phase, the clock signal becomes at a high potential, the start signal remains at a high potential, the second node becomes at a low potential, the first node becomes at a high potential, and the sensed output signal changes from a low potential to a high potential; in the maintenance phase after the output phase, the clock signal becomes at a low potential, the start signal becomes at a low potential, the first node remains at a high potential, the second node remains at a low potential, and the sensed output signal remains at a high potential, so as to realize the step-by-step transmission of the start signal and the sensed output signal, and the control step size of the step-by-step transmission is two pulse widths of the clock signal. With the gate driving circuit of the present invention, only one set of clock signals is needed to reduce signal traces and reduce the bezel of the display panel; and, based on the clock signal, the control step size for the step-by-step transmission of the start signal and the sensing output signal is only two pulse widths of the clock signal. This reduces the control step size of the sensing output signal, which is beneficial for the compensation circuit to accurately control the compensation effect. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the gate drive circuit in an embodiment of the present invention. Figure 1 ;

[0025] Figure 2 This is a schematic diagram of the gate drive circuit in an embodiment of the present invention. Figure 2 ;

[0026] Figure 3 This is a schematic diagram of the gate drive circuit in an embodiment of the present invention. Figure 3 ;

[0027] Figure 4 This is a signal timing diagram of the gate drive circuit in an embodiment of the present invention. Detailed Implementation

[0028] The following descriptions of the embodiments are with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. In the description of the invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the module or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] This invention provides a gate driving circuit, such as... Figure 1 As shown, it includes a first control module 100, an output pull-up module 200, an output pull-down module 300, and a second control module 400. Wherein:

[0031] The first control module 100 is connected to the first node Q and receives a clock signal CK / XCK, a start signal STV and a first low potential signal VGL1 to control the potential of the first node Q.

[0032] The output pull-up module 200 is connected to the first node Q and connected to a high-potential signal VGH, which is used to output and pull up the potential of the sensing output signal Sense[n]. The start signal STV is the previous level signal Sense[n-1] of the sensing output signal Sense[n]. The start signal STV and the sensing output signal Sense[n] are pulse signals.

[0033] The output pull-down module 300 is connected to the first control module 100 and the second node QB, and is connected to the second low potential VGL2 signal to pull down the potential of the sensing output signal Sense[n].

[0034] The second control module 400 is connected to the first node Q and the second node QB, and is connected to the high-potential signal VGH, the cascade signal Cout and the start signal STV to maintain the low potential of the second node QB.

[0035] like Figure 4 As shown, during the reset phase, the clock signal CK / XCK is at a low level, the start signal STV remains at a high level, the first node Q is at a low level, the second node QB is at a high level, and the sense output signal Sense[n] remains at a low level.

[0036] In the output phase after the reset phase, the clock signal CK / XCK goes high, the start signal STV remains high, the second node QB goes low, the first node Q goes high, and the sense output signal Sense[n] goes from low to high.

[0037] During the maintenance phase following the output phase, the clock signal CK / XCK goes low, the start signal STV goes low, the first node Q remains high, the second node QB remains low, and the sensing output signal Sense[n] remains high, so as to realize the step-by-step transmission of the start signal STV / Sense[n-1] and the sensing output signal Sense[n]. The step size of the step-by-step transmission is two pulse widths of the clock signal CK / XCK.

[0038] With the gate drive circuit of this embodiment, only one set of pulse clock signals CK / XCK is needed, thereby reducing signal traces and shrinking the bezel of the display panel. Furthermore, based on the pulses of the clock signal CK / XCK, when transitioning from the reset phase to the output phase, the start signal STV remains high, and the sense output signal Sense[n] changes from low to high; when transitioning from the output phase to the sustain phase, the start signal STV changes from high to low, and the sense output signal Sense[n] remains high. Thus, the step size for progressively controlling the start signal STV and the sense output signal Sense[n] based on the clock signal CK / XCK is only two pulse widths of the clock signal CK / XCK (one pulse width H in the reset phase and one pulse width H in the sustain phase). This reduction in the control step size of the start signal STV and the sense output signal Sense[n] facilitates precise control of the compensation effect by the compensation circuit.

[0039] In this embodiment, the stage transmission signal Cout, the clock signal CK / XCK, the sense output signal Sense[n], and the start signal STV are all wide pulse signals. The stage transmission signal Cout can be generated by a conventional gate scan control circuit. The clock signal CK / XCK includes a positive clock signal CK or an inverted clock signal XCK. Depending on the control requirements, either the positive clock signal CK or the inverted clock signal XCK can be selected as the input. The potentials of the positive clock signal CK and the inverted clock signal XCK are opposite. The duty cycle of the clock signal CK / XCK is 40% to 60%, and in this embodiment, the duty cycle is preferably 50%. The first low-potential signal VGL1 and the second low-potential signal VGL2 can be the same low-potential signal or different low-potential signals. The first low-potential signal VGL1 and the second low-potential signal VGL2 can be signals below a set potential, and the high-potential signal VGH can be a signal above a set potential.

[0040] In one embodiment, the second control module 400 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first storage capacitor C1; the gate and first electrode of the first transistor T1, and the gate of the second transistor T2 are all connected to a transmission signal Cout; the first electrode of the second transistor T2 and the second electrode of the first transistor T1 are connected to a third node N, and the gate of the third transistor T3 is connected to a fourth node M; the first electrode of the third transistor T3 is connected to a high-potential signal VGH, and the second electrode is connected to the third node N; the first storage capacitor C1... One end of the transistor is connected to the fourth node M, and the other end is connected to a high-potential signal VGH; the gate of the fourth transistor T4 is connected to the fourth node M, the first electrode is connected to the high-potential signal VGH, and the second electrode is connected to the second node QB; the gate of the fifth transistor T5 is connected to the first node Q, the first electrode is connected to the first low-potential signal VGL1, and the second electrode is connected to the second node QB; the gates of the sixth transistor T6 and the seventh transistor T7 are simultaneously connected to the start signal STV, the first electrode of the sixth transistor T6 is connected to the fourth node M, the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 are connected to the third node N, and the second electrode of the seventh transistor T7 is connected to the first low-potential signal VGL1.

[0041] Based on the above circuit structure, the first storage capacitor C1 can be used to store the potential of the fourth node M. When the transmission signal Cout is high, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, and the fourth node M is charged with a high potential to keep the fourth transistor T4 continuously turned on. The high potential signal VGH is transmitted to the second node QB through the fourth transistor T4, and the potential of the second node QB is pulled high.

[0042] When the start signal STV is high, the sixth transistor T6 and the seventh transistor T7 are turned on, the fourth node M is connected to the first low-level signal VGL1, and the discharge of the fourth node M is completed. The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned off.

[0043] When the first node Q is at a high potential, the fifth transistor T5 is turned on, and the first low potential signal VGL1 is transmitted to the second node QB through the fifth transistor T5, causing the potential of the second node QB to be pulled low.

[0044] In one embodiment, such as Figure 2 As shown, the second control module 400 also includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the gate of the sixth transistor T6 and the gate of the seventh transistor T7, and is simultaneously connected to the start signal STV. The first electrode of the eighth transistor T8 is connected to the first low potential signal VGL1, and the second electrode is connected to the second node QB.

[0045] Based on the above circuit structure, when the initial signal STV is high, the eighth transistor T8 turns on, and the first low-level signal VGL1 is transmitted to the second node QB through the eighth transistor T8, thus pulling down the potential of the second node QB. Simultaneously, when the first node Q is high, the fifth transistor T5 turns on, and the first low-level signal VGL1 is transmitted to the second node QB through the fifth transistor T5, so that when the first node Q is high, the second node QB remains at a low potential.

[0046] In one embodiment, such as Figure 3 As shown, the second control module 400 also includes a ninth transistor T9 and a tenth transistor T10; the gate of the ninth transistor T9 is connected to the clock signal CK / XCK, the first electrode is connected to the gate of the sixth transistor T6 and the gate of the seventh transistor T7, and is simultaneously connected to the start signal STV, and the second electrode is connected to the gate of the tenth transistor T10; the first electrode of the tenth transistor T10 is connected to the first low potential signal VGL1, and the second electrode is connected to the second node QB.

[0047] Based on the above circuit structure, when the clock signal CK / XCK is at a high level, the ninth transistor T9 turns on. At this time, the start signal STV is at a high level, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 turn on. The first low-level signal VGL1 is transmitted to the second node QB through the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10, so that the potential of the second node QB is pulled down.

[0048] In one embodiment, the first control module 100 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a second storage capacitor C2; the gate of the eleventh transistor T11 is connected to a clock signal CK / XCK, the first electrode is connected to a start signal STV, and the second electrode is connected to a first node Q; the gates of the twelfth transistor T12 and the thirteenth transistor T13 are simultaneously connected to a second node QB, the first electrode of the twelfth transistor T12 is connected to the first node Q, the second electrode and the first electrode of the thirteenth transistor T13 are connected to a third node N, and the second electrode of the thirteenth transistor T13 is connected to a first low-potential signal VGL1; the gate of the fourteenth transistor T14 is connected to the first node Q, the first electrode is connected to a high-potential signal VGH, and the second electrode is connected to the third node N; one end of the second storage capacitor C2 is connected to the first node Q, and the other end is connected to a sensing output signal Sense[n].

[0049] Based on the above circuit structure, when the clock signal CK / XCK is at a high level, the eleventh transistor T11 is turned on, and the start signal STV is transmitted to the first node Q through the eleventh transistor T11. When the start signal STV is at a high level, the first node Q is at a high level, the fourteenth transistor T14 and the output pull-up module 200 are turned on, the twelfth transistor T12 is also connected to the first node Q, and under the action of the second storage capacitor C2, the first node Q is maintained at a high level.

[0050] In one embodiment, the output pull-up module 200 includes a fifteenth transistor T15, the gate of which is connected to a first node Q, the first electrode is connected to a high-potential signal VGH, and the second electrode is connected to a sensing output signal Sense[n].

[0051] Based on the above circuit structure, when the first node Q is at a high potential, the fifteenth transistor T15 is turned on, and the first electrode of the fifteenth transistor T15 is connected to the high potential signal VGH, which pulls the potential of the sensing output signal Sense[n] of the second electrode high.

[0052] In one embodiment, the output pull-down module 300 includes a sixteenth transistor T16, the gate of the sixteenth transistor T16 is connected to the second node QB, the first electrode is connected to the second low-potential signal VGL2, and the second electrode is connected to the sensing output signal Sense[n].

[0053] Based on the above circuit structure, when the start signal STV and the clock signal CK / XCK are at a low level and the stage transmission signal Cout is at a high level, the first transistor T1 is turned on. When the start signal STV and the clock signal CK / XCK are at a low level and the stage transmission signal Cout is at a high level, the eighth transistor T8, or the ninth transistor T9 and the tenth transistor T10 are turned off. The second node QB is connected to the high-level signal VGH, the sixteenth transistor T16 is turned on, and the second low-level signal VGL2 is supplied. The potential of the output sensing signal is pulled down.

[0054] In one embodiment, during the termination phase following the maintenance phase, the start signal STV is at a low potential, the potential of the first node Q is pulled low, the cascade signal Cout is at a high potential, the potential of the second node QB is pulled high, the output pull-down module 300 is turned on, and the sensing output signal Sense[n] becomes low.

[0055] In this embodiment, the first transistor T1 to the sixteenth transistor T16 can all be thin-film transistors, specifically low-temperature polycrystalline silicon thin-film transistors, oxide semiconductor thin-film transistors, or amorphous silicon thin-film transistors.

[0056] Among them, amorphous silicon thin-film transistors (a-Si TFTs) are widely used thin-film transistors. They have advantages such as mature and stable technology, low driving voltage, low power consumption, and low cost, making them suitable for mass production.

[0057] Low-temperature poly-silicon thin film transistors (LTPS-TFTs) have outstanding advantages such as high carrier mobility and small size, and are a key technology for developing low-power, highly integrated display panels.

[0058] Oxide thin-film transistors (OTFTs) have a carrier concentration approximately ten times that of amorphous silicon (ASS) thin-film transistors (TFTs), and a carrier mobility 20-30 times higher. Therefore, OTFTs can significantly improve the charge-discharge rate of pixel electrodes, increasing pixel response speed and enabling faster refresh rates. OTFTs are well-suited for applications requiring fast response and high current, such as high-frequency, high-resolution, large-size displays and organic light-emitting diode (OLED) displays. OTFTs are increasingly becoming semiconductor components used in next-generation LCD and LED display devices.

[0059] In this embodiment, of the first electrode and the second electrode of each transistor, one is the source and the other is the drain.

[0060] The gate drive circuit in this embodiment is configured with four operating stages according to the signal timing sequence, namely, reset stage t1, output stage t2, sustain stage t3, and termination stage t4. For example... Figure 4 As shown, the specific signal timing is as follows:

[0061] 1) Reset phase t1: Clock signal CK / XCK is low, start signal STV / Sense[n-1] is high, sense output signal Sense[n] is low, transmission signal Cout is low, first node Q is low, second node QB is high, and fourth node M is low.

[0062] 2) Output stage t2: Clock signal CK / XCK goes high, start signal STV / Sense[n-1] remains high, stage signal Cout remains low, first node Q goes high, second node QB goes low, fourth node M remains low, sixteenth transistor T16 turns off, fifteenth transistor T15 turns on, and sense output signal Sense[n] changes from low to high. The gate drive circuit starts outputting a high-level sense output signal Sense[n].

[0063] 3) Maintenance phase t3: The clock signal CK / XCK turns low (off state), the start signal STV / Sense[n-1] turns low, the stage signal Cout remains low, the second capacitor maintains the high potential of the first node Q, the second node QB remains low, the sixteenth transistor T16 is turned off, and the sensing output signal Sense[n] remains high.

[0064] 4) Termination stage t4: Clock signal CK / XCK and start signal STV / Sense[n-1] go low, stage signal Cout goes high, first node Q is pulled down to low, second node QB is pulled up to high, sixteenth transistor T16 turns on, sense output signal Sense[n] goes low, and wide pulse signal output of gate drive circuit terminates.

[0065] Based on the gate driving circuit described above in this embodiment, only one set of pulse clock signals CK / XCK is needed to reduce signal traces and shrink the bezel of the display panel. Furthermore, based on the pulses of the clock signal CK / XCK, when transitioning from the reset phase to the output phase, the start signal STV remains at a high potential, and the sensing output signal Sense[n] changes from a low potential to a high potential; when transitioning from the output phase to the sustain phase, the start signal STV changes from a high potential to a low potential, and the sensing output signal Sense[n] remains at a high potential. Thus, the step size for progressively controlling the start signal STV and the sensing output signal Sense[n] based on the clock signal CK / XCK is only two pulse widths of the clock signal CK / XCK (one pulse width in the reset phase and one pulse width in the sustain phase). This reduces the control step size of the start signal STV / Sense[n-1] and the sensing output signal Sense[n], facilitating precise control of the compensation effect by the compensation circuit.

[0066] This invention also provides a display panel, including an array substrate and a gate driving circuit provided in the above embodiments, wherein the gate driving circuit is connected to the array substrate.

[0067] The gate drive circuit of this embodiment includes a first control module 100, an output pull-up module 200, an output pull-down module 300, and a second control module 400. Wherein:

[0068] The first control module 100 is connected to the first node Q and receives a clock signal CK / XCK, a start signal STV and a first low potential signal VGL1 to control the potential of the first node Q.

[0069] The output pull-up module 200 is connected to the first node Q and connected to a high-potential signal VGH, which is used to output and pull up the potential of the sensing output signal Sense[n]. The start signal STV is the previous level signal Sense[n-1] of the sensing output signal Sense[n]. The start signal STV and the sensing output signal Sense[n] are pulse signals.

[0070] The output pull-down module 300 is connected to the first control module 100 and the second node QB, and is connected to the second low potential signal to pull down the potential of the sensing output signal Sense[n].

[0071] The second control module 400 is connected to the first node Q and the second node QB, and is connected to the high-potential signal VGH, the cascade signal Cout and the start signal STV to maintain the low potential of the second node QB.

[0072] During the reset phase, the clock signal CK / XCK is low, the start signal STV is high, the first node Q is low, the second node QB is high, and the sense output signal Sense[n] is low.

[0073] In the output phase after the reset phase, the clock signal CK / XCK goes high, the start signal STV remains high, the second node QB goes low, the first node Q goes high, and the sense output signal Sense[n] goes from low to high.

[0074] During the maintenance phase following the output phase, the clock signal CK / XCK goes low, the start signal STV goes low, the first node Q remains high, the second node QB remains low, and the sensing output signal Sense[n] remains high, so as to realize the step-by-step transmission of the start signal STV and the sensing output signal Sense[n]. The step size of the step-by-step transmission is two pulse widths of the clock signal CK / XCK.

[0075] With the gate drive circuit of this embodiment, only one set of pulse clock signals CK / XCK is needed, thereby reducing signal traces and shrinking the bezel of the display panel. Furthermore, based on the pulses of the clock signal CK / XCK, when transitioning from the reset phase to the output phase, the start signal STV remains high, and the sense output signal Sense[n] changes from low to high; when transitioning from the output phase to the sustain phase, the start signal STV changes from high to low, and the sense output signal Sense[n] remains high. Thus, the step size for progressively controlling the start signal STV and the sense output signal Sense[n] based on the clock signal CK / XCK is only two pulse widths of the clock signal CK / XCK (one pulse width in the reset phase and one pulse width in the sustain phase). This reduction in the control step size of the start signal STV and the sense output signal Sense[n] facilitates precise control of the compensation effect by the compensation circuit.

[0076] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, include: The first control module is connected to the first node and receives a clock signal, a start signal, and a first low-potential signal to control the potential of the first node. An output pull-up module is connected to the first node and connected to a high-potential signal for outputting and pulling up the potential of the sensing output signal. The starting signal is the previous level signal of the sensing output signal, and both the starting signal and the sensing output signal are pulse signals. The output pull-down module is connected to the first control module and the second node, and is connected to a second low-potential signal to pull down the potential of the sensing output signal; The second control module is connected to the first node and the second node, and is connected to the high-potential signal, the transmission signal and the start signal, in order to maintain the low potential of the second node. During the reset phase, the clock signal is at a low level, the start signal remains at a high level, the first node is at a low level, the second node is at a high level, and the sensing output signal remains at a low level. In the output phase following the reset phase, the clock signal goes high, the start signal remains high, the second node goes low, the first node goes high, and the sensing output signal changes from low to high. In the maintenance phase following the output phase, the clock signal goes low, the start signal goes low, the first node remains high, the second node remains low, and the sensing output signal remains high, so as to realize the step-by-step transmission of the start signal and the sensing output signal. The control step size of the step-by-step transmission is two pulse widths of the clock signal.

2. The gate driving circuit according to claim 1, characterized in that, The second control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first storage capacitor; the gate and first electrode of the first transistor, and the gate of the second transistor are all connected to the stage transmission signal; The first electrode of the second transistor and the second electrode of the first transistor are connected to a third node, and the gate of the third transistor is connected to a fourth node; the first electrode of the third transistor is connected to the high-potential signal, and the second electrode is connected to the third node; one end of the first storage capacitor is connected to the fourth node, and the other end is connected to the high-potential signal; the gate of the fourth transistor is connected to the fourth node, the first electrode is connected to the high-potential signal, and the second electrode is connected to the second node; the gate of the fifth transistor is connected to the first node, the first electrode is connected to the first low-potential signal, and the second electrode is connected to the second node; the gates of the sixth transistor and the seventh transistor are simultaneously connected to a start signal, the first electrode of the sixth transistor is connected to the fourth node, the second electrode of the sixth transistor and the first electrode of the seventh transistor are connected to the third node, and the second electrode of the seventh transistor is connected to the first low-potential signal.

3. The gate driving circuit according to claim 2, characterized in that, The second control module further includes an eighth transistor, the gate of which is connected to the gates of the sixth transistor and the seventh transistor, and is simultaneously connected to the start signal. The first electrode of the eighth transistor is connected to the first low-potential signal, and the second electrode is connected to the second node.

4. The gate driving circuit according to claim 2, characterized in that, The second control module further includes a ninth transistor and a tenth transistor; the gate of the ninth transistor is connected to the clock signal, the first electrode is connected to the gates of the sixth transistor and the seventh transistor, and is simultaneously connected to the start signal, and the second electrode is connected to the gate of the tenth transistor; the first electrode of the tenth transistor is connected to the first low-potential signal, and the second electrode is connected to the second node.

5. The gate driving circuit according to claim 1, characterized in that, The first control module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second storage capacitor. The gate of the eleventh transistor is connected to the clock signal, the first electrode is connected to the start signal, and the second electrode is connected to the first node. The gates of the twelfth transistor and the thirteenth transistor are simultaneously connected to the second node. The first electrode of the twelfth transistor is connected to the first node, and the second electrode is connected to the first electrode of the thirteenth transistor at a third node. The second electrode of the thirteenth transistor is connected to the first low-potential signal. The gate of the fourteenth transistor is connected to the first node, the first electrode is connected to the high-potential signal, and the second electrode is connected to the third node. One end of the second storage capacitor is connected to the first node, and the other end is connected to the sensing output signal.

6. The gate driving circuit according to claim 1, characterized in that, The output pull-up module includes a fifteenth transistor, the gate of which is connected to the first node, the first electrode is connected to the high-potential signal, and the second electrode is connected to the sensing output signal.

7. The gate driving circuit according to claim 1, characterized in that, The output pull-down module includes a sixteenth transistor, the gate of which is connected to the second node, the first electrode is connected to the second low-potential signal, and the second electrode is connected to the sensing output signal.

8. The gate driving circuit according to claim 1, characterized in that, In the termination phase following the maintenance phase, the start signal is at a low potential, the potential of the first node is pulled low, the cascade signal is at a high potential, the potential of the second node is pulled high, the output pull-down module is activated, and the sensing output signal becomes low.

9. The gate driving circuit according to claim 1, characterized in that, The clock signal includes a positive clock signal or an inverted clock signal, wherein the potentials of the positive clock signal and the inverted clock signal are opposite, and the duty cycle of the clock signal is 40% to 60%.

10. A display panel, characterized in that, It includes an array substrate and a gate driving circuit as described in any one of claims 1 to 9, wherein the gate driving circuit is connected to the array substrate.

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