Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel, comprising a trigger module connected to a common point and a pull-down module connected with the trigger module; the pull-down module comprises a first transistor, a second transistor and a third transistor; the first output end and the first control end of the first transistor are connected with a first electric frequency signal, the first input end of the first transistor is connected with the second output end of the second transistor, the second output end is also connected with the trigger module, the second control end of the second transistor is connected with a second electric frequency signal, the third control end of the third transistor is connected with a first scanning signal, the third output end of the third transistor is connected with the second output end, and the second input end of the second transistor and the third input end of the third transistor are connected with a low-level signal. The circuit provided by the application realizes the pull-down function of the potential through the three transistors, thereby replacing the multi-stage dummy circuit, greatly saving the arrangement space of the circuit and facilitating the arrangement of other components in the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of liquid crystal display, in particular to a gate driving circuit and display panel. BACKGROUND

[0002] GOA (Gate Driver on Array) driving circuit (shift register unit) has been widely used in the field of display technology, the GOA circuit includes a pull-up control unit and a pull-down unit. The pull-up control unit is used for lifting the potential after receiving the signal, and the pull-down unit pulls down the potential after receiving the signal and ends the signal transmission. The function of GOA step-by-step output Gn signal is realized by the pull-up of each level circuit. In order to maintain the uniformity of the output signal in the plane, the GOA circuit is often provided with a plurality of dummy level circuits responsible for the termination of the output signal of the last few levels of circuit, and the dummy level circuit does not participate in the action of transmitting the signal to the plane. Therefore, additional space is needed to accommodate the dummy level circuit, which limits the layout of other areas in the space and increases the redundant signal load. SUMMARY

[0003] The present application provides a gate driving circuit and display panel to solve the technical problem of dummy level circuit occupying additional space in the prior art.

[0004] In order to solve the above technical problems, the present application discloses the following technical solutions:

[0005] In a first aspect, a gate driving circuit is provided, comprising a trigger module connected to a common point and a pull-down module connected to the trigger module;

[0006] The pull-down module comprises a first transistor, a second transistor and a third transistor; the first output end and the first control end of the first transistor are connected to a first electric frequency signal, the first input end of the first transistor is connected to the second output end of the second transistor, the second output end is also connected to the trigger module, the second control end of the second transistor is connected to a second electric frequency signal, the third control end of the third transistor is connected to a first scanning signal, the third output end of the third transistor is connected to the second output end, and the second input end of the second transistor and the third input end of the third transistor are connected to a low-level signal.

[0007] In conjunction with the first aspect, the trigger module includes a fourth transistor and a fifth transistor. The fourth control terminal of the fourth transistor and the fifth control terminal of the fifth transistor are both connected to the second output terminal. The fourth input terminal of the fourth transistor and the fifth input terminal of the fifth transistor are both connected to the low-level signal. The fourth output terminal of the fourth transistor is connected to a common point, and the fifth output terminal of the fifth transistor is connected to the second electrical frequency signal.

[0008] In conjunction with the first aspect, the gate drive circuit further includes a pull-down sustaining module connected to a common point. The pull-down sustaining module includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The sixth control terminal and the sixth output terminal of the sixth transistor are connected to a first oscillation signal. The seventh control terminal of the seventh transistor is connected to the common point. The seventh output terminal of the seventh transistor is connected to the sixth input terminal of the sixth transistor. The seventh input terminal of the seventh transistor is connected to the low-level signal. The eighth control terminal of the eighth transistor is connected to the seventh output terminal. The eighth output terminal of the eighth transistor is connected to the first oscillation signal. The eighth input terminal of the eighth transistor is connected to the ninth output terminal of the ninth transistor. The ninth control terminal of the ninth transistor is connected to the common point. The ninth input terminal of the ninth transistor is connected to the low-level signal.

[0009] In conjunction with the first aspect, the pull-down sustaining module further includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The tenth control terminal and the tenth output terminal of the tenth transistor are connected to the second oscillation signal. The eleventh control terminal of the eleventh transistor is connected to the common point. The eleventh output terminal of the eleventh transistor is connected to the tenth input terminal of the tenth transistor. The eleventh input terminal of the eleventh transistor is connected to the low-level signal. The twelfth control terminal of the twelfth transistor is connected to the tenth input terminal. The twelfth output terminal of the twelfth transistor is connected to the second oscillation signal. The twelfth input terminal of the twelfth transistor is connected to the thirteenth output terminal of the thirteenth transistor. The thirteenth control terminal of the thirteenth transistor is connected to the common point. The thirteenth input terminal of the thirteenth transistor is connected to the low-level signal.

[0010] In conjunction with the first aspect, the pull-down sustaining module further includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The fourteenth output terminal of the fourteenth transistor is connected to the second electrical frequency signal. The fourteenth control terminal of the fourteenth transistor and the fifteenth control terminal of the fifteenth transistor are connected to the first input terminal of the first transistor. The fifteenth control terminal of the fifteenth transistor and the seventeenth control terminal of the seventeenth transistor are connected to the second input terminal of the second transistor. The fifteenth output terminal of the fifteenth transistor and the seventeenth output terminal of the seventeenth transistor are connected to a common point. The fourteenth input terminal of the fourteenth transistor, the fifteenth input terminal of the fifteenth transistor, the sixteenth input terminal of the sixteenth transistor, and the seventeenth input terminal of the seventeenth transistor are all connected to the low-level signal.

[0011] In conjunction with the first aspect, the gate drive circuit further includes a pull-up module connected to a common point. The pull-up module includes an eighteenth transistor, a nineteenth transistor, and a capacitor. The eighteenth control terminal of the eighteenth transistor and the nineteenth control terminal of the nineteenth transistor are both connected to the common point. The eighteenth output terminal of the eighteenth transistor and the nineteenth output terminal of the nineteenth transistor are both connected to a second electrical frequency signal. The eighteenth input terminal of the eighteenth transistor is connected to the second control terminal of the second transistor. The nineteenth input terminal of the nineteenth transistor is connected to a first control signal. One end of the capacitor is connected to the eighteenth control terminal, and the other end is connected to the second control terminal of the second transistor.

[0012] In conjunction with the first aspect, the gate drive circuit further includes a pull-up control module connected to a common point. The pull-up control module includes a twentieth transistor, the twentieth control terminal of the twentieth transistor is connected to a second control signal, the twentieth output terminal of the twentieth transistor is connected to a first scan signal, and the twentieth input terminal of the twentieth transistor is connected to a common point.

[0013] In conjunction with the first aspect, the gate drive circuit further includes a reset module connected to a common point. The reset module includes a 21st transistor, the 21st control terminal of the 21st transistor is connected to a third control signal, the 21st output terminal of the 21st transistor is connected to the common point, and the 21st input terminal of the 21st transistor is connected to a low-level signal.

[0014] In conjunction with the first aspect, the first electrical frequency signal and the second electrical frequency signal are output in opposite phase.

[0015] Secondly, a display panel is provided, including:

[0016] Drive substrate and display unit;

[0017] The driving substrate is provided with a gate driving circuit as described in any one of the first aspects, the display unit is connected to the gate driving circuit, and the gate driving circuit controls the operation of the display unit.

[0018] One of the above technical solutions has the following advantages or beneficial effects:

[0019] Compared with the prior art, the gate driving circuit of this application includes a trigger module connected to a common point and a pull-down module connected to the trigger module. The pull-down module includes a first transistor, a second transistor, and a third transistor. The first output terminal and the first control terminal of the first transistor are both connected to a first electrical frequency signal. The first input terminal of the first transistor is connected to the second output terminal of the second transistor, and the second output terminal is also connected to the trigger module. The second control terminal of the second transistor is connected to the connection point G. The third control terminal of the third transistor is connected to a first scan signal. The third output terminal of the third transistor is connected to the second output terminal. The second input terminal of the second transistor and the third input terminal of the third transistor are both connected to a low-level signal. The driving circuit provided by this application realizes the pull-down function of the potential through the first transistor, the second transistor, and the third transistor, thereby replacing the multi-stage dummy stage circuit, greatly saving the circuit layout space, and facilitating the layout of other components in the circuit. Attached Figure Description

[0020] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0021] Figure 1 This is a schematic diagram of the gate drive circuit structure provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the signal waveform provided in an embodiment of this application.

[0023] The attached figures are labeled as follows:

[0024] 100 - Pull-up control module, 200 - Pull-down sustaining module, 300 - Reset module, 400 - Pull-up module, 500 - Pull-down module, 600 - Trigger module. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] The applicant noted that the function of a GOA (Gate Driver on Array) circuit is to output gate drive signals Gn stage by stage. A common design involves a single-stage GOA circuit outputting one stage of Gn. A single-stage GOA circuit can typically be further divided into modules such as pull-up control, pull-down sustaining, and pull-down modules. The complete operation of a single-stage GOA circuit (excluding the pull-down sustaining module) begins with the pull-up control module receiving a signal to raise the Qn signal potential, and ends with the pull-down module receiving a signal to pull Qn and Gn potentials low. The function of the GOA in outputting the Gn signal stage by stage is achieved through the pull-up and pull-down signals of each stage. For example, in a circuit with 2x CK signals, the Gn / STn signal generated by any stage will be passed to the x preceding stages and the x following stages to start or terminate the operation of that stage.

[0027] It should be noted that the control terminal of the transistor mentioned in this application is the gate of the transistor, the input terminal is the source of the transistor, and the output terminal is the drain of the transistor.

[0028] The specific implementation methods of this application are illustrated below through examples:

[0029] like Figure 1As shown, this application embodiment provides a gate driving circuit, including: a pull-down sustaining module 200, a pull-up control module 100, a pull-up module 400, a reset module 300, a pull-down module 500, and a trigger module 600; the pull-down sustaining module 200, the pull-up control module 100, the pull-up module 400, the reset module 300, and the pull-down module 500 are connected to a common point Q; the pull-down module 500 includes a first transistor T81, a second transistor T82, and a third transistor T83; the first output terminal and the first control terminal of the first transistor T81 are both connected to a first electrical frequency signal CK(n+x), and the first transistor... The first input terminal of transistor T81 is connected to the second output terminal of transistor T82, which is also connected to the trigger module 600. The second control terminal of transistor T82 is connected to connection point G. The eighteenth input terminal of transistor T21 is connected to connection point G, and the eighteenth output terminal of transistor T21 is connected to the second electrical frequency signal CKn. The third control terminal of transistor T83 is connected to the first scan signal G(nx), and the third output terminal of transistor T83 is connected to the second output terminal. The second input terminals of transistors T82 and T83 are both connected to the low-level signal VSS. Specifically, this application implements the pull-down function of the potential through transistors T81, T82, and T83, thereby replacing the multi-stage dummy circuit, significantly saving circuit layout space and facilitating the layout of other components in the circuit.

[0030] In this embodiment, the trigger module 600 includes a fourth transistor T41 and a fifth transistor T31. The fourth control terminal of the fourth transistor T41 and the fifth control terminal of the fifth transistor T31 are both connected to the second output terminal. The fourth input terminal of the fourth transistor T41 and the fifth input terminal of the fifth transistor T31 are both connected to a low-level signal VSS. The fourth output terminal of the fourth transistor T41 is connected to a common point Q, and the fifth output terminal of the fifth transistor T31 is connected to a connection point G. Specifically, in a circuit with 2x clock CK signals, the first scan signal G(nx) first turns on the twentieth transistor T11 to charge the common point Q in the first stage. At the same time, the third transistor T83 is turned on, while the fourth transistor T41 and the fifth transistor T31 are turned off to prevent abnormal charging of the common point Q. After the twentieth transistor T11 is turned off, the second frequency signal CKn arrives to charge the common point Q for the second time. At the same time, the eighteenth transistor T21 starts to output a high signal Gn. The high signal Gn causes the second transistor T82 to start working and continues to keep the fourth transistor T41 and the fifth transistor T31 in the off state. After Gn is output, the first frequency signal CK(n+x) arrives with a high signal. At this time, the first transistor T81 starts working, while the fourth transistor T41 and the fifth transistor T31 switch from the off state to the on state. The signals on the common point Q and the connection point G are pulled low to be the same as the low level signal VSS. This application achieves pull-down functionality without adding multiple dummy-level circuits through the cooperation of trigger module 600 and pull-down module 500. This simplifies the circuit, saves circuit layout space, facilitates routing on the source drive circuit side or opposite side, reduces signal load, and improves the display effect of the LCD.

[0031] In this embodiment, the pull-down sustaining module 200 includes a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, a ninth transistor T54, a tenth transistor T61, an eleventh transistor T62, a twelfth transistor T63, a thirteenth transistor T64, a fourteenth transistor T32, a fifteenth transistor T42, a sixteenth transistor T33, and a seventeenth transistor T43. The sixth control terminal and the sixth output terminal of the sixth transistor T51 are connected to the first oscillation signal LC1. The seventh control terminal of the seventh transistor T52 is connected to the common point Q. The seventh output terminal of the seventh transistor T52 is connected to the sixth input terminal of the sixth transistor T51. The seventh input terminal of the seventh transistor T52 is connected to the low-level signal VSS. The eighth control terminal of the eighth transistor T53 is connected to the seventh output terminal. The eighth output terminal of the eighth transistor T53 is connected to the first oscillation signal LC1. The eighth input terminal of the eighth transistor T53 is connected to the ninth output terminal of the ninth transistor T54. The ninth control terminal of the ninth transistor T54 is connected to the common point Q. The ninth input terminal of the ninth transistor T54 is connected to the low-level signal VSS. The tenth control terminal and tenth output terminal of the tenth transistor T61 are connected to the second oscillation signal LC2. The eleventh control terminal of the eleventh transistor T62 is connected to the common point Q. The eleventh output terminal of the eleventh transistor T62 is connected to the tenth input terminal of the tenth transistor T61. The eleventh input terminal of the eleventh transistor T62 is connected to the low-level signal VSS. The twelfth control terminal of the twelfth transistor T63 is connected to the tenth input terminal. The twelfth output terminal of the twelfth transistor T63 is connected to the second oscillation signal LC2. The twelfth input terminal of the twelfth transistor T63 is connected to the thirteenth output terminal of the thirteenth transistor T64. The thirteenth control terminal of the thirteenth transistor T64 is connected to the common point Q. The thirteenth input terminal of the thirteenth transistor T64 is connected to the low-level signal VSS. The fourteenth output terminal of the fourteenth transistor T32 is connected to connection point G. The fourteenth control terminal of the fourteenth transistor T32 and the fifteenth control terminal of the fifteenth transistor T42 are connected to the eighth input terminal of the eighth transistor T53. The sixteenth control terminal of the sixteenth transistor T33 and the seventeenth control terminal of the seventeenth transistor T43 are connected to the twelfth input terminal of the twelfth transistor T63. The fifteenth output terminal of the fifteenth transistor T42 and the seventeenth output terminal of the seventeenth transistor T43 are connected to the common point Q. The fourteenth input terminal of the fourteenth transistor T32, the fifteenth input terminal of the fifteenth transistor T42, the sixteenth input terminal of the sixteenth transistor T33, and the seventeenth input terminal of the seventeenth transistor T43 are all connected to the low-level signal VSS. Specifically, the function of the pull-down sustaining module in this application is to provide a pull-down sustaining function to ensure that the common point Q remains in a low-level state at a specific time or under specific conditions to meet timing requirements.

[0032] like Figure 1As shown in this embodiment, the pull-up module 400 includes an eighteenth transistor T21, a nineteenth transistor T22, and a capacitor. The eighteenth control terminal of the eighteenth transistor T21 and the nineteenth control terminal of the nineteenth transistor T22 are both connected to a common point Q. The eighteenth output terminal of the eighteenth transistor T21 and the nineteenth output terminal of the nineteenth transistor T22 are both connected to a second electrical frequency signal CKn. The eighteenth input terminal of the eighteenth transistor T21 is connected to the second control terminal of the second transistor T82. The nineteenth input terminal of the nineteenth transistor T22 is connected to a first control signal STn. One end of the capacitor is connected to the eighteenth control terminal, and the other end is connected to the second control terminal of the second transistor T82. Specifically, the main function of the pull-up module 400 is to pull the potential of the common point Q to a high level. In this gate drive circuit, when there is no external input signal, the pull-up module 400 can ensure that the potential of the common point Q remains at a high level to avoid uncertain logic states.

[0033] like Figure 1 As shown in the embodiment of this application, the pull-up control module 100 includes a twentieth transistor T11. The twentieth control terminal of the twentieth transistor T11 is connected to the second control signal ST(nx), the twentieth output terminal of the twentieth transistor T11 is connected to the first scan signal G(nx), and the twentieth input terminal of the twentieth transistor T11 is connected to the common point Q. Specifically, the main function of the pull-up control module 100 is to control the pull-up state of the common point Q. The pull-up control module 100 consists of a twentieth transistor T11, used to control the connection and disconnection of the common point Q. When the twentieth transistor T11 receives a signal to turn on, the common point Q is connected to the pull-up power supply, and the common point Q is pulled high. When the twentieth transistor T11 receives a signal to turn off, the common point Q is disconnected from the pull-up power supply, and the common point Q is pulled low.

[0034] like Figure 1 As shown in this embodiment, the reset module 300 includes a twenty-first transistor TrQ. The twenty-first control terminal of the twenty-first transistor TrQ is connected to a third control signal STV, the twenty-first output terminal of the twenty-first transistor TrQ is connected to a common point Q, and the twenty-first input terminal of the twenty-first transistor TrQ is connected to a low-level signal VSS. Specifically, the reset module 300 is used to implement the reset function of the gate drive circuit. When the gate drive circuit starts up or when a specific event occurs, it is necessary to restore the circuit or system to a known state. The reset module 300 restores the circuit to its initial state by transmitting a reset signal, ensuring controllable operation and avoiding uncertain logic states.

[0035] like Figure 2As shown, the first electrical frequency signal CK(n+x) and the second electrical frequency signal CKn are out of phase. Specifically, the third electrical frequency signal CK(nx) at the two x-th moments before the first electrical frequency signal CK(n+x) is in phase with the first electrical frequency signal CK(n+x), while the third electrical frequency signal CK(nx) is out of phase with the CKn signal. Therefore, it can be seen that the phase of the CK signal reverses every x moments. Figure 2 As can be seen from the diagram, the high level position of the first scan signal G(nx) is the same as the first high level moment of the first electrical frequency signal CK(n+x). Subsequently, the first scan signal G(nx) outputs a low level. The high level of the second scan signal Gn at the next x moment of the first scan signal G(nx) is the same as the first high level moment of CKn. Subsequently, the second scan signal Gn outputs a low level. The potential of the common point Q is first charged when the third electrical frequency signal CK(nx) is first high, so the potential rises. It is charged a second time when the second electrical frequency signal CKn is first high, and the potential rises again. Subsequently, the common point Q remains at a low level.

[0036] This application also provides a display panel, including: a driving substrate and a display unit; the driving substrate is provided with a gate driving circuit as provided in any of the above embodiments, the display unit is connected to the gate driving circuit, and the gate driving circuit controls the operation of the display unit.

[0037] The above provides a detailed description of a gate driving circuit and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate driving circuit, characterized in that, It includes a trigger module (600) connected to a common point and a pull-down module (500) connected to the trigger module (600); The pull-down module (500) includes a first transistor, a second transistor, and a third transistor; the first output terminal and the first control terminal of the first transistor are both connected to a first electrical frequency signal CK(n+x), the first input terminal of the first transistor is connected to the second output terminal of the second transistor, the second output terminal is also connected to the trigger module (600), the second control terminal of the second transistor is connected to connection point G, the third control terminal of the third transistor is connected to a first scan signal G(nx), the third output terminal of the third transistor is connected to the second output terminal, and the second input terminal of the second transistor and the third input terminal of the third transistor are both connected to a low-level signal, where n represents the signal number and x represents the time.

2. The gate driving circuit as described in claim 1, characterized in that, The trigger module includes a fourth transistor and a fifth transistor. The fourth control terminal of the fourth transistor and the fifth control terminal of the fifth transistor are both connected to the second output terminal. The fourth input terminal of the fourth transistor and the fifth input terminal of the fifth transistor are both connected to the low-level signal. The fourth output terminal of the fourth transistor is connected to a common point, and the fifth output terminal of the fifth transistor is connected to the connection point G.

3. The gate driving circuit as described in claim 1 or 2, characterized in that, The gate drive circuit further includes a pull-down sustaining module connected to a common point. The pull-down sustaining module includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The sixth control terminal and the sixth output terminal of the sixth transistor are connected to a first oscillation signal. The seventh control terminal of the seventh transistor is connected to the common point. The seventh output terminal of the seventh transistor is connected to the sixth input terminal of the sixth transistor. The seventh input terminal of the seventh transistor is connected to the low-level signal. The eighth control terminal of the eighth transistor is connected to the seventh output terminal. The eighth output terminal of the eighth transistor is connected to the first oscillation signal. The eighth input terminal of the eighth transistor is connected to the ninth output terminal of the ninth transistor. The ninth control terminal of the ninth transistor is connected to the common point. The ninth input terminal of the ninth transistor is connected to the low-level signal.

4. The gate driving circuit as described in claim 3, characterized in that, The pull-down sustaining module further includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The tenth control terminal and the tenth output terminal of the tenth transistor are connected to the second oscillation signal. The eleventh control terminal of the eleventh transistor is connected to the common point. The eleventh output terminal of the eleventh transistor is connected to the tenth input terminal of the tenth transistor. The eleventh input terminal of the eleventh transistor is connected to the low-level signal. The twelfth control terminal of the twelfth transistor is connected to the tenth input terminal. The twelfth output terminal of the twelfth transistor is connected to the second oscillation signal. The twelfth input terminal of the twelfth transistor is connected to the thirteenth output terminal of the thirteenth transistor. The thirteenth control terminal of the thirteenth transistor is connected to the common point. The thirteenth input terminal of the thirteenth transistor is connected to the low-level signal.

5. The gate driving circuit as described in claim 4, characterized in that, The pull-down sustaining module further includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The fourteenth output terminal of the fourteenth transistor is connected to the connection point G. The fourteenth control terminal of the fourteenth transistor and the fifteenth control terminal of the fifteenth transistor are connected to the eighth input terminal of the eighth transistor. The sixteenth control terminal of the sixteenth transistor and the seventeenth control terminal of the seventeenth transistor are connected to the twelfth input terminal of the twelfth transistor. The fifteenth output terminal of the fifteenth transistor and the seventeenth output terminal of the seventeenth transistor are connected to a common point. The fourteenth input terminal of the fourteenth transistor, the fifteenth input terminal of the fifteenth transistor, the sixteenth input terminal of the sixteenth transistor, and the seventeenth input terminal of the seventeenth transistor are all connected to the low-level signal.

6. The gate driving circuit as described in claim 1, characterized in that, The gate drive circuit further includes a pull-up module (400) connected to a common point. The pull-up module (400) includes an eighteenth transistor, a nineteenth transistor, and a capacitor. The eighteenth control terminal of the eighteenth transistor and the nineteenth control terminal of the nineteenth transistor are both connected to the common point. The eighteenth output terminal of the eighteenth transistor and the nineteenth output terminal of the nineteenth transistor are both connected to a second electrical frequency signal CKn. The eighteenth input terminal of the eighteenth transistor is connected to the second control terminal of the second transistor. The nineteenth input terminal of the nineteenth transistor is connected to a first control signal STn. One end of the capacitor is connected to the eighteenth control terminal, and the other end is connected to the second control terminal of the second transistor.

7. The gate driving circuit as described in claim 1, characterized in that, The gate drive circuit further includes a pull-up control module (100) connected to a common point. The pull-up control module (100) includes a twentieth transistor. The twentieth control terminal of the twentieth transistor is connected to a second control signal ST(nx). The twentieth output terminal of the twentieth transistor is connected to a first scan signal G(nx). The twentieth input terminal of the twentieth transistor is connected to a common point.

8. The gate driving circuit as described in claim 1, characterized in that, The gate drive circuit also includes a reset module (300) connected to a common point. The reset module (300) includes a 21st transistor. The 21st control terminal of the 21st transistor is connected to a third control signal STV. The 21st output terminal of the 21st transistor is connected to the common point. The 21st input terminal of the 21st transistor is connected to a low-level signal.

9. The gate driving circuit as described in claim 1, characterized in that, The first electrical frequency signal CK(n+x) and the second electrical frequency signal CKn are output in opposite phase.

10. A display panel, characterized in that, include: Drive substrate and display unit; The driving substrate is provided with a gate driving circuit as described in any one of claims 1-9, the display unit is connected to the gate driving circuit, and the gate driving circuit controls the operation of the display unit.

Images