Pipeline analog-to-digital converter and MDAC circuit thereof

Abstract

The application discloses a kind of pipeline ADC and its MDAC circuit, including full-differential switched capacitor circuit, including first sampling capacitor group and residual amplifier;Common-mode voltage adjustment circuit is used to provide common-mode reference voltage during the active phase of first clock signal to set common-mode voltage at the second end of first sampling capacitor group, and during the active phase of second clock signal, the input common-mode voltage of residual amplifier reaches preset input common-mode voltage, wherein, common-mode voltage adjustment circuit includes second sampling capacitor group and integration capacitor, second sampling capacitor group is sampled first common-mode voltage related to analog input signal and second common-mode voltage related to reference voltage signal in response to first clock signal and second clock signal respectively, and the operation of sampling result and preset input common-mode voltage is carried out on integration capacitor, to obtain common-mode reference voltage, to improve the working performance of pipeline ADC and its MDAC circuit.

Description

Technical Field

[0001] This invention relates to the field of pipelined analog-to-digital converter (ADC) technology, and particularly to a pipelined ADC and its MDAC circuit. Background Technology

[0002] In recent years, with the rapid development of wireless communication technology, the design requirements for analog-to-digital converters (ADCs) have become increasingly stringent, demanding higher precision and speed. Pipeline ADCs are a common structure for achieving high-speed, high-precision ADCs, and the MDAC circuit (Multiplying Digital to Analog Converter) is a key module that determines the performance of pipelined ADCs.

[0003] Figure 1 A schematic diagram of an MDAC circuit according to the prior art is shown; Figure 2 A timing diagram of an MDAC circuit according to the prior art is shown. See also Figure 1 The MDAC circuit includes sampling capacitors CSP and CSN, feedback capacitors CF1 and CF2, and a margin amplifier AMP. The first terminal of sampling capacitor CSP is simultaneously connected to the first terminals of switches SP1, SP2, and SP3. The second terminal of switch SP1 is connected to the analog input signal VIP, the second terminal of switch SP2 is connected to the reference voltage signal VRP, and the second terminal of switch SP3 is connected to the reference voltage signal VRN. The first terminal of sampling capacitor CSN is simultaneously connected to the first terminals of switches SN1, SN2, and SN3. The second terminal of switch SN1 is connected to the analog input signal VIN, the second terminal of switch SN2 is connected to the reference voltage signal VRP, and the second terminal of switch SN3 is connected to the reference voltage signal VRN. Switch SP5 is connected between the second terminal of sampling capacitor CSP and the common-mode reference voltage VCMS. A switch SP4 is connected between the second terminal of the sampling capacitor CSP and the non-inverting input terminal of the margin amplifier AMP; a switch SN5 is connected between the second terminal of the sampling capacitor CSN and the common-mode reference voltage VCMS; a switch SN4 is connected between the second terminal of the sampling capacitor CSN and the inverting input terminal of the margin amplifier AMP; a feedback capacitor CFP and a switch SP6 are connected between the non-inverting input terminal and the inverting output terminal of the margin amplifier AMP; a feedback capacitor CFN and a switch SN6 are connected between the inverting input terminal and the non-inverting output terminal of the margin amplifier AMP; the non-inverting output terminal of the margin amplifier AMP provides the output signal VOUTP; and the inverting output terminal of the margin amplifier AMP provides the output signal VOUTN.

[0004] See Figure 2The clock signals CKS and CKH are not simultaneously high. The high-level phase of the clock signal CKS corresponds to the sampling phase of the MDAC circuit, and the high-level phase of the clock signal CKH corresponds to the holding phase of the MDAC circuit.

[0005] Clock signal CKS controls the on / off states of switches SN1, SP1, SN5, and SP5, while clock signal CKH controls the on / off states of switches SN4, SP4, SN6, and SP6. During the sampling phase of the MDAC circuit, the common-mode voltage at the first terminals of sampling capacitors CSP and CSN is the first common-mode voltage VCMI = (VIN + VIP) / 2, and the common-mode voltage at the second terminals of CSP and CSN is the common-mode reference voltage VCMS. During the hold phase of the MDAC circuit, the common-mode voltage at the first terminals of sampling capacitors CSP and CSN is the second common-mode voltage VCMR = (VRP + VRN) / 2, and the common-mode voltage at the second terminals is the input common-mode voltage VCMB of the margin amplifier AMP. When the MDAC circuit switches from the sampling phase to the hold phase, the common-mode voltage at the first terminals of sampling capacitors CSP and CSN changes from VCMI to VCMR. At this time, the input common-mode voltage VCMB of the margin amplifier AMP is VCMS + VCMR - VCMI.

[0006] To ensure the proper functioning of the margin amplifier AMP, its input common-mode voltage VCMB needs to be equal to the preset input common-mode voltage VCMA (the expected input common-mode voltage of the margin amplifier AMP). Existing technology pre-sets the values ​​of the first common-mode voltage VCMI, the second common-mode voltage VCMR, the common-mode reference voltage VCMS, and the preset input common-mode voltage VCMA to be equal, so that the actual input common-mode voltage VCMB of the margin amplifier AMP equals the preset input common-mode voltage VCMA. However, when the first common-mode voltage VCMI changes or the reference voltage signal VRN / VRP uses a ground voltage, causing a change in the second common-mode voltage VCMR, the input common-mode voltage VCMB of the margin amplifier AMP will deviate from the preset input common-mode voltage VCMA. In severe cases, this can lead to a decrease in the performance of the margin amplifier AMP, affecting the accuracy and linearity of the pipelined ADC.

[0007] Therefore, a new pipelined ADC and its MDAC circuit are needed to solve the above problems. Summary of the Invention

[0008] In view of the above problems, the purpose of this invention is to provide a pipelined analog-to-digital converter and its MDAC circuit, thereby improving the performance of the pipelined analog-to-digital converter and its MDAC circuit.

[0009] According to one aspect of the present invention, an MDAC circuit is provided, comprising a fully differential switched capacitor circuit, including a first sampling capacitor bank and a margin amplifier, wherein a first terminal of the first sampling capacitor bank is connected to an analog input signal in response to a first clock signal and connected to a reference voltage signal in response to a second clock signal, and a second terminal of the first sampling capacitor bank is connected to the input terminal of the margin amplifier in response to the second clock signal; a common-mode voltage adjustment circuit is provided to provide a common-mode reference voltage during the valid phase of the first clock signal to set a common-mode voltage at the second terminal of the first sampling capacitor bank, and to make the input common-mode voltage of the margin amplifier reach a preset input common-mode voltage during the valid phase of the second clock signal, wherein the common-mode voltage adjustment circuit includes a second sampling capacitor bank and an integrating capacitor, wherein the second sampling capacitor bank samples a first common-mode voltage related to the analog input signal in response to the first clock signal and samples a second common-mode voltage related to the reference voltage signal in response to the second clock signal, and performs an operation on the integrating capacitor with the preset input common-mode voltage to obtain the common-mode reference voltage.

[0010] Optionally, the common-mode reference voltage = the first common-mode voltage + the preset input common-mode voltage - the second common-mode voltage.

[0011] Optionally, in response to the first clock signal, the first terminal of the second sampling capacitor group is connected to the first common-mode voltage, and the second terminal of the second sampling capacitor group is connected to the first terminal of the integrating capacitor; in response to the second clock signal, the first terminal of the second sampling capacitor group is connected to the second common-mode voltage, and the second terminal of the second sampling capacitor group is connected to the second terminal of the integrating capacitor.

[0012] Optionally, the preset input common-mode voltage is the input common-mode voltage expected by the margin amplifier.

[0013] Optionally, a buffer is provided between the first end of the integrating capacitor and the second end of the first sampling capacitor group.

[0014] Optionally, the second sampling capacitor group includes: a first sampling capacitor, the first end of which is connected to a first reference voltage signal via a first switch and to a first analog input signal via a second switch; a second sampling capacitor, the first end of which is connected to a second analog input signal via a third switch and to a second reference voltage signal via a fourth switch, the second end of which is connected to the second end of the first sampling capacitor, wherein the second end of the second sampling capacitor is also connected to the second end of the integrating capacitor via a fifth switch and to the first end of the integrating capacitor via a sixth switch, the first common-mode voltage being the average voltage of the first analog input signal and the second analog input signal, and the second common-mode voltage being the average voltage of the first reference voltage signal and the second reference voltage signal.

[0015] Optionally, the first reference voltage signal or the second reference voltage signal may be a ground voltage.

[0016] Optionally, the adjustment step size of the common-mode reference voltage is adjusted by changing the ratio of the equivalent capacitance of the second sampling capacitor group to the capacitance of the integrating capacitor, and the effective phases of the first clock signal and the second clock signal do not overlap.

[0017] Optionally, the first sampling capacitor group includes a third sampling capacitor and a fourth sampling capacitor. The first terminal of the third sampling capacitor is simultaneously connected to the first terminals of the seventh, eighth, and ninth switches. The second terminal of the seventh switch is connected to the first analog input signal, the second terminal of the eighth switch is connected to the second reference voltage signal, and the second terminal of the ninth switch is connected to the first reference voltage signal. A tenth switch is connected between the second terminal of the third sampling capacitor and the common-mode reference voltage, and an eleventh switch is connected between the second terminal of the third sampling capacitor and the non-inverting input terminal of the margin amplifier. The first terminal of the fourth sampling capacitor is simultaneously connected to the first terminals of the twelfth, thirteenth, and fourteenth switches, and the second terminal of the twelfth switch... A second analog input signal is connected; the second terminal of the thirteenth switch is connected to the second reference voltage signal; the second terminal of the fourteenth switch is connected to the first reference voltage signal; a fifteenth switch is connected between the second terminal of the fourth sampling capacitor and the common-mode reference voltage; a sixteenth switch is connected between the second terminal of the fourth sampling capacitor and the inverting input terminal of the margin amplifier; a first feedback capacitor and a seventeenth switch are connected between the non-inverting input terminal and the inverting output terminal of the margin amplifier; a second feedback capacitor and an eighteenth switch are connected between the inverting input terminal and the non-inverting output terminal of the margin amplifier; the non-inverting output terminal of the margin amplifier provides a first output signal; and the inverting output terminal of the margin amplifier provides a second output signal.

[0018] According to another aspect of the present invention, a pipelined analog-to-digital converter is provided, including the MDAC circuit as described above.

[0019] The present invention provides a pipelined ADC and its MDAC circuit. The MDAC circuit includes a fully differential switched capacitor circuit and a common-mode voltage adjustment circuit. The fully differential switched capacitor circuit includes a first sampling capacitor group and a margin amplifier. The common-mode voltage adjustment circuit includes a second sampling capacitor group and an integrating capacitor. The second sampling capacitor group samples a first common-mode voltage related to the analog input signal in response to a first clock signal, and samples a second common-mode voltage related to a reference voltage signal in response to a second clock signal. The sampling result is then calculated on the integrating capacitor along with a preset input common-mode voltage to obtain a common-mode reference voltage. During the effective phase of the first clock signal, the integrating capacitor stores the difference between the common-mode reference voltage at the end of the previous phase and the preset input common-mode voltage. During the effective phase of the first clock signal, the integrating capacitor shares charge with the second sampling capacitor group, causing the common-mode reference voltage to change. Ultimately, the common-mode reference voltage tends to a stable value, thereby ensuring that the actual input common-mode voltage of the margin amplifier reaches the preset input common-mode voltage and improving the performance of the margin amplifier. Furthermore, this invention uses an integrating capacitor as a passive integrator, which simplifies the circuit implementation, reduces power consumption, and ensures that the adjustment range of the common-mode reference voltage is not limited by the output swing of the active integrator amplifier. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of an MDAC circuit according to the prior art is shown;

[0022] Figure 2 It shows Figure 1 The diagram shows the timing sequence of the MDAC circuit.

[0023] Figure 3 A schematic diagram of another MDAC circuit according to the prior art is shown;

[0024] Figure 4 A schematic diagram of the common-mode voltage adjustment circuit of the MDAC circuit according to an embodiment of the present invention is shown;

[0025] Figure 5 A timing diagram of an MDAC circuit according to an embodiment of the present invention is shown;

[0026] Figure 6 A circuit diagram of an MDAC circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0027] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0028] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0029] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0030] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] Figure 3 A schematic diagram of another MDAC circuit according to the prior art is shown. Figure 3 The timing diagram of the MDAC circuit shown is as follows: Figure 2 The timing diagram shown is for the operation of the system.

[0032] Figure 3 The MDAC circuit shown is in Figure 1Based on the MDAC circuit shown, a common-mode voltage adjustment circuit 200 is added. The common-mode voltage adjustment circuit 200 adjusts the input common-mode voltage VCMB of the margin amplifier AMP by tracking the changes of the first common-mode voltage VCMI and the second common-mode voltage VCMR at the first terminal of the sampling capacitors CSP1 and CSN1 of the fully differential switched capacitor circuit 100 in real time.

[0033] Specifically, the common-mode voltage adjustment circuit 200 detects the first common-mode voltage VCMI and the second common-mode voltage VCMR through sampling capacitors CSP2 and CSN2, and clamps the preset input common-mode voltage VCMA of the margin amplifier AMP through operational amplifier AMP1, and integrates it with capacitor CF3, thereby adjusting the common-mode reference voltage VCMS output by operational amplifier AMP1. Due to the clamping of operational amplifier AMP1, the negative input terminal of operational amplifier AMP1 is always kept near the preset input common-mode voltage VCMA. During the hold phase of the pipelined ADC, sampling capacitors CSP2 and CSN2 sample the second common-mode voltage VCMR. At this time, the charge on capacitor CF3 is QF(1)=CF3*(VCMA-VCMS), and the charge on sampling capacitors CSP2 and CSN2 is QR(1)=CF3*(VCMA-VCMI). During the sampling phase of the MDAC circuit, the charge at the negative input terminal of operational amplifier AMP1 is conserved. Therefore, the output voltage of operational amplifier AMP1 changes. Its overall circuit can be regarded as an active integrator. After several cycles, the common-mode reference voltage VCMS stabilizes at a level that allows the input common-mode voltage VCMB across the margin amplifier AMP during the hold phase to approach the preset input common-mode voltage VCMA, thereby completing the input common-mode voltage adjustment of the margin amplifier AMP.

[0034] The common-mode adjustment circuit 200 described above has two drawbacks due to the use of an active integrator:

[0035] First, the circuit is complex and consumes a lot of power;

[0036] 2. When the first common-mode voltage VCMI and the second common-mode voltage VCMR differ significantly from the preset input common-mode voltage VCMA, the common-mode reference voltage VCMS needs to be adjusted to a value close to the power supply or ground. However, the output swing of the operational amplifier AMP1 will limit its boundary value.

[0037] To address the aforementioned problems, the inventors of this invention propose a novel pipelined ADC and MDAC circuit.

[0038] Figure 4 A schematic diagram of the common-mode voltage adjustment circuit of the MDAC circuit according to an embodiment of the present invention is shown; Figure 5 A timing diagram of the MDAC circuit according to an embodiment of the present invention is shown.

[0039] See Figure 4 The common-mode voltage adjustment circuit 2000 includes a second sampling capacitor bank CR and an integrating capacitor CRF. The first terminal of the second sampling capacitor bank CR is connected to the first common-mode voltage VCMI through switch SRN and to the second common-mode voltage VCMR through switch SRP. The second terminal of the second sampling capacitor bank CR is connected to the second terminal of the integrating capacitor CRF through switch SR5 and to the first terminal of the integrating capacitor CRF through switch SR6.

[0040] The second sampling capacitor bank CR samples the first common-mode voltage VCMI in response to the clock signal CKS, and samples the second common-mode voltage VCMR in response to the clock signal CKH. The sampling results are then calculated on the integrating capacitor CRF along with the preset input common-mode voltage VCMA to obtain the common-mode reference voltage VCMS.

[0041] See Figure 5 The operating timing of the MDAC circuit includes clock signals CKH and CKS, whose effective phases do not overlap. Taking high-level active as an example, when clock signal CKS is high, it corresponds to the sampling phase of the MDAC circuit, and when clock signal CKH is high, it corresponds to the hold phase. Therefore, switches SRN and SR6 are turned on during the sampling phase and turned off during the hold phase; switches SRP and SR5 are turned off during the sampling phase and turned on during the hold phase.

[0042] Specifically, in response to the clock signal CKS, the first terminal of the second sampling capacitor group CR is connected to the first common-mode voltage VCMI, and the second terminal of the second sampling capacitor group CR is connected to the first terminal of the integrating capacitor CRF. In response to the clock signal CKH, the first terminal of the second sampling capacitor group CR is connected to the second common-mode voltage VCMR, and the second terminal of the second sampling capacitor group CR is connected to the second terminal of the integrating capacitor CRF. The first terminal of the integrating capacitor CRF provides the common-mode reference voltage VCMS, where VCMS = VCMI - VCMR + VCMA. The principle is that during the holding phase, the integrating capacitor CRF stores the difference between the common-mode reference voltage VCMS at the end of the previous phase and the preset input common-mode voltage VCMA. During the sampling phase, it shares charge with the second sampling capacitor group CR, causing the common-mode reference voltage VCMS to change, ultimately making the common-mode reference voltage VCMS tend towards a stable value. This ensures that the input common-mode voltage VCMB of the margin amplifier AMP reaches the preset input common-mode voltage VCMA, thereby improving the operating performance of the margin amplifier AMP.

[0043] Figure 6 A circuit diagram of an MDAC circuit according to an embodiment of the present invention is shown. See also Figure 6When the common-mode voltage adjustment circuit 2000 is connected to the fully differential switched capacitor circuit 1000, a buffer 2100 can be added between the first terminal of the integrating capacitor CRF and the fully differential switched capacitor circuit 1000 to enhance the response speed of the common-mode voltage adjustment circuit 2000 during the sampling stage.

[0044] The fully differential switched capacitor circuit 1000 includes a first sampling capacitor group, feedback capacitors CFP and CFN, and a margin amplifier AMP. The first sampling capacitor group includes sampling capacitors CSP1 and CSN1.

[0045] The first terminal of sampling capacitor CSP1 is simultaneously connected to the first terminals of switches SP1, SP2, and SP3. The second terminal of switch SP1 is connected to the analog input signal VIP, the second terminal of switch SP2 is connected to the reference voltage signal VRP, and the second terminal of switch SP3 is connected to the reference voltage signal VRN. The first terminal of sampling capacitor CSN1 is simultaneously connected to the first terminals of switches SN1, SN2, and SN3. The second terminal of switch SN1 is connected to the analog input signal VIN, the second terminal of switch SN2 is connected to the reference voltage signal VRP, and the second terminal of switch SN3 is connected to the reference voltage signal VRN. Switch SP5 is connected between the second terminal of sampling capacitor CSP1 and the common-mode reference voltage VCMS. Switch SP4 is connected between the second terminal of sampling capacitor CSP1 and the non-inverting input terminal of the margin amplifier AMP. Switch SN5 is connected between the second terminal of sampling capacitor CSN1 and the common-mode reference voltage VCMS. Switch SN4 is connected between the second terminal of sampling capacitor CSN1 and the inverting input terminal of the margin amplifier AMP. A feedback capacitor CFP and a switch SP6 are connected between the non-inverting input and the inverting output of the margin amplifier AMP. A feedback capacitor CFN and a switch SN6 are connected between the inverting input and the non-inverting output of the margin amplifier AMP. The non-inverting output of the margin amplifier AMP provides the output signal VOUTP, and the inverting output of the margin amplifier AMP provides the output signal VOUTN.

[0046] The common-mode voltage adjustment circuit 2000 is used to provide a common-mode reference signal VCMS during the active phase of the clock signal CKS to set the common-mode voltage on the first sampling capacitor bank, and to make the input common-mode voltage VCMB of the margin amplifier AMP reach the desired input common-mode voltage during the active phase of the second clock signal.

[0047] The second sampling capacitor group CR of the common-mode voltage adjustment circuit 2000 includes sampling capacitors CSP2 and CSN2.

[0048] The first terminal of sampling capacitor CSP2 is connected to the first terminals of both switches SR1 and SR2. The second terminal of switch SR2 is connected to the analog input signal VIP, and the second terminal of switch SR1 is connected to the reference voltage signal VRN. The first terminal of sampling capacitor CSN2 is connected to the first terminals of both switches SR3 and SR4. The second terminal of switch SR3 is connected to the analog input signal VIN, and the second terminal of switch SR4 is connected to the reference voltage signal VRP. The second terminals of sampling capacitors CSP2 and CSN2 are connected to node A. The first terminal of integrating capacitor CRF provides the common-mode reference voltage VCMS, and the second terminal of integrating capacitor CRF is connected to the preset input common-mode voltage VCMA. Switch SR6 and switch SR5 are connected between the first terminal of integrating capacitor CRF and node A. The preset input common-mode voltage VCMA is the desired input common-mode voltage of the margin amplifier AMP. The second terminal of switch SR1 can also be connected to the reference voltage signal VRP, in which case the second terminal of switch SR4 is connected to the reference voltage signal VRN.

[0049] During the sampling phase of the MDAC circuit, the first terminal of sampling capacitor CSP1 is connected to the analog input signal VIP, and the first terminal of sampling capacitor CSN1 is connected to the analog input signal VIN. The second terminals of sampling capacitors CSP1 and CSN1 are connected to the common-mode reference voltage VCMS. The first terminal of sampling capacitor CSP2 is connected to the analog input signal VIP, and the first terminal of sampling capacitor CSN2 is connected to the analog input signal VIN. The second terminals of sampling capacitors CSP2 and CSN2 are connected to the first terminal of integrating capacitor CRF. At this time, the common-mode voltage at the first terminals of sampling capacitors CSP1 and CSN1 and sampling capacitors CSP2 and CSN2 is the first common-mode voltage VCMI = (VIP + VIN) / 2, and the common-mode voltage at the second terminals of sampling capacitors CSP1 and CSN1 and sampling capacitors CSP2 and CSN2 is the common-mode reference voltage VCMS.

[0050] During the hold phase of the MDAC circuit, the first terminal of sampling capacitor CSP1 is connected to the reference voltage signal VRP, and the first terminal of sampling capacitor CSN1 is connected to the reference voltage signal VRN. The specific VRN connection is determined by the digital code Di generated by the DAC in the pipeline stage, which has only two values: 0 and 1. Here, it's set that when the digital code is 0, sampling capacitor CSP1 is connected to both VRP and VRN; when the digital code is 1, sampling capacitor CSP1 is connected to both VRN and VRP. The situations at the two differential input terminals are exactly reversed. The second terminal of sampling capacitor CSP1 is connected to the non-inverting input of the margin amplifier AMP, and the second terminal of sampling capacitor CSN1 is connected to the inverting input of the margin amplifier AMP. The non-inverting input and inverting output of the margin amplifier AMP are connected together through feedback capacitor CFP, and the inverting input and non-inverting output of the margin amplifier AMP are connected together through feedback capacitor CFN. The first terminal of sampling capacitor CSP2 is connected to the reference voltage signal VRP, the first terminal of sampling capacitor CSN2 is connected to the reference voltage signal VRN, and the second terminals of sampling capacitors CSP2 and CSN2 are connected to the second terminal of integrating capacitor CRF. At this time, the common-mode voltage of the first terminals of sampling capacitors CSP1 and CSN1 and sampling capacitors CSP2 and CSN2 is the second common-mode voltage VCMR = (VRP + VRN) / 2, the common-mode voltage of the second terminals of sampling capacitors CSP1 and CSN1 is the input common-mode voltage VCMB of the margin amplifier AMP, and the common-mode voltage of the second terminals of sampling capacitors CSP2 and CSN2 is the preset input common-mode voltage VCMA.

[0051] For the fully differential switched capacitor circuit 1000, during the sampling phase, the first terminal of the first sampling capacitor bank samples the first common-mode voltage VCMI, and the common-mode voltage at the second terminal of the first sampling capacitor bank is the common-mode reference voltage VCMS. During the hold phase, the first terminal of the first sampling capacitor bank is disconnected from the analog input signals VIP and VIN and connected to the reference voltage signals VRN and VRP to sample the second common-mode voltage VCMR. The common-mode voltage at the second terminal of the first sampling capacitor bank is the input common-mode voltage VCMB of the margin amplifier AMP. Therefore, when switching from the sampling phase to the hold phase, the common-mode voltage at the first terminal of the first sampling capacitor bank changes from VCMI to VCMR, and the common-mode voltage at the second terminal changes from VCMS to VCMB. At the end of the sampling phase and the beginning of the hold phase, according to the principle of charge conservation, the charge on the first sampling capacitor bank remains unchanged, so VCMR - VCMI = VCMB - VCMS, that is, VCMB = VCMR - VCMI + VCMS. From the relationship, it can be seen that the input common-mode voltage VCMB of the margin amplifier AMP can be adjusted by changing the common-mode reference voltage VCMS.

[0052] For the common-mode voltage adjustment circuit 2000, during the hold phase, the first terminal of the second sampling capacitor group CR samples the second common-mode voltage VCMR. The second terminal of the second sampling capacitor group CR is connected to the second terminal of the integrating capacitor CRF. The voltage at the first terminal of the integrating capacitor CRF is the common-mode reference voltage VCMS at the end of the previous phase, and the voltage at the second terminal of the integrating capacitor CRF is the preset input common-mode voltage VCMA. That is, the integrating capacitor CRF stores the difference between the common-mode reference voltage VCMS at the end of the previous phase and the preset input common-mode voltage VCMA. During the sampling phase, the first terminal of the second sampling capacitor group CR samples the first common-mode voltage VCMI. The second terminal of the second sampling capacitor group CR is connected to the first terminal of the integrating capacitor CRF. The first terminal of the integrating capacitor CRF provides the common-mode reference voltage VCMS, and the second terminal is the preset input common-mode voltage VCMA. After switching from the hold phase to the sampling phase, according to the principle of charge conservation, when the input common-mode voltage VCMB of the margin amplifier AMP is not equal to the preset input common-mode voltage VCMA, the charge on the second sampling capacitor group CR and the integrating capacitor CRF will be shared, causing the common-mode reference voltage VCMS to change.

[0053] Assuming that the common-mode reference voltage VCMS is low at the end of the sampling phase of the first cycle, causing the input common-mode voltage VCMB of the hold phase margin amplifier AMP to be different from the preset input common-mode voltage VCMA, then in the sampling phase of the second cycle, the second sampling capacitor group CR and the integrating capacitor CRF of the common-mode voltage adjustment circuit 2000 share charge, causing the common-mode reference voltage VCMS to rise. After several cycles of charge sharing, the adjustment capacitor VCMS will gradually tend towards VCMS = VCMA + VCMI - VCMR. Therefore, according to VCMB = VCMR - VCMI + VCMS = VCMR - VCMI + VCMA + VCMI - VCMR = VCMA, the input common-mode voltage VCMB of the margin amplifier AMP tends towards the preset input common-mode voltage VCMA, thus enabling the margin amplifier AMP to operate in its optimal state. For details on the changes in the common-mode reference voltage VCMS, please refer to [link to relevant documentation]. Figure 5 .

[0054] Furthermore, the adjustment step size of the common-mode reference voltage VCMS can be changed by altering the ratio of the equivalent capacitance of the second sampling capacitor group CR to the capacitance of the integrating capacitor CRF.

[0055] Furthermore, the reference voltage signal VRN / VRP can be grounded, which allows the MDAC circuit to have one less buffer, thereby further saving power and area.

[0056] Furthermore, the present invention also provides a pipelined ADC, including the MDAC circuit described above.

[0057] The pipelined ADC and its MDAC circuit provided in this embodiment of the invention include a fully differential switched capacitor circuit 1000 and a common-mode voltage adjustment circuit 2000. The fully differential switched capacitor circuit 1000 includes a first sampling capacitor bank and a margin amplifier AMP. The common-mode voltage adjustment circuit 2000 includes a second sampling capacitor bank CR and an integrating capacitor CRF. The second sampling capacitor bank CR samples the first common-mode voltage VCMI related to the analog input signal VIP / VIN in response to the clock signal CKS, and samples the second common-mode voltage related to the reference voltage signal VRN / VRP in response to the clock signal CKH. The voltage VCMR is sampled, and the sampling result is calculated on the integrating capacitor CRF along with the preset input common-mode voltage VCMA to obtain the common-mode reference voltage VCMS. During the holding phase, the integrating capacitor CRF stores the difference between the common-mode reference voltage VCMS at the end of the previous phase and the preset input common-mode voltage VCMA. During the sampling phase, it shares charge with the second sampling capacitor group CR, causing the common-mode reference voltage VCMS to change. Ultimately, the common-mode reference voltage VCMS tends to a stable value, ensuring that the input common-mode voltage VCMB of the margin amplifier AMP reaches the preset input common-mode voltage VCMA.

[0058] Furthermore, the embodiments of the present invention use an integrating capacitor CRF as a passive integrator, which is simple to implement, has low power consumption, and the adjustment range of the common-mode reference voltage VCMS is not limited by the output swing of the active integrator operational amplifier.

[0059] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. An MDAC circuit, comprising: A fully differential switched capacitor circuit includes a first sampling capacitor bank and a margin amplifier. A first terminal of the first sampling capacitor bank is connected to an analog input signal in response to a first clock signal and to a reference voltage signal in response to a second clock signal. A second terminal of the first sampling capacitor bank is connected to the input terminal of the margin amplifier in response to the second clock signal. A common-mode voltage adjustment circuit is configured to provide a common-mode reference voltage during the valid phase of the first clock signal to set a common-mode voltage at the second terminal of the first sampling capacitor bank, and to ensure that the input common-mode voltage of the margin amplifier reaches a preset input common-mode voltage during the valid phase of the second clock signal. The common-mode voltage adjustment circuit includes a second sampling capacitor group and an integrating capacitor. The second sampling capacitor group samples the first common-mode voltage related to the analog input signal in response to the first clock signal, and samples the second common-mode voltage related to the reference voltage signal in response to the second clock signal. The sampling result is then calculated on the integrating capacitor along with the preset input common-mode voltage to obtain the common-mode reference voltage.

2. The MDAC circuit of claim 1, wherein, The common-mode reference voltage = the first common-mode voltage + the preset input common-mode voltage - the second common-mode voltage.

3. The MDAC circuit according to claim 1, wherein, In response to the first clock signal, the first terminal of the second sampling capacitor group is connected to the first common-mode voltage, and the second terminal of the second sampling capacitor group is connected to the first terminal of the integrating capacitor. In response to the second clock signal, the first terminal of the second sampling capacitor group is connected to the second common-mode voltage, and the second terminal of the second sampling capacitor group is connected to the second terminal of the integrating capacitor.

4. The MDAC circuit of claim 1, wherein, The preset input common-mode voltage is the input common-mode voltage expected by the margin amplifier.

5. The MDAC circuit of claim 1, wherein, A buffer is provided between the first end of the integrating capacitor and the second end of the first sampling capacitor group.

6. The MDAC circuit of claim 1, wherein, The second sampling capacitor bank includes: The first sampling capacitor has its first terminal connected to a first reference voltage signal via a first switch and to a first analog input signal via a second switch. The second sampling capacitor has its first terminal connected to a second analog input signal via a third switch and a second reference voltage signal via a fourth switch, and its second terminal connected to the second terminal of the first sampling capacitor. The second terminal of the second sampling capacitor is also connected to the second terminal of the integrating capacitor via a fifth switch, and to the first terminal of the integrating capacitor via a sixth switch. The first common-mode voltage is the average voltage of the first analog input signal and the second analog input signal, and the second common-mode voltage is the average voltage of the first reference voltage signal and the second reference voltage signal.

7. The MDAC circuit of claim 6, wherein, The first reference voltage signal or the second reference voltage signal is ground voltage.

8. The MDAC circuit of claim 1, wherein, The adjustment step size of the common-mode reference voltage is adjusted by changing the ratio of the equivalent capacitance of the second sampling capacitor group to the capacitance of the integrating capacitor, and the effective phases of the first clock signal and the second clock signal do not overlap.

9. The MDAC circuit of claim 1, wherein, The first sampling capacitor group includes a third sampling capacitor and a fourth sampling capacitor. The first end of the third sampling capacitor is simultaneously connected to the first ends of the seventh, eighth, and ninth switches. The second end of the seventh switch is connected to the first analog input signal. The second end of the eighth switch is connected to the second reference voltage signal. The second end of the ninth switch is connected to the first reference voltage signal. A tenth switch is connected between the second end of the third sampling capacitor and the common-mode reference voltage. An eleventh switch is connected between the second end of the third sampling capacitor and the non-inverting input of the margin amplifier. The first terminal of the fourth sampling capacitor is simultaneously connected to the first terminals of the twelfth, thirteenth, and fourteenth switches. The second terminal of the twelfth switch is connected to the second analog input signal. The second terminal of the thirteenth switch is connected to the second reference voltage signal. The second terminal of the fourteenth switch is connected to the first reference voltage signal. A fifteenth switch is connected between the second terminal of the fourth sampling capacitor and the common-mode reference voltage. A sixteenth switch is connected between the second terminal of the fourth sampling capacitor and the inverting input terminal of the margin amplifier. A first feedback capacitor and a seventeenth switch are connected between the non-inverting input terminal and the inverting output terminal of the margin amplifier. A second feedback capacitor and an eighteenth switch are connected between the inverting input terminal and the non-inverting output terminal of the margin amplifier. The non-inverting output terminal of the margin amplifier provides a first output signal, and the inverting output terminal of the margin amplifier provides a second output signal.

10. A pipelined analog-to-digital converter, comprising the MDAC circuitry as described in any one of claims 1-9.

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