A wideband signal decimation method and system based on polyphase filtering
By performing phase transformation and polyphase filtering on 2N baseband signals in a broadband signal system, the problem that traditional filtering structures cannot achieve N-fold decimation is solved, thus realizing efficient signal reduction and accurate decimation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INST OF RADIO MEASUREMENT
- Filing Date
- 2023-10-19
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technologies cannot achieve N-fold decimation in broadband digital signal systems. Traditional polyphase filter structures can only achieve 2N-fold decimation, which cannot meet the requirements of high sampling rates.
By performing phase transformation or reversal operations on the 2N baseband signals and processing the signals using polyphase filtering techniques, including duplication, delay, polyphase filtering, and summation operations, N-fold decimation is ultimately achieved.
This method achieves N-fold decimation in broadband signal systems, reducing the data stream rate and increasing signal processing speed. The accuracy of the decimation results is verified through spectrum comparison.
Smart Images
Figure CN117478155B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radio technology. More specifically, it relates to a broadband signal extraction method and system based on polyphase filtering. Background Technology
[0002] Software-defined radio (SDR) is based on modern communication theory, uses digital signal processing as its core, and is supported by microelectronics technology. It breaks through the limitations of traditional radio hardware, which has single function and poor scalability.
[0003] The core idea of software-defined radio (SDR) is to digitize radio frequency (RF) analog signals, transforming them into a data stream suitable for digital signal processors (DSPs). Then, various functions are performed through software algorithms, and high-speed A / D converters are placed as close as possible to the RF front end to directly sample and digitize the RF signals. This requires the A / D converter to have a high sampling rate and a high operating bandwidth. However, the problem with increasing the sampling rate is that the data stream rate after sampling is very high, causing the subsequent signal processing speed to lag behind. Therefore, it is necessary to perform decimation processing on the data stream after A / D conversion to achieve the purpose of speed reduction.
[0004] Currently, for broadband digital signal systems, A / D converters generally improve the sampling rate by outputting multiple data channels. For example, the AD9680 module outputs 2N data channels. However, using a traditional polyphase filter structure, only 2N times decimation can be achieved, not N times decimation. Summary of the Invention
[0005] The purpose of this invention is to provide a broadband signal extraction method and system based on multiphase filtering, which achieves N-fold signal extraction by performing phase transformation or reversal operation on 2N baseband signals, thereby solving at least one of the problems existing in the prior art.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] The first aspect of this invention provides a broadband signal extraction method based on polyphase filtering, comprising:
[0008] The intermediate frequency signal is converted from analog to digital to obtain a digital signal;
[0009] The digital signal is mixed to obtain 2N channels of the first baseband signal; where N is an integer greater than 1.
[0010] Copy 2N channels of the first baseband signal to obtain 2N channels of the second baseband signal;
[0011] The 2N channels of the first baseband signal are reversed to obtain the 2N channels of the first operation signal;
[0012] The second baseband signals from the first to the Nth channels are reversed, and the second baseband signals from the (N+1)th to the 2Nth channels are delayed by one clock cycle to obtain 2N second operation signals;
[0013] The 2N first operation signals are subjected to polyphase filtering respectively, and the filtered 2N first operation signals are summed to obtain the first filtering result;
[0014] The 2N second operation signals are subjected to polyphase filtering respectively, and the filtered 2N second operation signals are summed to obtain the second filtering result;
[0015] The first and second filtering results are combined to obtain an N-fold decimation result, where the phase of the second filtering result leads the phase of the first filtering result.
[0016] Furthermore, the step of performing polyphase filtering on the 2N first operation signals includes performing convolution operations on each first operation signal with the corresponding polyphase filtered component, and the step of performing polyphase filtering on the 2N second operation signals includes performing convolution operations on each second operation signal with the corresponding polyphase filtered component.
[0017] Furthermore, before merging the first filtering result and the second filtering result to obtain the N-fold extraction result, the method further includes responding to a user setting operation, obtaining the truncation bit, and respectively truncating the portion of the first filtering result and the second filtering result whose median is greater than the truncation bit.
[0018] Furthermore, after merging the first filtering result and the second filtering result to obtain the N-fold decimation result, the method further includes plotting the spectrum of the N-fold decimation signal based on the N-fold decimation result.
[0019] Plot the spectrum of the original signal after filtering and then decimating the 2N-channel first baseband signal by a factor of N;
[0020] Compare the spectrum of the N-fold decimated signal with the spectrum of the original signal to determine whether the data in the N-fold decimated signal spectrum is consistent with the corresponding data in the original signal spectrum: if yes, the N-fold decimation result is correct; otherwise, the N-fold decimation result is incorrect.
[0021] The second invention provides a broadband signal extraction system based on polyphase filtering, comprising:
[0022] The analog-to-digital converter module is used to convert intermediate frequency signals into digital signals and output them as digital signals.
[0023] The mixing module is used to mix digital signals separately and output 2N channels of first baseband signals, where N is an integer greater than 1.
[0024] The copy module is used to copy 2N channels of the first baseband signal and output 2N channels of the second baseband signal.
[0025] The operation module is used to reverse the order of 2N first baseband signals and output 2N first operation signals; it is also used to reverse the order of the first to Nth second baseband signals and delay the second baseband signals of the (N+1)th to 2Nth channels by one clock cycle and output 2N second operation signals.
[0026] The multiphase filtering module is used to perform multiphase filtering on 2N first operation signals, sum the filtered phase data and output the first filtering result, and also to perform multiphase filtering on 2N second operation signals, sum the filtered phase data and output the second filtering result.
[0027] The merging module is used to merge the first filtering result and the second filtering result and output an N-fold decimation result, wherein the phase of the second filtering result leads the phase of the first filtering result.
[0028] Furthermore, the multiphase filtering module is a prototype low-pass filter with multiphase components.
[0029] Furthermore, the system also includes a truncation module, which is used to respond to user setting operations, obtain the truncation bit, and truncate the portion of the first filtering result and the second filtering result whose median is greater than the truncation bit.
[0030] Furthermore, the system also includes a verification module, which comprises a spectrum generation module and a judgment module.
[0031] The spectrum generation module plots the spectrum of the N-fold decimation signal based on the N-fold decimation result; and plots the spectrum of the original signal after filtering and then decimating the 2N first baseband signals.
[0032] The judgment module is used to compare the spectrum of the N-fold extracted signal with the spectrum of the original signal to determine whether the data in the N-fold extracted signal spectrum is consistent with the corresponding data in the spectrum of the original signal: if so, the N-fold extraction result is determined to be correct; otherwise, the N-fold extraction result is determined to be incorrect.
[0033] Furthermore, the decimation factor of the multiphase filter module is 2N.
[0034] Furthermore, the system is implemented based on a field-programmable gate array (FPGA).
[0035] The beneficial effects of this invention are as follows:
[0036] This invention performs phase transformation or reversal operations on 2N first baseband signals and 2N second baseband signals through an operation module, performs multiphase filtering and summation through a multiphase filtering module, and finally merges the first and second filtering results through a merging module, thereby realizing N-fold decimation of 2N parallel output signals. Attached Figure Description
[0037] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0038] Figure 1 A flowchart of a broadband signal extraction method based on polyphase filtering according to an embodiment of the present invention is shown.
[0039] Figure 2 This diagram illustrates a broadband signal extraction system based on polyphase filtering, provided in an embodiment of the present invention, with no interception module and no verification module.
[0040] Figure 3 This diagram illustrates a broadband signal extraction system based on polyphase filtering, provided by an embodiment of the present invention, which includes an extraction module and a verification module.
[0041] Figure 4 A schematic diagram of the structure of a verification module provided in one embodiment of the present invention is shown.
[0042] Figure 5 A schematic diagram of the structure of a multiphase filtering module provided in an embodiment of the present invention is shown.
[0043] Figure 6 This diagram illustrates the structure of a multiphase filtering module for acquiring 2x decimation results and downsampling to 4 for 4-channel digital signals according to an embodiment of the present invention.
[0044] Figure 7 This diagram illustrates the structure of the extraction result output by the multiphase filtering module after directly inputting four first baseband signals into the multiphase filtering module according to an embodiment of the present invention.
[0045] Figure 8 This diagram illustrates the structure of a multiphase filter module, which performs phase transformation or reversal operations on four first baseband signals and four second baseband signals according to an embodiment of the present invention, and outputs the extraction result after the multiphase filter module. Detailed Implementation
[0046] To more clearly illustrate the present invention, the following description, in conjunction with embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.
[0047] like Figure 1 As shown, one embodiment of the present invention provides a broadband signal extraction method based on polyphase filtering, comprising:
[0048] Step S1: Convert the intermediate frequency signal into a digital signal by analog-to-digital conversion;
[0049] Step S2: Mix the digital signal to obtain 2N channels of the first baseband signal; where N is an integer greater than 1.
[0050] Step S3: Copy 2N channels of the first baseband signal to obtain 2N channels of the second baseband signal;
[0051] Step S4: Perform reverse order operation on the 2N channels of the first baseband signal to obtain the 2N channels of the first operation signal;
[0052] Step S5: Reverse the order of the second baseband signals from the 1st to the Nth channels and delay the second baseband signals from the (N+1)th to the 2Nth channels by one clock cycle to obtain 2N second operation signals;
[0053] Step S6: Perform polyphase filtering on the 2N first operation signals respectively, and sum the filtered 2N first operation signals to obtain the first filtering result;
[0054] Step S7: Perform polyphase filtering on the 2N second operation signals respectively, and sum the filtered 2N second operation signals to obtain the second filtering result;
[0055] Step S8: Combine the first filtering result and the second filtering result to obtain an N-fold extraction result, wherein the phase of the second filtering result leads the first filtering result.
[0056] In one possible implementation, performing polyphase filtering on the 2N first operation signals includes convolving each first operation signal with its corresponding polyphase filtered component, and performing polyphase filtering on the 2N second operation signals includes convolving each second operation signal with its corresponding polyphase filtered component.
[0057] In one possible implementation, before merging the first filtering result and the second filtering result to obtain the N-fold extraction result, the method further includes responding to a user setting operation, obtaining the truncation bit, and truncating the portion of the first filtering result and the second filtering result whose median is greater than the truncation bit.
[0058] In one possible implementation, after merging the first filtering result and the second filtering result to obtain the N-fold decimation result, the method further includes plotting the spectrum of the N-fold decimation signal based on the N-fold decimation result.
[0059] Plot the spectrum of the original signal after filtering and then decimating the 2N-channel first baseband signal by a factor of N;
[0060] Compare the spectrum of the N-fold decimated signal with the spectrum of the original signal to determine whether the data in the N-fold decimated signal spectrum is consistent with the corresponding data in the original signal spectrum: if yes, the N-fold decimation result is correct; otherwise, the N-fold decimation result is incorrect.
[0061] In this invention, filtering the 2N first baseband signals and then decimating them by N times is a traditional decimation method in the prior art. This invention compares the decimation results with the traditional decimation method to achieve the purpose of verifying the decimation results.
[0062] like Figure 2 As shown, another embodiment of the present invention provides a broadband signal decimation system based on polyphase filtering, comprising:
[0063] The analog-to-digital converter module is used to convert intermediate frequency signals into digital signals and output them as digital signals.
[0064] The mixing module is used to mix digital signals and output 2N channels of first baseband signals; where N is an integer greater than 1.
[0065] The copy module is used to copy 2N channels of the first baseband signal and output 2N channels of the second baseband signal;
[0066] The operation module is used to reverse the order of 2N first baseband signals and output 2N first operation signals; it is also used to reverse the order of the first to Nth second baseband signals and delay the N+1 to 2Nth second baseband signals by one clock cycle and output 2N second operation signals.
[0067] The multiphase filtering module is used to perform multiphase filtering on 2N first operation signals respectively, sum the filtered phase data and output the first filtering result, and also to perform multiphase filtering on 2N second operation signals respectively, sum the filtered phase data and output the second filtering result.
[0068] The merging module is used to merge the first filtering result and the second filtering result and output an N-fold decimation result, wherein the phase of the second filtering result leads the phase of the first filtering result.
[0069] In one possible implementation, the decimation factor of the polyphase filter module is 2N.
[0070] In one possible implementation, the system is based on a field-programmable gate array (FPGA).
[0071] More specifically, in this embodiment, the analog-to-digital conversion module uses the AD9680 module;
[0072] The polyphase filter module is an equal-ripple low-pass filter designed using MATLAB. It has a sampling frequency of 1 GHz, a passband frequency of 200 MHz, a stopband frequency of 250 MHz, an order of 48, an in-band flatness of less than 0.5 dB, and an out-of-band rejection of less than 70 dB. After generating the prototype filter coefficients h(n), these coefficients are divided into four groups, each representing the polyphase components of the prototype low-pass filter, with formats h(4n), h(4n+1), h(4n+2), and h(4n+3).
[0073] This invention performs phase transformation or reversal operations on 2N first baseband signals and 2N second baseband signals through an operation module, performs multiphase filtering and summation through a multiphase filtering module, and finally merges the first and second filtering results through a merging module, thereby realizing N-decimation of 2N parallel output signals.
[0074] In one possible implementation, the multiphase filtering module is a multiphase component of a prototype low-pass filter.
[0075] In one possible implementation, such as Figure 3 As shown, the system also includes a truncation module, which is used to respond to user setting operations, obtain the truncation bit, and truncate the portion of the first filtering result and the second filtering result whose median is greater than the truncation bit.
[0076] In one possible implementation, such as Figure 3 and Figure 4 As shown, the system also includes a verification module, which includes a spectrum generation module and a judgment module;
[0077] The spectrum generation module plots the spectrum of the N-fold decimation signal based on the N-fold decimation result; and plots the spectrum of the original signal after filtering and then decimating the 2N first baseband signals.
[0078] The judgment module is used to compare the spectrum of the N-fold extracted signal with the spectrum of the original signal to determine whether the data in the N-fold extracted signal spectrum is consistent with the corresponding data in the spectrum of the original signal: if so, the N-fold extraction result is determined to be correct; otherwise, the N-fold extraction result is determined to be incorrect.
[0079] In a specific example, this embodiment provides a method, system, device, and storage medium for broadband signal extraction based on polyphase filtering. The system of this invention is a digital circuit based on an FPGA. An FPGA is a type of programmable logic device that fully utilizes EDA technology for device development and application. Currently, FPGAs have become one of the mainstream platforms for implementing digital systems. An FPGA consists of several independent programmable logic modules, which users can connect to form the desired digital system through programming. The Xilinx XC7VX690T chip is selected as the core device for signal processing. The Xilinx Vivado software Simulink environment can be used to simulate and verify the results, and the algorithm can be converted into a reliable hardware implementation.
[0080] The intermediate frequency signal is sampled by the AD9680 module and output as a digital signal in four parallel channels with a sampling rate of 1 GHz and a data clock of 250 MHz for each channel.
[0081] The specific steps are as follows:
[0082] The intermediate frequency signal is converted from analog to digital by the AD9680 module and output as 4 digital signals; and after mixing by the mixer module, 4 first baseband signals are output.
[0083] The four first baseband signals are signed 16-bit integer data, and the four data formats are x(4n), x(4n+1), x(4n+2), and x(4n+3), respectively.
[0084] After obtaining the four first baseband signals, as Figure 5 As shown, the multiphase filtering module is a prototype low-pass filter with multiphase components. It adopts a multiphase filtering structure with a decimator. In this embodiment, a downsampling followed by filtering method is used. The multiphase filtering structure when the downsampling D=4 is as follows. Figure 6 As shown, according to Figure 6 The middle dashed section yields the following result: Figure 7 The results show that when the first baseband signal is directly input into the polyphase filter module, the output is a 4x decimation result.
[0085] To transform the 4x decimation result into a 2x decimation result, this invention performs relevant phase transformation or inversion operations on the first baseband signal, as follows:
[0086] The first baseband signal is copied by the copy module to obtain four second baseband signals; at this time, there are a total of eight signals, including the first baseband signal and the second baseband signal.
[0087] like Figure 8As shown, the four first baseband signals are reversed to obtain four first operation signals; the first and second second baseband signals are reversed and the third and fourth second baseband signals are delayed by one clock cycle to obtain four second operation signals; the four first operation signals are polyphase filtered, and the filtered four first operation signals are summed to obtain a first filtering result; the four second operation signals are polyphase filtered, and the filtered four second operation signals are summed to obtain a second filtering result. The polyphase filtering of the four first operation signals includes convolving each first operation signal with its corresponding polyphase filtered component, and the polyphase filtering of the four second operation signals includes convolving each second operation signal with its corresponding polyphase filtered component. This section utilizes the Xilinx IP core FIR Compiler 7.2 to input four sets of filter coefficients into four polyphase filtering modules. An asymmetric structure is chosen for the IP core coefficients. After convolution, truncation is crucial; excess data bits are removed while maintaining the original data precision to avoid unnecessary resource consumption. The polyphase filtering result obtained from the four first operation signals is y(4n+3), and the polyphase filtering result obtained from the four second operation signals is y(4n+1).
[0088] The first and second filtering results are combined to obtain a 2-decimation result, in which the phase of the second filtering result leads the phase of the first filtering result.
[0089] Finally, to verify the correctness of the 2x decimation result, the 2x decimation result was output, and then the spectrum of the 2x decimation signal was plotted using the MATLAB module.
[0090] Plot the spectrum of the original signal after filtering and then decimating the four first baseband signals by a factor of 2.
[0091] Compare the spectrum of the 2x decimated signal with the spectrum of the original signal to determine whether the data in the spectrum of the 2x decimated signal is consistent with the corresponding data in the spectrum of the original signal: if they are consistent, the 2x decimation result is considered to be correct; otherwise, the 2x decimation result is considered to be incorrect.
[0092] In summary, in this embodiment, the present invention utilizes polyphase filtering technology to solve the problem of decimating four parallel output signals by a factor of two through channel transformation. Computer simulation results verify the correctness of the structure. Furthermore, this structure is implemented using an FPGA, improving the speed of multi-channel parallel processing. In addition, the present invention reverses the order of four first baseband signals and outputs four first operation signals through an operation module; it reverses the order of the first and second second baseband signals and delays the third and fourth second baseband signals by one clock cycle to obtain four second operation signals. Decimating four parallel signals by a factor of two can be achieved simply through delay and reversal operations. This method is simple and reduces the complexity and resource utilization of the polyphase filtering module, as well as its processing speed, enabling better real-time processing. Simultaneously, parallel processing fully demonstrates the characteristics of efficient resource reuse.
[0093] Those skilled in the art should understand that although the above steps are described in the order of S1-S8, it does not mean that they must be executed in this order. For example, S5 can be executed first, followed by S4, as long as it does not violate the logic.
[0094] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.
[0095] It should also be noted that in the description of this invention, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0096] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.
Claims
1. A broadband signal extraction method based on polyphase filtering, characterized in that, include: The intermediate frequency signal is converted from analog to digital to obtain a digital signal; The digital signal is mixed to obtain 2N channels of the first baseband signal; where N is an integer greater than 1. Copy 2N channels of the first baseband signal to obtain 2N channels of the second baseband signal; The 2N channels of the first baseband signal are reversed to obtain the 2N channels of the first operation signal; The second baseband signals from the first to the Nth channels are reversed, and the second baseband signals from the (N+1)th to the 2Nth channels are delayed by one clock cycle to obtain 2N second operation signals; The 2N first operation signals are subjected to polyphase filtering respectively, and the filtered 2N first operation signals are summed to obtain the first filtering result; The 2N second operation signals are subjected to polyphase filtering respectively, and the filtered 2N second operation signals are summed to obtain the second filtering result; The first and second filtering results are combined to obtain an N-fold decimation result, where the phase of the second filtering result leads the phase of the first filtering result.
2. The method according to claim 1, characterized in that, The step of performing polyphase filtering on the 2N first operation signals includes performing convolution operations on each first operation signal with its corresponding polyphase filter component. The step of performing polyphase filtering on the 2N second operation signals includes performing convolution operations on each second operation signal with its corresponding polyphase filter component.
3. The method according to claim 1, characterized in that, Before merging the first filtering result and the second filtering result to obtain the N-fold extraction result, the method further includes: responding to the user setting operation, obtaining the truncation number, and truncating the portion of the first filtering result and the second filtering result whose median is greater than the truncation number.
4. The method according to claim 1, characterized in that, After merging the first and second filtering results to obtain an N-fold extraction result, the method further includes: Plot the spectrum of the N-fold decimation signal based on the N-fold decimation result; Plot the spectrum of the original signal after filtering and then decimating the 2N-channel first baseband signal by a factor of N; Compare the spectrum of the N-fold decimated signal with the spectrum of the original signal to determine whether the data in the N-fold decimated signal spectrum is consistent with the corresponding data in the original signal spectrum: if yes, the N-fold decimation result is correct; otherwise, the N-fold decimation result is incorrect.
5. A broadband signal decimation system based on polyphase filtering, characterized in that, include, The analog-to-digital converter module is used to convert intermediate frequency signals into digital signals and output them as digital signals. The mixing module is used to mix digital signals and output 2N channels of first baseband signals; where N is an integer greater than 1. The copy module is used to copy 2N channels of the first baseband signal and output 2N channels of the second baseband signal; The operation module is used to reverse the order of 2N first baseband signals and output 2N first operation signals; it is also used to reverse the order of the first to Nth second baseband signals and delay the N+1 to 2Nth second baseband signals by one clock cycle and output 2N second operation signals. The multiphase filtering module is used to perform multiphase filtering on 2N first operation signals respectively, sum the filtered phase data and output the first filtering result, and also to perform multiphase filtering on 2N second operation signals respectively, sum the filtered phase data and output the second filtering result. The merging module is used to merge the first filtering result and the second filtering result and output an N-fold decimation result, wherein the phase of the second filtering result leads the phase of the first filtering result.
6. The system according to claim 5, characterized in that, The multiphase filtering module is a prototype low-pass filter with multiphase components.
7. The system according to claim 5, characterized in that, The system also includes a truncation module, which is used to respond to user setting operations, obtain the truncation bit, and truncate the portion of the first filtering result and the second filtering result whose median is greater than the truncation bit.
8. The system according to claim 5, characterized in that, The system also includes a verification module, which includes a spectrum generation module and a judgment module. The spectrum generation module plots the spectrum of the N-fold decimation signal based on the N-fold decimation result; and plots the spectrum of the original signal after filtering and then decimating the 2N first baseband signals. The judgment module is used to compare the spectrum of the N-fold extracted signal with the spectrum of the original signal to determine whether the data in the N-fold extracted signal spectrum is consistent with the corresponding data in the spectrum of the original signal: if so, the N-fold extraction result is determined to be correct; otherwise, the N-fold extraction result is determined to be incorrect.
9. The system according to claim 5, characterized in that, The decimation factor of the multiphase filter module is 2N.
10. The system according to claim 5, characterized in that, The system is based on a field-programmable gate array (FPGA).