Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel, comprising: a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units; the plurality of scan lines are arranged on the substrate at intervals along the column direction; the plurality of data lines are arranged on the substrate at intervals along the row direction; the pixel unit is arranged between two adjacent data lines, the pixel unit comprises a thin film transistor, a switching electrode and a pixel electrode, the thin film transistor is electrically connected to the scan line and the data line, two switching electrodes located in the row direction are arranged on both sides of the scan line, the switching electrode comprises a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole, the second sub-switching electrode is electrically connected to the first sub-switching electrode, and the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction. The advantage is that the problem of dark spots on the display panel can be avoided, and the display effect of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to an array substrate and a display panel. Background Art

[0002] The pixel density of LCD displays for VR products has exceeded 1500PPI and will develop towards 1700PPI and 2000PPI.

[0003] When the PPI of the LCD display is higher, the size of the pixel unit in the LCD display will be smaller; the size of two adjacent through holes along the row direction on the array substrate is limited by the process and cannot be reduced as the size of the pixel unit is reduced, resulting in the distance between the first via hole and the data line on the array substrate and the distance between the first via hole and the transfer electrode cannot meet the safety distance. During the manufacturing process of the array substrate, once an error occurs in the process, the transfer electrode cannot completely cover the first via hole. Then, when etching the transfer electrode, the etching solution used to etch the transfer electrode will enter the first via hole and etch the drain of the thin film transistor, causing the transfer electrode to be unable to charge, resulting in dark spots on the display panel. Summary of the invention

[0004] The purpose of the present application is to provide an array substrate and a display panel to solve the problem of dark spots on the display panel.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising:

[0006] substrate;

[0007] A plurality of scanning lines, wherein the plurality of scanning lines are arranged on the substrate at intervals along a column direction;

[0008] A plurality of data lines, wherein the plurality of data lines are arranged on the substrate at intervals along a row direction;

[0009] A plurality of pixel units, wherein the pixel unit is arranged between two adjacent data lines, the pixel unit includes a thin film transistor, a switching electrode and a pixel electrode, the thin film transistor is electrically connected to the scan line and the data line, the pixel electrode is electrically connected to the switching electrode, two adjacent switching electrodes located in the row direction are arranged on both sides of the scan line, the switching electrode includes a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating a film layer between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, the second sub-switching electrode is electrically connected to the first sub-switching electrode, and the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction.

[0010] Furthermore, the orthographic projection of the first sub-switching electrode on the substrate is located on one side of the orthographic projection of the scanning line on the substrate, and the orthographic projection of the second sub-switching electrode on the substrate overlaps with the orthographic projection of the scanning line on the substrate.

[0011] Furthermore, the orthographic projections of the first sub-switching electrode and the second sub-switching electrode on the substrate are both located on one side of the orthographic projection of the scanning line on the substrate.

[0012] Furthermore, along the positive direction of the row direction, the first sub-switching electrode has a first protruding portion relative to the first via hole, and along the negative direction of the row direction, the first sub-switching electrode has a second protruding portion relative to the first via hole.

[0013] Furthermore, along a direction parallel to the column direction and opposite to the second sub-switching electrode, the first sub-switching electrode has a third protruding portion relative to the first via hole.

[0014] Furthermore, the edges of the first protruding portion and the second protruding portion are both arc-shaped.

[0015] Furthermore, two adjacent switching electrodes located in the row direction are centrally symmetrical with respect to the intersection of the scanning line and the data line.

[0016] Furthermore, the second sub-switching electrodes of two adjacent switching electrodes in the column direction are both located on the same side of the first sub-switching electrodes of the switching electrodes.

[0017] Furthermore, the data lines located on both sides of the switching electrode are spaced equal to the switching electrode.

[0018] In a second aspect, an embodiment of the present invention provides a display panel, wherein the display panel comprises the array substrate.

[0019] Beneficial effects of the present invention:

[0020] The present application provides an array substrate, comprising: a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units; the plurality of scan lines are arranged on the substrate at intervals along a column direction; the plurality of data lines are arranged on the substrate at intervals along a row direction; the pixel unit is arranged between two adjacent data lines, the pixel unit comprises a thin film transistor, a switching electrode and a pixel electrode, the thin film transistor is electrically connected to the scan line and the data line, the pixel electrode is electrically connected to the switching electrode, two adjacent switching electrodes located in the row direction are arranged on both sides of the scan line, the switching electrode comprises a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating a film layer between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, and the second The sub-switching electrode is electrically connected to the first sub-switching electrode, and the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction; by setting the switching electrode to include the first sub-switching electrode and the second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating the film layer between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, the second sub-switching electrode is electrically connected to the first sub-switching electrode, the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction, when etching the switching electrode, it can be avoided that the etching liquid for etching the switching electrode enters the first via hole to etch the thin film transistor, causing the switching electrode to be unable to charge, resulting in the problem of dark spots on the display panel, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a top view of an array substrate in the prior art;

[0022] Figure 2 is a top view of the array substrate in the prior art when the transfer electrode does not completely cover the first via hole;

[0023] Figure 3 yes Figure 2 A scanning electron microscope image of the array substrate when the transfer electrode does not completely cover the first via hole;

[0024] Figure 4 is a top view of the first structure of the array substrate in the present application;

[0025] Figure 5 is a top view of the second structure of the array substrate in the present application;

[0026] Figure 6 yes Figure 5A cross-sectional view of the array substrate shown;

[0027] Figure 7 is a top view of the third structure of the array substrate in the present application;

[0028] Figure 8 is a top view of a fourth structure of the array substrate in the present application;

[0029] Fig. 9 is a top view of the fifth structure of the array substrate in the present application;

[0030] Fig.10 It is a top view of the sixth structure of the array substrate in the present application.

[0031] 100-scanning line; 200-data line; 300-pixel unit, 310-thin film transistor, 311-substrate, 312-first gate insulating layer, 313-gate metal layer, 314-second gate insulating layer, 315-semiconductor layer, 316-third gate insulating layer, 317-first interlayer insulating layer, 318-second interlayer insulating layer, 319-source metal, 320-first via hole, 330-transfer electrode, 331-first sub-transfer electrode, 3311-first protruding portion, 3312-second protruding portion, 3313-third protruding portion, 332-second sub-transfer electrode, 340-pixel electrode, 400-substrate; 500-reference axis. DETAILED DESCRIPTION

[0032] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of narrating and understanding this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0033] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0034] When the PPI of the LCD display is higher, the size of the pixel unit 300 in the LCD display will be smaller. Figure 1-Figure 3 The size of two adjacent through holes along the row direction on the array substrate is limited by the process and cannot be reduced as the size of the pixel unit 300 is reduced, resulting in the distance between the first via hole 320 and the data line 200 on the array substrate and the distance between the first via hole 320 and the transfer electrode 330 cannot meet the safety distance. During the manufacturing process of the array substrate, once an error occurs in the process, that is, the transfer electrode 330 is offset to one side of the reference axis 500, the transfer electrode 330 cannot completely cover the first via hole 320. When etching the transfer electrode 330, the etching liquid for etching the transfer electrode 330 will enter the first via hole 320 and etch the drain of the thin film transistor 310, causing the transfer electrode 330 to be unable to charge, resulting in the problem of dark spots on the display panel.

[0035] Therefore, an embodiment of the present invention provides a display panel, referring to Figure 4 The display panel includes an array substrate, an opposing substrate and a liquid crystal layer, wherein the liquid crystal layer is disposed between the array substrate and the opposing substrate; the array substrate includes a substrate, a plurality of scanning lines 100, a plurality of data lines 200 and a plurality of pixel units 300.

[0036] refer to Figure 4 In this embodiment, a plurality of scan lines 100 are arranged on the substrate at intervals along the column direction; a plurality of data lines 200 are arranged on the substrate at intervals along the row direction; a pixel unit 300 is arranged between two adjacent data lines 200, and the pixel unit 300 includes a thin film transistor 310, a switching electrode 330 and a pixel electrode 340, the thin film transistor 310 is electrically connected to the scan line 100 and the data line 200, the pixel electrode 340 is electrically connected to the switching electrode 330, the switching electrode 330 is connected to the thin film transistor 310 through a first via hole 320 penetrating a film layer between the thin film transistor 310 and the switching electrode 330, and the switching electrode 330 covers the first via hole 320, along the positive direction of the row direction, the switching electrode 330 extends a first protruding portion 3311 relative to the first via hole 320, and along the reverse direction of the row direction, the switching electrode 330 extends a second protruding portion 3312 relative to the first via hole 320.

[0037] In the positive direction of the row direction, the first protruding portion 3311 of the transfer electrode 330 is extended relative to the first via hole 320, and in the reverse direction of the row direction, the second protruding portion 3312 of the transfer electrode 330 is extended relative to the first via hole 320, thereby increasing the area of ​​the transfer electrode 330, so that the transfer electrode 330 can better cover the first via hole 320. When etching the transfer electrode 330, it is possible to prevent the etching liquid for etching the transfer electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, causing the transfer electrode 330 to be unable to charge, resulting in the problem of dark spots on the display panel, thereby improving the display effect of the display panel.

[0038] refer to Figure 5 In this embodiment, a plurality of scan lines 100 are arranged on the substrate at intervals along the column direction; a plurality of data lines 200 are arranged on the substrate at intervals along the row direction; a pixel unit 300 is arranged between two adjacent data lines 200, the pixel unit 300 includes a thin film transistor 310, a switching electrode 330 and a pixel electrode 340, the thin film transistor 310 is electrically connected to the scan line 100 and the data line 200, the pixel electrode 340 is electrically connected to the switching electrode 330, the switching electrode 330 includes a first sub-switching electrode 331 and a second sub-switching electrode 332, the first sub-switching electrode 331 is connected to the thin film transistor 310 through a first via hole 320 penetrating a film layer between the thin film transistor 310 and the switching electrode 330, and the first sub-switching electrode 331 covers the first via hole 320, the second sub-switching electrode 332 is electrically connected to the first sub-switching electrode 331, and a length L1 of the first sub-switching electrode 331 in the row direction is greater than a length L2 of the second sub-switching electrode 332 in the row direction.

[0039] By setting the transfer electrode 330 to include a first sub-transfer electrode 331 and a second sub-transfer electrode 332, the first sub-transfer electrode 331 is connected to the thin film transistor 310 through a first via hole 320 penetrating a film layer between the thin film transistor 310 and the transfer electrode 330, and the first sub-transfer electrode 331 covers the first via hole 320, the second sub-transfer electrode 332 is electrically connected to the first sub-transfer electrode 331, and the length L1 of the first sub-transfer electrode 331 in the row direction is greater than the length L2 of the second sub-transfer electrode 332 in the row direction. When etching the transfer electrode 330, it is possible to prevent the etching solution for etching the transfer electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, causing the transfer electrode 330 to be unable to charge, resulting in the problem of dark spots on the display panel, thereby improving the display effect of the display panel.

[0040] refer to Figure 6In this embodiment, the array substrate includes a substrate 400, a buffer layer 311 disposed on the substrate 400, a first gate insulating layer 312, a gate metal layer 313, a second gate insulating layer 314, a semiconductor layer 315, a third gate insulating layer 316, a first interlayer insulating layer 317, a second interlayer insulating layer 318, a source metal 319, a transfer electrode 330 (drain metal) and a pixel electrode 340. The source metal 319 is connected to the source of the semiconductor layer 315 through the second via hole, and the transfer electrodes 330320 are connected to the drain in the semiconductor layer 315 through the first via hole 320. Specifically, the first via hole 320 penetrates the second interlayer insulating layer 318, the first interlayer insulating layer 317 and the third gate insulating layer 316, so that the transfer electrode 330 is electrically connected to the drain of the semiconductor layer 315, the transfer electrode 330 is electrically connected to the drain of the semiconductor layer 315 through the first through hole 320, the pixel electrode 340 is electrically connected to the transfer electrode 330, and the second via hole penetrates the first interlayer insulating layer 317 and the third gate insulating layer 316, so that the source metal 319 is electrically connected to the source on the semiconductor layer 315.

[0041] In this embodiment, the length L1 of the first sub-transfer electrode 331 in the row direction is greater than the length L2 of the second sub-transfer electrode 332 in the row direction. Although this reduces the distance between two adjacent transfer electrodes 330, it is easy to cause the transfer electrodes 330 of two adjacent pixel units 300 on the array substrate to be short-circuited, resulting in a short circuit in the pixel unit 300. Therefore, two adjacent transfer electrodes 330 in the row direction are arranged on both sides of the scan line 100, increasing the distance between the two adjacent transfer electrodes 330 and reducing the probability of line short circuit or open circuit.

[0042] It should be noted that, since the first sub-switch electrode 331 covers the first via hole 320 , two adjacent first via holes 320 in the row direction are staggered, which increases the distance between the two first via holes 320 and reduces the difficulty of manufacturing the pixel unit 300 .

[0043] refer to Figure 5 , Figure 7 , Figure 8 and Fig.10 In this embodiment, the orthographic projection of the first sub-switching electrode 331 on the substrate 400 is located on one side of the orthographic projection of the scanning line 100 on the substrate 400 , and the orthographic projection of the second sub-switching electrode 332 on the substrate 400 overlaps with the orthographic projection of the scanning line 100 on the substrate 400 .

[0044] refer to Figure 8In this embodiment, when the switching electrode 330 is directly opposite to the scan line 100, the charge will form a short circuit path between the switching electrode 330 and the scan line 100, causing the charge to flow from the switching electrode 330 to the scan line 100, interfering with the normal operation of other pixel units 300. Therefore, the orthographic projections of the first sub-switching electrode 331 and the second sub-switching electrode 332 on the substrate 400 are both located on one side of the orthographic projection of the scan line 100 on the substrate 400, which can prevent the pixel unit 300 from being disturbed during operation, thereby improving the stability of the array substrate during operation.

[0045] refer to Figure 7 In this embodiment, along the positive direction of the row direction, the first sub-switching electrode 331 has a first protruding portion 3311 relative to the first via hole 320. By providing the first protruding portion 3311, the square area of ​​the first sub-switching electrode 331 in the row direction is increased, and the positive direction of the row direction of the first sub-switching electrode 331 of the switching electrode 330 is prevented from being too small, resulting in the first sub-switching electrode 331 of the switching electrode 330 not being able to completely cover the first via hole 320, thereby preventing the etching solution for etching the switching electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, thereby improving the display effect of the display panel.

[0046] refer to Figure 8 In this embodiment, along the opposite direction of the row direction, the first sub-transfer electrode 331 has a second protruding portion 3312 relative to the first via hole 320. By providing the second protruding portion 3312, the area of ​​the first sub-transfer electrode 331 in the opposite direction of the row direction is increased, so as to avoid the first sub-transfer electrode 331 of the transfer electrode 330 not being able to completely cover the first via hole 320 due to the area of ​​the first sub-transfer electrode 331 of the transfer electrode 330 in the opposite direction of the row direction being too small, thereby preventing the etching liquid for etching the transfer electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, thereby improving the display effect of the display panel.

[0047] refer to Figure 5 In this embodiment, the first sub-transfer electrode 331 has a third protruding portion 3313 in parallel with the column direction and in a direction opposite to the second sub-transfer electrode 332 relative to the first via hole 320. By providing the third protruding portion 3313, the area of ​​the first sub-transfer electrode 331 in a direction away from the second sub-transfer electrode 332 is increased, so as to avoid the first sub-transfer electrode 331 of the transition electrode 330 being too small in a direction away from the second sub-transfer electrode 332, resulting in the first sub-transfer electrode 331 of the transition electrode 330 not being able to completely cover the first via hole 320, thereby preventing the etching solution for etching the transition electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, thereby improving the display effect of the display panel.

[0048] refer to Fig.10 In this embodiment, along the positive direction of the row direction, the first sub-transfer electrode 331 has a first protruding portion 3311 relative to the first via hole 320, and along the negative direction of the row direction, the first sub-transfer electrode 331 has a second protruding portion 3312 relative to the first via hole 320. By providing the first protruding portion 3311 and the second protruding portion 3312, the area of ​​the first sub-transfer electrode 331 in the row direction and the negative direction of the row direction is increased at the same time, so as to avoid the first sub-transfer electrode 331 of the transfer electrode 330 not being able to completely cover the first via hole 320 due to the area of ​​the first sub-transfer electrode 331 in the positive direction of the row direction or the negative direction of the row direction being too small, thereby preventing the etching solution for etching the transfer electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, thereby improving the display effect of the display panel.

[0049] In this embodiment, the first protruding portion 3311 and the second protruding portion 3312 have the same shape and the same size.

[0050] refer to Figure 5 In this embodiment, the switching electrode 330 is T-shaped or inverted T-shaped. Specifically, the array substrate has a plurality of pixel units 300, and the pixel units 300 are arranged along the column direction and the row direction. For the switching electrodes 330 in the column direction, the shapes of the plurality of switching electrodes 330 in the same column direction are the same, and the shapes of the two adjacent switching electrodes 330 in the same row direction are different, that is, the plurality of switching electrodes 330 in the same column direction are all T-shaped or inverted T-shaped, and one of the two adjacent switching electrodes 330 in the same row direction is T-shaped, and the other is inverted T-shaped.

[0051] refer to Fig.10 In this embodiment, the edges of the first protruding portion 3311 and the second protruding portion 3312 are both arc-shaped. By setting the edges of the first protruding portion 3311 and the second protruding portion 3312 to be arc-shaped, the distance between the first sub-switching electrode 331 and the data line 200 can be increased, and a short circuit between the switching electrode 330 and the data line 200 can be avoided, and the parasitic capacitance can be reduced, thereby improving the stability of the array substrate.

[0052] refer to Fig.10In this embodiment, the first sub-switching electrode 331 has a first protruding portion 3311 extending in the positive direction of the row direction, the first sub-switching electrode 331 has a second protruding portion 3312 extending in the reverse direction of the row direction, and the first sub-switching electrode 331 has a third protruding portion 3313 extending in the direction away from the second sub-switching electrode 332. By providing the first protruding portion 3311, the second protruding portion 3312 and the third protruding portion 3313, the area of ​​the first sub-switching electrode 331 in the row direction and the opposite direction of the row direction is increased at the same time, so as to avoid the first sub-switching electrode 331 of the switching electrode 330 having an area in the positive direction of the row direction and the opposite direction of the row direction being too small and an area in the direction away from the second sub-switching electrode 332 being too small, resulting in the first sub-switching electrode 331 of the switching electrode 330 not being able to completely cover the first via hole 320, thereby preventing the etching liquid for etching the switching electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, thereby improving the display effect of the display panel.

[0053] In this embodiment, the first protruding portion 3311 , the second protruding portion 3312 , and the third protruding portion 3313 have the same shape and the same size.

[0054] refer to Fig.10 In this embodiment, the edges of the first protruding portion 3311, the second protruding portion 3312, and the third protruding portion 3313 are all arc-shaped. By setting the edges of the first protruding portion 3311 and the second protruding portion 3312 to be arc-shaped, the distance between the first sub-switching electrode 331 and the data line 200 can be increased, and a short circuit between the switching electrode 330 and the data line 200 can be avoided, and the parasitic capacitance can be reduced, thereby improving the stability of the array substrate.

[0055] refer to Figure 5 In this embodiment, two adjacent switching electrodes 330 in the row direction are centrally symmetrical with respect to the intersection of the scan line 100 and the data line 200. Specifically, a plurality of data lines 200 are arranged at equal intervals on the array substrate, and two adjacent switching electrodes 330 in the row direction are centrally symmetrical with respect to the intersection of the scan line 100 and the data line 200. Then, the first sub-switching electrodes 331 on the two adjacent switching electrodes 330 have the same distance to the same data line 200, and the second sub-switching electrodes 332 on the two adjacent switching electrodes 330 have the same distance to the same data line 200.

[0056] In this embodiment, the data lines 200 located on both sides of the switching electrode 330 are spaced at the same distance from the switching electrode 330 , that is, the switching electrode 330 is located in the middle of the area formed by two adjacent data lines 200 .

[0057] In this embodiment, the data lines 200 located on both sides of the switching electrode 330 are spaced apart from the switching electrode 330 , that is, the switching electrode 330 is offset toward the data line 200 on one side.

[0058] refer to Figure 5 In this embodiment, the second sub-switching electrodes 332 of two adjacent switching electrodes 330 in the column direction are both located on the same side of the first sub-switching electrodes 331 of the switching electrode 330. Specifically, the second sub-switching electrodes 332 of the plurality of switching electrodes 330 in the same column direction all extend in the positive direction of the column direction or in the reverse direction of the column direction.

[0059] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of scanning lines, wherein the plurality of scanning lines are arranged on the substrate at intervals along a column direction; A plurality of data lines, wherein the plurality of data lines are arranged on the substrate at intervals along a row direction; A plurality of pixel units, wherein the pixel unit is arranged between two adjacent data lines, the pixel unit includes a thin film transistor, a switching electrode and a pixel electrode, the thin film transistor is electrically connected to the scan line and the data line, the pixel electrode is electrically connected to the switching electrode, two adjacent switching electrodes located in the row direction are arranged on both sides of the scan line, the switching electrode includes a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating a film layer between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, the second sub-switching electrode is electrically connected to the first sub-switching electrode, and the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the first sub-switching electrode on the substrate is located on one side of the orthographic projection of the scanning line on the substrate, and the orthographic projection of the second sub-switching electrode on the substrate overlaps with the orthographic projection of the scanning line on the substrate.

3. The array substrate according to claim 1, characterized in that: The orthographic projections of the first sub-switching electrode and the second sub-switching electrode on the substrate are both located on one side of the orthographic projection of the scanning line on the substrate.

4. The array substrate according to any one of claims 1 to 3, characterized in that: Along the positive direction of the row direction, the first sub-switching electrode has a first protruding portion relative to the first via hole, and along the negative direction of the row direction, the first sub-switching electrode has a second protruding portion relative to the first via hole.

5. The array substrate according to claim 4, characterized in that: The first sub-switching electrode has a third protruding portion relative to the first via hole, parallel to the column direction and facing away from the second sub-switching electrode.

6. The array substrate according to claim 4, characterized in that: The edges of the first protruding portion and the second protruding portion are both arc-shaped.

7. The array substrate according to claim 1, characterized in that: Two adjacent switching electrodes located in the row direction are centrally symmetrical with respect to the intersection of the scanning line and the data line.

8. The array substrate according to claim 1, characterized in that: The second sub-switching electrodes of two adjacent switching electrodes in the column direction are both located on the same side of the first sub-switching electrodes of the switching electrodes.

9. The array substrate according to claim 1, characterized in that: The data lines located at both sides of the switching electrode are spaced equal to the switching electrode.

10. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 9.

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