A storage, dynamic switching, fault recovery system and method of FPGA waveform components

Abstract

The application provides a FPGA waveform component storage, dynamic switching and fault recovery system and method, which comprises at least a FPGA, a CPU and a FLASH; the FPGA comprises at least a FLASH programming module, and a first module and a second module connected with the FLASH programming module; the FLASH programming module is used for receiving a first instruction sent by the CPU through the first module, storing configuration files of the FPGA into corresponding address spaces in the FLASH in sequence, and feeding back to the CPU; and / or receiving a second instruction sent by the CPU through the second module, jumping to load corresponding configuration files in the FLASH, and switching global files or corresponding local communication waveform components of the FPGA based on the configuration files. The system and method of the application utilize a low-power CPU, a FPGA and a FLASH, not only meet the high real-time processing capacity of business, but also meet the requirements of miniaturization and low power consumption, and realize the storage, dynamic switching and fault recovery of the FPGA waveform component.

Description

A system and method for storing, dynamically switching, and recovering faults of FPGA waveform components. Technical Field

[0001] This invention relates to the field of software-defined radio communication technology, and more particularly to a system and method for storing, dynamically switching, and recovering faults of FPGA waveform components. Background Technology

[0002] The core idea of ​​software-defined radio (SDR) communication technology is hardware generalization and dynamic software reconfigurability. Therefore, with the gradual development of SDR technology, in order to meet the high real-time service processing requirements, the communication waveform algorithm design based on DSP (Digital Signal Processor) has been gradually replaced by FPGA (Field Programmable Gate Array, a type of digital integrated circuit chip). This has led to a series of systems based on a combination of CPU (Central Processing Unit) and FPGA to implement communication service transmission and reception.

[0003] Currently, in the most common CPU and FPGA systems, there are two main ways to load and configure the FPGA:

[0004] One approach is to mount the FLASH chip on a dedicated interface of the FPGA, and then use a JTAG emulator to embed the configuration file into the FLASH chip. After power-on, the configuration file is automatically read from the FLASH and loaded for execution. However, this method has the following drawbacks: (1) Device upgrades are cumbersome, and the configuration file cannot be upgraded online in real time using the emulator during device operation; (2) After the FPGA is powered on, only one global bin loading and execution can be achieved, and dynamic switching and partial dynamic reconstruction are not possible.

[0005] Another approach is to mount a FLASH (flash memory) chip on the CPU and upgrade the FPGA configuration file by generating a loading timing sequence through the CPU. Although this method can update the configuration file in the FLASH via the network and can also perform partial dynamic reconstruction of the FPGA, it still has drawbacks: (1) This method requires many CPU peripherals and consumes a lot of power; (2) Dynamically configuring the FPGA involves first reading the FLASH through the CPU and then loading the configuration file into the FPGA's RAM for execution. This means that after a power outage and restart, the FPGA will not automatically load the latest upgraded configuration file, and the CPU will need to reload the configuration again. Summary of the Invention

[0006] This invention provides a storage, dynamic switching, and fault recovery system and method for FPGA waveform components, which improves the deficiencies in the application of FPGA waveform components in the prior art.

[0007] On the one hand, the present invention provides a storage, dynamic switching, and fault recovery system for FPGA waveform components, the system comprising at least: FPGA, CPU, and FLASH;

[0008] The FPGA includes at least a FLASH programming module, and a first module and a second module that are simultaneously connected to the FLASH programming module;

[0009] The FLASH programming module is used for

[0010] The first module receives the first instruction issued by the CPU, stores the FPGA configuration file sequentially into the corresponding address space in the FLASH, and feeds it back to the CPU.

[0011] And / or,

[0012] The second module receives a second instruction from the CPU, jumps to load the corresponding configuration file in the FLASH, and switches the global file or the corresponding local communication waveform component of the FPGA based on the configuration file.

[0013] Furthermore, the first module includes the following components connected in sequence:

[0014] The interface module connects to the CPU and is used to receive the first instruction from the CPU and send it back to the CPU.

[0015] A parsing module is configured and connected to the FLASH programming module to parse the first instruction and transmit it to the FLASH programming module.

[0016] Furthermore, the second module includes the following components connected in sequence:

[0017] The mode selection module, connected to the CPU, is used to receive the CPU's second instruction and parse out the address space of the FLASH.

[0018] The jump loading module, connected to the FLASH programming module, is used to jump to the address space and load the corresponding configuration file in the address space into the FPGA for execution.

[0019] Furthermore, the address space corresponds one-to-one with the configuration file;

[0020] The address space includes at least a boot file address space, a global file address space, and a local file address space; the configuration file includes at least a boot file, a global file, and a local file.

[0021] The Boot file and global file in the configuration file both include at least the files for the FLASH programming module, the first module, and the second module.

[0022] Furthermore, the address space also includes an identification information address space; the global file address space includes a main address space and a backup address space.

[0023] On the other hand, the present invention also provides a method for storing, dynamically switching, and fault recovering FPGA waveform components, the method comprising at least:

[0024] The FPGA receives the first instruction from the CPU, obtains the FPGA's configuration file, stores the configuration file sequentially into the corresponding address space in the FLASH, and then feeds back to the CPU after completion.

[0025] The FPGA receives a second instruction from the CPU and jumps to load the corresponding configuration file in the FLASH; based on the configuration file, it switches the FPGA's global file or the corresponding local communication waveform component.

[0026] Furthermore, the method for obtaining the FPGA configuration file includes:

[0027] The FPGA parses the first instruction, processes the address space corresponding to the FLASH according to the parsed first instruction, and feeds back to the CPU after the processing is completed. The CPU then transmits the FPGA's configuration file to the FPGA.

[0028] Furthermore, the method for redirecting to load the corresponding configuration file in the FLASH includes:

[0029] Based on the mapping relationship between the logic combination of GPIO and the corresponding jump address, jump to the corresponding address space in the FLASH; and load the configuration file corresponding to the address space into the FPGA for execution.

[0030] Furthermore, the address space corresponds one-to-one with the configuration file;

[0031] The address space includes at least a boot file address space, a global file address space, and a local file address space; the configuration file includes at least a boot file, a global file, and a local file.

[0032] The Boot file and global file in the configuration file both include at least the files for the FLASH programming module, the first module, and the second module.

[0033] Furthermore, the address space also includes an identification information address space; the global file address space includes a main address space and a backup address space.

[0034] In summary, the technical solution conceived in this invention provides a system and method for storing, dynamically switching, and recovering faults of FPGA waveform components, which achieves the following beneficial effects compared with the prior art:

[0035] Firstly, by utilizing low-power CPUs, FPGAs, and FLASH memory, and employing heterogeneous multi-core SIP packaging, the system can meet the requirements of high real-time processing capabilities while also taking into account dynamic switching, miniaturization, and low power consumption.

[0036] Secondly, a novel method for upgrading and dynamically switching FPGA communication waveform components is employed. The CPU pre-upgrades and stores various FPGA communication waveform components in the FLASH memory mounted on the FPGA. This allows the CPU to directly load the configuration file at the specified address in the FLASH memory when online switching of communication waveform components is required during system operation. This simplifies the operation, reduces online switching time, and improves waveform component reassembly efficiency. Furthermore, the CPU can directly and rapidly reassemble fine-grained FPGA waveform components based on instructions to construct new waveforms, adapting to changes in current communication channel characteristics and significantly enhancing the waveform's anti-interference capability.

[0037] Thirdly, since the FPGA configuration files are all stored in FLASH, the FPGA will automatically load the latest stored and upgraded configuration files after the system is powered off and restarted, instead of having to reload the configuration files using the CPU as in the traditional method; this is more convenient and runs faster.

[0038] Fourthly, the address space in FLASH includes the Boot file address space, global file address space, local file address space, and identification information address space, and the global file address space includes the main address space and the backup address space; this can prevent anomalies when updating the global file. Even if the system fails to boot normally due to an abnormal power outage, or if the global file itself is faulty, the system can be restored normally and booted. Furthermore, the FPGA uses a JTAG emulator to burn the smaller Boot.bin file into the Boot file address space of the FLASH, resulting in a shorter burning time and saving time. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 is a schematic diagram of the system structure of an FPGA waveform component storage, dynamic switching, and fault recovery system and method provided by the present invention;

[0041] Figure 2 is a schematic diagram of the configuration file storage process of an FPGA waveform component storage, dynamic switching, and fault recovery system and method provided by the present invention.

[0042] Figure 3 is a schematic diagram of the configuration file trigger jump loading process of an FPGA waveform component storage, dynamic switching, and fault recovery system and method provided by the present invention.

[0043] Figure 4 is a schematic flowchart of a system and method for storing, dynamically switching, and recovering faults of FPGA waveform components provided by the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to Figures 1-4 and the embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0045] It should be noted that, in the description of the embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a system, process, or method that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a system, process, or method. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the system, process, or method that includes said element.

[0046] When the hardware system transmits and receives data, it uses the CPU, FPGA and RF daughter card to realize the communication service transmission and reception functions.

[0047] Specifically, when the system sends data, the CPU transmits the data to the FPGA via PCIe. The service data transceiver interface module in the FPGA, connected to the CPU, transmits the data to the communication waveform module for processing. Then, the processed data is sent to the RF daughter card via the service data transceiver interface module connected to the RF daughter card, thus completing the data transmission. When the system receives data, the RF daughter card transmits the received data to the FPGA. The service data transceiver interface module in the FPGA, connected to the RF daughter card, transmits the data to the communication waveform module for processing. Then, the processed data is sent to the CPU via PCIe via the service data transceiver interface module connected to the CPU, thus completing the data reception.

[0048] However, existing hardware systems for communication service transceiver functions have several drawbacks. Therefore, this invention provides a method for storing, dynamically switching, and recovering faults of FPGA waveform components, as well as a system architecture diagram of the system, as shown in Figure 1. The system includes, but is not limited to, FPGA (Field Programmable Gate Array, a type of digital integrated circuit chip), CPU (Central Processing Unit), and FLASH (Flash Memory), in order to solve the shortcomings of existing technologies.

[0049] The hardware system of this invention mainly includes a CPU, an FPGA, and a FLASH, which are packaged into a SIP (System-in-Package). The CPU uses a low-power processing chip and connects to the FPGA's configuration interface through simple SPI and GPIO. The FLASH is externally connected to a dedicated interface on the FPGA and is mainly used to store the Boot.bin file, global bin files, local bin files, identification information, etc.

[0050] The FPGA includes at least a FLASH programming module, as well as a first module and a second module that are connected to the FLASH programming module.

[0051] The FLASH programming module is used to receive the first instruction issued by the CPU through the first module, store the FPGA configuration file sequentially into the corresponding address space in the FLASH, and feed it back to the CPU; and / or, to receive the second instruction issued by the CPU through the second module, jump to load the corresponding configuration file in the FLASH, and switch the FPGA's global file or corresponding local communication waveform component based on the configuration file.

[0052] By utilizing low-power CPUs, FPGAs, and FLASH memory, and employing heterogeneous multi-core SIP packaging, the system can meet the requirements of high real-time processing capabilities while also achieving dynamic switching, miniaturization, and low power consumption.

[0053] More specifically, the first module includes, in sequence: an interface module, connected to the CPU, for receiving the first instruction from the CPU and feeding it back to the CPU; and a configuration parsing module, connected to the FLASH programming module, for parsing the first instruction and transmitting it to the FLASH programming module.

[0054] As one embodiment of the present invention, the configuration file storage function is implemented through an SPI interface module, a configuration parsing module, and a FLASH programming module. Specifically, the FPGA receives the erase command from the CPU through the SPI interface module; the configuration parsing module parses the erase command and transmits the parsed command to the FLASH programming module, which performs erase processing on the corresponding address space in the FLASH memory. After the erase processing is completed, the erase completion command is fed back to the CPU; the CPU selects the bin file or identification information to be burned and transmits it to the FPGA via SPI; the FPGA writes the bin file or identification information to the corresponding address space in the FLASH memory through the FLASH programming module, and feeds back the completed storage to the CPU.

[0055] After the global bin file is stored, the identification information is rewritten, and the system automatically jumps to load the global bin file through the ICAP jump loading module and the FLASH programming module.

[0056] The second module includes, in sequence: a mode selection module, connected to the CPU, used to receive the CPU's second instruction and parse out the address space mapped from the FLASH; and a jump loading module, connected to the FLASH programming module, used to jump to the address space and load the corresponding configuration file in the address space into the FPGA for execution.

[0057] As an embodiment of the present invention, the switching and / or reassembly of communication waveform components are realized through a GPIO mode selection module, an ICAP jump loading module, and a FLASH programming module.

[0058] The CPU triggers a GPIO interrupt to the FPGA. Based on the mapping relationship between the logical combination of GPIO and the corresponding jump address, the FLASH storage address space of the global bin file or local bin file to be loaded is configured. Then, the configuration file of the corresponding storage address space of the loaded FLASH is loaded into the FPGA's internal RAM for execution through the ICAP jump loading module and the FLASH programming module.

[0059] Furthermore, each address space corresponds one-to-one with a configuration file; the address space includes at least a Boot file address space, a global file address space, and a local file address space, and the configuration file includes at least a Boot file, a global file, and a local file; each address space is used to configure the Boot file, global file, and local file respectively. The Boot file and global file in the configuration file each include at least the files for the FLASH programming module, the first module, and the second module.

[0060] It should be noted that the Boot file is the Boot.bin file, which has configuration storage, automatic jump loading, and triggered jump loading functions. It is small in size and has a short JTAG firmware installation time. The global file is a global bin file, including all modules and interfaces in the FPGA. Besides having the configuration storage and jump loading functions of the Boot.bin file, it also includes functional modules required for service channels such as external control interfaces, data interfaces, and communication waveforms. The local files are local bin files, namely various fine-grained communication waveform components of the FPGA, including encoding / decoding components, modulation / demodulation components, etc.

[0061] To prevent abnormal updates to the global file, this invention, based on the above system operation, further adds an identification information address space to the address space in FLASH, and divides the global file address space into a main address space and a backup address space.

[0062] The identification information address space is used to store identification information. The identification information represents the address space where the global bin file to be updated is stored. For example, 0x55 means that the global bin file to be updated is stored in the main address space, and 0xAA means that the global bin file to be updated is stored in the backup address space.

[0063] As an embodiment of the present invention, as shown in Figure 1, the address space in the FLASH includes: Boot.bin address space, identifier address space, main address space, backup address space, local address space 1, local address space 2, ..., local address space n. Each local address space corresponds one-to-one with a communication waveform component.

[0064] On the other hand, the present invention also provides a method for storing, dynamically switching, and fault recovery of FPGA waveform components. The method includes at least the following steps: the FPGA receives a first instruction from the CPU, obtains the FPGA configuration file, stores the configuration file sequentially into the corresponding address space in the FLASH, and then feeds back to the CPU; the FPGA receives a second instruction from the CPU, jumps to load the corresponding configuration file in the FLASH; and switches between global files or corresponding local communication waveform components in the FPGA based on the configuration file.

[0065] The method for obtaining the FPGA configuration file includes: the FPGA parses the first instruction, processes the address space corresponding to the FLASH memory based on the parsed first instruction, and feeds back the processed data to the CPU. The CPU then transmits the FPGA configuration file to the FPGA. The configuration file includes a Boot file, a global file, and local files. After obtaining these files, the configuration files are sequentially stored in the corresponding address spaces within the FLASH memory.

[0066] It should be noted that the first instruction includes, but is not limited to, the frame assembly parameters such as frame header, erase instruction, FLASH address, and file size.

[0067] Specifically, as shown in Figure 2, the FPGA receives the erase command from the CPU through the SPI interface module; the FPGA parses the erase command and, based on the parsed command, erases the corresponding address space of the FLASH through the FLASH programming module. After erasure, it returns an erase completion command to the CPU; then, the CPU selects the bin file or identification information to be burned through the flash loader and transmits it to the FPGA through SPI; finally, the FPGA writes the bin file or identification information to the corresponding address space of the FLASH through the FLASH programming module and returns a storage completion command to the CPU.

[0068] In addition, the method for jumping to load the corresponding configuration file in FLASH includes: based on the mapping relationship between the logic combination of GPIO and the corresponding jump address, jumping to the corresponding address space in FLASH; and loading the corresponding configuration file in the address space into the FPGA for execution.

[0069] Specifically, jump loading includes automatic jump loading and triggered jump loading. Automatic jump loading involves rewriting the identifier information after configuring and storing the global file, automatically jumping, and loading the corresponding bin file from the FLASH address space into the FPGA's internal RAM for execution. As shown in Figure 3, triggered jump loading involves the CPU triggering a GPIO0 interrupt to the FPGA. Based on the mapping relationship between the GPIO logic combination and the corresponding jump address, the FLASH storage address of the global or local bin file to be loaded is configured. The bin file from the corresponding address space in the FLASH is then loaded into the FPGA's internal RAM for execution via the ICAP jump loading module and the FLASH programming module.

[0070] As an embodiment of the present invention, the mapping relationship between the logical combination of GPIO and the corresponding jump address is shown in Table 1 below:

[0071] Table 1. Mapping relationship between GPIO logic combinations and corresponding jump addresses

[0072] GPIO1GPIO2…GPIOm-2GPIOm-1GPIOm corresponds to the following FLASH address space jumps: 00…001 Main area global bin storage address space; 00…010 Backup area global bin storage address space; 00…011 Local bin1 storage address space; 100…100 Local bin2 storage address space; 2…………………11…111 Local binn storage address space. surface

[0073] As a specific embodiment of the present invention, the specific method steps include:

[0074] Step 1: Power on the hardware system and harden the Boot file. Specifically, use an FPGA emulator to harden the Boot.bin or Boot.mcs file into a fixed storage area in the FLASH memory starting at address 0x00000000 using the JTAG port. It should be noted that the size of this fixed storage area does not exceed 0x00200000. This Boot.bin file is used for identifying information in other address spaces of the FLASH memory, for storing and upgrading global and local bin files, and for executing jump addressing to load bin files. Hardening the Boot.bin file only needs to be performed once.

[0075] Step 2: After the Boot file is burned, power off and restart the hardware system. The hardware is configured by default in master serial mode. The FPGA automatically loads and runs the Boot file and runs it in the FPGA's internal RAM address space.

[0076] Step 3: Store the global file in the global fixed address space of FLASH; it should be noted that the CPU obtains the FPGA global bin file through the host computer network. At this time, the FPGA is running the Boot.bin file, and the CPU stores the global file in the global fixed address space of FLASH in the above manner.

[0077] Step 4: Once the global file is stored, the system will automatically jump to load and execute the global file; this will enable the transmission and reception of communication services from baseband to radio frequency.

[0078] Step 5: Similarly, the CPU stores the local files of the FPGA communication waveform module in the corresponding address spaces in the FLASH in the same way as described above. Specifically, as shown in Figure 1, the CPU obtains the local bin files of the FPGA fine-grained communication waveform components through the host computer network, and writes the FPGA communication waveform components bin1, bin2, ..., binn that need to be stored and upgraded into the corresponding local address spaces 1, 2, ..., n in the FLASH, thereby completing the storage upgrade of all local files of the FPGA in sequence.

[0079] Step 6: After the global and local file storage upgrade is completed, the hardware system is powered off and restarted. After the FPGA executes Boot.bin, it automatically jumps after a delay to load and execute the global file, thereby completing the operation of the hardware system.

[0080] Step 7: During operation, when the characteristics of the communication channel change and it is necessary to dynamically switch the FPGA communication waveform components, the CPU only needs to follow the above trigger jump loading steps to dynamically load the corresponding local bin files, including encoding / decoding components, modulation / demodulation components, etc., so as to realize the dynamic reorganization of waveform components to form new waveforms, thereby adapting to the characteristics of the communication channel and improving anti-interference capabilities online.

[0081] Of course, in order to prevent abnormalities in updating the global bin file, this invention also provides a global bin backup and recovery method based on the above-mentioned operation process. That is, the address space in FLASH is set to include at least the Boot file address space, the global file address space, the local file address space and the identification information address space, and the global file address space includes the main address space and the backup address space.

[0082] Specifically, two fixed address spaces for global bin files are allocated in the FLASH memory, called the main address space and the backup address space, respectively. An address space is also allocated in the FLASH memory to store identification information. This identification information indicates the address space where the global bin file to be updated will be stored. For example, 0x55 means that the global bin file to be updated will be stored in the main address space, and 0xAA means that the global bin file to be updated will be stored in the backup address space.

[0083] As another specific embodiment of the present invention, as shown in Figure 4, based on the above-described operating process, if the global bin file update fails, the fault recovery steps are as follows:

[0084] Step 1: After the Boot.bin file is hardened, power off and restart the hardware system. Following the steps to configure the storage function, the CPU transmits a message containing the identifier information 0x55 to the FPGA via SPI and stores it in the fixed address space of FLASH.

[0085] Step 2: The CPU transmits the main global bin file to the FPGA via SPI. The FPGA stores the main global bin file in its main address space based on the current identifier information 0x55. After storage, it rewrites the identifier information 0x55 to 0xAA and automatically jumps to load and execute the main global bin file. If there is a power failure and restart, the main global bin file will be loaded and executed from the main address space by default based on the identifier information 0xAA.

[0086] Step 3: When updating the backup global bin file, the CPU transmits the backup global bin file to the FPGA via SPI. The FPGA stores the backup global bin file in the backup address space based on the current identifier information 0xAA. After storage, it rewrites the identifier information 0xAA to 0x55 and automatically jumps to load and execute the backup global bin file. If there is a power failure and restart, the backup global bin file will be loaded and executed from the backup address space by default, based on the identifier information 0x55.

[0087] Step 4: Repeat steps 3 and 4, and repeat as needed, to alternately update the global bin file in the main address space and the backup address space.

[0088] It should be noted that abnormal situations typically include the first type of abnormal situation and the second type of abnormal situation.

[0089] The first abnormal situation is: an abnormal power outage during the update of the global bin file in the main area or the global bin file in the backup area, resulting in the update failing.

[0090] If an abnormal power outage occurs during the update of the main area global bin file, the hardware system restarts. Since the identifier information is still 0x55, the backup area global bin file is loaded and executed. The CPU then sends the main area global bin file to be updated to the FPGA again. Based on the current identifier information 0x55, the FPGA stores the main area global bin file in the main address space, rewrites the identifier information from 0x55 to 0xAA, and automatically jumps to load and execute the main area global bin file. This allows for the re-updating of the main area global bin file.

[0091] Similarly, if an abnormal power outage occurs during the update of the backup area global bin file, the hardware system will restart. Since the identifier information is still 0xAA, the main area global bin file will be loaded and executed. The CPU will then transfer the backup area global bin file to be updated to the FPGA again. Based on the current identifier information 0xAA, the backup area global bin file will be stored in the backup address space, and the identifier information 0xAA will be rewritten to 0x55. The CPU will then automatically jump to load and execute the backup area global bin file. This allows the backup area global bin file to be updated again.

[0092] The second abnormal situation is: the updated global bin file of the main area (global bin file of the backup area) is abnormal, which causes the system to be unable to execute this global bin file normally after power-on.

[0093] If the updated main area global bin file (backup area global bin file) itself malfunctions, causing the system to fail to execute this global bin file normally, a power-off restart will occur. Before the automatic jump to Boot.bin, a GPIO interrupt will be manually triggered, and the jump address will be configured via GPIO to the address space of the backup area global bin file (main area global bin file). The FPGA will load and execute the backup area global bin file (main area global bin file), the system will start normally, and the identification information will be rewritten, thus allowing the main area global bin file (backup area global bin file) to be updated again.

[0094] In summary, this invention can not only rapidly reassemble FPGA fine-grained waveform components based on CPU instructions to construct new waveforms, thereby adapting to changes in current communication channel characteristics and greatly improving the waveform's anti-interference capability, but also prevents anomalies when updating global files. Even if the system fails to start normally due to abnormal power failure or if the global file itself is abnormal, the system can be restored normally and the system can be started.

[0095] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A system for storing, dynamically switching, and recovering faults of an FPGA waveform component, characterized in that, The system includes at least an FPGA, a CPU, and a FLASH memory. The FPGA includes at least a FLASH programming module, and a first module and a second module connected to the FLASH programming module. The FLASH programming module receives a first instruction from the CPU via the first module, sequentially stores the FPGA's configuration file into the corresponding address space in the FLASH memory, and feeds it back to the CPU. The first module includes an SPI interface module and a configuration parsing module, which store the configuration file through the SPI interface module, configuration parsing module, and FLASH programming module. The second module receives a second instruction from the CPU, jumps to load the corresponding configuration file in the FLASH memory, and... The configuration file allows switching between the global file or the corresponding local communication waveform components of the FPGA; the second module includes a GPIO mode selection module and an ICAP jump loading module, which, along with the FLASH programming module, enable the switching and / or reassembly of communication waveform components; the CPU pre-upgrades and stores various FPGA communication waveform components in the FLASH mounted on the FPGA, so that when the communication waveform components need to be switched online during system operation, the configuration file in the specified address space of the FLASH is directly read and loaded according to the CPU's GPIO; and the FPGA communication waveform components are quickly reassembled based on the CPU's instructions to construct a new waveform.

2. The FPGA waveform component storage, dynamic switching, and fault recovery system as described in claim 1, characterized in that, The first module includes, in sequence: an SPI interface module connected to the CPU, for receiving the first instruction from the CPU and feeding it back to the CPU; and a configuration parsing module connected to the FLASH programming module, for parsing the first instruction and transmitting it to the FLASH programming module.

3. The FPGA waveform component storage, dynamic switching, and fault recovery system as described in claim 1, characterized in that, The second module includes, in sequence: a GPIO mode selection module, connected to the CPU, for receiving the CPU's second instruction and parsing out the address space of the FLASH; and an ICAP jump loading module, connected to the FLASH programming module, for jumping to the address space and loading the corresponding configuration file in the address space into the FPGA for execution.

4. The FPGA waveform component storage, dynamic switching, and fault recovery system as described in claim 1, characterized in that, The address space corresponds one-to-one with the configuration file; wherein, the address space includes at least the Boot file address space, the global file address space, and the local file address space; the configuration file includes at least the Boot file, the global file, and the local file; the Boot file and the global file in the configuration file each include at least the files of the FLASH programming module, the first module, and the second module.

5. The FPGA waveform component storage, dynamic switching, and fault recovery system as described in claim 4, characterized in that, The address space also includes an identification information address space; the global file address space includes a main address space and a backup address space.

6. A method for storing, dynamically switching, and fault recovering FPGA waveform components, characterized in that, The method is implemented using a storage, dynamic switching, and fault recovery system for any FPGA waveform component as described in claims 1-5. The method includes at least the following steps: the FPGA receives a first instruction from the CPU, obtains the FPGA's configuration file, stores the configuration file sequentially into the corresponding address space in the FLASH, and then feeds back to the CPU; the FPGA receives a second instruction from the CPU, jumps to load the corresponding configuration file in the FLASH; and switches the FPGA's global file or corresponding local communication waveform component based on the configuration file.

7. The method for storing, dynamically switching, and fault recovering FPGA waveform components as described in claim 6, characterized in that, The method for obtaining the FPGA configuration file includes: the FPGA parses the first instruction, processes the address space corresponding to the FLASH according to the parsed first instruction, and feeds back the processing results to the CPU. The CPU then transmits the FPGA configuration file to the FPGA.

8. The method for storing, dynamically switching, and fault recovering FPGA waveform components as described in claim 6, characterized in that, The method for jumping to load the corresponding configuration file in the FLASH includes: based on the mapping relationship between the logic combination of GPIO and the corresponding jump address, jumping to the corresponding address space in the FLASH; and loading the configuration file corresponding to the address space into the FPGA for execution.

9. The method for storing, dynamically switching, and fault recovering FPGA waveform components as described in claim 6, characterized in that, The address space corresponds one-to-one with the configuration file; wherein, the address space includes at least the Boot file address space, the global file address space, and the local file address space; the configuration file includes at least the Boot file, the global file, and the local file; the Boot file and the global file in the configuration file each include at least the files of the FLASH programming module, the first module, and the second module.

10. The method for storing, dynamically switching, and fault recovering FPGA waveform components as described in claim 9, characterized in that, The address space also includes an identification information address space; the global file address space includes a main address space and a backup address space.

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