Pixel circuit, driving method thereof, display substrate and display device

Abstract

A pixel circuit and a driving method thereof, a display substrate and a display device, wherein the pixel circuit is arranged in the display substrate, the display substrate comprises a display stage and a non-display stage, the pixel circuit is arranged to drive a light emitting element to emit light in the display stage, and comprises a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light emitting control sub-circuit and a driving sub-circuit; the third control sub-circuit is electrically connected with a third reset signal end, a control signal end and a third node respectively, and is arranged to provide a first signal to the third node under the control of the third reset signal end in the display stage, and provide a second signal to the third node or obtain a signal of the third node in the non-display stage; a voltage value of the first signal is less than that of a signal of a third initial signal end, and a voltage value of the second signal is greater than that of the signal of the third initial signal end.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a pixel circuit and its driving method, a display substrate, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a pixel circuit disposed in a display substrate, the display substrate including a display stage and a non-display stage, the pixel circuit being configured to drive a light-emitting element to emit light in the display stage, and including: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit.

[0005] The first control sub-circuit is electrically connected to the first power supply terminal, the second scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first initial signal terminal, the second initial signal terminal, the first node, the third node, and the fourth node, respectively. It is configured to provide the first initial signal terminal or the third node to the first node under the control of the first reset signal terminal and the second scan signal terminal, and to provide the second initial signal terminal to the fourth node under the control of the second reset signal terminal.

[0006] The second control sub-circuit is electrically connected to the first scan signal terminal, the third reset signal terminal, the third initial signal terminal, the data signal terminal, and the second node, respectively, and is configured to provide the third initial signal terminal or the data signal terminal to the second node under the control of the third reset signal terminal and the first scan signal terminal;

[0007] The third control sub-circuit is electrically connected to the third reset signal terminal, the control signal terminal, and the third node, respectively. It is configured to provide a first signal to the third node during the display phase and provide a second signal to the third node or acquire the signal of the third node during the non-display phase under the control of the third reset signal terminal.

[0008] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the first node and the second node;

[0009] The light-emitting control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node under the control of the light-emitting signal terminal.

[0010] The light-emitting element is electrically connected to the fourth node and the second power supply terminal, respectively.

[0011] The voltage value of the first signal is less than the voltage value of the signal at the third initial signal terminal, and the voltage value of the second signal is greater than the voltage value of the signal at the third initial signal terminal.

[0012] In some possible implementations, during the display phase, when the signal at the first reset signal terminal is an active level signal, the signal at the third reset signal terminal is an active level signal, and the signals at the first scan signal terminal, the second scan signal terminal, and the light emission signal terminal are inactive level signals.

[0013] When the first scan signal terminal is a valid level signal, the signal of the second scan signal terminal is a valid level signal, and the signals of the first reset signal terminal, the third reset signal terminal, and the light emission signal terminal are invalid level signals.

[0014] The voltage values ​​of the signals at the first initial signal terminal, the second initial signal terminal, and the third initial signal terminal are constant.

[0015] In some possible implementations, during the display phase, the occurrence time of the second reset signal terminal being at a valid level is before the occurrence time of the first reset signal terminal being at a valid level, or the occurrence time of the second reset signal terminal being at a valid level is within the occurrence time of the third reset signal terminal being at a valid level, or the occurrence time of the second reset signal terminal being at a valid level is within the occurrence time of the first scan signal terminal being at a valid level, or the occurrence time of the second reset signal terminal being at a valid level is after the occurrence time of the first scan signal terminal being at a valid level.

[0016] In some possible implementations, when the time when the signal at the second reset signal terminal is at an active level is within the time when the signal at the third reset signal terminal is at an active level, the signal at the second reset signal terminal is the same as the signal at the third reset signal terminal.

[0017] When the time when the signal at the second reset signal terminal is at an effective level is within the time when the signal at the first scan signal terminal is at an effective level, the signal at the second reset signal terminal is the same as the signal at the first scan signal terminal.

[0018] In some possible implementations, the first control sub-circuit includes: a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, and a storage sub-circuit;

[0019] The first reset sub-circuit is electrically connected to the first reset signal terminal, the first initial signal terminal, and the first node, respectively, and is configured to provide the signal of the first initial signal terminal to the first node under the control of the first reset signal terminal;

[0020] The second reset sub-circuit is electrically connected to the second reset signal terminal, the second initial signal terminal, and the fourth node, respectively, and is configured to provide the signal of the second initial signal terminal to the fourth node under the control of the second reset signal terminal;

[0021] The compensation sub-circuit is electrically connected to the first node, the third node, and the second scanning signal terminal, respectively, and is configured to provide the signal of the third node to the first node under the control of the second scanning signal terminal;

[0022] The storage sub-circuit is electrically connected to the first power supply terminal and the first node, respectively, and is configured to store the voltage difference between the signal of the first power supply terminal and the signal of the first node.

[0023] In some possible implementations, the second control sub-circuit includes: a third reset sub-circuit and a write sub-circuit;

[0024] The third reset sub-circuit is electrically connected to the third reset signal terminal, the third initial signal terminal, and the second node, respectively, and is configured to provide the signal of the third initial signal terminal to the second node under the control of the third reset signal terminal;

[0025] The writing sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the second node, respectively, and is configured to provide the data signal terminal to the second node under the control of the first scan signal terminal.

[0026] In some possible implementations, the first reset sub-circuit includes a first transistor, the second reset sub-circuit includes a seventh transistor, the compensation sub-circuit includes a second transistor, and the storage sub-circuit includes a capacitor, the capacitor including a first plate and a second plate.

[0027] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0028] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0029] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0030] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0031] In some possible implementations, the write sub-circuit includes a fourth transistor, and the third reset sub-circuit includes an eighth transistor;

[0032] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0033] The control terminal of the eighth transistor is electrically connected to the third reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node.

[0034] In some possible implementations, the third control sub-circuit includes: a ninth transistor;

[0035] The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the control signal terminal, and the second terminal of the ninth transistor is electrically connected to the third node.

[0036] In some possible implementations, the first control sub-circuit includes: a first transistor, a second transistor, a seventh transistor, and a capacitor, the capacitor including: a first plate and a second plate; the second control sub-circuit includes: a fourth transistor and an eighth transistor; the third control sub-circuit includes: a ninth transistor; the driving sub-circuit includes: a third transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0037] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0038] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0039] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0040] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0041] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0042] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0043] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0044] The control terminal of the eighth transistor is electrically connected to the third reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node.

[0045] The control electrode of the ninth transistor is electrically connected to the third reset signal terminal, the first electrode of the ninth transistor is electrically connected to the control signal terminal, and the second electrode of the ninth transistor is electrically connected to the third node.

[0046] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0047] In some possible implementations, the first transistor and the second transistor are of the opposite transistor type to the third to the ninth transistor;

[0048] The first transistor and the second transistor are oxide transistors, and are N-type transistors.

[0049] Secondly, this disclosure also provides a display substrate, comprising: a substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate, wherein the light-emitting structure layer comprises: a light-emitting element, and the circuit structure layer comprises: the aforementioned pixel circuits arranged in an array.

[0050] In some possible implementations, when the time when the signal at the second reset signal terminal is at an effective level is before the time when the signal at the first reset signal terminal is at an effective level, the signal at the second reset signal terminal of the i-th row pixel circuit is the same as the signal at the first scan signal terminal of the (i-1)-th row pixel circuit.

[0051] When the time when the signal at the second reset signal terminal is at an effective level is after the time when the signal at the first scan signal terminal is at an effective level, the signal at the second reset signal terminal of the i-th row pixel circuit is the same as the signal at the first scan signal terminal of the (i+1)-th row pixel circuit.

[0052] In some possible implementations, the circuit structure layer further includes: a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of third reset signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, a plurality of light emission signal lines, and a plurality of control signal lines extending along a first direction and arranged along a second direction, as well as a plurality of first power supply lines and a plurality of data signal lines extending along the second direction and arranged along the first direction, wherein the first direction intersects the second direction;

[0053] The pixel circuit has a first reset signal terminal electrically connected to a first reset signal line, a second reset signal terminal electrically connected to a second reset signal line, a third reset signal terminal electrically connected to a third reset signal line, a first scan signal terminal electrically connected to a first scan signal line, a second scan signal terminal electrically connected to a second scan signal line, an emission signal terminal electrically connected to an emission signal line, a first initial signal terminal electrically connected to a first initial signal line, a second initial signal terminal electrically connected to a second initial signal line, a control signal terminal electrically connected to a control signal line, a first power supply terminal electrically connected to a first power supply line, and a data signal terminal electrically connected to a data signal line.

[0054] In some possible implementations, it also includes: a first chip connected to the control signal line and a second chip connected to the data signal line;

[0055] The first chip is configured to provide a first signal to the control signal line during the display phase, provide a second signal to the control signal line during the non-display phase, or acquire the signal of the control signal line. It is also configured to obtain the threshold voltage of the third transistor based on the signal of the control signal line, generate a control signal based on the threshold voltage of the third transistor, and send the control signal to the second chip.

[0056] The second chip provides signals to the data signal line according to the control signal.

[0057] In some possible implementations, the pixel structure of adjacent pixel circuits in the same row is symmetrical with respect to a dummy straight line extending along the second direction;

[0058] The adjacent pixel circuits located in the same row as the pixel circuits include: the first adjacent pixel circuit and the second adjacent pixel circuit.

[0059] In some possible implementations, the pixel circuit includes: a first transistor to a ninth transistor, wherein the control electrode of the first transistor and the control electrode of the second transistor each include: a first control electrode and a second control electrode;

[0060] The first reset signal line includes: a first sub-reset signal line and a second sub-reset signal line that are disposed on different layers and connected to each other, wherein the first sub-reset signal line is disposed on the same layer as the first control electrode of the first transistor, and the second sub-reset signal line is disposed on the same layer as the second control electrode of the first transistor;

[0061] The second scan signal line includes: a first sub-scan signal line and a second sub-scan signal line that are disposed on different layers and interconnected, wherein the first sub-scan signal line is disposed on the same layer as the first control electrode of the second transistor, and the second sub-scan signal line is disposed on the same layer as the second control electrode of the second transistor.

[0062] In some possible implementations, the pixel circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate. The circuit structure layer includes a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a seventh insulating layer, a first planarization layer, and a fifth conductive layer, which are sequentially stacked on the substrate.

[0063] The first semiconductor layer includes: the active layer of the third transistor to the active layer of the ninth transistor located in at least one pixel circuit;

[0064] The first conductive layer includes: a first scan signal line, a light emission signal line, and a first electrode of a capacitor located in at least one pixel circuit, and the control electrode of a third transistor to the control electrode of a ninth transistor;

[0065] The second conductive layer includes: a first initial signal line, a first sub-reset signal line, a first sub-scan signal line, a control signal line, and a second plate of a capacitor located in at least one pixel circuit, a first control electrode of a first transistor, and a first control electrode of a second transistor;

[0066] The second semiconductor layer includes: an active layer of a first transistor located in at least one pixel circuit, an active layer of a second transistor, and an active connection portion; the active connection portion is configured to connect the active layer of the first transistor and the active layer of the second transistor.

[0067] The third conductive layer includes: a second sub-reset signal line, a second sub-scan signal line, a third reset signal line, and a third initial signal line, as well as a second control electrode of a first transistor and a second control electrode of a second transistor located in at least one pixel circuit;

[0068] The fourth conductive layer includes: a second initial signal line and a first and second electrode of a first transistor, a first and second electrode of a second transistor, a first electrode of a fourth transistor, a first electrode of a fifth transistor, a second electrode of a sixth transistor, a first and second electrode of a seventh transistor, a first electrode of an eighth transistor, a first electrode of a ninth transistor, and a first connection electrode; the first connection electrode is configured to connect the control electrode of the eighth transistor, the control electrode of the ninth transistor, and the third reset signal line.

[0069] The fifth conductive layer includes: a first power line, a data signal line, and a second connection electrode located in at least one pixel circuit, wherein the second connection electrode is configured to connect the second electrode of the sixth transistor and the light-emitting element.

[0070] In some possible implementations, the circuit structure layer further includes: a light-shielding layer located on the side of the first insulating layer near the substrate, the light-shielding layer including: light-shielding portions and light-shielding connecting portions arranged in an array and spaced apart from each other, the light-shielding connecting portions being configured to connect adjacent light-shielding portions;

[0071] The orthographic projection of the light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate.

[0072] In some possible implementations, the control electrode of the eighth transistor and the control electrode of the ninth transistor are integrally formed.

[0073] The first scan signal line and the light emission signal line connected to the pixel circuit are located on both sides of the first plate of the capacitor in the pixel circuit. The integrated structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor is located between the first plate of the capacitor and the light emission signal line connected to the pixel circuit.

[0074] In some possible implementations, the first control electrode of the first transistor and the first sub-reset signal line are integrally formed, and the first control electrode of the second transistor and the first sub-scan signal line are integrally formed.

[0075] The first initial signal line, the first sub-reset signal line, and the first sub-scan signal line connected to the pixel circuit extend along the first direction and are located on the same side of the second plate of the capacitor of the pixel circuit. The first sub-reset signal line is located on the side of the first initial signal line that is closer to the second plate of the capacitor of the pixel circuit, and the first sub-scan signal line is located on the side of the first sub-reset signal line that is closer to the second plate of the capacitor of the pixel circuit. The control signal line is located on the side of the second plate of the capacitor of the pixel circuit that is away from the first sub-scan signal line.

[0076] The orthographic projection of the first scan signal line on the substrate is located between the orthographic projection of the first sub-reset signal line on the substrate and the orthographic projection of the first sub-scan signal line on the substrate.

[0077] The orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate is located between the orthographic projection of the second plate of the capacitor on the substrate and the orthographic projection of the control signal line on the substrate.

[0078] The orthographic projection of the control signal line on the substrate is located between the orthographic projection of the light-emitting signal line on the substrate and the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate.

[0079] The second plate of the capacitor in the pixel circuit is electrically connected to the second plate of the capacitor in the first adjacent pixel circuit.

[0080] In some possible implementations, the active layer of the first transistor and the active layer of the second transistor are located on both sides of the active connection portion, respectively.

[0081] The orthographic projection of the active layer of the first transistor onto the substrate overlaps with the orthographic projection of the first initial signal line onto the substrate;

[0082] The orthographic projection of the active layer of the second transistor onto the substrate overlaps with the orthographic projection of the first sub-scan signal line onto the substrate;

[0083] The orthographic projection of the active connection portion on the substrate at least partially overlaps with the orthographic projection of the first scan signal line on the substrate.

[0084] In some possible implementations, the second control electrode of the first transistor and the second sub-reset signal line are integrally formed, and the second control electrode of the second transistor and the second sub-scan signal line are integrally formed.

[0085] The second sub-scan signal line is located between the second sub-reset signal line and the third reset signal line, and the third initial signal line is located on the side of the third reset signal line away from the second sub-reset signal line.

[0086] The orthographic projection of the second sub-reset signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-reset signal line on the substrate, and is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first scan signal line on the substrate.

[0087] The orthographic projection of the second sub-scan signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line on the substrate, and is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the second plate of the capacitor on the substrate.

[0088] The orthographic projection of the third reset signal line on the substrate is located between the orthographic projection of the second plate of the capacitor on the substrate and the orthographic projection of the integral structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate.

[0089] The orthographic projection of the third initial signal line on the substrate is located on the side of the second plate of the capacitor away from the orthographic projection of the control signal line on the substrate, and overlaps with the orthographic projections of the light-emitting signal line EL and the control signal line on the substrate.

[0090] In some possible implementations, the sixth insulating layer is provided with a plurality of via patterns, including: a first to a seventh via formed on the second to the sixth insulating layers, an eighth and a ninth via formed on the third to the sixth insulating layers, a tenth to a twelfth via formed on the fourth to the sixth insulating layers, a thirteenth to a fifteenth via formed on the fifth and sixth insulating layers, and a sixteenth and a seventeenth via formed on the sixth insulating layer;

[0091] The third via exposes the active layer of the fifth transistor, the tenth via exposes the first initial signal line, and the eleventh via exposes the second plate of the capacitor; a virtual straight line extending along the second direction passes through the third and eleventh vias.

[0092] The third via of the pixel circuit is the same as the third via of the first adjacent pixel circuit;

[0093] The eleventh via of the pixel circuit is the same via as the eleventh via of the first adjacent pixel circuit;

[0094] The tenth via of the pixel circuit and the tenth via of the second adjacent pixel circuit are the same via.

[0095] In some possible implementations, the first electrode of the fifth transistor of the pixel circuit is the same electrode as the first electrode of the fifth transistor of the first adjacent pixel circuit.

[0096] The orthographic projection of the second initial signal line on the substrate overlaps with the orthographic projections of the first reset signal line and the first scan signal line on the substrate.

[0097] The orthographic projection of the integral structure of the second electrode of the first transistor and the second electrode of the second transistor on the substrate at least partially overlaps with the orthographic projection of the active connection portion, the second scan signal line and the second plate of the capacitor on the substrate.

[0098] The orthogonal projection of the first electrode of the fifth transistor onto the substrate overlaps with the orthogonal projections of the second plate of the capacitor, the third reset signal line, the control signal line, the light emission signal line, and the third initial signal line onto the substrate.

[0099] The orthographic projection of the first connection electrode on the substrate at least partially overlaps with the orthographic projections of the third reset signal line and the control electrode of the eighth transistor on the substrate;

[0100] The orthographic projection of the first electrode of the eighth transistor onto the substrate overlaps with the orthographic projections of the control signal line, the light emission signal line, and the third initial signal line onto the substrate;

[0101] The orthographic projection of the first electrode of the ninth transistor onto the substrate overlaps with the orthographic projection of the control signal line onto the substrate.

[0102] In some possible implementations, the data signal line and the first power supply line connected to the pixel circuit are located on the same side of the second connection electrode;

[0103] The first power line includes: a power body and a power connection part connected to each other, wherein the power connection part is located on the side of the power body away from the data signal line;

[0104] The power connection portion of the first power line connected to the pixel circuit is interconnected with the power connection portion of the first power line connected to the second adjacent pixel circuit.

[0105] The orthographic projection of the power connection portion on the substrate overlaps with the orthographic projections of the active connection portion, the second scan signal line, the first scan signal line, and the second initial signal line on the substrate.

[0106] Thirdly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0107] Fourthly, this disclosure also provides a method for driving a pixel circuit, configured to drive the aforementioned pixel circuit, the method comprising:

[0108] Under the control of the first reset signal terminal and the second scan signal terminal, the first control sub-circuit provides the first initial signal terminal or the signal of the third node to the first node, and under the control of the second reset signal terminal, provides the signal of the second initial signal terminal to the fourth node.

[0109] Under the control of the third reset signal terminal and the first scan signal terminal, the second control sub-circuit provides the third initial signal terminal or the data signal terminal to the second node;

[0110] Under the control of the third reset signal terminal, the third control sub-circuit provides a first signal to the third node during the display phase and provides a second signal to the third node or acquires the signal of the third node during the non-display phase.

[0111] The driving sub-circuit provides driving current to the third node under the control of the first and second nodes;

[0112] Under the control of the light emission signal terminal, the light emission control sub-circuit provides the first power supply terminal signal to the second node and the third node signal to the fourth node.

[0113] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0114] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0115] Figure 1 This is a schematic diagram of the pixel circuit provided in an embodiment of the present disclosure;

[0116] Figure 2 A schematic diagram of the structure of a first control sub-circuit provided for an exemplary embodiment;

[0117] Figure 3 A schematic diagram of the structure of a second control sub-circuit provided in an exemplary embodiment;

[0118] Figure 4 An equivalent circuit diagram of a first control sub-circuit provided for an exemplary embodiment;

[0119] Figure 5 An equivalent circuit diagram of a second control sub-circuit provided for an exemplary embodiment;

[0120] Figure 6 An equivalent circuit diagram of a third control sub-circuit provided for an exemplary embodiment;

[0121] Figure 7 An equivalent circuit diagram of a light-emitting control sub-circuit and a driving sub-circuit provided for an exemplary embodiment;

[0122] Figure 8 An equivalent circuit diagram of a pixel circuit provided for an exemplary embodiment;

[0123] Figure 9 for Figure 8 The provided pixel circuit operating timing Figure 1 ;

[0124] Figure 10 for Figure 8 The provided pixel circuit operating timing Figure 2 ;

[0125] Figure 11 for Figure 8 The provided pixel circuit operating timing Figure 3 ;

[0126] Figure 12 for Figure 8 The provided pixel circuit operating timing Figure 4 ;

[0127] Figure 13A This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0128] Figure 13B for Figure 13A Cross-sectional view along direction AA;

[0129] Figure 14 This is a schematic diagram of the light-shielding layer pattern;

[0130] Figure 15A This is a schematic diagram of the pattern of the first semiconductor layer;

[0131] Figure 15B This is a schematic diagram after the first semiconductor layer pattern has been formed;

[0132] Figure 16A This is a schematic diagram of the pattern of the first conductive layer;

[0133] Figure 16B This is a schematic diagram after the first conductive layer pattern has been formed;

[0134] Figure 17A This is a schematic diagram of the pattern of the second conductive layer;

[0135] Figure 17B This is a schematic diagram after the second conductive layer pattern has been formed;

[0136] Figure 18A This is a schematic diagram of the pattern of the second semiconductor layer;

[0137] Figure 18B This is a schematic diagram after the second semiconductor layer pattern has been formed;

[0138] Figure 19A This is a schematic diagram of the pattern of the third conductive layer;

[0139] Figure 19BThis is a schematic diagram after the third conductive layer pattern has been formed;

[0140] Figure 20 This is a schematic diagram showing the formation of the sixth insulating layer pattern;

[0141] Figure 21A This is a schematic diagram of the pattern of the fourth conductive layer;

[0142] Figure 21B This is a schematic diagram after the fourth conductive layer pattern has been formed;

[0143] Figure 22 This is a schematic diagram after the first flattening layer pattern has been formed;

[0144] Figure 23A This is a schematic diagram of the pattern of the fifth conductive layer;

[0145] Figure 23B This is a schematic diagram after the fifth conductive layer pattern has been formed. Detailed Implementation

[0146] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0147] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0148] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0149] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0150] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0151] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0152] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0153] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0154] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0155] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0156] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0157] The display substrate uses Low Temperature Poly-Silicon (LTPS) technology, which boasts advantages such as high resolution, fast response speed, high brightness, and high aperture ratio. Despite its market popularity, LTPS technology also has some drawbacks, such as high production costs and high power consumption. To address these, Low Temperature Polycrystalline Oxide (LTPO) technology emerged. Compared to LTPS, LTPO technology has lower leakage current and faster pixel response. The addition of an oxide layer to the display substrate reduces the energy required to excite the pixels, thus lowering the power consumption during screen display. However, in display products using LTPO technology, the aging rates of the driving transistors in different pixel circuits vary, and the display substrate cannot monitor the threshold voltage of the driving transistors, which reduces the display effect, lifespan, and reliability of the display substrate.

[0158] Figure 1 This is a schematic diagram of the pixel circuit provided in an embodiment of the present disclosure. Figure 1 As shown, the pixel circuit provided in this embodiment is disposed in a display substrate, the display substrate including a display stage and a non-display stage, the pixel circuit is configured to drive the light-emitting element to emit light in the display stage, and includes: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit.

[0159] like Figure 1As shown, the first control sub-circuit is electrically connected to the first power supply terminal VDD, the second scan signal terminal Gate2, the first reset signal terminal Reset1, the second reset signal terminal Reset2, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, the first node N1, the third node N3, and the fourth node N4, respectively. It is configured to provide the first initial signal terminal Vinit1 or the third node N3 signal to the first node N1 under the control of the first reset signal terminal Reset1 and the second scan signal terminal Gate2, and to provide the second initial signal terminal Vinit2 signal to the fourth node N4 under the control of the second reset signal terminal Reset2. The second control sub-circuit is electrically connected to the first scan signal terminal Gate1, the third reset signal terminal Reset3, the third initial signal terminal Vinit3, the data signal terminal Data, and the second node N2, respectively. It is configured to control the third reset signal terminal Reset3 and the first scan signal terminal Gate1. Under the control of the third initial signal terminal Vinit3 or the data signal terminal Data, a third control sub-circuit is provided to the second node N2. The third control sub-circuit is electrically connected to the third reset signal terminal Reset3, the control signal terminal S and the third node N3, respectively. It is configured to provide a first signal to the third node N3 during the display phase and provide a second signal to the third node N3 or acquire the signal of the third node N3 during the non-display phase under the control of the third reset signal terminal Reset3. The driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively. It is configured to provide a driving current to the third node N3 under the control of the first node N1 and the second node N2. The light emission control sub-circuit is electrically connected to the light emission signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3 and the fourth node N4, respectively. It is configured to provide the first power supply terminal VDD signal to the second node N2 and the third node N3 signal to the fourth node N4 under the control of the light emission signal terminal EM.

[0160] like Figure 1 As shown, the light-emitting element is electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0161] In one exemplary embodiment, the voltage value of the signal at the first initial signal terminal Vinit1 is constant and is a DC signal; the voltage value of the signal at the first initial signal terminal Vinit1 can be -3V.

[0162] In one exemplary embodiment, the voltage value of the signal at the second initial signal terminal Vinit2 is constant and is a DC signal; the voltage value of the signal at the second initial signal terminal Vinit2 can be 0V.

[0163] In one exemplary embodiment, the voltage value of the signal at the third initial signal terminal Vinit3 is constant and is a DC signal; the voltage value of the signal at the third initial signal terminal Vinit3 can be 5V.

[0164] In one exemplary embodiment, the voltage value of the first signal is less than the voltage value of the signal at the third initial signal terminal Vinit3.

[0165] In one exemplary embodiment, the voltage value of the first signal can be constant, and a constant voltage value of the first signal can make the aging degree of the third node of the pixel circuit uniform. The voltage value of the first signal can be 0V.

[0166] In one exemplary embodiment, the voltage value of the second signal is greater than the voltage value of the signal at the third initial signal terminal Vinit3, and the voltage value of the second signal can be 6V. This greater voltage value of the second signal compared to the third initial signal terminal Vinit3 allows for better current flow in the driving sub-circuit during non-display phases.

[0167] In one exemplary embodiment, the light-emitting element may be electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0168] In one exemplary embodiment, the non-display phase may include a power-on phase, a power-off phase, and a blank phase between the display phases.

[0169] In one exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal VSS continuously provides a low-level signal.

[0170] In one exemplary embodiment, the DC signal can be one whose magnitude and direction do not change over time. For example, the first signal can be a DC signal with a constant voltage value.

[0171] In one exemplary embodiment, the threshold voltage of the driving sub-circuit can be obtained based on the signal of the third node acquired by the control signal terminal. Based on the threshold voltage of the driving sub-circuit, the signal of the data signal terminal is controlled to achieve external compensation for the pixel circuit, thereby improving the display effect of the display substrate.

[0172] In one exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the organic light-emitting diode is electrically connected to a fourth node N4, and the cathode of the organic light-emitting diode is electrically connected to a second power supply terminal VSS.

[0173] In one exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0174] In some exemplary embodiments, during the display phase, when the signal of the first reset signal terminal Reset1 is an active level signal, the signal of the third reset signal terminal Reset3 is an active level signal, and the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the light emission signal terminal are inactive level signals.

[0175] In some exemplary embodiments, when the first scan signal terminal Gate1 is an active level signal, the signal of the second scan signal terminal Gate2 is an active level signal, and the signals of the first reset signal terminal Reset1, the third reset signal terminal Reset3, and the light emission signal terminal are inactive level signals.

[0176] In some exemplary embodiments, during the display phase, the time when the signal of the second reset signal terminal Reset2 is at an effective level is before the time when the signal of the first reset signal terminal Reset1 is at an effective level, or the time when the signal of the second reset signal terminal Reset2 is at an effective level is within the time when the signal of the third reset signal terminal Reset3 is at an effective level, or the time when the signal of the second reset signal terminal Reset2 is at an effective level is within the time when the signal of the first scan signal terminal Gate1 is at an effective level, or the time when the signal of the second reset signal terminal Reset2 is at an effective level is after the time when the signal of the first scan signal terminal Gate1 is at an effective level.

[0177] In some exemplary embodiments, when the time when the signal of the second reset signal terminal Reset2 is at an effective level is within the time when the signal of the third reset signal terminal Reset3 is at an effective level, the signal of the second reset signal terminal Reset2 is the same as the signal of the third reset signal terminal Reset3.

[0178] In some exemplary embodiments, when the time when the signal of the second reset signal terminal Reset2 is at an effective level is within the time when the signal of the first scan signal terminal Gate1 is at an effective level, the signal of the second reset signal terminal Reset2 is the same as the signal of the first scan signal terminal Gate1.

[0179] In one exemplary embodiment, the signal lines connected to the signal terminals with the same signal can be the same signal line or they can be different signal lines.

[0180] The pixel circuit provided in this embodiment is disposed in a display substrate, the display substrate including a display stage and a non-display stage. The pixel circuit is configured to drive a light-emitting element to emit light in the display stage, and includes: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit. The first control sub-circuit is electrically connected to a first power supply terminal, a second scan signal terminal, a first reset signal terminal, a second reset signal terminal, a first initial signal terminal, a second initial signal terminal, a first node, a third node, and a fourth node, respectively. It is configured to provide a signal from the first initial signal terminal or the third node to the first node under the control of the first reset signal terminal and the second scan signal terminal, and to provide a signal from the second initial signal terminal to the fourth node under the control of the second reset signal terminal. The second control sub-circuit is electrically connected to the first scan signal terminal, the third reset signal terminal, the third initial signal terminal, a data signal terminal, and the second node, respectively. It is configured to control the light emitted by the light emitted by the light emitted by the light emitted by the third reset signal terminal and the first scan signal terminal. The system provides a signal from the third initial signal terminal or data signal terminal to the second node; a third control sub-circuit, electrically connected to the third reset signal terminal, control signal terminal, and third node respectively, is configured to provide a first signal to the third node during the display phase and a second signal or acquire the signal of the third node during the non-display phase under the control of the third reset signal terminal; a driving sub-circuit, electrically connected to the first node, second node, and third node respectively, is configured to provide a driving current to the third node under the control of the first node and second node; a light-emitting control sub-circuit, electrically connected to the light-emitting signal terminal, first power supply terminal, second node, third node, and fourth node respectively, is configured to provide a signal from the first power supply terminal to the second node and a signal from the third node to the fourth node under the control of the light-emitting signal terminal; a light-emitting element, electrically connected to the fourth node and second power supply terminal respectively; the voltage value of the first signal is less than the voltage value of the signal from the third initial signal terminal, and the voltage value of the second signal is greater than the voltage value of the signal from the third initial signal terminal. This disclosure, by setting a third control sub-circuit, can provide a first signal with a constant voltage value to the third node during the display phase, and provide a second signal to the third node or acquire the signal of the third node during the non-display phase. This not only ensures that the aging degree of the driving sub-circuit is the same, but also allows monitoring of the threshold voltage of the driving sub-circuit, thereby performing external compensation on the pixel circuit and improving the display effect, service life and reliability of the display substrate.

[0181] Figure 2 A schematic diagram of the structure of a first control sub-circuit provided for an exemplary embodiment. (See diagram below.) Figure 2 As shown, in one exemplary embodiment, the first control sub-circuit may include: a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, and a storage sub-circuit.

[0182] like Figure 2As shown, the first reset sub-circuit is electrically connected to the first reset signal terminal Reset1, the first initial signal terminal Vinit1, and the first node N1, respectively, and is configured to provide the signal of the first initial signal terminal Vinit1 to the first node N1 under the control of the first reset signal terminal Reset1; the second reset sub-circuit is electrically connected to the second reset signal terminal Reset2, the second initial signal terminal Vinit2, and the fourth node N4, respectively, and is configured to provide the signal of the second initial signal terminal Vinit2 to the fourth node N4 under the control of the second reset signal terminal Reset2; the compensation sub-circuit is electrically connected to the first node N1, the third node N3, and the second scan signal terminal Gate2, respectively, and is configured to provide the signal of the third node N3 to the first node N1 under the control of the second scan signal terminal Gate2; the storage sub-circuit is electrically connected to the first power supply terminal VDD and the first node N1, respectively, and is configured to store the voltage difference between the signal of the first power supply terminal VDD and the signal of the first node N1.

[0183] Figure 3 A schematic diagram of the structure of a second control sub-circuit provided for an exemplary embodiment. (See diagram below.) Figure 3 As shown, in one exemplary embodiment, the second control sub-circuit may include a third reset sub-circuit and a write sub-circuit.

[0184] like Figure 3 As shown, the third reset sub-circuit is electrically connected to the third reset signal terminal Reset3, the third initial signal terminal Vinit3, and the second node N2, respectively, and is configured to provide the signal of the third initial signal terminal Vinit3 to the second node N2 under the control of the third reset signal terminal Reset3; the write sub-circuit is electrically connected to the first scan signal terminal Gate1, the data signal terminal Data, and the second node N2, respectively, and is configured to provide the signal of the data signal terminal Data to the second node N2 under the control of the first scan signal terminal Gate1.

[0185] Figure 4 An equivalent circuit diagram of a first control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 4 As shown, in an exemplary embodiment, the first reset sub-circuit may include: a first transistor T1; the second reset sub-circuit includes: a seventh transistor T7; the compensation sub-circuit includes: a second transistor T2; and the storage sub-circuit includes: a capacitor C, wherein the capacitor C includes: a first plate C1 and a second plate C2.

[0186] like Figure 4As shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power supply terminal VDD.

[0187] Figure 4 An exemplary structure of the first control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited to this.

[0188] Figure 5 An equivalent circuit diagram of a second control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 5 As shown, in one exemplary embodiment, the write sub-circuit may include a fourth transistor T4, and the third reset sub-circuit may include an eighth transistor T8.

[0189] like Figure 5 As shown, the control terminal of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control terminal of the eighth transistor T8 is electrically connected to the third reset signal terminal Reset3, the first terminal of the eighth transistor T8 is electrically connected to the third initial signal terminal Vinit3, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2.

[0190] Figure 5 An exemplary structure of the second control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0191] Figure 6 An equivalent circuit diagram of a third control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 6 As shown, in one exemplary embodiment, the third control sub-circuit may include: a ninth transistor T9.

[0192] like Figure 6As shown, the control terminal of the ninth transistor T9 is electrically connected to the third reset signal terminal Reset3, the first terminal of the ninth transistor T9 is electrically connected to the control signal terminal S, and the second terminal of the ninth transistor T9 is electrically connected to the third node N3.

[0193] Figure 6 An exemplary structure of the third control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0194] Figure 7 An equivalent circuit diagram of a light-emitting control sub-circuit and a driving sub-circuit is provided for an exemplary embodiment. (See diagram below.) Figure 7 As shown, in an exemplary embodiment, the driving sub-circuit may include a third transistor T3, and the light-emitting control sub-circuit may include a fifth transistor T5 and a sixth transistor T6.

[0195] like Figure 7 As shown, the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0196] Figure 7 An exemplary structure of the light-emitting control subcircuit and the driving subcircuit is shown. It will be readily understood by those skilled in the art that the implementation of the light-emitting control subcircuit and the driving subcircuit is not limited to this.

[0197] Figure 8 An equivalent circuit diagram of a pixel circuit provided for an exemplary embodiment. For example... Figure 8 As shown, in an exemplary embodiment, the first control sub-circuit includes: a first transistor T1, a second transistor T2, a seventh transistor T7, and a capacitor C, wherein the capacitor C includes: a first plate C1 and a second plate C2; ​​the second control sub-circuit includes: a fourth transistor T4 and an eighth transistor T8; the third control sub-circuit includes: a ninth transistor T9; the driving sub-circuit includes: a third transistor T3; and the light-emitting control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6.

[0198] like Figure 8As shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first terminal of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second terminal of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the light emission signal terminal EM, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the first node N2. The control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal terminal Reset3, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal terminal Vinit3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal Reset3, the first electrode of the ninth transistor T9 is electrically connected to the control signal terminal S, and the second electrode of the ninth transistor T9 is electrically connected to the third node N3; the first plate C1 of capacitor C is electrically connected to the first node N1, and the second plate C2 of capacitor C is electrically connected to the first power supply terminal VDD.

[0199] In one exemplary embodiment, the third transistor T3 can be referred to as the driving transistor, and the third transistor T3 determines the driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on the potential difference between its control terminal and the first terminal.

[0200] In one exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When the signal at the light-emitting signal terminal EM is an active level signal, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a drive current path between the first power supply terminal VDD and the second power supply terminal VSS.

[0201] In one exemplary embodiment, some of the transistors in the first transistor T1 to the ninth transistor T9 can be oxide transistors, and some transistors can be low-temperature polysilicon transistors. Oxide transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0202] In some exemplary embodiments, the first transistor T1 and the second transistor T2 are of the opposite transistor type to the third transistor T3 through the ninth transistor T9. For example, the first transistor T1 and the second transistor T2 may be N-type transistors, and the third transistor T3 through the ninth transistor T9 may be P-type transistors.

[0203] In one exemplary embodiment, the first transistor T1 and the second transistor T2 can be oxide transistors, and the third transistor T3 to the ninth transistor T9 can be low-temperature polycrystalline silicon transistors.

[0204] In this disclosure, the operation of the pixel circuit in the non-display stage may include: a reverse bias stage and a threshold voltage acquisition stage.

[0205] During the reverse bias phase, the signal at the first reset signal terminal Reset1 is an active level signal, providing the signal at the first initial signal terminal Vinit1 to the first node N1. The signal at the third reset signal terminal Reset3 is an active level signal, providing the signal at the third initial signal terminal Vinit3 to the second node N2. The second signal provided by the control signal terminal S is provided to the third node N3. Since the voltage value of the second signal is greater than that of the third initial signal terminal Vinit3, the third transistor T3 is reverse-biased.

[0206] This disclosure improves the aging problem caused by the long-term forward conduction of the third transistor by setting the third transistor T3 to be reverse-biased during the reverse bias stage, thereby increasing the service life of the third transistor and improving the service life and reliability of the display substrate.

[0207] During the threshold voltage acquisition stage, the signal at the third reset signal terminal Reset3 is an effective level signal, and the control signal terminal S acquires the signal at the third node N3 to obtain the threshold voltage of the third transistor T3.

[0208] This disclosure obtains the threshold voltage of the third transistor T3 during the threshold voltage acquisition stage, thereby obtaining the threshold voltage offset of the third transistor. Based on the threshold voltage offset of the third transistor, the signal at the data signal terminal is adjusted in real time, realizing external compensation for the pixel circuit, which can extend the service life of the pixel circuit and improve the display effect and reliability of the display substrate.

[0209] The following is through Figure 8The operation of the example pixel circuit during the display stage illustrates an exemplary embodiment of this disclosure. Figure 8 This explanation uses the example of transistors T1 and T2 being N-type transistors, and transistors T3 through T9 being P-type transistors. Figure 6 The pixel circuit includes transistors T1 to T9, a capacitor C, and 12 signal terminals (data signal terminal Data, first scan signal terminal Gate1, second scan signal terminal Gate2, first reset signal terminal Reset1, second reset signal terminal Reset2, third reset signal terminal Reset3, first initial signal terminal Vinit1, second initial signal terminal Vinit2, third initial signal terminal Vinit3, control signal terminal S, light emission signal terminal EM, and first power supply terminal VDD). Figure 9 for Figure 8 The provided pixel circuit operating timing Figure 1 , Figure 10 for Figure 8 The provided pixel circuit operating timing Figure 2 , Figure 11 for Figure 8 The provided pixel circuit operating timing Figure 3 , Figure 12 for Figure 8 The provided pixel circuit operating timing Figure 4 .like Figure 9 This explanation is based on the example where the effective level signal of the second reset signal terminal Reset2 occurs before the effective level signal of the first reset signal terminal Reset1. Figure 10 This explanation is based on the example where the effective level signal of the second reset signal terminal Reset2 occurs within the effective level signal of the third reset signal terminal Reset3. Figure 11 This explanation is based on the example where the effective signal level of the second reset signal terminal Reset2 occurs within the effective signal level of the first scan signal terminal Gate1. Figure 12 The explanation is based on the fact that the effective level signal of the second reset signal terminal Reset2 occurs after the effective level signal of the first scan signal terminal Gate1.

[0210] In one exemplary embodiment, such as Figures 9 to 12 As shown, the control signal terminal S provides a first signal S1 with a constant voltage value during the display stage.

[0211] Combination Figure 8 and Figure 9 The operation of a pixel circuit can include:

[0212] In the first stage P11, also known as the first initialization stage, the signal at the second reset signal terminal Reset2 is a low-level signal, the seventh transistor T7 is turned on, and the signal at the second initial signal terminal Vinit2 is written to the fourth node N4 through the turned-on seventh transistor T7 to initialize (reset) the anode of the light-emitting element L, clear its internal pre-stored voltage, and complete the initialization.

[0213] The second stage, P12, is called the second initialization stage. The first reset signal terminal, Reset1, is high, turning on the first transistor T1. The signal from the first initial signal terminal, Vinit1, is written to the first node N1 through the turned-on transistor T1, initializing (resetting) node N1 and clearing its internal pre-stored voltage, thus completing the initialization. The third reset signal terminal, Reset3, is low, turning on the eighth transistor T8 and the ninth transistor T9. The signal from the third initial signal terminal, Vinit3, is written to the second node N2 through the turned-on transistor T8, initializing (resetting) node N2 and clearing its internal pre-stored voltage, thus completing the initialization. The first signal from the control signal terminal S is written to the third node N3 through the turned-on transistor T9, initializing (resetting) node N3 and clearing its internal pre-stored voltage, thus completing the initialization.

[0214] The third stage, P13, is called the data writing stage or threshold compensation stage. The first scan signal terminal, Gate1, is at a low level, and the data signal terminal, Data, outputs a data voltage. During this stage, since the first node, N1, is at a low level, the third transistor, T3, is turned on. With the first scan signal terminal, Gate1, at a low level, the fourth transistor, T4, is turned on. The second scan signal terminal, Gate2, at a high level, the second transistor, T2, is turned on. The data voltage output from the Data signal terminal is supplied to the first node, N1, via the turned-on fourth transistor, T4, N2, T3, and T2. The difference between the data voltage output from the Data signal terminal and the threshold voltage of the third transistor, T3, is charged into capacitor C until the voltage at the first node, N1, is Vd - |Vth|, where Vd is the data voltage output from the Data signal terminal and Vth is the threshold voltage of the third transistor, T3.

[0215] The fourth stage, P14, is called the light-emitting stage. The signal at the light-emitting signal terminal EM is a low-level signal. The fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting element L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element L to emit light.

[0216] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is:

[0217] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0218] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0219] Combination Figure 8 and Figure 10 , Figure 9 The provided pixel circuit operating timing and Figure 10 The commonality in the provided pixel circuit timing diagrams is that... Figure 10 The working process of the second phase P22 provided is similar to Figure 9 The working process provided for the third stage, P13, is consistent. Figure 10 The working process provided in the third stage, P23, is similar to... Figure 9 The working process of the fourth stage, P14, is the same, except that... Figure 10 The first phase, P21, is provided.

[0220] In the first stage, P21, called the initialization stage, the first reset signal terminal Reset1 is high, the first transistor T1 is turned on, and the signal of the first initial signal terminal Vinit1 is written to the first node N1 through the turned-on first transistor T1, initializing (resetting) the first node N1, clearing its internal pre-stored voltage, and completing the initialization. The second reset signal terminal Reset2 is low, the seventh transistor T7 is turned on, and the signal of the second initial signal terminal Vinit2 is written to the fourth node N4 through the turned-on seventh transistor T7, initializing (resetting) the anode of the light-emitting element L, clearing its internal pre-stored voltage, and completing the initialization. The third reset signal terminal Reset3 is low, the eighth transistor T8 and the ninth transistor T9 are turned on, and the signal of the third initial signal terminal Vinit3 is written to the second node N2 through the turned-on eighth transistor T8, initializing (resetting) the second node N2, clearing its internal pre-stored voltage, and completing the initialization. The first signal of the control signal terminal S is written to the third node N3 through the conducting ninth transistor T9 to initialize (reset) the third node N3, clear its internal pre-stored voltage, and complete the initialization.

[0221] Combination Figure 8 and Figure 11 , Figure 9 The provided pixel circuit operating timing and Figure 11 The commonality in the provided pixel circuit timing diagrams is that... Figure 11 The first phase of P31's working process and Figure 9 The working process provided for the second stage, P12, is consistent. Figure 11 The working process of the third stage P33 provided is as follows: Figure 9 The working process of the fourth stage, P14, is the same, except that... Figure 10 The second phase, P32, is provided.

[0222] In the second stage, P32, also known as the data writing stage or threshold compensation stage, the first scan signal terminal Gate1 is at a low level, and the data signal terminal Data outputs the data voltage. During this stage, since the first node N1 is at a low level, the third transistor T3 is turned on. The first scan signal terminal Gate1 is at a low level, and the fourth transistor T4 is turned on. The second scan signal terminal Gate2 is at a high level, and the second transistor T2 is turned on. The data voltage output from the data signal terminal Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal terminal Data and the threshold voltage of the third transistor T3 is charged into capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output from the data signal terminal Data and Vth is the threshold voltage of the third transistor T3. The second reset signal terminal Reset2 is at a low level, and the seventh transistor T7 is turned on. The signal from the second initial signal terminal Vinit2 is written to the fourth node N4 through the turned-on seventh transistor T7, which initializes (resets) the anode of the light-emitting element L, clears its internal pre-stored voltage, and completes the initialization.

[0223] Combination Figure 8 and Figure 12 , Figure 9 The provided pixel circuit operating timing and Figure 12 The commonality in the provided pixel circuit timing diagrams is that... Figure 12 The working process of the first phase P41 provided and Figure 9 The working process provided for the second stage, P12, is consistent. Figure 12 The working process of the second phase P42 provided is as follows: Figure 9 The working process provided for the third stage, P13, is consistent. Figure 12 The working process of the fourth stage, P44, is provided. Figure 9 The working process of the fourth stage, P14, is the same, except that... Figure 12 The third stage is provided on page 43.

[0224] In the third stage, P43, which is called the second initialization stage, the signals of the second reset signal terminal Reset2 are low-level signals, the seventh transistor T7 is turned on, and the signal of the second initial signal terminal Vinit2 is written to the fourth node N4 through the turned-on seventh transistor T7 to initialize (reset) the anode of the light-emitting element L, clear its internal pre-stored voltage, and complete the initialization.

[0225] This disclosure resets the first node N1, the second node N2, and the third node N3 during the display phase, ensuring that the voltage between the electrodes of the driving transistors in the pixel circuit remains consistent during each initialization phase. The driving transistors are in a fixed bias conducting state during the initialization phase, and then enter the data writing and compensation phase. This guarantees that the electrodes of the driving transistors have a consistent aging effect, which can improve the short-term or medium-term image retention problem caused by the hysteresis effect due to inconsistent aging states of the driving transistors, improve the display effect of the display substrate, and enhance the service life and reliability of the display substrate.

[0226] Figure 13A This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. Figure 13A As shown in Figure 13, the present disclosure also provides a display substrate comprising: a substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate. The light-emitting structure layer includes light-emitting elements, and the circuit structure layer includes pixel circuits arranged in an array. Figure 13 illustrates an example of a four-column pixel circuit per row.

[0227] The pixel circuit is the same as the pixel circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0228] In one exemplary embodiment, the display substrate may be a low-temperature polycrystalline oxide (LTPO) display substrate.

[0229] In one exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be one or more of glass and conductive foil, but is not limited to; the flexible substrate may be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber, but is not limited to.

[0230] In one exemplary embodiment, the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on a substrate; the anode layer includes an anode, the organic structure layer includes an organic light-emitting layer, and the cathode layer includes a cathode.

[0231] In one exemplary embodiment, the light-emitting element may include: a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element, wherein the first light-emitting element emits red light, the second light-emitting element emits blue light, and the third and fourth light-emitting elements emit green light; the area of ​​the anode of the second light-emitting element is larger than the area of ​​the anode of the first light-emitting element, and the anodes of the third and fourth light-emitting elements are symmetrical about a virtual straight line extending along a first direction.

[0232] In one exemplary embodiment, when the occurrence of a valid level signal at the second reset signal terminal precedes the occurrence of a valid level signal at the first reset signal terminal, the signal at the second reset signal terminal of the i-th row pixel circuit is the same as the signal at the first scan signal terminal of the (i-1)-th row pixel circuit. When the occurrence of a valid level signal at the second reset signal terminal precedes the occurrence of a valid level signal at the first scan signal terminal, the signal at the second reset signal terminal of the i-th row pixel circuit is the same as the signal at the first scan signal terminal of the (i+1)-th row pixel circuit.

[0233] In one exemplary embodiment, such as Figure 13A As shown, the circuit structure layer also includes: multiple first reset signal lines RL1, multiple second reset signal lines RL2, multiple third reset signal lines RL3, multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple first initial signal lines INL1, multiple second initial signal lines INL2, multiple third initial signal lines INL3, multiple light emission signal lines EL, and multiple control signal lines SL, as well as multiple first power supply lines VDDL and multiple data signal lines DL, which extend along the second direction and are arranged along the first direction, and the first direction intersects the second direction. Specifically, the pixel circuit has the following components: a first reset signal terminal electrically connected to a first reset signal line; a second reset signal terminal electrically connected to a second reset signal line; a third reset signal terminal electrically connected to a third reset signal line; a first scan signal terminal electrically connected to a first scan signal line; a second scan signal terminal electrically connected to a second scan signal line; an emission signal terminal electrically connected to an emission signal line; a first initial signal terminal electrically connected to a first initial signal line; a second initial signal terminal electrically connected to a second initial signal line; a second initial signal terminal electrically connected to a second initial signal line; a control signal terminal electrically connected to a control signal line; a first power supply terminal electrically connected to a first power supply line; and a data signal terminal electrically connected to a data signal line.

[0234] In one exemplary embodiment, the system further includes a first chip connected to a control signal line and a second chip connected to a data signal line. The first chip is configured to provide a first signal to the control signal line during a display phase, provide a second signal to the control signal line during a non-display phase, or acquire a signal from the control signal line. It is also configured to obtain a threshold voltage of a third transistor based on the signal from the control signal line, generate a control signal based on the threshold voltage of the third transistor, and send the control signal to the second chip. The second chip provides a signal to the data signal line based on the control signal to perform external compensation on the pixel circuitry.

[0235] In one exemplary embodiment, the signal of the control signal line can be a current I flowing through the control signal line.

[0236] In one exemplary embodiment, the first chip uses the formula I = μ*W*Cox*(Vgs-Vth) based on the signal from the control signal line. 2 / 2L, to obtain the threshold voltage Vth of the third transistor. Where μ is the mobility of the third transistor, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor, L is the length of the channel region of the third transistor, W is the width of the channel region of the third transistor, and Cox is the gate oxide capacitance per unit area of ​​the third transistor.

[0237] In one exemplary embodiment, such as Figure 13A As shown, the pixel structure of adjacent pixel circuits located in the same row is symmetrical with respect to a dummy straight line extending along the second direction. The adjacent pixel circuits located in the same row as the pixel circuits include: a first adjacent pixel circuit and a second adjacent pixel circuit.

[0238] In one exemplary embodiment, the pixel circuit includes: a first transistor to a ninth transistor, wherein the control electrode of the first transistor and the control electrode of the second transistor both include: a first control electrode and a second control electrode.

[0239] In one exemplary embodiment, the first reset signal line may include: a first sub-reset signal line and a second sub-reset signal line that are disposed on different layers and interconnected, wherein the first sub-reset signal line is disposed on the same layer as the first control electrode of the first transistor, and the second sub-reset signal line is disposed on the same layer as the second control electrode of the first transistor. The second scan signal line may include: a first sub-scan signal line and a second sub-scan signal line that are disposed on different layers and interconnected, wherein the first sub-scan signal line is disposed on the same layer as the first control electrode of the second transistor, and the second sub-scan signal line is disposed on the same layer as the second control electrode of the second transistor.

[0240] In one exemplary embodiment, the pixel circuit may further include a capacitor, which includes a first electrode and a second electrode.

[0241] In one exemplary embodiment, Figure 13B for Figure 13A A cross-sectional view along the AA direction, as shown below. Figure 13A and Figure 13B As shown, the circuit structure layer may include: a first insulating layer 21, a first semiconductor layer, a second insulating layer 22, a first conductive layer, a third insulating layer 23, a second conductive layer, a fourth insulating layer 24, a second semiconductor layer, a fifth insulating layer 25, a third conductive layer, a sixth insulating layer 26, a fourth conductive layer, a seventh insulating layer 27, a first planarization layer 28, and a fifth conductive layer, which are sequentially stacked on the substrate 10.

[0242] The first semiconductor layer may include: the active layer of the third transistor to the active layer T91 of the ninth transistor located in at least one pixel circuit;

[0243] The first conductive layer may include: a first scan signal line, a light emission signal line, and a first electrode of a capacitor located in at least one pixel circuit, and the control electrode of the third transistor to the control electrode T92 of the ninth transistor;

[0244] The second conductive layer may include: a first initial signal line, a first sub-reset signal line, a first sub-scan signal line, a control signal line, and a second plate of a capacitor located in at least one pixel circuit, a first control electrode of a first transistor, and a first control electrode of a second transistor;

[0245] The second semiconductor layer may include: an active layer of a first transistor located in at least one pixel circuit, an active layer of a second transistor, and an active connection portion; the active connection portion is configured to connect the active layer of the first transistor and the active layer of the second transistor.

[0246] The third conductive layer may include: a second sub-reset signal line, a second sub-scan signal line, a third reset signal line, and a third initial signal line, as well as a second control electrode of a first transistor and a second control electrode of a second transistor located in at least one pixel circuit;

[0247] The fourth conductive layer may include: a second initial signal line and the first and second electrodes of a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a first connection electrode VL1 located in at least one pixel circuit; the first connection electrode is configured to connect the control electrode T82 of the eighth transistor, the control electrode T92 of the ninth transistor, and the third reset signal line;

[0248] The fifth conductive layer may include: a first power line VDDL, a data signal line, and a second connection electrode located in at least one pixel circuit, wherein the second connection electrode is configured to connect the second electrode of the sixth transistor and the light-emitting element.

[0249] In one exemplary embodiment, the circuit structure layer may further include a light-shielding layer located on the side of the first insulating layer 21 near the substrate. The light-shielding layer includes light-shielding portions and light-shielding connection portions SHC arranged in an array and spaced apart from each other. The light-shielding connection portions are configured to connect adjacent light-shielding portions; the orthographic projection of the light-shielding portions on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate.

[0250] In one exemplary embodiment, the control electrode T82 of the eighth transistor and the control electrode T92 of the ninth transistor are integrally formed; the first scan signal line and the light emission signal line connected to the pixel circuit are respectively located on both sides of the first plate of the capacitor of the pixel circuit, and the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor is located between the first plate of the capacitor and the light emission signal line connected to the pixel circuit.

[0251] In one exemplary embodiment, the first control electrode of the first transistor and the first sub-reset signal line are integrally formed, and the second control electrode of the second transistor and the first sub-scan signal line are integrally formed; the first initial signal line, the first sub-reset signal line, and the first sub-scan signal line connected to the pixel circuit extend along a first direction and are located on the same side of the second plate of the capacitor of the pixel circuit; the first sub-reset signal line is located on the side of the first initial signal line close to the second plate of the capacitor of the pixel circuit, and the first sub-scan signal line is located on the side of the first sub-reset signal line close to the second plate of the capacitor of the pixel circuit; the control signal line is located on the side of the second plate of the capacitor of the pixel circuit away from the first sub-scan signal line.

[0252] In one exemplary embodiment, the orthographic projection of the first scan signal line on the substrate is located between the orthographic projection of the first sub-reset signal line on the substrate and the orthographic projection of the first sub-scan signal line on the substrate; the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate is located between the orthographic projection of the second electrode plate of the capacitor on the substrate and the orthographic projection of the control signal line on the substrate; the orthographic projection of the control signal line on the substrate is located between the orthographic projection of the light emission signal line on the substrate and the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate; the second electrode plate of the capacitor of the pixel circuit is electrically connected to the second electrode plate of the capacitor of the first adjacent pixel circuit.

[0253] In one exemplary embodiment, the active layer of the first transistor and the active layer of the second transistor are located on opposite sides of the active connection portion; the orthographic projection of the active layer of the first transistor on the substrate overlaps with the orthographic projection of the first initial signal line on the substrate; the orthographic projection of the active layer of the second transistor on the substrate overlaps with the orthographic projection of the first sub-scan signal line on the substrate; and the orthographic projection of the active connection portion on the substrate at least partially overlaps with the orthographic projection of the first scan signal line on the substrate.

[0254] In one exemplary embodiment, the second control electrode of the first transistor and the second sub-reset signal line are integrally formed, and the first control electrode of the second transistor and the second sub-scan signal line are integrally formed; the second sub-scan signal line is located between the second sub-reset signal line and the third reset signal line, and the third initial signal line is located on the side of the third reset signal line away from the second sub-reset signal line; the orthographic projection of the second sub-reset signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-reset signal line on the substrate, and is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first scan signal line on the substrate; the second sub-scan signal line on the substrate... The orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line on the substrate, and is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the second plate of the capacitor on the substrate; the orthographic projection of the third reset signal line on the substrate is located between the orthographic projection of the second plate of the capacitor on the substrate and the orthographic projection of the integral structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate; the orthographic projection of the third initial signal line on the substrate is located on the side of the orthographic projection of the control signal line on the substrate away from the orthographic projection of the second plate of the capacitor on the substrate, and partially overlaps with the orthographic projections of the light-emitting signal line and the control signal line on the substrate.

[0255] In one exemplary embodiment, the sixth insulating layer may have a plurality of via patterns, including: a first to a seventh via formed on the second to sixth insulating layers, an eighth and a ninth via formed on the third to sixth insulating layers, a tenth to a twelfth via formed on the fourth to sixth insulating layers, a thirteenth to a fifteenth via formed on the fifth and sixth insulating layers, and a sixteenth and a seventeenth via formed on the sixth insulating layer; a third via exposes the active layer of the fifth transistor, a tenth via exposes the first initial signal line, and an eleventh via exposes the second plate of the capacitor; a virtual straight line extending along a second direction passes through the third and eleventh vias; the third via of the pixel circuit is the same as the third via of the first adjacent pixel circuit; the eleventh via of the pixel circuit is the same as the eleventh via of the first adjacent pixel circuit; and the tenth via of the pixel circuit is the same as the tenth via of the second adjacent pixel circuit.

[0256] In one exemplary embodiment, the first electrode of the fifth transistor of the pixel circuit is the same electrode as the first electrode of the fifth transistor of the first adjacent pixel circuit; the orthographic projection of the second initial signal line on the substrate overlaps with the orthographic projections of the first reset signal line and the first scan signal line on the substrate; the orthographic projection of the second electrode of the first transistor and the integrally formed structure of the second electrode of the second transistor on the substrate overlaps at least partially with the orthographic projections of the active connection portion, the second scan signal line, and the second plate of the capacitor on the substrate; the orthographic projection of the first electrode of the fifth transistor on the substrate overlaps with the orthographic projections of the second plate of the capacitor, the third reset signal line, the control signal line, the light emission signal line, and the third initial signal line on the substrate; the orthographic projection of the first connection electrode on the substrate overlaps at least partially with the orthographic projections of the third reset signal line and the control electrode of the eighth transistor on the substrate; the orthographic projection of the first electrode of the eighth transistor on the substrate overlaps with the orthographic projections of the control signal line, the light emission signal line, and the third initial signal line on the substrate; and the orthographic projection of the first electrode of the ninth transistor on the substrate overlaps with the orthographic projection of the control signal line on the substrate.

[0257] In one exemplary embodiment, the data signal line and the first power line connected to the pixel circuit are located on the same side of the second connection electrode; the first power line may include a power supply body portion and a power supply connection portion connected to each other, wherein the power supply connection portion is located on the side of the power supply body portion away from the data signal line; the power supply connection portion of the first power line connected to the pixel circuit is connected to the power supply connection portion of the first power line connected to the second adjacent pixel circuit. The orthographic projection of the power supply connection portion on the substrate overlaps with the orthographic projection portions of the active connection portion, the second scan signal line, the first scan signal line, and the second initial signal line on the substrate.

[0258] The structure of a display substrate is illustrated below using an example of the fabrication process of the display substrate. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying and spin coating; and etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0259] Figures 14 to 23B A schematic diagram of the fabrication process of a display substrate provided for an exemplary embodiment. Figures 14 to 23B This explanation uses a four-row pixel circuit as an example, where the second reset signal and the first scan signal line are the same signal line. Figures 14 to 23B As shown, the fabrication process of a display substrate provided in an exemplary embodiment may include:

[0260] (1) Forming a light-shielding layer pattern on a substrate, including: depositing a light-shielding film on the substrate, and patterning the light-shielding film using a patterning process to form a light-shielding layer pattern, such as... Figure 14 As shown, Figure 14 This is a schematic diagram of the light-shielding layer pattern.

[0261] In one exemplary embodiment, such as Figure 14 As shown, the light-shielding layer may include: light-shielding portions SHL arranged in an array and spaced apart from each other, and light-shielding connecting portions SHL. The light-shielding connecting portions SHL are configured to connect adjacent light-shielding portions SHL.

[0262] In one exemplary embodiment, such as Figure 14 As shown, the shape of the light-shielding part SHL can be square.

[0263] In one exemplary embodiment, such as Figure 14 As shown, the light-shielding connecting portion SHL connecting adjacent light-shielding portions SHL located in the same row extends along a first direction, and the light-shielding connecting portion SHL connecting adjacent light-shielding portions SHL located in the same column extends along a second direction.

[0264] (2) Forming a first semiconductor layer pattern includes: depositing a first insulating film and a first semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the first insulating film and the first semiconductor film using a patterning process to form a first insulating layer pattern and a first semiconductor layer pattern formed on the first insulating layer pattern, such as... Figure 15A and Figure 15B As shown, Figure 15A This is a schematic diagram of the pattern of the first semiconductor layer. Figure 15B This is a schematic diagram after the first semiconductor layer pattern has been formed.

[0265] In one exemplary embodiment, such as Figure 15A and Figure 15B As shown, the first semiconductor layer may include: an active layer T31 of a third transistor, an active layer T41 of a fourth transistor, an active layer T51 of a fifth transistor, an active layer T61 of a sixth transistor, a seventh transistor T71, an active layer T81 of an eighth transistor, and an active layer T91 of a ninth transistor located in at least one pixel circuit.

[0266] In one exemplary embodiment, the active layer T31 of the third transistor to the active layer T91 of the ninth transistor can be an integrally formed structure.

[0267] In an exemplary embodiment, the active layer T31 of the third transistor may be in a "ji" shape.

[0268] In an exemplary embodiment, the sides of the active layer of the third transistor include: a first side, a second side, a third side, and a fourth side, where the first side and the second side are oppositely arranged, and the third side and the fourth side are oppositely arranged. Among them, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor are located on the first side of the active layer T31 of the third transistor and extend along the second direction. The active layer T61 of the sixth transistor is located on the second side of the active layer T31 of the third transistor and extends along the second direction. The active layer T81 of the eighth transistor is located near the active layer T61 of the sixth transistor of the active layer T51 of the fifth transistor, and the active layer T91 of the ninth transistor is located near the active layer T51 of the fifth transistor of the active layer T61 of the sixth transistor. The shapes of the active layer T81 of the eighth transistor and the active layer T91 of the ninth transistor may be an inverted "L" shape.

[0269] In an exemplary embodiment, the orthographic projection of the active layer T31 of the third transistor on the substrate at least partially overlaps with the orthographic projection of the light-shielding portion on the substrate.

[0270] (3) Form a first conductive layer pattern, including: on the substrate on which the foregoing pattern is formed, sequentially deposit a second insulating film and a first conductive film, and pattern the second insulating film and the first conductive film through a patterning process to form a second insulating layer pattern and a first conductive layer pattern located on the second insulating layer, as Figure 16A and Figure 16B shown, where Figure 16A is a schematic diagram of the first conductive layer pattern, Figure 16B is a schematic diagram after forming the first conductive layer pattern.

[0271] In an exemplary embodiment, as Figure 16A and Figure 16B shown, the first conductive layer may include: a first scan signal line GL1, a light-emitting signal line EL, and a first electrode plate C1 of a capacitor in at least one pixel circuit, a control electrode T32 of the third transistor, a control electrode T42 of the fourth transistor, a control electrode T52 of the fifth transistor, a control electrode T62 of the sixth transistor, a control electrode T72 of the seventh transistor, a control electrode T82 of the eighth transistor, and a control electrode T92 of the ninth transistor.

[0272] In an exemplary embodiment, as Figure 16A and Figure 16BAs shown, for any pixel circuit, the control electrode T32 of the third transistor and the first plate C1 of the capacitor are integrally formed; the control electrode T42 of the fourth transistor, the control electrode T72 of the seventh transistor and the first scan signal line GL1 connected to the pixel circuit are integrally formed; the control electrode T52 of the fifth transistor and the control electrode T62 of the sixth transistor and the light emission signal line EL connected to the pixel circuit are integrally formed; and the control electrode T82 of the eighth transistor and the control electrode T9 of the ninth transistor are integrally formed.

[0273] In this disclosure, the control electrode T82 of the eighth transistor and the control electrode T9 of the ninth transistor are integrally molded, which can simplify the manufacturing process of the display substrate and improve the reliability of the display substrate.

[0274] In one exemplary embodiment, such as Figure 16A and Figure 16B As shown, the first scan signal line GL1 and the light emission signal line EL connected to the pixel circuit extend along the first direction and are located on both sides of the first plate C1 of the capacitor of the pixel circuit.

[0275] In one exemplary embodiment, such as Figure 16A and Figure 16B As shown, the integral structure of the control electrode T82 of the eighth transistor and the control electrode T92 of the ninth transistor extends along the first direction and is located between the first plate C1 of the capacitor and the light-emitting signal line EL connected to the pixel circuit.

[0276] In one exemplary embodiment, the orthographic projection of the first plate of the capacitor onto the substrate at least partially overlaps with the orthographic projection of the light-shielding portion onto the substrate.

[0277] In one exemplary embodiment, the control electrode T32 of the third transistor is disposed across the active layer of the third transistor, the control electrode T42 of the fourth transistor is disposed across the active layer of the fourth transistor, the control electrode T52 of the fifth transistor is disposed across the active layer of the fifth transistor, the control electrode T62 of the sixth transistor is disposed across the active layer of the sixth transistor, the control electrode T72 of the seventh transistor is disposed across the active layer of the seventh transistor, the control electrode T82 of the eighth transistor is disposed across the active layer of the eighth transistor, and the control electrode T92 of the ninth transistor is disposed across the active layer of the ninth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0278] In one exemplary embodiment, the process further includes a conductor-enhancing process. The conductor-enhancing process involves, after forming the first conductive layer pattern, using the semiconductor layer in the control electrode shielding region of multiple transistors (i.e., the region where the semiconductor layer overlaps with the control electrode) as the channel region of the transistor, and processing the semiconductor layer in the region not shielded by the first conductive layer into a conductor-enhancing layer to form the first electrode connection portion and the second electrode connection portion of the transistor. For example... Figure 16B As shown, the first electrode connection portion of the active layer of the third transistor can be reused as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the second electrode T84 of the eighth transistor. The second electrode connection portion of the active layer of the third transistor can be reused as the second electrode T34 of the third transistor, the second electrode T64 of the sixth transistor, and the second electrode T94 of the ninth transistor.

[0279] (4) Forming a second conductive layer pattern includes: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; and patterning the third insulating film and the second conductive film using a patterning process to form a third insulating layer pattern and a second conductive layer pattern located on the second insulating layer. Figure 17A and Figure 17B As shown, Figure 17A This is a schematic diagram of the pattern of the second conductive layer. Figure 17B This is a schematic diagram after the second conductive layer pattern has been formed.

[0280] In one exemplary embodiment, such as Figure 17A and Figure 17B As shown, the second conductive layer may include: a first initial signal line INL1, a first sub-reset signal line RL1A, a first sub-scan signal line GL2A, a control signal line SL, and a second plate C2 of a capacitor located in at least one pixel circuit, a first control electrode T12A of a first transistor, and a first control electrode T22A of a second transistor.

[0281] In one exemplary embodiment, the first control electrode T12A of the first transistor and the first sub-reset signal line RL1A are integrally formed, and the first control electrode T22A of the second transistor and the first sub-scan signal line GL2A are integrally formed.

[0282] In one exemplary embodiment, such as Figure 17A and Figure 17BAs shown, the first initial signal line INL1, the first sub-reset signal line RL1A, and the first sub-scan signal line GL2A connected to the pixel circuit extend along the first direction and are located on the same side of the second plate C2 of the capacitor in the pixel circuit. The first sub-reset signal line RL1A is located on the side of the first initial signal line INL1 closest to the second plate C2 of the capacitor in the pixel circuit, and the first sub-scan signal line GL2A is located on the side of the first sub-reset signal line RL1A closest to the second plate C2 of the capacitor in the pixel circuit. The control signal line SL extends along the first direction and is located on the side of the second plate C2 of the capacitor in the pixel circuit away from the first sub-scan signal line GL2A.

[0283] In one exemplary embodiment, the orthographic projection of the second plate C2 of the capacitor in the pixel circuit onto the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor onto the substrate, and the second plate C2 of the capacitor is provided with a through hole V0 exposing the first plate of the capacitor.

[0284] In one exemplary embodiment, the orthographic projection of the first scan signal line GL1 onto the substrate is located between the orthographic projection of the first sub-reset signal line RL1A onto the substrate and the orthographic projection of the first sub-scan signal line GL2A onto the substrate.

[0285] In one exemplary embodiment, the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate is located between the orthographic projection of the second plate C2 of the capacitor on the substrate and the orthographic projection of the control signal line SL on the substrate.

[0286] In one exemplary embodiment, the orthographic projection of the control signal line SL connected to the pixel circuit on the substrate is located between the orthographic projection of the light emission signal line EL on the substrate and the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate.

[0287] In one exemplary embodiment, the second plate C2 of the capacitor of the pixel circuit is electrically connected to the second plate C2 of the capacitor of the first adjacent pixel circuit.

[0288] (5) Forming a second semiconductor layer pattern includes: on a substrate on which the aforementioned pattern is formed, including: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate, and patterning the fourth insulating film and the second semiconductor film using a patterning process to form a fourth insulating layer pattern and a second semiconductor layer pattern located on a third insulating layer, such as... Figure 18A and Figure 18B As shown, Figure 18A This is a schematic diagram of the pattern of the second semiconductor layer. Figure 18B This is a schematic diagram after the second semiconductor layer pattern has been formed.

[0289] In one exemplary embodiment, such as Figure 18A and Figure 18B As shown, the second semiconductor layer may include: an active layer T11 of a first transistor located in at least one pixel circuit, an active layer T21 of a second transistor, and an active connection portion AL.

[0290] In one exemplary embodiment, such as Figure 18A and Figure 18B As shown, the active layer T11 of the first transistor, the active layer T21 of the second transistor, and the active connection portion AL are integrally formed structures.

[0291] In one exemplary embodiment, such as Figure 18A and Figure 18B As shown, the active layer T11 of the first transistor and the active layer T21 of the second transistor extend along the second direction and are located on both sides of the active connection portion AL, respectively.

[0292] In one exemplary embodiment, such as Figure 18A and Figure 18B As shown, the orthographic projection of the active layer T11 of the first transistor onto the substrate overlaps with the orthographic projection of the first initial signal line INL1 onto the substrate. The orthographic projection of the active layer T211 of the second transistor onto the substrate overlaps with the orthographic projection of the first sub-scan signal line GL2A onto the substrate.

[0293] In one exemplary embodiment, such as Figure 18A and Figure 18B As shown, the orthographic projection of the active connection portion AL on the substrate at least partially overlaps with the orthographic projection of the first scan signal line GL1 on the substrate, and its shape can be square.

[0294] In one exemplary embodiment, the active layer T11 of the first transistor is disposed across the first control electrode of the first transistor, and the active layer T21 of the second transistor is disposed across the first control electrode of the second transistor.

[0295] (6) Forming a third conductive layer includes: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; and patterning the fifth insulating film and the third conductive film using a patterning process to form a fifth insulating layer pattern and a third conductive layer pattern located on the fourth insulating layer. Figure 19A and Figure 19B As shown, Figure 19A This is a schematic diagram of the pattern of the third conductive layer. Figure 19B This is a schematic diagram after the third conductive layer pattern has been formed.

[0296] In one exemplary embodiment, such as Figure 19A and Figure 19BAs shown, the third conductive layer may include: a second sub-reset signal line RL1B, a second sub-scan signal line GL2B, a third reset signal line RL3 and a third initial signal line INL3, as well as the second control electrode T12B of the first transistor and the second control electrode T22B of the second transistor located in at least one pixel circuit.

[0297] In one exemplary embodiment, the second control electrode T12B of the first transistor and the second sub-reset signal line RL1A are integrally formed, and the second control electrode T22B of the second transistor and the second sub-scan signal line GL2A are integrally formed.

[0298] In one exemplary embodiment, such as Figure 19A and Figure 19B As shown, the second sub-reset signal line RL1B, the second sub-scan signal line GL2B, the third reset signal line RL3, and the third initial signal line INL3 connected to the pixel circuit all extend along the first direction. The second sub-scan signal line GL2B is located between the second sub-reset signal line RL1B and the third reset signal line RL3, and the third initial signal line INL3 is located on the side of the third reset signal line RL3 away from the second sub-reset signal line RL1B.

[0299] In one exemplary embodiment, such as Figure 19A and Figure 19B As shown, the orthographic projection of the second sub-reset signal line RL1B on the substrate at least partially overlaps with the orthographic projection of the first sub-reset signal line on the substrate, and is located between the orthographic projection of the first initial signal line INL1 on the substrate and the orthographic projection of the first scan signal line GL1 on the substrate.

[0300] In one exemplary embodiment, such as Figure 19A and Figure 19B As shown, the orthographic projection of the second sub-scan signal line GL2B on the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line on the substrate, and is located between the orthographic projection of the first scan signal line GL1 on the substrate and the orthographic projection of the second plate of the capacitor on the substrate.

[0301] In one exemplary embodiment, such as Figure 19A and Figure 19B As shown, the orthographic projection of the third reset signal line RL3 on the substrate is located between the orthographic projection of the second plate of the capacitor on the substrate and the orthographic projection of the integral structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate.

[0302] In one exemplary embodiment, such as Figure 19A and Figure 19BAs shown, the orthographic projection of the third initial signal line INL3 on the substrate is located on the side of the second plate of the capacitor away from the orthographic projection of the control signal line SL on the substrate, and overlaps with the orthographic projections of the light-emitting signal line EL and the control signal line SL on the substrate.

[0303] (7) Forming a sixth insulating layer pattern includes: depositing a fifth insulating film on a substrate having the aforementioned pattern, and patterning the sixth insulating film using a patterning process to form a sixth insulating layer pattern covering the aforementioned pattern. The sixth insulating layer has multiple via patterns, such as... Figure 20 As shown, Figure 20 This is a schematic diagram after the sixth insulating layer pattern has been formed.

[0304] In one exemplary embodiment, such as Figure 20 As shown, the via patterns include: first vias V1 to V7 on the second to sixth insulating layers; eighth vias V8 and ninth vias V9 on the third to sixth insulating layers; tenth vias V10 to twelfth vias V12 on the fourth to sixth insulating layers; thirteenth vias V13 to fifteenth vias V15 on the fifth and sixth insulating layers; and sixteenth vias V16 and seventeenth vias V17 on the sixth insulating layer. Specifically, the first via V1 exposes the active layer of the third transistor; the second via V2 exposes the active layer of the fourth transistor; the third via V3 exposes the active layer of the fifth transistor; the fourth via V4 exposes the active layer of the sixth transistor; the fifth via V5 exposes the active layer of the seventh transistor; the sixth via V6 exposes the active layer of the eighth transistor; the seventh via V7 exposes the active layer of the ninth transistor; the eighth via V8 exposes the first electrode; and the ninth via V9 exposes the control electrode of the eighth transistor. The structure is integrally formed with the control electrode of the ninth transistor. The tenth via V10 exposes the first initial signal line, the eleventh via V11 exposes the second plate of the capacitor, the twelfth via V12 exposes the control signal line, the thirteenth via V13 exposes the active layer of the first transistor, the fourteenth via V14 exposes the active layer of the second transistor, the fifteenth via V15 exposes the active connection portion, the sixteenth via V16 exposes the third reset signal line, and the seventeenth via V17 exposes the third initial signal line.

[0305] In one exemplary embodiment, such as Figure 20 As shown, the adjacent pixel circuits located in the same row as the pixel circuits include the first adjacent pixel circuit and the second adjacent pixel circuit.

[0306] In one exemplary embodiment, such as Figure 20As shown, the third via V3 of the pixel circuit shares the same via as the third via V3 of the first adjacent pixel circuit. This sharing of the same via with the third via V3 of the first adjacent pixel circuit simplifies the manufacturing process of the display substrate.

[0307] In one exemplary embodiment, such as Figure 20 As shown, the eleventh via V11 of the pixel circuit and the eleventh via V11 of the first adjacent pixel circuit are the same via. Having the same via as the first adjacent pixel circuit simplifies the manufacturing process of the display substrate.

[0308] In one exemplary embodiment, such as Figure 20 As shown, the tenth via V10 of the pixel circuit and the tenth via V10 of the second adjacent pixel circuit share the same via. This sharing of the tenth via V10 of the pixel circuit and the tenth via V10 of the second adjacent pixel circuit simplifies the manufacturing process of the display substrate.

[0309] In one exemplary embodiment, such as Figure 20 As shown, the virtual straight line extending along the second direction passes through the third via V3 and the eleventh via V11.

[0310] (8) Forming a fourth conductive layer pattern includes: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern, such as... Figure 21A and Figure 21B As shown, Figure 21A This is a schematic diagram of the pattern of the fourth conductive layer. Figure 21B This is a schematic diagram after the fourth conductive layer pattern has been formed.

[0311] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the fourth conductive layer may include: a second initial signal line INL2 and a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 and a second electrode T24 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, a first electrode T73 and a second electrode T74 of a seventh transistor, a first electrode T83 of an eighth transistor, a first electrode T93 of a ninth transistor, and a first connection electrode VL1.

[0312] In one exemplary embodiment, such as Figure 21A and Figure 21BAs shown, the first electrode T53 of the fifth transistor in the pixel circuit is the same electrode as the first electrode T53 of the fifth transistor in the first adjacent pixel circuit, and the shape of the first electrode T53 of the fifth transistor in the pixel circuit can be an inverted "T" shape.

[0313] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the first electrode T73 and the second initial signal line INL2 of the seventh transistor are integrally molded structures, the second electrode T14 of the first transistor and the second electrode T24 of the second transistor are integrally molded structures, and the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor are integrally molded structures.

[0314] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the first electrode T13 of the first transistor is connected to the active layer of the first transistor through the thirteenth via, and to the first initial signal line through the tenth via. The integrated structure of the second electrode T14 of the first transistor and the first electrode T23 of the second transistor is connected to the active connection portion through the fifteenth via, and to the first electrode plate of the capacitor through the eighth via. The second electrode T24 of the second transistor is connected to the first electrode of the third transistor through the first via, and to the active layer of the second transistor through the fourteenth via. The first electrode T43 of the fourth transistor is connected to the active layer of the fourth transistor through the second via. The first electrode T53 of the fifth transistor is connected to the active layer of the fifth transistor through the third via, and to the second electrode plate through the eleventh via. The integrated structure of the second electrodes T64 of the sixth transistor and T74 of the seventh transistor is connected to the active layer of the sixth transistor through the fourth via. The first electrode T73 of the seventh transistor is connected to the active layer of the seventh transistor through the fifth via. The first terminal T83 of the eighth transistor is connected to the active layer of the eighth transistor through the sixth via, and to the third initial signal line through the seventeenth via. The first terminal T93 of the ninth transistor is connected to the active layer of the ninth transistor through the seventh via, and to the control signal line through the twelfth via. The first connection terminal VL1 is connected to the integrated structure of the control terminals of the eighth and ninth transistors through the ninth via, and to the third reset signal line through the sixteenth via.

[0315] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the orthographic projection of the second initial signal line INL2 on the substrate overlaps with the orthographic projections of the first reset signal line and the first scan signal line on the substrate.

[0316] In one exemplary embodiment, such as Figure 21A and Figure 21BAs shown, the orthographic projection of the integrally formed structure of the second electrode T14 of the first transistor and the second electrode T24 of the second transistor on the substrate at least partially overlaps with the orthographic projection of the active connection portion, the second scan signal line and the second electrode plate of the capacitor on the substrate.

[0317] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the orthographic projection of the first electrode of the fifth transistor on the substrate overlaps with the orthographic projections of the second electrode of the capacitor, the third reset signal line, the control signal line, the light emission signal line, and the third initial signal line on the substrate.

[0318] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the orthographic projection of the first connection electrode VL1 on the substrate at least partially overlaps with the orthographic projections of the third reset signal line and the control electrode of the eighth transistor on the substrate.

[0319] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the orthographic projection of the first electrode T83 of the eighth transistor onto the substrate overlaps with the orthographic projections of the control signal line, the light emission signal line, and the third initial signal line onto the substrate.

[0320] In one exemplary embodiment, such as Figure 21A and Figure 21B As shown, the orthographic projection of the first electrode T93 of the ninth transistor onto the substrate overlaps with the orthographic projection of the control signal line onto the substrate.

[0321] (9) Forming a first planarization layer pattern includes: depositing a seventh insulating film on a substrate having the aforementioned pattern; patterning the seventh insulating film using a patterning process to form a seventh insulating layer; coating a first planarization film on a sixth insulating layer; and patterning the first planarization film using a patterning process to form a first planarization layer pattern covering the aforementioned pattern. The first planarization layer has multiple via patterns, such as... Figure 22 As shown, Figure 22 This is a schematic diagram after the first flattening layer pattern has been formed.

[0322] In one exemplary embodiment, such as Figure 22 As shown, the multiple via patterns include eighteenth vias V18 to twentieth vias V20 formed on the seventh insulating layer and the first planarization layer. Among them, eighteenth via V18 exposes the first terminal of the fourth transistor, nineteenth via V19 exposes the second terminal of the sixth transistor, and twentieth via V20 exposes the first terminal of the fifth transistor.

[0323] (10) Forming a fifth conductive layer pattern includes: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern, such as... Figure 23A and Figure 23B As shown, Figure 23A This is a schematic diagram of the pattern of the fifth conductive layer. Figure 23B This is a schematic diagram after the fifth conductive layer pattern has been formed.

[0324] In one exemplary embodiment, such as Figure 23A and Figure 23B As shown, the fifth conductive layer may include: a first power line VDDL, a data signal line DL, and a second connection electrode VL2.

[0325] In one exemplary embodiment, the data signal line DL and the first power supply line VDDL connected to the pixel circuit are located on the same side of the second connection electrode VL2.

[0326] In one exemplary embodiment, the first power line VDDL connected to the pixel circuit may include a power body portion VDDL1 and a power connection portion VDDL2 connected to each other, wherein the power connection portion VDDL2 is located on the side of the power body portion VDDL1 away from the data signal line DL. The power connection portion of the first power line connected to the pixel circuit is interconnected with the power connection portion of the first power line connected to the second adjacent pixel circuit.

[0327] In one exemplary embodiment, the power supply body portion VDDL1 extends along a second direction.

[0328] In one exemplary embodiment, the orthographic projection of the power connection portion VDDL2 onto the substrate overlaps with the orthographic projections of the active connection portion, the second scan signal line, the first scan signal line, and the second initial signal line onto the substrate. The power connection portion VDDL2 may be square in shape.

[0329] In one exemplary embodiment, the data signal line DL connected to the pixel circuit is electrically connected to the first electrode of the fourth transistor through the eighteenth via, the second connection electrode VL2 is electrically connected to the second electrode of the sixth transistor through the nineteenth via, and the first power supply line VDDL connected to the pixel circuit is electrically connected to the first electrode of the fifth transistor through the twentieth via.

[0330] (10) Forming a light-emitting structure layer includes: coating a second planar thin film on a substrate on which the aforementioned pattern is formed, patterning the second planar thin film to form a second planar layer pattern, depositing an anode thin film on the substrate on which the aforementioned pattern is formed, patterning the anode thin film through a patterning process to form an anode layer pattern, depositing a pixel definition thin film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition thin film through a patterning process to form a pixel definition layer pattern exposing the anode layer pattern, coating an organic light-emitting material on the substrate on which the pixel definition layer pattern is formed, patterning the organic light-emitting material through a patterning process to form an organic structure layer pattern, and depositing a cathode thin film on the substrate on which the organic material layer pattern is formed, patterning the cathode thin film through a patterning process to form a cathode layer.

[0331] In one exemplary embodiment, the organic structure layer may include an organic light-emitting layer of a light-emitting element.

[0332] In one exemplary embodiment, the cathode layer may include the cathodes of a plurality of light-emitting elements.

[0333] In one exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0334] In one exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0335] In one exemplary embodiment, the first conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0336] In one exemplary embodiment, the second conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the second conductive layer may include molybdenum.

[0337] In one exemplary embodiment, the third conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the third conductive layer may include molybdenum.

[0338] In one exemplary embodiment, the fourth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the third conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0339] In one exemplary embodiment, the fifth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0340] In one exemplary embodiment, the anode layer may be made of a transparent conductive material, such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0341] In one exemplary embodiment, the cathode layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0342] In one exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0343] In one exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials.

[0344] The display substrate described in this embodiment can be used in display products of any resolution.

[0345] This disclosure also provides a method for driving a pixel circuit. The method for driving a pixel circuit may include the following steps:

[0346] Step 100: Under the control of the first reset signal terminal and the second scan signal terminal, the first control sub-circuit provides the first initial signal terminal or the signal of the third node to the first node, and under the control of the second reset signal terminal, provides the second initial signal terminal to the fourth node.

[0347] Step 200: Under the control of the third reset signal terminal and the first scan signal terminal, the second control sub-circuit provides the third initial signal terminal or data signal terminal to the second node;

[0348] Step 300: Under the control of the third reset signal terminal, the third control sub-circuit provides a first signal to the third node during the display phase, and provides a second signal to the third node or acquires the signal of the third node during the non-display phase.

[0349] Step 400: Under the control of the first and second nodes, the driving sub-circuit provides driving current to the third node;

[0350] Step 500: Under the control of the light emission signal terminal, the light emission control sub-circuit provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

[0351] The pixel circuit is the same as the pixel circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0352] This disclosure also provides a display device, including a display substrate.

[0353] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0354] In one exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0355] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0356] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0357] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel circuit disposed in a display substrate, the display substrate comprising: In both the display and non-display phases, the pixel circuit is configured to drive the light-emitting element to emit light during the display phase, and includes: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit. The first control sub-circuit is electrically connected to the first power supply terminal, the second scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first initial signal terminal, the second initial signal terminal, the first node, the third node, and the fourth node, respectively. It is configured to provide the first initial signal terminal or the third node to the first node under the control of the first reset signal terminal and the second scan signal terminal, and to provide the second initial signal terminal to the fourth node under the control of the second reset signal terminal. The second control sub-circuit is electrically connected to the first scan signal terminal, the third reset signal terminal, the third initial signal terminal, the data signal terminal, and the second node, respectively, and is configured to provide the third initial signal terminal or the data signal terminal to the second node under the control of the third reset signal terminal and the first scan signal terminal; The third control sub-circuit is electrically connected to the third reset signal terminal, the control signal terminal, and the third node, respectively. It is configured to provide a first signal to the third node during the display phase and provide a second signal to the third node or acquire the signal of the third node during the non-display phase under the control of the third reset signal terminal. The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the first node and the second node; The light-emitting control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node under the control of the light-emitting signal terminal. The light-emitting element is electrically connected to the fourth node and the second power supply terminal, respectively. The voltage value of the first signal is less than the voltage value of the signal at the third initial signal terminal, and the voltage value of the second signal is greater than the voltage value of the signal at the third initial signal terminal.

2. The pixel circuit according to claim 1, wherein, During the display phase, when the signal at the first reset signal terminal is a valid level signal, the signal at the third reset signal terminal is a valid level signal, and the signals at the first scan signal terminal, the second scan signal terminal, and the light emission signal terminal are invalid level signals. When the first scan signal terminal is a valid level signal, the signal of the second scan signal terminal is a valid level signal, and the signals of the first reset signal terminal, the third reset signal terminal, and the light emission signal terminal are invalid level signals. The voltage values ​​of the signals at the first initial signal terminal, the second initial signal terminal, and the third initial signal terminal are constant.

3. The pixel circuit according to claim 2, wherein, During the display phase, the occurrence time of the second reset signal terminal signal being at an effective level is before the occurrence time of the first reset signal terminal signal being at an effective level, or the occurrence time of the second reset signal terminal signal being at an effective level is within the occurrence time of the third reset signal terminal signal being at an effective level, or the occurrence time of the second reset signal terminal signal being at an effective level is within the occurrence time of the first scan signal terminal signal being at an effective level, or the occurrence time of the second reset signal terminal signal being at an effective level is after the occurrence time of the first scan signal terminal signal being at an effective level.

4. The pixel circuit according to claim 3, wherein, When the time when the signal at the second reset signal terminal is at an active level is within the time when the signal at the third reset signal terminal is at an active level, the signal at the second reset signal terminal is the same as the signal at the third reset signal terminal. When the time when the signal at the second reset signal terminal is at an effective level is within the time when the signal at the first scan signal terminal is at an effective level, the signal at the second reset signal terminal is the same as the signal at the first scan signal terminal.

5. The pixel circuit according to claim 1, wherein, The first control sub-circuit includes: a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, and a storage sub-circuit; The first reset sub-circuit is electrically connected to the first reset signal terminal, the first initial signal terminal, and the first node, respectively, and is configured to provide the signal of the first initial signal terminal to the first node under the control of the first reset signal terminal; The second reset sub-circuit is electrically connected to the second reset signal terminal, the second initial signal terminal, and the fourth node, respectively, and is configured to provide the signal of the second initial signal terminal to the fourth node under the control of the second reset signal terminal; The compensation sub-circuit is electrically connected to the first node, the third node, and the second scanning signal terminal, respectively, and is configured to provide the signal of the third node to the first node under the control of the second scanning signal terminal; The storage sub-circuit is electrically connected to the first power supply terminal and the first node, respectively, and is configured to store the voltage difference between the signal of the first power supply terminal and the signal of the first node.

6. The pixel circuit according to claim 1, wherein, The second control sub-circuit includes: a third reset sub-circuit and a write sub-circuit; The third reset sub-circuit is electrically connected to the third reset signal terminal, the third initial signal terminal, and the second node, respectively, and is configured to provide the signal of the third initial signal terminal to the second node under the control of the third reset signal terminal; The writing sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the second node, respectively, and is configured to provide the data signal terminal to the second node under the control of the first scan signal terminal.

7. The pixel circuit according to claim 5, wherein, The first reset sub-circuit includes a first transistor; the second reset sub-circuit includes a seventh transistor; the compensation sub-circuit includes a second transistor; and the storage sub-circuit includes a capacitor, which includes a first plate and a second plate. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

8. The pixel circuit according to claim 6, wherein, The write sub-circuit includes a fourth transistor, and the third reset sub-circuit includes an eighth transistor; The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node. The control terminal of the eighth transistor is electrically connected to the third reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node.

9. The pixel circuit according to claim 1, wherein, The third control sub-circuit includes: a ninth transistor; The control terminal of the ninth transistor is electrically connected to the third reset signal terminal, the first terminal of the ninth transistor is electrically connected to the control signal terminal, and the second terminal of the ninth transistor is electrically connected to the third node.

10. The pixel circuit according to claim 1, wherein, The first control sub-circuit includes: a first transistor, a second transistor, a seventh transistor, and a capacitor, the capacitor including: a first plate and a second plate; the second control sub-circuit includes: a fourth transistor and an eighth transistor; the third control sub-circuit includes: a ninth transistor; the driving sub-circuit includes: a third transistor; the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node. The control terminal of the eighth transistor is electrically connected to the third reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the second node. The control electrode of the ninth transistor is electrically connected to the third reset signal terminal, the first electrode of the ninth transistor is electrically connected to the control signal terminal, and the second electrode of the ninth transistor is electrically connected to the third node. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

11. The pixel circuit according to claim 10, wherein, The first transistor and the second transistor are of the opposite transistor type to the third to the ninth transistor; The first transistor and the second transistor are oxide transistors, and are N-type transistors.

12. A display substrate, comprising: A substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate, wherein the light-emitting structure layer includes a light-emitting element, and the circuit structure layer includes an array of pixel circuits as described in any one of claims 1 to 11.

13. The display substrate according to claim 12, wherein, When the time when the signal at the second reset signal terminal is at an effective level is before the time when the signal at the first reset signal terminal is at an effective level, the signal at the second reset signal terminal of the i-th row pixel circuit is the same as the signal at the first scan signal terminal of the (i-1)-th row pixel circuit. When the time when the signal at the second reset signal terminal is at an effective level is after the time when the signal at the first scan signal terminal is at an effective level, the signal at the second reset signal terminal of the i-th row pixel circuit is the same as the signal at the first scan signal terminal of the (i+1)-th row pixel circuit.

14. The display substrate according to claim 12, wherein, The circuit structure layer further includes: multiple first reset signal lines, multiple second reset signal lines, multiple third reset signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple first initial signal lines, multiple second initial signal lines, multiple third initial signal lines, multiple light emission signal lines, and multiple control signal lines extending along the first direction and arranged along the second direction, as well as multiple first power lines and multiple data signal lines extending along the second direction and arranged along the first direction, wherein the first direction intersects the second direction; The pixel circuit has a first reset signal terminal electrically connected to a first reset signal line, a second reset signal terminal electrically connected to a second reset signal line, a third reset signal terminal electrically connected to a third reset signal line, a first scan signal terminal electrically connected to a first scan signal line, a second scan signal terminal electrically connected to a second scan signal line, an emission signal terminal electrically connected to an emission signal line, a first initial signal terminal electrically connected to a first initial signal line, a second initial signal terminal electrically connected to a second initial signal line, a control signal terminal electrically connected to a control signal line, a first power supply terminal electrically connected to a first power supply line, and a data signal terminal electrically connected to a data signal line.

15. The display substrate according to claim 14, further comprising: A first chip connected to the control signal line and a second chip connected to the data signal line; The first chip is configured to provide a first signal to the control signal line during the display phase, provide a second signal to the control signal line during the non-display phase, or acquire the signal of the control signal line. It is also configured to obtain the threshold voltage of the third transistor based on the signal of the control signal line, generate a control signal based on the threshold voltage of the third transistor, and send the control signal to the second chip. The second chip provides signals to the data signal line according to the control signal.

16. The display substrate according to claim 14, wherein, The pixel structure of adjacent pixel circuits located in the same row is symmetrical with respect to the dummy straight line extending along the second direction; The adjacent pixel circuits located in the same row as the pixel circuits include: the first adjacent pixel circuit and the second adjacent pixel circuit.

17. The display substrate according to claim 14 or 16, wherein, The pixel circuit includes: a first transistor to a ninth transistor, wherein the control electrode of the first transistor and the control electrode of the second transistor each include: a first control electrode and a second control electrode; The first reset signal line includes: a first sub-reset signal line and a second sub-reset signal line that are disposed on different layers and connected to each other, wherein the first sub-reset signal line is disposed on the same layer as the first control electrode of the first transistor, and the second sub-reset signal line is disposed on the same layer as the second control electrode of the first transistor; The second scan signal line includes: a first sub-scan signal line and a second sub-scan signal line that are disposed on different layers and interconnected, wherein the first sub-scan signal line is disposed on the same layer as the first control electrode of the second transistor, and the second sub-scan signal line is disposed on the same layer as the second control electrode of the second transistor.

18. The display substrate according to claim 17, wherein, The pixel circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate. The circuit structure layer includes a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a seventh insulating layer, a first planarization layer, and a fifth conductive layer, which are sequentially stacked on the substrate. The first semiconductor layer includes: the active layer of the third transistor to the active layer of the ninth transistor located in at least one pixel circuit; The first conductive layer includes: a first scan signal line, a light emission signal line, and a first electrode of a capacitor located in at least one pixel circuit, and the control electrode of a third transistor to the control electrode of a ninth transistor; The second conductive layer includes: a first initial signal line, a first sub-reset signal line, a first sub-scan signal line, a control signal line, and a second plate of a capacitor located in at least one pixel circuit, a first control electrode of a first transistor, and a first control electrode of a second transistor; The second semiconductor layer includes: an active layer of a first transistor located in at least one pixel circuit, an active layer of a second transistor, and an active connection portion; the active connection portion is configured to connect the active layer of the first transistor and the active layer of the second transistor. The third conductive layer includes: a second sub-reset signal line, a second sub-scan signal line, a third reset signal line, and a third initial signal line, as well as a second control electrode of a first transistor and a second control electrode of a second transistor located in at least one pixel circuit; The fourth conductive layer includes: a second initial signal line and a first and second electrode of a first transistor, a first and second electrode of a second transistor, a first electrode of a fourth transistor, a first electrode of a fifth transistor, a second electrode of a sixth transistor, a first and second electrode of a seventh transistor, a first electrode of an eighth transistor, a first electrode of a ninth transistor, and a first connection electrode; the first connection electrode is configured to connect the control electrode of the eighth transistor, the control electrode of the ninth transistor, and the third reset signal line. The fifth conductive layer includes: a first power line, a data signal line, and a second connection electrode located in at least one pixel circuit, wherein the second connection electrode is configured to connect the second electrode of the sixth transistor and the light-emitting element.

19. The display substrate according to claim 18, wherein, The circuit structure layer further includes: a light-shielding layer located on the side of the first insulating layer near the substrate, the light-shielding layer including: light-shielding parts and light-shielding connecting parts arranged in an array and spaced apart from each other, the light-shielding connecting parts being configured to connect adjacent light-shielding parts; The orthographic projection of the light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate.

20. The display substrate according to claim 18 or 19, wherein, The control electrode of the eighth transistor and the control electrode of the ninth transistor are integrally molded. The first scan signal line and the light emission signal line connected to the pixel circuit are located on both sides of the first plate of the capacitor in the pixel circuit. The integrated structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor is located between the first plate of the capacitor and the light emission signal line connected to the pixel circuit.

21. The display substrate according to claim 18 or 19, wherein, The first control electrode of the first transistor and the first sub-reset signal line are integrally formed, and the first control electrode of the second transistor and the first sub-scan signal line are integrally formed. The first initial signal line, the first sub-reset signal line, and the first sub-scan signal line connected to the pixel circuit extend along the first direction and are located on the same side of the second plate of the capacitor of the pixel circuit. The first sub-reset signal line is located on the side of the first initial signal line that is closer to the second plate of the capacitor of the pixel circuit, and the first sub-scan signal line is located on the side of the first sub-reset signal line that is closer to the second plate of the capacitor of the pixel circuit. The control signal line is located on the side of the second plate of the capacitor of the pixel circuit that is away from the first sub-scan signal line. The orthographic projection of the first scan signal line on the substrate is located between the orthographic projection of the first sub-reset signal line on the substrate and the orthographic projection of the first sub-scan signal line on the substrate. The orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate is located between the orthographic projection of the second plate of the capacitor on the substrate and the orthographic projection of the control signal line on the substrate. The orthographic projection of the control signal line on the substrate is located between the orthographic projection of the light-emitting signal line on the substrate and the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate. The second plate of the capacitor in the pixel circuit is electrically connected to the second plate of the capacitor in the first adjacent pixel circuit.

22. The display substrate according to claim 18 or 19, wherein, The active layer of the first transistor and the active layer of the second transistor are located on both sides of the active connection portion, respectively. The orthographic projection of the active layer of the first transistor onto the substrate overlaps with the orthographic projection of the first initial signal line onto the substrate; The orthographic projection of the active layer of the second transistor onto the substrate overlaps with the orthographic projection of the first sub-scan signal line onto the substrate; The orthographic projection of the active connection portion on the substrate at least partially overlaps with the orthographic projection of the first scan signal line on the substrate.

23. The display substrate according to claim 18 or 19, wherein, The second control electrode of the first transistor and the second sub-reset signal line are integrally formed, and the second control electrode of the second transistor and the second sub-scan signal line are integrally formed; The second sub-scan signal line is located between the second sub-reset signal line and the third reset signal line, and the third initial signal line is located on the side of the third reset signal line away from the second sub-reset signal line. The orthographic projection of the second sub-reset signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-reset signal line on the substrate, and is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first scan signal line on the substrate. The orthographic projection of the second sub-scan signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line on the substrate, and is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the second plate of the capacitor on the substrate. The orthographic projection of the third reset signal line on the substrate is located between the orthographic projection of the second plate of the capacitor on the substrate and the orthographic projection of the integral structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the substrate. The orthographic projection of the third initial signal line on the substrate is located on the side of the second plate of the capacitor away from the orthographic projection of the control signal line on the substrate, and overlaps with the orthographic projections of the light-emitting signal line and the control signal line on the substrate.

24. The display substrate according to claim 18 or 19, wherein, The sixth insulating layer has multiple via patterns, including: the first to seventh vias on the second to sixth insulating layers, the eighth and ninth vias on the third to sixth insulating layers, the tenth to twelfth vias on the fourth to sixth insulating layers, the thirteenth to fifteenth vias on the fifth and sixth insulating layers, and the sixteenth and seventeenth vias on the sixth insulating layer; The third via exposes the active layer of the fifth transistor, the tenth via exposes the first initial signal line, and the eleventh via exposes the second plate of the capacitor; a virtual straight line extending along the second direction passes through the third and eleventh vias. The third via of the pixel circuit is the same as the third via of the first adjacent pixel circuit; The eleventh via of the pixel circuit is the same via as the eleventh via of the first adjacent pixel circuit; The tenth via of the pixel circuit and the tenth via of the second adjacent pixel circuit are the same via.

25. The display substrate according to claim 18 or 19, wherein, The first electrode of the fifth transistor in the pixel circuit is the same as the first electrode of the fifth transistor in the first adjacent pixel circuit. The orthographic projection of the second initial signal line on the substrate overlaps with the orthographic projections of the first reset signal line and the first scan signal line on the substrate. The orthographic projection of the integral structure of the second electrode of the first transistor and the second electrode of the second transistor on the substrate at least partially overlaps with the orthographic projection of the active connection portion, the second scan signal line and the second plate of the capacitor on the substrate. The orthogonal projection of the first electrode of the fifth transistor onto the substrate overlaps with the orthogonal projections of the second plate of the capacitor, the third reset signal line, the control signal line, the light emission signal line, and the third initial signal line onto the substrate. The orthographic projection of the first connection electrode on the substrate at least partially overlaps with the orthographic projections of the third reset signal line and the control electrode of the eighth transistor on the substrate; The orthographic projection of the first electrode of the eighth transistor onto the substrate overlaps with the orthographic projections of the control signal line, the light emission signal line, and the third initial signal line onto the substrate; The orthographic projection of the first electrode of the ninth transistor onto the substrate overlaps with the orthographic projection of the control signal line onto the substrate.

26. The display substrate according to claim 18 or 19, wherein, The data signal line and the first power supply line connected to the pixel circuit are located on the same side of the second connection electrode; The first power line includes: a power body and a power connection part connected to each other, wherein the power connection part is located on the side of the power body away from the data signal line; The power connection portion of the first power line connected to the pixel circuit is interconnected with the power connection portion of the first power line connected to the second adjacent pixel circuit. The orthographic projection of the power connection portion on the substrate overlaps with the orthographic projections of the active connection portion, the second scan signal line, the first scan signal line, and the second initial signal line on the substrate.

27. A display device, comprising: The display substrate as described in any one of claims 12 to 26.

28. A method for driving a pixel circuit, configured to drive the pixel circuit as described in any one of claims 1 to 11, the method comprising: Under the control of the first reset signal terminal and the second scan signal terminal, the first control sub-circuit provides the first initial signal terminal or the signal of the third node to the first node, and under the control of the second reset signal terminal, provides the signal of the second initial signal terminal to the fourth node. Under the control of the third reset signal terminal and the first scan signal terminal, the second control sub-circuit provides the third initial signal terminal or the data signal terminal to the second node; Under the control of the third reset signal terminal, the third control sub-circuit provides a first signal to the third node during the display phase and provides a second signal to the third node or acquires the signal of the third node during the non-display phase. The driving sub-circuit provides driving current to the third node under the control of the first and second nodes; Under the control of the light emission signal terminal, the light emission control sub-circuit provides the first power supply terminal signal to the second node and the third node signal to the fourth node.

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