Display substrate and display device

Abstract

A display substrate and a display device, the display substrate has a plurality of sub-pixels, and comprises a substrate substrate, a pixel driving circuit layer, a pixel definition layer and a spacer layer, the pixel driving circuit layer is arranged on the substrate substrate, the pixel definition layer is arranged on the side of the pixel driving circuit layer away from the substrate substrate, and comprises a plurality of sub-pixel openings, wherein each of the plurality of sub-pixels comprises a pixel driving circuit arranged in the pixel driving circuit layer and a light emitting device at least partially arranged in the sub-pixel opening, the spacer layer is arranged on the side of the pixel definition layer away from the substrate substrate, and comprises a plurality of spacers, wherein the light transmittance of the plurality of spacers is less than 5%. The display substrate basically does not produce adverse phenomena such as color separation, and has better display effect.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) displays possess a range of advantages, including self-illumination, high contrast, high definition, wide viewing angle, low power consumption, fast response time, and low manufacturing cost. As a result, they have become a key development direction for next-generation display devices and are receiving increasing attention. In OLED displays, the arrangement of various structures and their relative positions are crucial factors affecting the display's performance. Summary of the Invention

[0003] This disclosure provides at least one embodiment of a display substrate having a plurality of sub-pixels and including a substrate, a pixel driving circuit layer, a pixel defining layer, and a spacer layer. The pixel driving circuit layer is disposed on the substrate, and the pixel defining layer is disposed on the side of the pixel driving circuit layer away from the substrate, including a plurality of sub-pixel openings. Each of the plurality of sub-pixels includes a pixel driving circuit disposed in the pixel driving circuit layer and a light-emitting device at least partially disposed in the sub-pixel opening. The spacer layer is disposed on the side of the pixel defining layer away from the substrate and includes a plurality of spacers, wherein the transmittance of the plurality of spacers is less than 5%.

[0004] For example, in a display substrate provided in at least one embodiment of this disclosure, the transmittance of the pixel defining layer in the portion other than the plurality of sub-pixel openings is less than 5%.

[0005] For example, in at least one embodiment of the display substrate provided in this disclosure, the spacer layer is made of the same material as the pixel defining layer.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, the minimum distance between the plurality of spacers and the plurality of sub-pixel openings is L, and 1 micrometer < L < 8 micrometers.

[0007] For example, in at least one embodiment of the display substrate provided in this disclosure, at least some of the plurality of spacers have a rectangular planar shape.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the length and width of the rectangle range from 13 micrometers to 19 micrometers, and the height of the plurality of spacers in the direction perpendicular to the substrate is from 0.5 micrometers to 2.0 micrometers.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit layer includes a plurality of pixel driving circuits, a plurality of scan signal lines providing scan signals to the plurality of pixel driving circuits, and a plurality of reset control signal lines providing reset control signals to the plurality of pixel driving circuits. In a direction parallel to the substrate, at least a portion of the plurality of spacers are respectively located between a reset control signal line and a scan signal line closest to the reset control signal line.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit layer includes a plurality of pixel driving circuits, a plurality of scan signal lines providing scan signals to the plurality of pixel driving circuits, and a plurality of reset control signal lines providing reset control signals to the plurality of pixel driving circuits. In a direction perpendicular to the substrate, at least a portion of the plurality of spacers overlaps with at least one of a reset control signal line and a scan signal line closest to the reset control signal line.

[0011] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a black matrix layer disposed on the side of the light-emitting device away from the substrate. The black matrix layer includes a plurality of first light-transmitting openings. The orthographic projections of the plurality of sub-pixel openings on the substrate are respectively located inside the orthographic projections of the plurality of first light-transmitting openings on the substrate. The distance between the boundary of the orthographic projection of the plurality of sub-pixel openings on the substrate and the boundary of the orthographic projection of the plurality of first light-transmitting openings on the substrate is 1.0 micrometer to 6.5 micrometers.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a plurality of color filters, wherein the plurality of color filters are at least partially disposed in the plurality of first light-transmitting openings; for a first light-transmitting opening and a color filter at least partially disposed in the first light-transmitting opening, the orthographic projection of the first light-transmitting opening on the substrate is located inside the orthographic projection of the color filter on the substrate.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, the black matrix layer further includes a plurality of second light-transmitting openings, the plurality of second light-transmitting openings being respectively disposed between two adjacent first light-transmitting openings among the plurality of first light-transmitting openings.

[0014] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a light-shielding layer disposed on the substrate, wherein the pixel driving circuit layer is disposed on the side of the light-shielding layer away from the substrate, the light-shielding layer includes a plurality of third light-transmitting openings, and at least a portion of the orthographic projections of the plurality of third light-transmitting openings on the substrate respectively overlap with at least a portion of the orthographic projections of the plurality of second light-transmitting openings on the substrate.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projections of the plurality of third light-transmitting openings on the substrate are respectively located within the orthographic projections of the plurality of second light-transmitting openings on the substrate.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the distance between the boundary of the orthographic projection of at least a portion of the plurality of third light-transmitting openings on the substrate and the boundary of the orthographic projection of the plurality of second light-transmitting openings on the substrate is 0.5 micrometers to 1.5 micrometers.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. At least a portion of the plurality of second light-transmitting openings are located between the first light-transmitting openings corresponding to adjacent first sub-pixels and third sub-pixels, and the distance from the first light-transmitting opening corresponding to the first sub-pixel is different from the distance from the first light-transmitting opening corresponding to the third sub-pixel.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the first sub-pixel and the third sub-pixel are arranged in multiple rows and columns, multiple first sub-pixels and multiple third sub-pixels located in the same column are arranged alternately, and a second light-transmitting opening is provided between the first light-transmitting openings corresponding to adjacent first sub-pixels and third sub-pixels located in the same column.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, a first sub-pixel, two second sub-pixels and a third sub-pixel form a repeating unit, and multiple repeating units are arranged in an array. Multiple second sub-pixels in the multiple repeating units are arranged in multiple rows and columns, and a second light-transmitting opening is also disposed between the first light-transmitting openings corresponding to adjacent second sub-pixels in the row direction.

[0020] For example, in a display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of each of the plurality of spacers on the substrate is respectively located between the orthographic projections of the sub-pixel openings of adjacent second sub-pixels in the column direction on the substrate, and respectively located between the orthographic projections of the sub-pixel openings of adjacent first and third sub-pixels in the row direction on the substrate.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the shortest distance between the orthographic projection of each of the plurality of spacers on the substrate and the orthographic projection of the sub-pixel opening of the first sub-pixel among the adjacent first and third sub-pixels on the substrate is greater than the shortest distance between the orthographic projection of the sub-pixel opening of the third sub-pixel among the adjacent first and third sub-pixels on the substrate.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of each of the plurality of spacers on the substrate is substantially the same as the shortest distance of the orthographic projection of the sub-pixel opening of the adjacent second sub-pixel on the substrate.

[0023] For example, in a display substrate provided in at least one embodiment of this disclosure, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0024] For example, at least one embodiment of the present disclosure provides a display substrate that further includes an encapsulation layer disposed on the side of the light-emitting device away from the substrate and a touch layer disposed on the side of the encapsulation layer away from the substrate. The black matrix layer is disposed on the side of the encapsulation layer away from the substrate, and the touch layer is disposed on the side of the touch layer away from the substrate. The touch layer includes multiple touch traces, and the orthographic projections of the multiple touch traces on the substrate do not overlap with the orthographic projections of the multiple second light-transmitting openings on the substrate.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, the first sub-pixel and the third sub-pixel are arranged in multiple rows and columns, and multiple first sub-pixels and multiple third sub-pixels located in the same column are arranged alternately, wherein at least a portion of the multiple touch traces have gaps between adjacent first sub-pixels and third sub-pixels located in the same column.

[0026] For example, in the display substrate provided in at least one embodiment of this disclosure, at least a portion of the plurality of touch traces has a notch on the side closer to the third sub-pixel or on the side closer to the first sub-pixel among adjacent first sub-pixels and third sub-pixels located in the same column; or at least a portion of the plurality of touch traces has a notch on both the side closer to the third sub-pixel and the side closer to the first sub-pixel among adjacent first sub-pixels and third sub-pixels located in the same column.

[0027] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0029] Figure 1A This is a schematic diagram of a partial cross-section of a display substrate;

[0030] Figure 1B for Figure 1A The color separation test results of the display substrate in the image;

[0031] Figure 2 This is a partial cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 3 This is a partial planar schematic diagram of the stacked black matrix layer and spacer layer in a display substrate provided in at least one embodiment of the present disclosure;

[0033] Figure 4 A color separation test result diagram of a display substrate provided in at least one embodiment of this disclosure;

[0034] Figure 5 This is a partial planar schematic diagram of the stacked black matrix layer, spacer layer, and first color filter in a display substrate provided in at least one embodiment of the present disclosure.

[0035] Figure 6 This is a partial cross-sectional schematic diagram of the stacked black matrix layer, spacer layer, and color filter layer in a display substrate provided in at least one embodiment of the present disclosure.

[0036] Figure 7 A partial planar schematic diagram of the stacked black matrix layer and spacer layer, first color filter and second color filter in a display substrate provided in at least one embodiment of the present disclosure;

[0037] Figure 8 This is a partial planar schematic diagram of the stacked layers of black matrix layer and spacer layer, first color filter, second color filter and third color filter in a display substrate provided in at least one embodiment of the present disclosure;

[0038] Figure 9 This is a schematic cross-sectional view of another portion of the display substrate provided in at least one embodiment of the present disclosure;

[0039] Figure 10 This is a plan view of the stacked second and third light-transmitting openings in a display substrate provided in at least one embodiment of the present disclosure.

[0040] Figure 11This is a partial planar schematic diagram of the stacked layers of a black matrix layer, a touch layer, a first color filter, a second color filter, and a third color filter in a display substrate provided in at least one embodiment of the present disclosure.

[0041] Figure 12 An equivalent circuit diagram of an 8T1C pixel driving circuit provided for at least one embodiment of this disclosure;

[0042] Figure 13 A timing diagram of a pixel driving circuit is provided for at least one embodiment of this disclosure; and

[0043] Figures 14-25 This is a planar schematic diagram of each layer in a display substrate provided in at least one embodiment of the present disclosure. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0045] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0046] Figure 1A A cross-sectional schematic diagram of a display panel is shown, such as... Figure 1AAs shown, the display panel includes structures such as light-emitting devices (EMs) and pixel driving circuits that drive the EMs. The pixel driving circuits include thin-film transistors (TFTs) and storage capacitors. A pixel defining layer (PDL) is disposed above the pixel driving circuits to define the light-emitting area of ​​the EMs. A spacer (PS) is disposed above the PDL, for example, to support structures such as photomasks during the fabrication of the display panel. The PDL and PS are typically made of organic insulating materials such as polyimide.

[0047] In some embodiments, the display panel further includes a color filter (CF). Light emitted by the light-emitting device (EM) passes through the color filter and exits to form purer monochromatic light. In some cases, such as under strong light, ambient light may also pass through the color filter (CF) and enter the display panel, and be reflected by some structures in the display panel, such as the chamfered portions of the pixel delimiter layer (PDL) and spacers (PS) (the portion within the circular dashed box in the figure). The reflected light continues to exit from the color filter (CF), affecting the normal display of the display panel and making the dark state effect of the display panel poor, visually manifesting as reflected color separation.

[0048] For example, Figure 1B It shows Figure 1A The image shows the actual color separation test results of the display panel. During the test, a color separation testing device was used to test the color separation of 432 points (6 points in 72 directions, each a step of 5°) and the fitted color separation. The results are shown in the image. Figure 1B The cloud map shown illustrates how, when the display panel is in a dark state, a light source shines on the screen, as... Figure 1B As shown, from dark to light, the more severe the color separation, the more seriously the color separation phenomenon will affect the display effect of the display panel.

[0049] At least one embodiment of this disclosure provides a display substrate and a display device. The display substrate has a plurality of sub-pixels and includes a substrate, a pixel driving circuit layer, a pixel defining layer, and a spacer layer. The pixel driving circuit layer is disposed on the substrate, and the pixel defining layer is disposed on the side of the pixel driving circuit layer away from the substrate and includes a plurality of sub-pixel openings. Each of the plurality of sub-pixels includes a pixel driving circuit disposed in the pixel driving circuit layer and a light-emitting device at least partially disposed in the sub-pixel opening. The spacer layer is disposed on the side of the pixel defining layer away from the substrate and includes a plurality of spacers, wherein the light transmittance of the plurality of spacers is less than 5%.

[0050] In the display substrate provided in this embodiment, the spacer is basically opaque and absorbs light. Therefore, ambient light is not reflected and emitted within the display panel. As a result, the display panel does not produce color separation or other defects and has a better display effect.

[0051] The display substrate and display device provided in this disclosure are described below through several specific embodiments.

[0052] This disclosure provides a display substrate in at least one embodiment. Figure 2 A partial cross-sectional schematic diagram of the display panel is shown. Figure 3 A plan view of part of the display panel structure is shown. (See diagram below.) Figure 2 and Figure 3 As shown, the display substrate has multiple sub-pixels and includes a substrate 110, a pixel driving circuit layer 120, a pixel defining layer PDL, and a spacer layer 140.

[0053] The pixel driving circuit layer 120 is disposed on the substrate 110 and includes multiple pixel driving circuits. Each pixel driving circuit includes structures such as thin-film transistors (TFTs) and storage capacitors (not shown), and can be formed as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structures, which will be described in detail later. For example, as... Figure 2 As shown, a thin-film transistor (TFT) includes an active layer 121, a gate 122, a first electrode 123, and a second electrode 124.

[0054] The pixel delimiting layer (PDL) is disposed on the side of the pixel driving circuit layer 120 away from the substrate 110, and includes a plurality of sub-pixel openings 130. Each of the plurality of sub-pixels includes a pixel driving circuit disposed in the pixel driving circuit layer 120 and a light-emitting device (EM) disposed at least partially in the sub-pixel opening 130.

[0055] For example, such as Figure 2 As shown, the light-emitting device (EM) includes a first electrode 141, a light-emitting material layer 142, and a second electrode 143. For example, the first electrode 141 serves as the anode and is electrically connected to the source / drain electrodes 123 of the thin-film transistor (TFT). The light-emitting material layer 142 includes an organic light-emitting material and is configured to emit monochromatic light or white light. The second electrode 143 serves as the cathode and is formed as a surface electrode, that is, the second electrodes 143 of multiple sub-pixels are continuously arranged in a surface shape to completely cover the substrate 110; or, in some embodiments, at locations where the transmittance of the display substrate needs to be increased, the second electrode 143 may have a pattern directly opposite the first electrode 141, that is, the second electrode 143 is patterned to improve the transmittance of the display substrate at that location.

[0056] The spacer layer 140 is disposed on the side of the pixel defining layer PDL away from the substrate 110, and includes a plurality of spacers PS. The transmittance of the plurality of spacers PS is less than 5%, for example less than 2%. The plurality of spacers PS can support devices such as photomasks during the fabrication of the display substrate.

[0057] For example, in some embodiments, the multiple spacers PS can be formed of a black opaque material, such as a black opaque material formed by doping a resin material with a black dye. This material has a good light absorption effect, so when ambient light shines on the spacers PS, the ambient light will not be reflected but absorbed, thus reducing or even eliminating the color separation phenomenon.

[0058] For example, in some embodiments, the transmittance of the pixel defining layer (PDL) is less than 5%, for example, less than 2%, in the portion excluding the plurality of sub-pixel openings 130. For example, the material of the pixel defining layer (PDL) can be the same as the material of the plurality of spacers (PS), so that it can be formed in the same patterning process using a halftone mask, or the two can be formed separately using the same or different materials.

[0059] Therefore, when ambient light shines on the pixel boundary layer (PDL), the ambient light will not be reflected by the PDL, thus further reducing or even eliminating color separation.

[0060] For example, Figure 4 The following diagram illustrates the measured color separation results of the display panel provided in this embodiment of the present disclosure. Figure 4 As shown, the color separation phenomenon exhibited from dark to light colors is compared to Figure 1B The color separation is significantly reduced, even to the point of being difficult to detect with the naked eye, thereby greatly improving the display effect of the display panel. For example, relative to the CIE 1976 Lab coordinate system, the color separation effect can achieve a lab < 4 ( The a-axis represents the relative colors of red and green (+a represents red, -a represents green), and the b-axis represents the relative colors of yellow and blue (+b represents yellow, -b represents blue), which can greatly improve the performance of the display substrate under outdoor sunlight.

[0061] For example, in some embodiments, the minimum distance between the plurality of spacers PS and the plurality of sub-pixel openings 130 is L, and 1 micrometer < L < 8 micrometers, for example, L is 2 micrometers, 4 micrometers, 6 micrometers, or 8 micrometers. Thus, the plurality of spacers PS and the plurality of sub-pixel openings 130 are spaced at a certain distance. Since the sidewalls of the sub-pixel openings 130 typically have a certain tilt angle, if the distance between the plurality of spacers PS and the plurality of sub-pixel openings 130 is too close, the spacers PS may be formed on the sidewalls of the sub-pixel openings 130, thereby reducing the height of the spacers PS relative to the substrate 110 and making it difficult to achieve a sufficient spacer effect.

[0062] For example, in some embodiments, such as Figure 3As shown, at least some of the spacers PS have a rectangular planar shape. For example, the length L1 and width W1 of the rectangle range from 13 micrometers to 19 micrometers. For example, the length L1 can be 15 micrometers, 17 micrometers, or 19 micrometers, and the width W1 can be 13 micrometers, 15 micrometers, or 17 micrometers, etc. In some embodiments, at least some of the spacers PS can also have a square planar shape. In this case, the side length of the square can be 12 micrometers, 15 micrometers, 17 micrometers, or 19 micrometers, etc.

[0063] For example, in some other embodiments, at least some of the spacers PS may have a circular planar shape, in which case the diameter of the circle may be 13-19 micrometers, such as 15 micrometers or 17 micrometers; or, in still other embodiments, the multiple spacers PS may include a main spacer and a secondary spacer, both of which may have a circular planar shape, in which case the sum of the diameters of the circles of the main spacer and the secondary spacer may be 13-19 micrometers, such as 15 micrometers or 17 micrometers.

[0064] For example, as shown in Figure 1, in the direction perpendicular to the substrate 110, that is, in the vertical direction shown in the figure, the height H of the multiple spacers PS is 0.5 micrometers to 2.0 micrometers, such as 1.0 micrometers or 1.5 micrometers, so as to fully realize the spacer function.

[0065] For example, such as Figure 2 As shown, the display substrate also includes a black matrix layer BM disposed on the side of the light-emitting device EM away from the substrate 110. The black matrix layer BM includes a plurality of first light-transmitting openings BM1. Figure 5 A schematic diagram of the planar arrangement of the first light-transmitting opening BM1 is shown, as follows: Figure 5 As shown, the orthographic projections of the multiple sub-pixel openings 130 on the substrate 110 are respectively located inside the orthographic projections of the multiple first light-transmitting openings BM1 on the substrate 110. For example, the distance L2 between the boundary of the orthographic projection of the multiple sub-pixel openings 130 on the substrate 110 and the boundary of the orthographic projection of the multiple first light-transmitting openings BM1 on the substrate 110 is 1.0 μm to 6.5 μm, for example, 3 μm to 6 μm, such as 3.5 μm, 4 μm, 4.5 μm, 5 μm, or 5.5 μm, etc. That is, the first light-transmitting opening BM1 is extended outward by 1.0 μm to 6.5 μm relative to the corresponding sub-pixel opening 130, so that the light emitted by the light-emitting device EM can be fully emitted through the first light-transmitting opening BM1.

[0066] For example, in some embodiments, such as Figure 2As shown, the display substrate also includes a plurality of color filters CF, which are at least partially disposed in a plurality of first light-transmitting openings BM1. For a first light-transmitting opening BM1 and a color filter CF at least partially disposed in the first light-transmitting opening BM1, the orthographic projection of the first light-transmitting opening BM1 on the substrate 110 is located inside the orthographic projection of the color filter CF on the substrate 110. That is, the setting range of the color filter CF is larger than the setting range of the first light-transmitting opening BM1.

[0067] For example, in some embodiments, the plurality of sub-pixels includes a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B, and the plurality of color filters CF includes a first color filter RCF for the first sub-pixel R, a second color filter GCF for the second sub-pixel G, and a third color filter BCF for the third sub-pixel B.

[0068] For example, in some embodiments, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel; correspondingly, the first color filter RCF is a red filter, the second color filter GCF is a green filter, and the third color filter BCF is a blue filter.

[0069] Alternatively, in some other embodiments, the first sub-pixel R can also be a green sub-pixel or a blue sub-pixel, the second sub-pixel G can also be a red sub-pixel or a blue sub-pixel, and the third sub-pixel B can also be a red sub-pixel or a green sub-pixel. In this case, a color filter of the corresponding color is set on each sub-pixel.

[0070] For example, in some embodiments, the display substrate may further include a color filter layer disposed on the side of the black matrix layer BM away from the substrate, the color filter layer having a mesh-like structure. For example, the color filter layer may include at least one of a first color filter layer (e.g., a red filter layer), a second color filter layer (e.g., a green filter layer), and a third color filter layer (e.g., a blue filter layer). In this case, the first color filter layer is cut out at the second light-transmitting opening BM2 corresponding to the second sub-pixel G and the third sub-pixel B, for example, by filling the cutout with a first color filter RCF; the second color filter layer is cut out at the second light-transmitting opening BM2 corresponding to the first sub-pixel R and the third sub-pixel B, for example, by filling the cutout with a second color filter GCF; the third color filter layer is cut out at the second light-transmitting opening BM2 corresponding to the first sub-pixel R and the second sub-pixel G, for example, by filling the cutout with a third color filter BCF. This can further reduce the reflectivity of light in the display substrate.

[0071] For example, Figure 5 A schematic diagram of the planar arrangement of multiple first color filters (RCFs) is shown. For example... Figure 15As shown, the setting range of the first color filter RCF is larger than the setting range of the first light-transmitting opening BM1 corresponding to the first sub-pixel R. For example, Figure 6 A partial cross-sectional schematic diagram of the first light-transmitting opening BM1, the first color filter RCF, and the sub-pixel opening 130 is shown, as follows: Figure 5 and Figure 6 As shown, the setting range of the first light-transmitting opening BM1 is larger than the setting range of the sub-pixel opening 130, the setting range of the first color filter RCF is larger than the setting range of the first light-transmitting opening BM1, and the distance L2 between the boundary of the orthographic projection of the sub-pixel opening 130 on the substrate 110 and the boundary of the orthographic projection of the first light-transmitting opening BM1 on the substrate 110 is 1.0 micrometers to 6.5 micrometers, for example, 3 micrometers to 6 micrometers.

[0072] For example, such as Figure 6 As shown, the width of the spacer PS can be smaller than the width of the non-transparent area of ​​the black matrix layer BM. In other embodiments, the width of the spacer PS can also be larger than the width of the non-transparent area of ​​the black matrix layer BM. In this case, even if light shines on the spacer PS, the spacer PS will not reflect light and cause color separation, thereby improving the design freedom of the black matrix layer BM.

[0073] For example, Figure 7 It shows in Figure 5 The case where a second color filter GCF is set on top of the existing one. Figure 8 It shows in Figure 7 The case where a third color filter (BCF) is added to the existing setup. For example... Figure 7 and Figure 8 As shown, in both the second and third sub-pixels, the setting range of the first light-transmitting opening BM1 is larger than the setting range of the sub-pixel opening 130, and the setting range of the second color filter GCF / third color filter BCF is larger than the setting range of the first light-transmitting opening BM1. Furthermore, the distance L2 between the boundary of the orthographic projection of the sub-pixel opening 130 on the substrate 110 and the boundary of the orthographic projection of the first light-transmitting opening BM1 on the substrate 110 is 1.0 micrometers to 6.5 micrometers, for example, 3 micrometers to 6 micrometers.

[0074] For example, in some embodiments, such as Figure 5 , Figure 7 and Figure 8 As shown, the black matrix layer BM also includes multiple second light-transmitting openings BM2, which are respectively disposed between two adjacent first light-transmitting openings BM1. The multiple second light-transmitting openings BM2 can transmit signal light, such as that required for fingerprint recognition or for devices like cameras, proximity sensors, and infrared sensors.

[0075] For example, in some embodiments, such as Figure 9 As shown, the display substrate further includes a light-shielding layer S disposed on the substrate 110, and a pixel driving circuit layer 120 disposed on the side of the light-shielding layer S away from the substrate 110. The light-shielding layer S includes a plurality of third light-transmitting openings S1, and the orthographic projection of at least a portion of the plurality of third light-transmitting openings S1 on the substrate 110 respectively overlaps at least partially with the orthographic projection of the plurality of second light-transmitting openings BM2 on the substrate 110.

[0076] Thus, the third light-transmitting opening S1 and the second light-transmitting opening BM2 form a sleeve to transmit signal light, for example, for fingerprint recognition. At this time, an image sensor can be set on the side of the substrate 110 away from the light-emitting device EM. The image sensor can receive the signal light through the second light-transmitting opening BM2 and the third light-transmitting opening S1 to perform texture acquisition and recognition functions.

[0077] For example, in some embodiments, the material of the light-shielding layer 110 can be a metal material such as copper or aluminum, or an alloy material; or, the light-shielding layer 110 can also be a black opaque layer formed by doping a black dye into a resin material.

[0078] In the embodiments of this disclosure, the light-shielding layer S can transmit signal light for fingerprint recognition at the first light-transmitting opening S1, and block light emitted by the light-emitting device EM of the display substrate and non-signal light such as ambient light at other locations, so as to prevent non-signal light from illuminating the image sensor located on the non-display side of the display substrate, thereby improving the recognition speed and accuracy of the image sensor.

[0079] For example, in some embodiments, the pixel driving circuit layer includes multiple metal layers, such as the metal layers containing the gate 122, the first electrode 123, and the second electrode 124. The orthographic projection of the circuit pattern formed by these metal layers on the substrate 110 does not overlap with the orthographic projection of the multiple first light-transmitting openings S1 on the substrate 110, nor with the orthographic projection of the third light-transmitting opening BM2 on the substrate 110, so as to avoid the circuit pattern affecting the transmission of signal light.

[0080] For example, Figure 10 A schematic diagram showing the orthographic projection of a third light-transmitting opening S1 and the corresponding second light-transmitting opening BM2 onto the substrate 110 is shown, as follows. Figure 10 As shown, the orthographic projections of the plurality of third light-transmitting openings S1 on the substrate 110 are respectively located within the orthographic projections of the plurality of second light-transmitting openings BM2 on the substrate 110.

[0081] For example, such as Figure 10As shown, in some embodiments, the distance L3 between the boundary of the orthographic projection of at least a portion of the third light-transmitting openings S1 onto the substrate 110 and the boundary of the orthographic projection of the multiple second light-transmitting openings BM2 onto the substrate 110 is 0.5 micrometers to 1.5 micrometers, such as 0.8 micrometers, 1.0 micrometers, 1.2 micrometers, or 1.5 micrometers, so that the signal light can fully pass through the second light-transmitting openings BM2 and the third light-transmitting openings S1 to reach the image sensor.

[0082] For example, in some embodiments, such as Figure 7 As shown, at least a portion of the plurality of second light-transmitting openings BM2 are located between the first light-transmitting openings BM1 corresponding to the adjacent first sub-pixel R and the third sub-pixel B, and the distance to the first light-transmitting opening BM1 corresponding to the first sub-pixel R is different from the distance to the first light-transmitting opening BM1 corresponding to the third sub-pixel B, for example, the distance to the first light-transmitting opening BM1 corresponding to the third sub-pixel B is closer.

[0083] For example, in some embodiments, such as Figure 7 As shown, the first sub-pixel R and the third sub-pixel B are arranged in multiple rows and columns. Multiple first sub-pixels R and multiple third sub-pixels B located in the same column are arranged alternately, and a second light-transmitting opening BM2 is set between the first light-transmitting openings BM1 corresponding to adjacent first sub-pixels R and third sub-pixels B located in the same column.

[0084] For example, in some embodiments, such as Figure 7 As shown, a first sub-pixel R, two second sub-pixels G, and a third sub-pixel B form a repeating unit. Multiple repeating units are arranged in an array. Multiple second sub-pixels G in the multiple repeating units are arranged in multiple rows and columns. The second light-transmitting opening BM2 is also set between the first light-transmitting opening BM1 corresponding to adjacent second sub-pixels R in the row direction.

[0085] With the above arrangement, the setting of the second light-transmitting opening BM2 and the third light-transmitting opening S1 will not affect the original circuit settings on the display substrate, and the original circuit settings will not affect the signal light passing through the second light-transmitting opening BM2 and the third light-transmitting opening S1 to reach the image sensor.

[0086] For example, refer to Figure 5 Each of the plurality of spacers PS has its orthographic projection on the substrate 110 located between the orthographic projections of the sub-pixel openings 130 of the adjacent second sub-pixel G in the column direction on the substrate 110, and between the orthographic projections of the sub-pixel openings 130 of the adjacent first sub-pixel R and third sub-pixel B in the row direction on the substrate 110.

[0087] For example, refer to Figure 3The shortest distance L11 between the orthographic projection of each of the multiple spacers PS on the substrate 110 and the orthographic projection of the sub-pixel opening 130 of the first sub-pixel R in the adjacent first sub-pixel R and third sub-pixel B on the substrate 110 is greater than the shortest distance L12 between the orthographic projection of the sub-pixel opening 130 of the third sub-pixel B in the adjacent first sub-pixel R and third sub-pixel B on the substrate 110. That is, the spacers PS disposed between the adjacent first sub-pixel R and third sub-pixel B are closer to the sub-pixel opening 130 of the third sub-pixel B than the sub-pixel opening 130 of the first sub-pixel R.

[0088] For example, in some embodiments, reference Figure 3 The shortest distance L13 between the orthographic projection of each of the multiple spacers PS on the substrate 110 and the orthographic projection of the sub-pixel opening 130 of the adjacent second sub-pixel G on the substrate 110 is basically the same. That is, the distance between the spacers PS disposed between adjacent second sub-pixels G and the sub-pixel opening 130 of the adjacent second sub-pixel G is basically the same.

[0089] Thus, multiple spacers PS and the third light-transmitting opening S1 are periodically arranged in the display substrate without affecting each other.

[0090] For example, in some embodiments, such as Figure 8 As shown, a first sub-pixel R, two second sub-pixels G, and a third sub-pixel B constitute a repeating unit, and each repeating unit corresponds to two third light-transmitting openings S1. For example, each third light-transmitting opening S1 corresponds to a second light-transmitting opening BM2. Alternatively, in some embodiments, one of every two or more third light-transmitting openings S1 corresponds to one second light-transmitting opening BM2, that is, one of every two or more third light-transmitting openings S1 corresponds to one second light-transmitting opening BM2 to form a hole, while the other third light-transmitting openings S1 are blocked by the black matrix layer BM and are not used to form holes.

[0091] For example, in some embodiments, such as Figure 8 As shown, each repeating unit is provided with a spacer PS. Alternatively, in other embodiments, two or more repeating units may be provided with a spacer PS. The embodiments disclosed herein do not limit this.

[0092] For example, in some embodiments, such as Figure 2 and Figure 9As shown, the display substrate also includes an encapsulation layer EN disposed on the side of the light-emitting device EM away from the substrate 110, and a black matrix layer BM disposed on the side of the encapsulation layer EN away from the substrate 110. For example, the encapsulation layer EN can be a composite encapsulation layer, including a first inorganic encapsulation layer, a first organic encapsulation layer and a second inorganic encapsulation layer (not shown in the figure) disposed sequentially on the light-emitting device EM, to improve the encapsulation effect.

[0093] For example, in some embodiments, color filters for multiple sub-pixels can be disposed in a composite encapsulation layer, such as between two adjacent sub-encapsulation layers in the composite encapsulation layer. For example, in one example, the composite encapsulation layer includes a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, and a third inorganic encapsulation layer sequentially disposed on the light-emitting device EM, in which case the color filter can be disposed between the second inorganic encapsulation layer and the third inorganic encapsulation layer.

[0094] For example, in some embodiments, such as Figure 9 As shown, the display substrate also includes a touch layer FM disposed on the side of the encapsulation layer EN away from the substrate 110, and a black matrix layer BM disposed on the side of the touch layer FM away from the substrate 110.

[0095] For example, Figure 11 A planar schematic diagram of the touch layer FM is shown, as follows: Figure 9 and Figure 11 As shown, the touch layer FM includes multiple touch traces TL. The orthographic projections of the multiple touch traces TL on the substrate 110 do not overlap with the orthographic projections of the multiple second light-transmitting openings BM2 on the substrate 110. For example, the orthographic projections of the multiple touch traces TL on the substrate 110 also do not overlap with the orthographic projections of the multiple first light-transmitting openings BM1 on the substrate 110. Therefore, the multiple touch traces TL are shielded by the black matrix layer BM to prevent light from shining on the touch traces TL and affecting their signal transmission performance.

[0096] For example, in some embodiments, such as Figure 11 As shown, in the same direction parallel to the substrate 110, the distances between multiple touch traces TL and at least two of the first color filter RCF, the second color filter GCF, and the third color filter BCF are different. For example, at the location indicated by the dashed box, in Figure 11 In the horizontal direction, the distance between the touch trace TL and the third color filter BCF is greater than the distance between the touch trace TL and the first color filter RCF. Because the shape and arrangement of the third color filter BCF are irregular, setting a larger distance between the touch trace TL and the third color filter BCF in this direction can prevent the touch trace TL and the third color filter BCF from overlapping in this direction, or from overlapping by too much.

[0097] For example, in some embodiments, such as Figure 11 As shown, the first sub-pixel R and the third sub-pixel B are arranged in multiple rows and columns, and multiple first sub-pixels R and multiple third sub-pixels B located in the same column are arranged alternately. For example, at least some of the multiple touch lines TL have gaps NT1 / NT2 / NT3 between adjacent first sub-pixels R and third sub-pixels B located in the same column.

[0098] For example, such as Figure 11 As shown, at least a portion of the multiple touch traces TL have a gap NT1 on either the side closer to the third sub-pixel B or the side closer to the first sub-pixel R among adjacent first sub-pixels R and third sub-pixels B in the same column. In this case, at least a portion of the multiple touch traces TL has one gap between adjacent first sub-pixels R and third sub-pixels B in the same column; or, at least a portion of the multiple touch traces TL has gaps NT2 / NT3 on both the side closer to the third sub-pixel B and the side closer to the first sub-pixel R among adjacent first sub-pixels R and third sub-pixels B in the same column. In this case, at least a portion of the multiple touch traces TL has two gaps between adjacent first sub-pixels R and third sub-pixels B in the same column.

[0099] For example, in some embodiments, such as Figure 11 As shown, at least a portion of the multiple touch traces TL have a gap NT1 on either the side closer to the third sub-pixel B or the side closer to the first sub-pixel R in adjacent first sub-pixels R and third sub-pixels B located in the Nth column, and at least a portion of the multiple touch traces TL have gaps NT2 / NT3 on both the side closer to the third sub-pixel B and the side closer to the first sub-pixel R in adjacent first sub-pixels R and third sub-pixels B located in the N+1th column. In this case, in every two adjacent columns of first sub-pixels R and third sub-pixels B, there is one gap between adjacent first sub-pixels R and third sub-pixels B in one column, and two gaps between adjacent first sub-pixels R and third sub-pixels B in the other column.

[0100] For example, the display substrate may also include other structures such as a cover plate, which can be found in relevant technologies and will not be elaborated here.

[0101] For example, in various embodiments of this disclosure, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 12 This is a schematic diagram of an equivalent circuit for an 8T1C pixel driving circuit. (Example:) Figure 12As shown, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8), one storage capacitor C, and multiple signal lines (e.g., data signal line Data, first scan signal line Gate, second scan signal line GateN, reset control signal line Reset, first initial signal line INIT1, second initial signal line INIT2, first power supply line VDD, second power supply line VSS, and light emission control signal line EM, etc.).

[0102] For example, the gate of the first transistor T1 is connected to the reset control signal line Reset, the first terminal of the first transistor T1 is connected to the second initial signal line INIT2, and the second terminal of the first transistor T1 is connected to the fifth node N5. The gate of the second transistor T2 is connected to the first scan signal line Gate, the first terminal of the second transistor T2 is connected to the fifth node N5, and the second terminal of the second transistor T2 is connected to the third node N3. The gate of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3. The gate of the fourth transistor T4 is connected to the first scan signal line Gate, the first terminal of the fourth transistor T4 is connected to the data signal line Data, and the second terminal of the fourth transistor T4 is connected to the second node N2. The gate of the fifth transistor T5 is connected to the light emission control signal line EM, the first terminal of the fifth transistor T5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2. The gate of the sixth transistor T6 is connected to the light-emitting control signal line EM. The first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first terminal of the light-emitting device). The gate of the seventh transistor T7 is connected to the first scan signal line Gate or the reset control signal line Reset. The first terminal of the seventh transistor T7 is connected to the first initial signal line INIT1, and the second terminal of the seventh transistor T7 is connected to the fourth node N4. The gate of the eighth transistor T8 is connected to the second scan signal line GateN. The first terminal of the eighth transistor T8 is connected to the fifth node N5, and the second terminal of the eighth transistor T8 is connected to the first node N1. The first terminal of the storage capacitor C is connected to the first power supply line VDD, and the second terminal of the storage capacitor C is connected to the first node N1.

[0103] In some embodiments, the first transistor T1 to the seventh transistor T7 may be N-type thin-film transistors and the eighth transistor T8 may be P-type thin-film transistors; or, the first transistor T1 to the seventh transistor T7 may be P-type thin-film transistors and the eighth transistor T8 may be N-type thin-film transistors.

[0104] In some embodiments, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon (LTPS) thin film transistors (TFTs), and the eighth transistor T8 can be an indium gallium zinc oxide (IGZO) thin film transistor.

[0105] In the above embodiments, indium gallium zinc oxide (IGN) thin-film transistors (LTVs) generate less leakage current compared to low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS). Therefore, setting the eighth transistor T8 as an IGNV can significantly reduce leakage current, thereby improving the low-frequency, low-brightness flicker problem of the display panel. Furthermore, the first transistor T1 and the second transistor T2 do not need to be IGNVs. Since the size of LTPS is generally smaller than that of IGNVs, the pixel driving circuit of this embodiment occupies less space, which is beneficial for improving the resolution of the display panel.

[0106] The pixel driving circuit provided in this embodiment combines the good switching characteristics of LTPS-TFT and the low leakage current characteristics of Oxide-TFT, enabling low-frequency driving (1Hz to 60Hz) and significantly reducing the power consumption of the display screen.

[0107] In some embodiments, the second electrode of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a continuously low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The signal of the first scan signal line Gate is the scan signal in the pixel driving circuit of this display row, and the signal of the reset control signal line Reset is the scan signal in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n-1). The signal of the reset control signal line Reset of this display row and the signal of the first scan signal line Gate in the pixel driving circuit of the previous display row can be the same signal to reduce the signal lines of the display panel and achieve a narrow bezel of the display panel.

[0108] In some embodiments, the first scan signal line Gate, the second scan signal line GateN, the reset control signal line Reset, the light emission control signal line EM, the first initial signal line INIT1, and the second initial signal line INIT2 all extend in the horizontal direction, while the second power line VSS, the first power line VDD, and the data signal line DATA all extend in the vertical direction.

[0109] In some embodiments, at least a portion of the first initial signal line INIT1, the second initial signal line INIT2, the second power line VSS, and the first power line VDD can be a mesh structure, that is, it includes portions extending in both the horizontal and vertical directions.

[0110] Figure 13 This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 12 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 12 The pixel driving circuit includes eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. In this embodiment, the first transistor T1 to the seventh transistor T7 are P-type transistors, the eighth transistor T8 is an N-type transistor, and the gate of the seventh transistor T7 is connected to the first scan signal line Gate for illustration.

[0111] For example, in some embodiments, the operation of the pixel driving circuit can be carried out in the following stages.

[0112] In the first stage, t1, also known as the reset stage, the signals on the first scan signal line Gate, the reset control signal line Reset, the second scan signal line GateN, and the light emission control signal line EM are all high-level signals, while the signal on the reset control signal line Reset is low-level. The high-level signal on the light emission control signal line EM turns off the fifth transistor T5 and the sixth transistor T6. The high-level signal on the second scan signal line GateN turns on the eighth transistor T8. The low-level signal on the reset control signal line Reset turns on the first transistor T1. Therefore, the voltage at the first node N1 is reset to the second initial voltage Vinit2 provided by the second initial signal line INIT2. Then, the reset control signal line Reset goes high, and the first transistor T1 turns off. Because the fifth transistor T5 and the sixth transistor T6 are off, the light-emitting device EL does not emit light during this stage.

[0113] In the second stage, t2, known as the data writing stage, the first scan signal line Gate is at a low level. Transistors T4, T2, and T7 are turned on, and the data signal line Data outputs a data voltage. The voltage at node N4 is reset to the first initial voltage Vinit1 provided by the first initial voltage line INIT1, completing initialization. During this stage, since node N1 is low, transistor T3 is turned on. The turn-on of transistors T4 and T2 allows the data voltage output from the data signal line Data to be supplied to node N1 via the turned-on transistors T4, N2, T3, N3, T2, N5, and T8. The sum of the data voltage output from the data signal line Data and the threshold voltage of transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of storage capacitor C (node ​​N1) is Vdata + Vth, where Vdata is the data voltage output from the data signal line Data, and Vth is the threshold voltage of transistor T3. When the light-emitting control signal line EM is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned off, ensuring that the light-emitting device EL does not emit light.

[0114] The third stage, t3, is called the light-emitting stage. During this stage, the first scan signal line (Gate) and the reset control signal line (Reset) are both high-level signals, while the light-emitting control signal line (EM) and the second scan signal line (GateN) are both low-level signals. The high-level signal on the reset control signal line (Reset) turns off the seventh transistor (T7), and the low-level signal on the light-emitting control signal line (EM) turns on the fifth transistor (T5) and the sixth transistor (T6). The power supply voltage output from the first power supply line (VDD) provides a driving voltage to the first terminal (i.e., the fourth node N4) of the light-emitting device EL through the conducting fifth transistor (T5), third transistor (T3), and sixth transistor (T6), driving the light-emitting device EL to emit light.

[0115] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (i.e., the third transistor) is determined by the voltage difference between its gate and its first terminal. Since the voltage at the first node N1 is Vdata + Vth, the driving current of the third transistor T3 is:

[0116] I = K * (Vgs - Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdata-Vdd)] 2

[0117] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the gate and the first terminal of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0118] As can be seen from the above formula, the current I flowing through the light-emitting device EL is independent of the threshold voltage Vth of the third transistor T3, thus eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0119] Based on the above working timing, the pixel driving circuit eliminates the residual positive charge of the light-emitting device EL after the last emission, realizes the compensation of the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light-emitting device EL, and improves the uniformity of the displayed image and the display quality of the display panel.

[0120] The pixel driving circuit of this embodiment can adjust the reset voltage of the light-emitting device EL and the reset voltage of the first node N1 respectively by initializing the fourth node N4 to the signal of the first initial signal line INIT1 and the fifth node N5 to the signal of the second initial signal line INIT2, thereby achieving a better display effect and improving problems such as low-frequency flicker.

[0121] For example, Figures 14-25 A planar schematic diagram showing the sequentially stacked layers of a display substrate provided in at least one embodiment of the present disclosure is shown.

[0122] For example, Figure 14 A planar schematic diagram of the light-shielding layer is shown, which includes multiple first light-transmitting openings (third openings) S1.

[0123] Figure 15 A planar schematic diagram of the first semiconductor layer stacked behind a light-shielding layer is shown. The first semiconductor layer includes the active layers of multiple thin-film transistors. The first semiconductor layer may be made of silicon, including amorphous silicon and polycrystalline silicon; in some embodiments, the first semiconductor layer may be made of amorphous silicon a-Si, which may be crystallized or laser annealed to form polycrystalline silicon.

[0124] Figure 15 The area indicated by the dashed box represents the setting range of the pixel driving circuit for one sub-pixel. For example... Figure 15As shown, the first semiconductor layer may include a first active layer 10 of a first transistor T1, a second active layer 20 of a second transistor T2, a third active layer 30 of a third transistor T3, a fourth active layer 40 of a fourth transistor T4, a fifth active layer 50 of a fifth transistor T5, a sixth active layer 60 of a sixth transistor T6, and a seventh active layer 70 of a seventh transistor T7. The first active layer 10, the second active layer 20, the third active layer 30, the fourth active layer 40, the fifth active layer 50, the sixth active layer 60, and the seventh active layer 70 are an integrally connected structure.

[0125] In some embodiments, the shape of the third active layer 30 may be in a "ji" shape, and the shapes of the first active layer 10, the second active layer 20, the fourth active layer 40, the fifth active layer 50, the sixth active layer 60, and the seventh active layer 70 may be in a "1" shape.

[0126] In some embodiments, in the second direction Y, the first semiconductor layers of any two adjacent columns of sub-pixels are mirror-symmetric structures.

[0127] In some embodiments, the channel regions of the third active layer 30 extend in the row direction, and the channel regions of the first active layer 10, the second active layer 20, the fourth active layer 40, the fifth active layer 50, the sixth active layer 60, and the seventh active layer 70 extend in the column direction.

[0128] For example, the orthographic projection of the third light-transmitting opening S1 on the substrate 110 is adjacent to the orthographic projections of the sixth active layer 60 and the seventh active layer 70 on the substrate 110. Correspondingly, the orthographic projection of the second light-transmitting opening BM2 on the substrate 110 is adjacent to the orthographic projections of the sixth active layer 60 and the seventh active layer 70 on the substrate 110.

[0129] In some embodiments, the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may all be LTPS thin-film transistors.

[0130] For example, Figure 16 shows a planar schematic diagram of the first conductive layer stack after the first semiconductor layer. In some embodiments, as Figure 16 shown, the first conductive layer may include: a first scan signal line Gate_P, a reset control signal line Reset_P, a light-emitting control signal line EM_P, and a first electrode plate Ce1 of the storage capacitor C. In some embodiments, the first conductive layer may be referred to as the first gate metal (GATE 1) layer.

[0131] In some embodiments, in the second direction Y, the first conductive layers of any two adjacent columns of sub-pixels are mirror-symmetric structures.

[0132] In some embodiments, the first scan signal line Gate_P, the reset control signal line Reset_P, and the light emission control signal line EM_P all extend along a first direction X. Within each sub-pixel, the reset control signal line Reset_P is located on the side of the first scan signal line Gate_P away from the light emission control signal line EM_P, and the first plate Ce1 of the storage capacitor is disposed between the first scan signal line Gate_P and the light emission control signal line EM_P.

[0133] For example, the pixel driving circuit layer (e.g., the first conductive layer described above) includes a first signal line (e.g., a light emission control signal line EM_P in some embodiments) and a second signal line (e.g., a reset control line Reset_P in some embodiments) arranged parallel to each other and periodically. The first signal line and the second signal line are configured to provide different electrical signals to multiple sub-pixels. The orthographic projections of multiple third light-transmitting openings S1 on the substrate 110 are respectively located between the orthographic projection of a first signal line (e.g., a light emission control signal line EM_P) on the substrate 110 and the orthographic projection of a second signal line (e.g., a reset control line Reset_P) closest to that first signal line on the substrate 110. Correspondingly, the orthographic projections of multiple second light-transmitting openings BM2 on the substrate 110 are respectively located between the orthographic projection of a first signal line (e.g., a light emission control signal line EM_P) on the substrate 110 and the orthographic projection of a second signal line (e.g., a reset control line Reset_P) closest to that first signal line on the substrate 110.

[0134] For example, multiple sub-pixels include a first row of sub-pixels RO1 and a second row of sub-pixels RO2 adjacent to and below the first row of sub-pixels RO1. The pixel driving circuit of the first row of sub-pixels RO1 shares a light emission control signal line EM_P and a reset control line Reset_P. The pixel driving circuit of the second row of sub-pixels RO2 shares a light emission control signal line EM_P and a reset control line Reset_P. The orthographic projection of the light emission control signal line EM_P shared by the pixel driving circuit of the first row of sub-pixels RO1 on the substrate 110 and the orthographic projection of the reset control line Reset_P shared by the pixel driving circuit of the second row of sub-pixels RO2 on the substrate 110 includes the orthographic projection of a third light-transmitting opening S1 on the substrate 110. Accordingly, between the orthographic projection of the light-emitting control signal line EM_P shared by the pixel driving circuit of the first row of sub-pixels RO1 on the substrate 110 and the orthographic projection of the reset control line Reset_P shared by the pixel driving circuit of the second row of sub-pixels RO1 on the substrate 110, there is an orthographic projection of a second light-transmitting opening BM2 on the substrate 110.

[0135] In some embodiments, the first electrode plate Ce1 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode plate Ce1 on the substrate 110 overlaps with the orthographic projection of the third active layer 30 of the third transistor T3 on the substrate 110. In some embodiments, the first electrode plate Ce1 also serves as the gate of the third transistor T3.

[0136] In some embodiments, the region where the reset control signal line Reset_P overlaps with the first active layer of the first transistor T1 serves as the gate of the first transistor T1; the region where the first scan signal line Gate_P overlaps with the second active layer of the second transistor T2 serves as the gate of the second transistor T2; the region where the first scan signal line Gate_P overlaps with the fourth active layer of the fourth transistor T4 serves as the gate of the fourth transistor T4; the region where the light emission control signal line EM_P overlaps with the fifth active layer of the fifth transistor T5 serves as the gate of the fifth transistor T5; and the region where the light emission control signal line EM_P overlaps with the sixth active layer of the sixth transistor T6 serves as the gate of the sixth transistor T6. In the next row of sub-pixels, the region where the reset control signal line Reset_P (with the same signal as the first scan signal line Gate_P in the current row of sub-pixels) overlaps with the seventh active layer of the seventh transistor T7 in the current row of sub-pixels serves as the gate of the seventh transistor T7.

[0137] For example, Figure 17 A planar schematic diagram shows the second conductive layer stacked after the first conductive layer. (See diagram below.) Figure 17 As shown, the second conductive layer includes: a second electrode Ce2 of the storage capacitor C and a first branch GateN_B1 of the second scan signal line GateN. In some embodiments, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0138] In some embodiments, in the second direction Y, the second conductive layer of any two adjacent columns of sub-pixels has a mirror-symmetric structure.

[0139] In some embodiments, the first branch GateN_B1 of the second scan signal line GateN extends along the first direction X. Within each sub-pixel, the second plate Ce2 of the storage capacitor is located between the first branch GateN_B1 of the second scan signal line GateN and the light emission control signal line EM_P.

[0140] In some embodiments, the outline of the second electrode plate Ce2 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate Ce2 on the substrate 110 overlaps with the orthographic projection of the first electrode plate Ce1 on the substrate 110. An opening H is provided on the second electrode plate Ce2, and the opening H can be located in the middle of the second electrode plate Ce2. The opening H can be a regular hexagon, so that the second electrode plate Ce2 forms a ring structure. The opening H exposes the third insulating layer covering the first electrode plate Ce1, and the orthographic projection of the first electrode plate Ce1 on the substrate 110 includes the orthographic projection of the opening H on the substrate 110. In some embodiments, the opening H is configured to accommodate a subsequently formed fourth via, which is located within the opening H and exposes the first electrode plate Ce1, so that the second electrode of the subsequently formed eighth transistor T8 is connected to the first electrode plate Ce1.

[0141] For example, Figure 18 A planar schematic diagram of the second semiconductor layer stacked behind the second conductive layer is shown.

[0142] In some embodiments, such as Figure 18 As shown, the second semiconductor layer of each sub-pixel may include the eighth active layer 80 of the eighth transistor T8. In some embodiments, the eighth active layer 80 extends along the second direction Y, and the shape of the eighth active layer 80 may be dumbbell-shaped.

[0143] In the second direction Y, the second semiconductor layer of any two adjacent columns of sub-pixels has a mirror-symmetric structure.

[0144] In some embodiments, the second semiconductor layer may be an oxide layer, i.e., the eighth transistor is an oxide thin-film transistor.

[0145] For example, Figure 19 A planar schematic diagram shows the third conductive layer stacked after the second conductive layer. (See diagram below.) Figure 19 As shown, the third conductive layer includes: a second branch GateN_B2 of the second scan signal line GateN and a second initial signal line INIT2. In some embodiments, the third conductive layer may be referred to as the third gate metal (GATE3) layer.

[0146] In some embodiments, in the second direction Y, the third conductive layer of any two adjacent columns of sub-pixels has a mirror-symmetric structure.

[0147] In some embodiments, the second branch GateN_B2 of the second scan signal line GateN extends along the first direction X, and the second branch GateN_B2 of the second scan signal line Gate is close to the second branch Gate_B2 of the first scan signal line Gate. In some embodiments, the region where the second branch GateN_B2 of the second scan signal line GateN overlaps with the eighth active layer 80 serves as the gate of the eighth transistor.

[0148] In some embodiments, the orthographic projection of the second branch GateN_B2 of the second scan signal line on the substrate 110 overlaps with the orthographic projection of the first branch GateN_B1 of the second scan signal line on the substrate 110. In some embodiments, the first branch GateN_B1 and the second branch GateN_B2 of the second scan signal line can be connected by a signal line in the peripheral region.

[0149] In some embodiments, the second initial signal line INIT2 extends along the first direction X, and within each row of sub-pixels, the second initial signal line INIT2 is disposed on the side of the reset control signal line Reset_P away from the first scan signal line Gate_P.

[0150] For example, the orthographic projection of the third light-transmitting opening S1 on the substrate 110 is also located between the orthographic projections of the light-emitting control signal line EM_P and the second initial signal line INIT2, which is closest to the light-emitting control signal line EM_P, on the substrate 110. Correspondingly, the orthographic projection of the second light-transmitting opening BM2 on the substrate 110 is also located between the light-emitting control signal line EM_P and the second initial signal line INIT2, which is closest to the light-emitting control signal line EM_P, on the substrate 110.

[0151] For example, Figure 20 A planar distribution diagram of multiple vias in the insulating layer formed on the third conductive layer is shown. (See diagram for reference.) Figure 20 As shown, the insulating layer is provided with multiple vias, including: first via V1, second via V2, third via V3, fourth via V4, fifth via V5, sixth via V6, seventh via V7, eighth via V8, ninth via V9, tenth via V10 and eleventh via V11.

[0152] For example, a first via V1 exposes the surface of the second region of the eighth active layer 80. A second via exposes the surface of the first region of the eighth active layer 80. A third via V3 exposes the surface of the first region of the second active layer. The third via V3 is configured to allow the first electrode of a subsequently formed second transistor T2 to be connected to the second active layer through this via.

[0153] The fourth via V4 is located within the opening H of the second electrode plate Ce2. The orthographic projection of the fourth via V4 onto the substrate 110 lies within the range of the orthographic projection of the opening H onto the substrate 110. The fourth via V4 exposes the surface of the first electrode plate Ce1. The fourth via V4 is configured to allow the subsequently formed third connecting electrode 43 to connect to the first electrode plate Ce1 through this via.

[0154] The fifth via V5 exposes the surface of the first region of the fifth active layer. The fifth via V5 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the fifth active layer through this via.

[0155] The sixth via V6 is located in the region where the second electrode plate Ce2 is located. The orthographic projection of the sixth via V6 onto the substrate 110 lies within the range of the orthographic projection of the second electrode plate Ce2 onto the substrate 110. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the sixth via V6 are etched away, exposing the surface of the second electrode plate Ce2. The sixth via V6 is configured to allow the subsequently formed fifth connection electrode 45 to be connected to the second electrode plate Ce2 through this via.

[0156] A seventh via V7 exposes the surface of the first region of the first active layer. The seventh via V7 is configured to connect the first electrode of a subsequently formed first transistor T1 to the first active layer via this via. An eighth via V8 exposes the surface of the first region of the seventh active layer. The eighth via V8 is configured to connect the subsequently formed first initial signal line to the seventh active layer via this via. A ninth via V9 exposes the surface of the second region of the sixth active layer. The ninth via V9 is configured to connect the second electrode of a subsequently formed sixth transistor T6 to the sixth active layer via this via, and also to connect the second electrode of a subsequently formed seventh transistor T7 to the seventh active layer via this via.

[0157] The tenth via V10 exposes the surface of the first region of the fourth active layer. The tenth via V10 is configured to allow the subsequently formed second connection electrode 42 to connect to the fourth active layer through this via. The eleventh via V11 exposes the surface of the second initial signal line INIT2. The eleventh via V11 is configured to allow the subsequently formed sixth connection electrode 46 to connect to the second initial signal line INIT2 through this via.

[0158] Figure 21 A planar schematic diagram shows the fourth conductive layer stacked behind the third conductive layer. (See diagram below.) Figure 21 As shown, the fourth conductive layer includes: a first initial signal line INIT1, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, and a sixth connection electrode 46. In some embodiments, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0159] In some embodiments, in the second direction Y, the fourth conductive layer of any two adjacent columns of sub-pixels has a mirror-symmetric structure.

[0160] In some embodiments, the first initial signal line INIT1 extends along the first direction X, and the first initial signal line INIT1 is connected to the first region of the seventh active layer through the eighth via V8, so that the first electrode of the seventh transistor T7 has the same potential as the first initial signal line INIT1.

[0161] In some embodiments, one end of the first connection electrode 41 is connected to the first region of the second active layer (which is also the second region of the first active layer) through the third via V3, and the other end is connected to the first region of the eighth active layer through the second via V2. In some embodiments, the first connection electrode 41 can serve as the first electrode of the eighth transistor T8, the first electrode of the second transistor, and the second electrode of the first transistor.

[0162] In some embodiments, the second connection electrode 42 is connected to the first region of the fourth active layer through the tenth via V10, and to the subsequently formed data signal line Data through the subsequently formed thirteenth via V13. In some embodiments, the second connection electrode 42 can serve as the first electrode of the fourth transistor T4.

[0163] In some embodiments, one end of the third connection electrode 43 is connected to the second region of the eighth active layer through a first via V1, and the other end is connected to the first electrode plate Ce1 through a fourth via V4. In some embodiments, the third connection electrode 43 can serve as the second electrode of the eighth transistor T8.

[0164] In some embodiments, the fourth connection electrode 44 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the ninth via V9, and to the subsequently formed first electrode connection electrode through the subsequently formed twelfth via V12. In some embodiments, the fourth connection electrode 44 can simultaneously serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7.

[0165] In some embodiments, the fifth connection electrode 45 (power connection electrode) is connected to the second electrode plate Ce2 through the sixth via V6 and to the first region of the fifth active layer through the fifth via V5. The fifth connection electrode 45 is configured to be connected to the subsequently formed first power line VDD through the subsequently formed fourteenth via V14.

[0166] In some embodiments, one end of the sixth connection electrode 46 is connected to the first region of the first active layer through the seventh via V7, and the other end is connected to the second initial signal line through the eleventh via V11, so that the first electrode of the first transistor T1 and the second initial signal line INIT2 have the same potential.

[0167] Figure 22A planar schematic diagram is shown showing the first planarization layer stack after the fourth conductive layer and the fifth conductive layer stack, following the first planarization layer. In some embodiments, such as Figure 22 As shown, the first planarization layer 97 includes a twelfth via V12, a thirteenth via V13, and a fourteenth via V14, and the fifth conductive layer includes a data signal line Data, a first power line VDD, and a first electrode connection electrode 51. In some embodiments, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0168] In some embodiments, the fifth conductive layer of any two adjacent columns of sub-pixels in the second direction Y is a mirror-symmetric structure. In other exemplary embodiments, the fifth conductive layer of any two adjacent columns of sub-pixels in the second direction Y may not be a mirror-symmetric structure. The area of ​​the second source / drain metal layer below the second or third opening can be increased as needed to increase the flatness of the first electrode (anode) formed on the upper layer, so that the sub-pixels are all located on a plane, thereby reducing color shift and improving display quality.

[0169] In some embodiments, such as Figure 22 As shown, within a repeating unit, the first power lines VDD in two adjacent columns of sub-pixels can be interconnected as a single structure. By making the first power lines VDD in two adjacent columns of sub-pixels form an interconnected single structure, the anode formed in the upper layer can be made flatter.

[0170] For example, the driving circuit layer includes third signal lines (e.g., the aforementioned first power line VDD) arranged in parallel and periodic order. These third signal lines extend along a second direction Y, intersecting with the first and second signal lines respectively. The third signal lines are configured to provide power signals to multiple sub-pixels, such as... Figure 18 As shown, the third signal line includes a cutout portion OD, and the orthographic projection of the third light-transmitting opening S1 on the substrate 110 is located within the orthographic projection of the cutout portion OD on the substrate 110. Correspondingly, the orthographic projection of the second light-transmitting opening BM2 on the substrate 110 is located within the orthographic projection of the cutout portion OD1 on the substrate 110.

[0171] In some embodiments, the first electrode connecting electrode 51 may be rectangular, and the first electrode connecting electrode 51 is connected to the fourth connecting electrode 44 through the twelfth through hole V12.

[0172] In some embodiments, the first power line VDD is connected to the fifth connection electrode 45 through the fourteenth via V14.

[0173] In some embodiments, the data signal line Data extends along the second direction Y and is connected to the second connection electrode 42 through the thirteenth via V13. Since the second connection electrode 42 is connected to the first region of the fourth active layer through the tenth via V10, the connection between the data signal line and the first electrode of the fourth transistor is realized, so that the data signal transmitted by the data signal line Data can be written into the fourth transistor.

[0174] For example, Figure 23 A planar schematic diagram of the second planarization layer stack behind the fifth conductive layer is shown. In some embodiments, such as Figure 23 As shown, the second planarization layer 98 includes a fifteenth via V15.

[0175] In some embodiments, the fifteenth via V15 is located in the region where the first electrode connection electrode 51 is located. The second planarization layer in the fifteenth via V15 is removed to expose the surface of the first electrode connection electrode 51. The fifteenth via V15 is configured to allow a subsequently formed first electrode (e.g., an anode) to be connected to the first electrode connection electrode 51 through the via.

[0176] For example, to show clearly, Figure 24 A planar schematic diagram of the first electrode layer is shown. (See diagram below.) Figure 24 As shown, the first electrode layer includes a plurality of first electrodes 141 of sub-pixels. Each first electrode 141 includes a main body portion 141A and a connecting portion 141B. The main body portion 141A is exposed by the sub-pixel opening 130, and the connecting portion 141B is connected to the first electrode connecting electrode 51 through the fifteenth via V15.

[0177] Since the first electrode connecting electrode 51 is connected to the fourth connecting electrode 44 through the twelfth via V12, and the fourth connecting electrode 44 is also connected to the sixth active layer through the ninth via V9, the pixel driving circuit can drive the light-emitting device to emit light.

[0178] For example, Figure 25 A planar schematic diagram of the pixel delimiting layer (PDL) is shown, as follows. Figure 25 As shown, the pixel delimiting layer (PDL) includes a plurality of sub-pixel openings 130. The shape of the plurality of sub-pixel openings 130 is the same as that of the shape substrate of the main body portion 141A of the first electrode 141, and the size is slightly smaller than that of the main body portion 141A, so as to fully expose the main body portion 141A.

[0179] For example, the structure and positional relationship of the spacer layer 140 above the pixel definition layer PDL, the touch layer FM, the black matrix layer BM, and the color filter can be found in [reference needed]. Figure 3 , Figure 5 , Figures 7-9 as well as Figure 11 Etc., will not be elaborated upon here.

[0180] For example, in some embodiments, reference Figure 23 The pixel driving circuit layer includes multiple pixel driving circuits and multiple scan signal lines Gate (e.g., Gate_P as an example) providing scan signals to the multiple pixel driving circuits, and multiple reset control signal lines Reset (e.g., Reset_P as an example) providing reset control signals to the multiple pixel driving circuits. In a direction parallel to the substrate, at least a portion of the multiple spacers PS are respectively located between a reset control signal line Reset (e.g., Reset_P) and the scan signal line Gate (e.g., Gate_P) closest to the reset control signal line Reset. For example, the reset control signal line Reset and the scan signal line Gate closest to the reset control signal line Reset are used to provide electrical signals to the same row of pixel driving circuits.

[0181] Alternatively, in other embodiments, due to the large size of the spacers PS or alignment differences, at least a portion of the plurality of spacers PS overlaps with at least one of a reset control signal line Reset (e.g., Reset_P) and a scan signal line Gate (e.g., Gate_P) closest to the reset control signal line in the direction perpendicular to the substrate. For example, as shown in the figure, it overlaps with the scan signal line Gate (e.g., Gate_P). In other embodiments, it may also overlap with the reset control signal line Reset (e.g., Reset_P), or overlap with both simultaneously. In this case, at least a portion of the structure of the spacers PS is located between the aforementioned reset control signal line Reset (e.g., Reset_P) and the scan signal line Gate closest to the reset control signal line.

[0182] In embodiments of this disclosure, the substrate 110 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, while the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0183] For example, the first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single-layer, multi-layer, or composite layer. The planarization layer can be made of organic materials, and the multiple traces (TL) of the touch layer (FM) can be made of metal oxide materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first semiconductor layer can be made of polycrystalline silicon (p-Si), and the second semiconductor layer (SML2) can be made of oxides.

[0184] The stacked structure of the display substrate provided in this disclosure is merely an exemplary illustration. In some embodiments, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs. The embodiments of this disclosure are not limited here.

[0185] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0186] The following points also need to be explained:

[0187] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0188] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0189] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0190] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate having a plurality of sub-pixels, and comprising: Substrate A pixel driving circuit layer is disposed on the substrate. A pixel defining layer, disposed on the side of the pixel driving circuit layer away from the substrate, includes a plurality of sub-pixel openings, wherein each of the plurality of sub-pixels includes a pixel driving circuit disposed in the pixel driving circuit layer and a light-emitting device at least partially disposed in the sub-pixel opening. A spacer layer, disposed on the side of the pixel defining layer away from the substrate, includes a plurality of spacers, wherein the transmittance of the plurality of spacers is less than 5%, and A black matrix layer is disposed on the side of the light-emitting device away from the substrate. The plurality of sub-pixels includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, wherein the plurality of first sub-pixels and the plurality of third sub-pixels are arranged in multiple rows and columns. Multiple first sub-pixels and multiple third sub-pixels located in the same column are arranged alternately. The plurality of second sub-pixels are arranged in multiple rows and columns. The orthographic projection of each of the plurality of spacers on the substrate is respectively located between the orthographic projections of the sub-pixel openings of adjacent second sub-pixels in the column direction on the substrate, and respectively located between the orthographic projections of the sub-pixel openings of adjacent first and third sub-pixels in the row direction on the substrate. The shortest distance between the orthographic projection of each of the plurality of spacers on the substrate and the orthographic projection of the subpixel opening of the first subpixel of the adjacent first subpixel and third subpixel on the substrate is greater than the shortest distance between the orthographic projection of the subpixel opening of the third subpixel of the adjacent first subpixel and third subpixel on the substrate. 2.The display substrate of claim 1, wherein, The transmittance of the pixel defining layer is less than 5% in the portion excluding the plurality of sub-pixel openings. 3.The display substrate according to claim 1 or 2, wherein, The spacer layer is made of the same material as the pixel defining layer. 4.The display substrate according to claim 1 or 2, wherein The minimum distance between the plurality of spacers and the plurality of sub-pixel openings is L, and 1 micrometer < L < 8 micrometers. 5.The display substrate according to claim 1 or 2, wherein At least some of the spacers are rectangular in shape. 6.The display substrate of claim 5, wherein, The length and width of the rectangle range from 13 micrometers to 19 micrometers. The height of the plurality of spacers is 0.5 micrometers to 2.0 micrometers in a direction perpendicular to the substrate. 7.The display substrate according to claim 1 or 2, wherein The pixel driving circuit layer includes multiple pixel driving circuits, multiple scan signal lines providing scan signals to the multiple pixel driving circuits, and multiple reset control signal lines providing reset control signals to the multiple pixel driving circuits. In a direction parallel to the substrate, at least a portion of the plurality of spacers are respectively located between a reset control signal line and a scan signal line closest to the reset control signal line. 8.The display substrate of claim 7, wherein, The pixel driving circuit layer includes multiple pixel driving circuits, multiple scan signal lines providing scan signals to the multiple pixel driving circuits, and multiple reset control signal lines providing reset control signals to the multiple pixel driving circuits. In a direction perpendicular to the substrate, at least a portion of the plurality of spacers overlap with at least one of a reset control signal line and a scan signal line closest to the reset control signal line.

9. The display substrate according to claim 1 or 2, wherein, The black matrix layer includes multiple first light-transmitting openings. The orthographic projections of the plurality of sub-pixel openings on the substrate are respectively located inside the orthographic projections of the plurality of first light-transmitting openings on the substrate, and the distances between the boundaries of the orthographic projections of the plurality of sub-pixel openings on the substrate and the boundaries of the orthographic projections of the plurality of first light-transmitting openings on the substrate are 1.0 micrometers to 6.5 micrometers.

10. The display substrate according to claim 9, further comprising a plurality of color filters, wherein, The plurality of color filters are respectively disposed at least partially in the plurality of first light-transmitting openings; For a first light-transmitting opening and at least partially disposed in a color filter in the first light-transmitting opening, the orthographic projection of the first light-transmitting opening on the substrate is located inside the orthographic projection of the color filter on the substrate.

11. The display substrate according to claim 10, wherein, The black matrix layer also includes a plurality of second light-transmitting openings, which are respectively disposed between two adjacent first light-transmitting openings among the plurality of first light-transmitting openings.

12. The display substrate according to claim 11, further comprising a light-shielding layer disposed on the substrate, wherein, The pixel driving circuit layer is disposed on the side of the light-shielding layer away from the substrate, and the light-shielding layer includes a plurality of third light-transmitting openings. At least a portion of the orthographic projections of the plurality of third light-transmitting openings onto the substrate overlap at least partially with the orthographic projections of the plurality of second light-transmitting openings onto the substrate.

13. The display substrate according to claim 12, wherein, The orthographic projections of the plurality of third light-transmitting openings on the substrate are respectively located within the orthographic projections of the plurality of second light-transmitting openings on the substrate.

14. The display substrate according to claim 13, wherein, The boundaries of the orthographic projections of at least a portion of the plurality of third light-transmitting openings onto the substrate are respectively 0.5 micrometers to 1.5 micrometers apart from the boundaries of the orthographic projections of the plurality of second light-transmitting openings onto the substrate.

15. The display substrate according to claim 12, wherein, At least a portion of the plurality of second light-transmitting openings are located between the first light-transmitting openings corresponding to adjacent first and third sub-pixels, and the distance from the first light-transmitting opening corresponding to the first sub-pixel is different from the distance from the first light-transmitting opening corresponding to the third sub-pixel.

16. The display substrate according to claim 15, wherein, A second light-transmitting opening is provided between the first light-transmitting openings corresponding to the first and third sub-pixels located in the same column.

17. The display substrate according to claim 16, wherein, A repeating unit consists of a first sub-pixel, two second sub-pixels, and a third sub-pixel; multiple repeating units are arranged in an array. The second light-transmitting opening is also disposed between the first light-transmitting openings corresponding to adjacent second sub-pixels in the row direction.

18. The display substrate according to claim 1, wherein, The orthographic projection of each of the plurality of spacers on the substrate is substantially the same as the shortest distance of the orthographic projection of the subpixel opening of the adjacent second subpixel on the substrate.

19. The display substrate according to claim 1, wherein, The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

20. The display substrate according to claim 11, further comprising an encapsulation layer disposed on the side of the light-emitting device away from the substrate and a touch layer disposed on the side of the encapsulation layer away from the substrate. in, The black matrix layer is disposed on the side of the encapsulation layer away from the substrate, and the touch layer is disposed on the side of the touch layer away from the substrate. The touch layer includes multiple touch traces. The orthographic projections of the multiple touch traces on the substrate do not overlap with the orthographic projections of the multiple second light-transmitting openings on the substrate.

21. The display substrate according to claim 20, wherein, At least some of the multiple touch traces have gaps between adjacent first and third sub-pixels located in the same column.

22. The display substrate according to claim 21, wherein, At least a portion of the multiple touch traces have a gap on the side closer to the third sub-pixel or the side closer to the first sub-pixel in adjacent first and third sub-pixels located in the same column; or At least some of the multiple touch traces have gaps on both the side closer to the third sub-pixel and the side closer to the first sub-pixel in adjacent first and third sub-pixels located in the same column.

23. A display device comprising the display substrate according to any one of claims 1-22.

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