Display panel and display device

Abstract

A display panel and a display device, the display panel comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor (T3) and a fourth transistor (T4), the first electrode of the fourth transistor (T4) being connected to a data line (Da), and the second electrode of the fourth transistor (T4) being connected to the first electrode of the driving transistor (T3), the display panel further comprising: a substrate (91), a first conductive layer, a second conductive part (12), and a third conductive part (23), the first conductive layer being located on one side of the substrate (91), the first conductive layer comprising a first gate line (G1) and a first conductive part (11), the first gate line (G1) extending along a first direction (X) in the orthographic projection of the first gate line (G1) on the substrate (91), and part of the structure of the first gate line (G1) being used to form a gate electrode of the fourth transistor (T4), and the first conductive part (11) being used to form a gate electrode of the driving transistor (T3); the second conductive part (12) being connected to the first gate line (G1); the third conductive part (23) at least partially overlapping the second conductive part (12) in the orthographic projection of the third conductive part (23) on the substrate (91); and a fourth conductive layer being located on the side of the first conductive layer away from the substrate (91), the fourth conductive layer comprising a first bridge part (41), the first bridge part (41) being connected to the third conductive part (23) and the first conductive part (11) through vias, respectively. The display panel can reduce the data voltage of a black picture.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] In the related art, a data signal voltage required for displaying a black picture by a display panel is large, thereby resulting in high power consumption of the display panel.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] According to an aspect of the present disclosure, a display panel is provided, the display panel comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a fourth transistor, a first electrode of the fourth transistor connected to a data line, a second electrode of the fourth transistor connected to a first electrode of the driving transistor, the display panel further comprising: a substrate, a first conductive layer, a second conductive part, a third conductive part, a fourth conductive layer, the first conductive layer located on one side of the substrate, the first conductive layer comprising a first gate line and a first conductive part, a projection of the first gate line on the substrate extending along a first direction, and part of the structure of the first gate line being used to form a gate electrode of the fourth transistor, the first conductive part being used to form a gate electrode of the driving transistor; the second conductive part connected to the first gate line; the third conductive part and the second conductive layer being located in different conductive layers, and a projection of the third conductive part on the substrate at least partially overlapping with a projection of the second conductive part on the substrate; the fourth conductive layer located on a side of the first conductive layer away from the substrate, the fourth conductive layer comprising a first bridge part, the first bridge part connected to the third conductive part and the first conductive part through vias, respectively.

[0005] In an exemplary embodiment of the present disclosure, the pixel driving circuit further comprises an eighth transistor, a first transistor, and a second transistor; a first electrode of the eighth transistor connected to a gate electrode of the driving transistor, a second electrode of the eighth transistor connected to a second electrode of the first transistor, a first electrode of the first transistor connected to a first initial signal line, a first electrode of the second transistor connected to a second electrode of the eighth transistor, and a second electrode of the second transistor connected to a second electrode of the driving transistor.

[0006] In an exemplary embodiment of the present disclosure, the conductive layer where the second conductive part is located is located between the first conductive layer and the fourth conductive layer; and the conductive layer where the third conductive part is located is located between the conductive layer where the second conductive part is located and the fourth conductive layer.

[0007] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, a second electrode of the capacitor is connected to a power supply line, and the first conductive part is further used to form the first electrode of the capacitor. The display panel further comprises a second conductive layer between the first conductive layer and the fourth conductive layer, the second conductive layer comprises a fourth conductive part, a projection of the fourth conductive part on the substrate substrate at least partially overlaps with a projection of the first conductive part on the substrate substrate, and the fourth conductive part is used to form the second electrode of the capacitor. The third conductive part is located in the second conductive layer.

[0008] In an example embodiment of the present disclosure, the display panel further comprises a second active layer between the first conductive layer and the fourth conductive layer, the second active layer comprises an eighth active part, and the eighth active part is used to form a channel region of the eighth transistor. The third conductive part is located in the second active layer.

[0009] In an example embodiment of the present disclosure, a projection of the second conductive part on the substrate substrate is located on a side of a projection of the first gate line on the substrate substrate away from a projection of the first conductive part on the substrate substrate, and a projection of the third conductive part on the substrate substrate is located on a side of a projection of the first gate line on the substrate substrate away from a projection of the first conductive part on the substrate substrate.

[0010] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, a second electrode of the second transistor is connected to the second electrode of the driving transistor, and part of the structure of the first gate line is used to form a gate of the second transistor. The display panel further comprises a first active layer between the substrate substrate and the first conductive layer, the first active layer comprises a second active part and a fourth active part, a projection of the first gate line on the substrate substrate covers a projection of the second active part on the substrate substrate and a projection of the fourth active part on the substrate substrate, the second active part is used to form a channel region of the second transistor, and the fourth active part is used to form a channel region of the fourth transistor. In the first direction, a projection of the second conductive part on the substrate substrate is located between a projection of the second active part on the substrate substrate and a projection of the fourth active part on the substrate substrate.

[0011] In an example embodiment of the present disclosure, in the first direction, a projection of the third conductive portion on the substrate substrate is located between a projection of the second active portion on the substrate substrate and a projection of the fourth active portion on the substrate substrate; a distance between the projection of the third conductive portion on the substrate substrate and the projection of the fourth active portion on the substrate substrate in the first direction is greater than a distance between the projection of the third conductive portion on the substrate substrate and the projection of the second active portion on the substrate substrate in the first direction.

[0012] In an example embodiment of the present disclosure, the third conductive portion includes a first edge and a second edge oppositely arranged in the first direction, and a third edge and a fourth edge oppositely arranged in a second direction intersecting the first direction; the second conductive portion includes a fifth edge and a sixth edge oppositely arranged in the first direction; in the first direction, a projection of the fifth edge on the substrate substrate is located between a projection of the first edge on the substrate substrate and a projection of the second edge on the substrate substrate, and a projection of the sixth edge on the substrate substrate is located between the projection of the first edge on the substrate substrate and the projection of the second edge on the substrate substrate; the projection of the third edge on the substrate substrate and the projection of the fourth edge on the substrate substrate both intersect the projection of the second conductive portion on the substrate substrate.

[0013] In an example embodiment of the present disclosure, the display panel further includes:

[0014] A second active layer between the first conductive layer and the fourth conductive layer, the second active layer including an eighth active portion, the eighth active portion being configured to form a channel region of the eighth transistor;

[0015] A third conductive layer between the second active layer and the fourth conductive layer, the third conductive layer including a second gate line, a projection of the second gate line on the substrate substrate extending along the first direction and covering a projection of the eighth active portion on the substrate substrate, and a part of the structure of the second gate line being configured to form a top gate of the eighth transistor.

[0016] In an example embodiment of the present disclosure, the projection of the second gate line on the substrate substrate is located between the projection of the first conductive portion on the substrate substrate and the projection of the first gate line on the substrate substrate.

[0017] In an example embodiment of the present disclosure, the display panel further includes:

[0018] The second conductive layer is located between the first conductive layer and the second active layer, and includes: a third gate line, a projection of the third gate line on the substrate substrate extends along the first direction and covers a projection of the eighth active part on the substrate substrate, and part of the structure of the third gate line is used to form a bottom gate of the eighth transistor.

[0019] The third conductive layer further includes a fifth conductive part, the fifth conductive part connects the second gate line, and a projection of the fifth conductive part on the substrate substrate is located on a side of a projection of the second gate line on the substrate substrate facing a projection of the first gate line on the substrate substrate, the fifth conductive part includes a seventh edge away from the second gate line, and an eighth edge connected with the seventh edge, a projection of the seventh edge on the substrate substrate extends along the first direction and intersects with a projection of the eighth edge on the substrate substrate; the second gate line includes a ninth edge and a tenth edge oppositely arranged in a second direction, the second direction intersects with the first direction, a projection of the ninth edge on the substrate substrate and a projection of the tenth edge on the substrate substrate both extend along the first direction, a projection of the ninth edge on the substrate substrate is located on a side of a projection of the tenth edge on the substrate substrate facing a projection of the first gate line on the substrate substrate, and the ninth edge is connected with the eighth edge, an included angle between a projection of the eighth edge on the substrate substrate and a projection of the ninth edge on the substrate substrate is less than 180°; the third gate line includes an eleventh edge and a twelfth edge oppositely arranged in a second direction, a projection of the eleventh edge on the substrate substrate and a projection of the twelfth edge on the substrate substrate both extend along the first direction, a projection of the eleventh edge on the substrate substrate is located on a side of a projection of the twelfth edge on the substrate substrate facing a projection of the first gate line on the substrate substrate; a projection of the first bridge part on the substrate substrate intersects with a projection of the seventh edge on the substrate substrate, a projection of the tenth edge on the substrate substrate, a projection of the eleventh edge on the substrate substrate, and a projection of the twelfth edge on the substrate substrate; a projection of part of the structure of the first bridge part on the substrate substrate overlaps with a projection of the second gate line on the substrate substrate and a projection of the third gate line on the substrate substrate at the same time.

[0020] In an example embodiment of the present disclosure, a distance between a projection of the seventh edge on the substrate substrate and a projection of the eleventh edge on the substrate substrate in the second direction is greater than a distance between a projection of the ninth edge on the substrate substrate and a projection of the eleventh edge on the substrate substrate in the second direction.

[0021] In an example embodiment of the present disclosure, a projection of the seventh edge on the substrate substrate is located on a projection of the first gate line on the substrate substrate.

[0022] In an example embodiment of the present disclosure, the display panel further comprises a light emitting unit, and the pixel driving circuit further comprises a fifth transistor, a sixth transistor and a seventh transistor, a first electrode of the fifth transistor is connected to a power supply line, a second electrode of the fifth transistor is connected to a first electrode of the driving transistor, a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit. The display panel further comprises a first active layer between the substrate substrate and the first conductive layer, the first active layer comprises a first active part, a fifth active part, a sixth active part and a seventh active part, the first active part is used to form a channel region of the first transistor, the fifth active part is used to form a channel region of the fifth transistor, the sixth active part is used to form a channel region of the sixth transistor, and the seventh active part is used to form a channel region of the seventh transistor. The first conductive layer further comprises an enable signal line, a first reset signal line and a second reset signal line, a projection of the enable signal line on the substrate substrate extends along the first direction and covers a projection of the fifth active part on the substrate substrate and a projection of the sixth active part on the substrate substrate, part of a structure of the enable signal line is used to form a gate of the fifth transistor, and another part of the structure of the enable signal line is used to form a gate of the sixth transistor, a projection of the first reset signal line on the substrate substrate extends along the first direction and covers a projection of the first active part on the substrate substrate, and part of a structure of the first reset signal line is used to form a gate of the first transistor, a projection of the second reset signal line on the substrate substrate extends along the first direction and covers a projection of the seventh active part on the substrate substrate, and part of a structure of the second reset signal line is used to form a gate of the seventh transistor, wherein the projection of the enable signal line on the substrate substrate is located on a side of a projection of the first conductive part on the substrate substrate away from a projection of the first gate line on the substrate substrate, the projection of the second reset signal line on the substrate substrate is located on a side of the projection of the enable signal line on the substrate substrate away from the projection of the first conductive part on the substrate substrate, and the projection of the first reset signal line on the substrate substrate is located on a side of the projection of the first gate line on the substrate substrate away from the projection of the first conductive part on the substrate substrate.

[0023] In an example embodiment of the present disclosure, the first direction is a row direction, and the second reset signal line in a neighboring previous row of the pixel driving circuit is multiplexed as the first reset signal line in the current row of the pixel driving circuit.

[0024] In an example embodiment of the present disclosure, the first direction is a row direction, and the third conductive layer further includes: the first initial signal line, a projection of the first initial signal line on the substrate substrate extends along the first direction, and is located on a side of the projection of the first reset signal line on the substrate substrate away from the projection of the first conductive part on the substrate substrate; the projection of the first initial signal line on the substrate substrate in a neighboring next row of the pixel driving circuit is located between the projection of the second reset signal line on the substrate substrate in the current row of the pixel driving circuit and the projection of the first conductive part on the substrate substrate in the current row of the pixel driving circuit, and the projection of the first initial signal line on the substrate substrate in the neighboring next row of the pixel driving circuit at least partially overlaps with the projection of the enable signal line on the substrate substrate in the current row of the pixel driving circuit.

[0025] In an example embodiment of the present disclosure, the first direction is a row direction, and the fourth conductive layer further includes: the second initial signal line, a projection of the second initial signal line on the substrate substrate extends along the first direction, and is located on a side of the projection of the second reset signal line on the substrate substrate away from the projection of the first conductive part on the substrate substrate; the projection of the second initial signal line on the substrate substrate in a neighboring previous row of the pixel driving circuit is located between the projection of the first reset signal line on the substrate substrate in the current row of the pixel driving circuit and the projection of the first gate line on the substrate substrate in the current row of the pixel driving circuit.

[0026] In an example embodiment of the present disclosure, the display panel further comprises: a second active layer, a fifth conductive layer, the second active layer is located between the first conductive layer and the fourth conductive layer, the second active layer comprises an eighth active part, and the eighth active part is used to form a channel region of the eighth transistor; the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate, and the fifth conductive layer comprises a power supply line, the power supply line comprises: a first extension part, a second extension part, and a third extension part, the second extension part is connected between the first extension part and the third extension part; a size of a projection of the second extension part on the substrate in the first direction is greater than a size of a projection of the first extension part on the substrate in the first direction, and a size of a projection of the second extension part on the substrate in the first direction is greater than a size of a projection of the third extension part on the substrate in the first direction; the projection of the second extension part on the substrate covers a projection of the eighth active part on the substrate and a projection of the first bridge part on the substrate.

[0027] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a capacitor, a first electrode of the capacitor is connected to a gate of the driving transistor, and a second electrode of the capacitor is connected to a power supply line; the power supply line comprises: a first extension part, a second extension part, and a third extension part, the second extension part is connected between the first extension part and the third extension part; the first direction is a row direction, the display panel comprises a plurality of repeating units distributed along a row-column direction, each of the repeating units comprises two pixel driving circuits, the two pixel driving circuits comprise a first pixel driving circuit and a second pixel driving circuit distributed along the row direction, and the first pixel driving circuit and the second pixel driving circuit are mirror-symmetrically arranged; one of the power supply lines is arranged corresponding to each column of the pixel driving circuits, and the second extension parts of the two power supply lines in the same repeating unit are connected; the display panel further comprises: a second conductive layer, the second conductive layer is located between the first conductive layer and the fourth conductive layer, and the second conductive layer comprises: a fourth conductive part, a projection of the fourth conductive part on the substrate and a projection of the first conductive part on the substrate at least partially overlap, and the fourth conductive part is used to form the second electrode of the capacitor; in the repeating units adjacent in the row direction, adjacent fourth conductive parts are connected.

[0028] In an example embodiment of the present disclosure, the second conductive layer further comprises a first connecting portion, in the adjacent repeating units in the row direction, the adjacent fourth conductive portions are connected by the first connecting portion; the pixel driving circuit further comprises a fifth transistor, a first electrode of the fifth transistor is connected to the power supply line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor; the display panel further comprises a first active layer between the substrate and the first conductive layer, the first active layer comprises a third active portion, a fifth active portion, and a ninth active portion, the third active portion is used to form a channel region of the driving transistor, the fifth active portion is used to form a channel region of the fifth transistor, and the ninth active portion is connected to one side of the fifth active portion away from the third active portion and is connected between two fifth active portions in the adjacent repeating units in the row direction. The fourth conductive layer further comprises a second bridge portion, the second bridge portion is connected to the ninth active portion and the first connecting portion by vias, and the second bridge portion is connected to the power supply line by a via.

[0029] In an example embodiment of the present disclosure, the first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors, and the eighth transistor is an N-type transistor.

[0030] According to an aspect of the present disclosure, a display device is provided, which comprises the display panel described above.

[0031] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0033] Figure 1 FIG. 1 is a schematic circuit structure diagram of a pixel driving circuit in an example embodiment of the display panel of the present disclosure;

[0034] Figure 2 FIG. 2 is a functional block diagram of an example embodiment of the display panel of the present disclosure;

[0035] Figure 3 FIG. 3 is a timing diagram of signals on the output end of a partial shift register unit in an example embodiment of the display panel of the present disclosure; Figure 2

[0036] ​Figure 4 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0037] Figure 5 for Figure 4 Structural layout of the intermediate light-shielding layer;

[0038] Figure 6 for Figure 4 Structural layout of the first active layer;

[0039] Figure 7 for Figure 4 Structural layout of the first conductive layer;

[0040] Figure 8 for Figure 4 Structural layout of the second conductive layer;

[0041] Figure 9 for Figure 4 Structural layout of the second active layer;

[0042] Figure 10 for Figure 4 Structural layout of the third conductive layer;

[0043] Figure 11 for Figure 4 Structural layout of the fourth conductive layer;

[0044] Figure 12 for Figure 4 The structural layout of the fifth conductive layer;

[0045] Figure 13 for Figure 4 Structural layout of the middle electrode layer;

[0046] Figure 14 for Figure 4 Structural layout of the intermediate light-shielding layer and the first active layer;

[0047] Figure 15 for Figure 4 Structural layout of the intermediate light-shielding layer, the first active layer, and the first conductive layer;

[0048] Figure 16 for Figure 4 Structural layout of the intermediate light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer;

[0049] Figure 17 for Figure 4 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer;

[0050] Figure 18 for Figure 4The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer;

[0051] Figure 19 for Figure 4 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer;

[0052] Figure 20 for Figure 4 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer;

[0053] Figure 21 for Figure 4 The diagram shows a partial sectional view of the display panel cut along the dashed line AA. Detailed Implementation

[0054] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0055] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0056] like Figure 1As shown, it is a circuit structure schematic diagram of a pixel driving circuit in an exemplary embodiment of the display panel. The pixel driving circuit can include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. The first electrode of the eighth transistor T8 is connected to the gate of the driving transistor T3, and the gate is connected to a second gate driving signal end G2. The first electrode of the first transistor T1 is connected to a first initial signal end Vinit1, the second electrode is connected to the second electrode of the eighth transistor T8, and the gate is connected to a first reset signal end Re1. The first electrode of the second transistor T2 is connected to the second electrode of the eighth transistor T8, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to a first gate driving signal end G1. The first electrode of the fourth transistor T4 is connected to a data signal end Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate driving signal end G1. The first electrode of the fifth transistor T5 is connected to a first power supply end VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to an enable signal end EM. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the gate is connected to the enable signal end EM. The first electrode of the seventh transistor T7 is connected to a second initial signal end Vinit2, the second electrode is connected to the second electrode of the sixth transistor T6, and the gate is connected to a second reset signal end Re2. The first electrode of the capacitor is connected to the gate of the driving transistor T3, and the second electrode is connected to the first power supply end VDD. The pixel driving circuit can be used to drive the light emitting unit OLED to emit light. The first electrode of the light emitting unit OLED is connected to the second electrode of the sixth transistor T6, and the second electrode of the light emitting unit OLED is connected to a second power supply end VSS. The first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors, and the eighth transistor T8 can be an N-type transistor.

[0057] As Figure 2As shown, it is a functional block diagram of an exemplary embodiment of the display panel of the present disclosure. The display panel includes a plurality of pixel driving circuits arranged in a row-column direction, wherein ROW1 represents the first row of pixel driving circuits, ROW2 represents the second row of pixel driving circuits, and ROWn represents the nth row of pixel driving circuits, wherein n is a positive integer greater than 4. The display panel can also include a first gate driving circuit GOAP, a second gate driving circuit GOAN, and a third gate driving circuit GOAEM. The first gate driving circuit GOAP can include a plurality of cascaded first shift register units Re1…Re(n+16), which sequentially output shift signals. The output terminal of the first stage first shift register unit Re1 is connected to the first reset signal terminal of the first row of pixel driving circuits Row1, the second stage first shift register unit Re2 is connected to the first reset signal terminal in the second row of pixel driving circuits Row2, and so on, and the output terminal of the nth stage first shift register unit Ren is connected to the first reset signal terminal of the nth row of pixel driving circuits. In addition, the output terminal of the (n+10)th stage first shift register unit Re(n+10) can also be connected to the first gate driving signal terminal in the nth-4 row of pixel driving circuits. The second gate driving circuit GOAN includes a plurality of cascaded second shift register units GN1&2, GN3&4…GNn&(n+1), GN(n+2)&(n+3). Among them, the first stage second shift register unit GN1&2 is connected to the second gate driving signal terminal G2 in the first row of pixel driving circuits Row1 and the second row of pixel driving circuits Row2, and so on, and the (n+1) / 2 stage second shift register unit GNn&(n+1) is connected to the second gate driving signal terminal in the nth row of pixel driving circuits Rown and the nth+1 row of pixel driving circuits Row(n+1). The third gate driving circuit GOAEM can include a plurality of third shift register units EM1&2, EM3&4, EMn&(n+1), Em(n+2)&(n+3) cascaded in turn, wherein the first stage third shift register unit EM1&2 is connected to the enable signal terminal EM in the first row of pixel driving circuits Row1 and the second row of pixel driving circuits Row2, and so on, and the (n+1) / 2 stage third shift register unit EMn&(n+1) is connected to the enable signal terminal in the nth row of pixel driving circuits Rown and the nth+1 row of pixel driving circuits Row(n+1). In addition, in the display panel, the first reset signal terminal in the current row of pixel driving circuits and the second reset signal terminal in the adjacent previous row of pixel driving circuits can be connected to the output terminal of the same stage first shift register unit.The display panel can be equipped with two sets of first gate driving circuits (GOAP), two sets of second gate driving circuits (GOAN), and two sets of third gate driving circuits (GOAEM). The two sets of first gate driving circuits (GOAP) are respectively located on both sides of the display panel in the horizontal direction to drive corresponding gate lines. Similarly, the two sets of second gate driving circuits (GOAN) are respectively located on both sides of the display panel in the horizontal direction to drive corresponding gate lines. Finally, the two sets of third gate driving circuits (GOAEM) are respectively located on both sides of the display panel in the horizontal direction to drive corresponding gate lines.

[0058] like Figure 3 As shown, Figure 2 The timing diagram shows the signals at the output terminals of the shift register units in the middle section. Here, Ren represents the timing diagram of the signals at the output terminal of the first shift register unit (Ren) of the nth stage; Re(n+1) represents the timing diagram of the signals at the output terminal of the first shift register unit (Re(n+1)) of the (n+1)th stage; Re(n+14) represents the timing diagram of the signals at the output terminal of the first shift register unit (Re(n+14)) of the (n+14)th stage; GNn&(n+1) represents the timing diagram of the signals at the output terminal of the second shift register unit (GNn&(n+1)) of the (n+1) / 2th stage; and EMn&(n+1) represents the timing diagram of the signals at the output terminal of the shift register unit (EMn&(n+1)). The first line represents the timing diagram of the signal at the output terminal of the third shift register unit EMn&(n+1) of the (n+1) / 2 stage. The second line represents the timing diagram of the signal at the output terminal of the second shift register unit (n+2)&(n+3) of the (n+3) / 2 stage. The third line represents the timing diagram of the signal at the output terminal of the third shift register unit EM(n+2)&(n+3) of the (n+3) / 2 stage.

[0059] The driving method of the pixel driving circuit in the present disclosure can include a first reset stage, a second reset stage, a data writing stage, and a light emitting stage. Taking the nth row of pixel driving circuit as an example, in the first reset stage t1 of the nth row of pixel driving circuit, the first shift register unit Ren inputs a low-level signal to the first reset signal end of the nth row of pixel driving circuit, the second shift register unit GNn&(n+1) inputs a high-level signal to the second gate driving signal end of the nth row of pixel driving circuit, the first transistor T1 and the eighth transistor T8 are turned on, and the first initial signal end Vinit1 inputs the first initial signal to the gate of the driving transistor T3. In the second reset stage t2, the first shift register unit Re(n+1) inputs a low-level signal to the second reset signal end of the nth row of pixel driving circuit, the second shift register unit GNn&(n+1) inputs a high-level signal to the second gate driving signal end of the nth row of pixel driving circuit, the seventh transistor T7 and the eighth transistor T8 are turned on, and the second initial signal end Vinit2 inputs the first initial signal to the second electrode of the seventh transistor T7. In the data writing stage t3, the first shift register unit Re(n+14) inputs a low-level signal to the first gate driving signal end of the nth row of pixel driving circuit, the second shift register unit GNn&(n+1) inputs a high-level signal to the second gate driving signal end of the nth row of pixel driving circuit, the eighth transistor T8, the fourth transistor T4, and the second transistor T2 are turned on, and the data signal end Da outputs the data signal to write the voltage Vdata+Vth to the gate of the driving transistor, wherein Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. In the light emitting stage t4, the third shift register unit EMn&(n+1) inputs a low-level signal to the enable signal end of the nth row of pixel driving circuit, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 drives the light emitting unit OLED to emit light under the voltage Vdata+Vth at the gate of the driving transistor. According to the output current formula I=(μWCox / 2L)(Vgs-Vth) of the driving transistor 2 , wherein μ is the carrier mobility, Cox is the unit area gate capacitance, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the driving transistor gate-source voltage difference, and Vth is the driving transistor threshold voltage. The output current I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) of the driving transistor in the pixel driving circuit in the present disclosure 2 . The pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current.

[0060] The present exemplary embodiments also provide a display panel, which can include a substrate, a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer, which are sequentially stacked. As shown in Figures 4-20 , Figure 4 The structure layout in an exemplary embodiment of the display panel of the present disclosure is shown in Figure 5 , Figure 4 The structure layout of the light shielding layer in the exemplary embodiment is shown in Figure 6 , Figure 4 The structure layout of the first active layer in the exemplary embodiment is shown in Figure 7 , Figure 4 The structure layout of the first conductive layer in the exemplary embodiment is shown in Figure 8 , Figure 4 The structure layout of the second conductive layer in the exemplary embodiment is shown in Figure 9 , Figure 4 The structure layout of the second active layer in the exemplary embodiment is shown in Figure 10 , Figure 4 The structure layout of the third conductive layer in the exemplary embodiment is shown in Figure 11 , Figure 4 The structure layout of the fourth conductive layer in the exemplary embodiment is shown in Figure 12 , Figure 4 The structure layout of the fifth conductive layer in the exemplary embodiment is shown in Figure 13 , Figure 4 The structure layout of the electrode layer in the exemplary embodiment is shown in Figure 14 , Figure 4 The structure layout of the light shielding layer and the first active layer in the exemplary embodiment is shown in Figure 15 , Figure 4 The structure layout of the light shielding layer, the first active layer, and the first conductive layer in the exemplary embodiment is shown in Figure 16 , Figure 4 The structure layout of the light shielding layer, the first active layer, the first conductive layer, and the second conductive layer in the exemplary embodiment is shown in Figure 17 , Figure 4 The structure layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in the exemplary embodiment is shown in Figure 18 , Figure 4 The structure layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in the exemplary embodiment is shown in Figure 19 , Figure 4 The structure layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in the exemplary embodiment is shown in Figure 20 , Figure 4 The structure layout of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in the exemplary embodiment is shown in. The display panel can include a plurality of pixel driving circuits as shown in Figure 1 , Figure 20As shown, the plurality of pixel driving circuits can include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 can be mirror-symmetrically arranged with respect to a mirror symmetry plane BB. The mirror symmetry plane BB can be perpendicular to the substrate. The first pixel driving circuit P1 and the second pixel driving circuit P2 can be symmetrically arranged with respect to the intersection line of the mirror symmetry plane BB and the substrate as the axis of symmetry. The first pixel driving circuit P1 and the second pixel driving circuit P2 can form a repeating unit, and the display panel can include a plurality of repeating units arranged in an array in the first direction X and the second direction Y. The first direction X can be the row direction, and the second direction Y can be the column direction.

[0061] As shown in FIG. 14, the light shielding layer can include a plurality of light shielding portions 71, and the adjacent light shielding portions 71 can be connected to each other. Figure 4 5 As shown in FIG. 14, the light shielding layer can include a plurality of light shielding portions 71, and the adjacent light shielding portions 71 can be connected to each other.

[0062] As shown in FIG. 14, the light shielding layer can include a plurality of light shielding portions 71, and the adjacent light shielding portions 71 can be connected to each other. Figure 4 6 ​​As shown in FIG. 15, the first active layer can include a first active part 61, a second active part 62, a third active part 63, a fourth active part 64, a fifth active part 65, a sixth active part 66, and a seventh active part 67. The first active part 61 is configured to form a channel region of the first transistor T1, the second active part 62 is configured to form a channel region of the second transistor T2, the third active part 63 is configured to form a channel region of the driving transistor T3, the fourth active part 64 is configured to form a channel region of the fourth transistor T4, the fifth active part 65 is configured to form a channel region of the fifth transistor T5, the sixth active part 66 is configured to form a channel region of the sixth transistor T6, and the seventh active part 67 is configured to form a channel region of the seventh transistor T7. In addition, the first active layer can further include a ninth active part 69, a tenth active part 610, an eleventh active part 611, a twelfth active part 612, a thirteenth active part 613, and a fourteenth active part 614. The thirteenth active part 613 is connected to one end of the seventh active part 67 away from the sixth active part 66, and in the same repeating unit, two seventh active parts 67 are connected through the thirteenth active part 613. The tenth active part 610 is connected between the sixth active part 66 and the seventh active part 67. The eleventh active part 611 is connected to one end of the first active part 61 away from the second active part 62. The twelfth active part 612 is connected to one end of the fourth active part 64 away from the third active part 63. The ninth active part 69 is connected to one end of the fifth active part 65 away from the third active part 63, and in the repeating unit adjacent in the first direction, two fifth active parts 65 are connected through the ninth active part 69. The fourteenth active part 614 is connected between the first active part 61 and the second active part 62. The light-shielding part 71 can cover the third active part 63 in the orthographic projection on the substrate, and the light-shielding part 71 can shield the third active part 63 to reduce the influence of light on the driving characteristics of the driving transistor T3. The first active layer can be formed of a polysilicon material, and the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon thin film transistors.

[0063] As Figure 4 、 7The first conductive layer can include a first reset signal line Re1, a first gate line G1, an enable signal line EM, a second reset signal line Re2, a first conductive portion 11, and a second conductive portion 12, as shown in FIG. 15. The orthogonal projection of the first reset signal line Re1 on the substrate, the orthogonal projection of the first gate line G1 on the substrate, the orthogonal projection of the enable signal line EM on the substrate, and the orthogonal projection of the second reset signal line Re2 on the substrate can extend along the first direction X. In the present exemplary embodiment, the orthogonal projection of a certain structure on the substrate extends along a certain direction, which can be understood as that the orthogonal projection of the structure on the substrate extends linearly or bends along the direction. The orthogonal projection of the first reset signal line Re1 on the substrate can cover the orthogonal projection of the first active portion 61 on the substrate, and part of the structure of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The first reset signal line Re1 can be used to provide the first reset signal end of the pixel driving circuit, as shown in FIG. 15. Figure 1 The orthogonal projection of the second reset signal line Re2 on the substrate can cover the orthogonal projection of the seventh active portion 67 on the substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The second reset signal line Re2 can be used to provide the second reset signal end of the pixel driving circuit, as shown in FIG. 15. Figure 1 The orthogonal projection of the first gate line G1 on the substrate can cover the orthogonal projection of the second active portion 62 on the substrate and the orthogonal projection of the fourth active portion 64 on the substrate, and part of the structure of the first gate line G1 can be used to form the gate of the second transistor T2. Another part of the structure of the first gate line G1 can be used to form the gate of the fourth transistor T4. The first gate line G1 can be used to provide the first gate driving signal end of the pixel driving circuit, as shown in FIG. 15. Figure 1 The orthogonal projection of the enable signal line EM on the substrate can cover the orthogonal projection of the fifth active portion 65 on the substrate and the orthogonal projection of the sixth active portion 66 on the substrate, and part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5. Another part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6. The enable signal line EM can be used to provide the enable signal end of the pixel driving circuit, as shown in FIG. 15. Figure 1The enable signal end in the pixel driving circuit. The first conductive part 11 can cover the orthographic projection of the third active part 63 on the substrate, and the first conductive part 11 can be used to form the gate of the driving transistor T3, and in addition, the first conductive part 11 can also be used to form the first electrode of the capacitor C. In the present exemplary embodiment, the light shielding layer can be formed of a conductive material, and the light shielding layer can be connected to a stable voltage source, so that the light shielding layer can shield the noise of the first conductive part 11 caused by external signals. In the present exemplary embodiment, the orthographic projection of the enable signal line EM on the substrate can be located on the side of the orthographic projection of the first conductive part 11 on the substrate away from the orthographic projection of the first gate line G1 on the substrate; the orthographic projection of the second reset signal line Re2 on the substrate is located on the side of the orthographic projection of the enable signal line EM on the substrate away from the orthographic projection of the first conductive part 11 on the substrate. The orthographic projection of the first reset signal line Re1 on the substrate is located on the side of the orthographic projection of the first gate line G1 on the substrate away from the orthographic projection of the first conductive part 11 on the substrate. The second reset signal line Re2 in the pixel driving circuit of the adjacent upper row can be multiplexed as the first reset signal line Re1 in the pixel driving circuit of the present row. This arrangement can reduce the size of the pixel driving circuit in the second direction Y. In addition, the display panel can use the first conductive layer as a mask to perform conductorization processing on the first active layer, that is, the region of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the region of the first active layer not covered by the first conductive layer forms a conductor structure.

[0064] As Figure 4 , 8 , 16, the second conductive layer can include a third gate line 2G2, a third conductive part 23, a fourth conductive part 24, and a first connecting part 21. The orthographic projection of the fourth conductive part 24 on the substrate can at least partially overlap the orthographic projection of the first conductive part 11 on the substrate, and the fourth conductive part 24 can be used to form the second electrode of the capacitor C. In the adjacent repeating unit in the first direction X, the adjacent fourth conductive parts 24 are connected by the first connecting part 21. The orthographic projection of the third conductive part 23 on the substrate can at least partially overlap the orthographic projection of the second conductive part 12 on the substrate.

[0065] As Figure 4 , 9As shown in Figure 17, the second active layer may include an eighth active portion 88, a fifteenth active portion 815, and a sixteenth active portion 816. The eighth active portion 88 is connected between the fifteenth active portion 815 and the sixteenth active portion 816, and is used to form the channel region of the eighth transistor. The orthogonal projection of the third gate line 2G2 on the substrate can cover the orthogonal projection of the eighth active portion 88 on the substrate. A portion of the structure of the third gate line 2G2 can be used to form the bottom gate of the eighth transistor T8, and the third gate line 2G2 can be used to provide... Figure 1 The second gate drive signal terminal in the transistor. The second active layer can be formed of indium gallium zinc oxide, and correspondingly, the eighth transistor T8 can be an N-type metal-oxide thin-film transistor.

[0066] like Figure 4 , 10 As shown in Figure 18, the third conductive layer may include: a second gate line 3G2 and a first initial signal line Vinit1. The orthographic projections of the second gate line 3G2 and the first initial signal line Vinit1 on the substrate can both extend along the first direction X. The orthographic projection of the second gate line 3G2 on the substrate can cover the orthographic projection of the eighth active portion 88 on the substrate. A portion of the structure of the second gate line 3G2 can be used to form the top gate of the eighth transistor T8. The second gate line 3G2 is used to provide... Figure 1 The second gate drive signal terminal in the circuit. The orthographic projection of the second gate line 3G2 on the substrate can be located between the orthographic projection of the first conductive part 11 on the substrate and the orthographic projection of the first gate line G1 on the substrate. The second gate line 3G2 and the third gate line 2G2 in the same row pixel drive circuit can be connected by a via, and the via connected between the second gate line 3G2 and the third gate line 2G2 can be located in the edge trace area outside the display area of ​​the display panel. The first initial signal line Vinit1 can be used to provide Figure 1The first initial signal terminal in the image. In this exemplary embodiment, the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit on the substrate can be located between the orthographic projection of the second reset signal line Re2 in the current row pixel driving circuit on the substrate and the orthographic projection of the first conductive portion 11 in the current row pixel driving circuit on the substrate, and the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit on the substrate can at least partially overlap with the orthographic projection of the enable signal line EM in the current row pixel driving circuit on the substrate. This arrangement can further reduce the size of the pixel driving circuit in the second direction Y. In addition, the display panel can use the third conductive layer as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0067] like Figure 4 , 11 As shown in Figure 19, the fourth conductive layer may include a second initial signal line Vinit2, a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, and a sixth bridging portion 46. The orthographic projection of the second initial signal line Vinit2 onto the substrate can extend along the first direction X. The second initial signal line Vinit2 can be used to provide... Figure 1The second initial signal line Vinit2 can be connected to the thirteenth active part 613 through a via hole H to connect the second initial signal end and the first electrode of the seventh transistor T7. Wherein, the black square represents the position of the via hole. The first bridge part 41 can be connected to the first conductive part 11 and the sixteenth active part 816 through a via hole, to connect the gate of the driving transistor T3 and the first electrode of the eighth transistor T8, wherein the fourth conductive part 24 is provided with an opening 241, and the orthographic projection of the via hole connecting the first bridge part 41 and the first conductive part 11 on the substrate is within the orthographic projection of the opening 241 on the substrate, so as to avoid the connection between the via hole and the fourth conductive part 24. The second bridge part 42 can be connected to the first connecting part 21 and the ninth active part 69 through a via hole, to connect the second electrode of the capacitor and the first electrode of the fifth transistor T5. Wherein, the adjacent pixel driving circuits in the adjacent repeating units in the first direction X can share the same second bridge part 42. The third bridge part 43 can be connected to the eleventh active part 611 and the first initial signal line Vinit1 through a via hole, to connect the first initial signal end and the first electrode of the first transistor. The fourth bridge part 44 is connected to the fifteenth active part 815 and the fourteenth active part 614 through a via hole, to connect the second electrode of the eighth transistor and the second electrode of the first transistor, the first electrode of the second transistor. The fifth bridge part 45 can be connected to the tenth active part 610 through a via hole, to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth bridge part 46 can be connected to the twelfth active part 612 through a via hole, to connect the first electrode of the fourth transistor.

[0068] In the present exemplary embodiment, due to the thickness of the second conductive layer and the third conductive layer, the insulating layer on the side away from the substrate of the third gate line 2G2 will be raised at the local position of the third gate line 2G2, and the insulating layer on the side away from the substrate of the second gate line 3G2 will be raised at the local position of the second gate line 3G2. A higher protrusion will appear at the overlapping position of the orthographic projection of the third gate line 2G2 on the substrate and the orthographic projection of the second gate line 3G2 on the substrate. As shown in FIG. 6, the orthographic projection of the part of the first bridge part 41 on the substrate overlaps with the orthographic projection of the second gate line 3G2 on the substrate and the orthographic projection of the third gate line 2G2 on the substrate, i.e., the part of the first bridge part 41 will have a higher height, thereby easily causing the first bridge part 41 to break. Figure 19 Figure 4 10 ​​As shown in Figures 11, 18, and 19, the third conductive layer may further include a fifth conductive portion 35. The fifth conductive portion 35 is connected to the second gate line 3G2, and its orthographic projection on the substrate is located on the side where the orthographic projection of the second gate line 3G2 on the substrate faces the orthographic projection of the first gate line G1 on the substrate. The fifth conductive portion 35 includes a seventh edge 357 away from the second gate line 3G2, and an eighth edge 358 connected to the seventh edge 357. The orthographic projection of the seventh edge 357 on the substrate extends along the first direction X. The second gate line 3G2 includes a ninth edge 3G9 and a tenth edge 3G10 disposed opposite each other in the second direction Y. The orthographic projections of the ninth edge 3G9 and the tenth edge 3G10 on the substrate both extend along the first direction X. The orthographic projection of the ninth edge 3G9 on the substrate is located on the side where the orthographic projection of the tenth edge 3G10 on the substrate faces the orthographic projection of the first gate line G1 on the substrate. The ninth edge 3G9 is connected to the eighth edge 358. The angle between the orthographic projections of the eighth edge 358 and the ninth edge 3G9 on the substrate is less than 180°; for example, the angle between the orthographic projections of the eighth edge 358 and the ninth edge 3G9 on the substrate is 90°. Figure 8 , 16 As shown, the third gate line 2G2 includes an eleventh edge 2G11 and a twelfth edge 2G12 disposed opposite each other in the second direction Y. The orthographic projections of the eleventh edge 2G11 and the twelfth edge 2G12 on the substrate both extend along the first direction X. The orthographic projection of the eleventh edge 2G11 on the substrate is located on the side where the orthographic projection of the twelfth edge 2G12 on the substrate faces the orthographic projection of the first gate line G1 on the substrate. Wherein, as... Figure 19 As shown, the orthographic projection of the first bridging portion 41 on the substrate intersects with the orthographic projections of the seventh edge 357, the tenth edge 3G10, the eleventh edge 2G11, and the twelfth edge 2G12 on the substrate. Figure 18As shown in FIG. 7, the distance between the orthogonal projection of the seventh edge 357 on the substrate and the orthogonal projection of the eleventh edge 2G11 on the substrate in the second direction Y is greater than the distance between the orthogonal projection of the ninth edge 3G9 on the substrate and the orthogonal projection of the eleventh edge 2G11 on the substrate in the second direction Y. The present exemplary embodiment adds the fifth conductive part 35, so that the seventh edge 357 and the eleventh edge 2G11 have a greater distance in the second direction Y, so that the seventh edge 357 and the eleventh edge 2G11 have a smaller slope, thereby reducing the risk of breaking the first bridge part 41.

[0069] In the present exemplary embodiment, as shown in FIG. 7, the orthogonal projection of the seventh edge 357 on the substrate can be located on the orthogonal projection of the first gate line G1 on the substrate. This arrangement can reduce the risk of breaking the first bridge part 41 by increasing the height of the position of the seventh edge 357. Figure 18

[0070] In the present exemplary embodiment, as shown in FIG. 7, the orthogonal projection of the second initial signal line Vinit2 in the adjacent previous row of pixel driving circuits on the substrate is located between the orthogonal projection of the first reset signal line Re1 on the substrate in the present row of pixel driving circuits and the orthogonal projection of the first gate line G1 on the substrate in the present row of pixel driving circuits. This arrangement can reduce the size of the pixel driving circuit in the second direction Y. Figure 19

[0071] As shown in FIG. 7, Figure 4 , 12 ​​​As shown in FIG. 20, the fifth conductive layer can include a data line Da, a power line VDD, and a seventh bridge portion 57. The data line Da and the power line VDD can each have a projection on the substrate substrate in the second direction Y. The data line Da is configured to provide a data signal terminal, and the power line VDD is configured to provide a first power terminal. The data line Da can be connected to the first electrode of the fourth transistor T4 and the data signal terminal through a via hole and the sixth bridge portion 46. The power terminal VDD can be connected to the first power terminal and the first electrode of the fifth transistor T5 through a via hole and the second bridge portion 42. The seventh bridge portion 57 can be connected to the second electrode of the sixth transistor T6 through a via hole and the fifth bridge portion 45. The power line VDD can include a first extension VDD1, a second extension VDD2, and a third extension VDD3. The second extension VDD2 is connected between the first extension VDD1 and the third extension VDD3. The size of the projection of the second extension VDD2 on the substrate substrate in the first direction X can be greater than the size of the projection of the first extension VDD1 on the substrate substrate in the first direction X. The size of the projection of the second extension VDD2 on the substrate substrate in the first direction X can be greater than the size of the projection of the third extension VDD3 on the substrate substrate in the first direction X. The projection of the second extension VDD2 on the substrate substrate can cover the projection of the eighth active portion 88 on the substrate substrate. The second extension VDD2 can reduce the influence of light on the characteristics of the eighth transistor T8. The projection of the second extension VDD2 on the substrate substrate can also cover the projection of the first bridge portion 41 on the substrate substrate. The second extension VDD2 can stabilize and shield the first bridge portion 41 to reduce the voltage fluctuation of the gate of the driving transistor T3 in the light-emitting stage. In the same repeating unit, the second extensions VDD2 of the two power lines VDD can be connected to each other, so that the power line VDD and the fourth conductive portion 24 can form a grid structure. The power line of the grid structure can reduce the voltage drop of the power signal thereon.

[0072] As Figure 4 、 13As shown, the electrode layer can include a plurality of electrode portions: R electrode portions R, G electrode portions G, and B electrode portions B. Each electrode portion can be connected to the second electrode of the sixth transistor through the via hole and the seventh bridge portion 57. In the plurality of electrode portions connected to the pixel driving circuit in the same row, the R electrode portions, the G electrode portions, and the B electrode portions are alternately arranged in the row direction. In the two adjacent pixel driving circuits in the column direction: the plurality of R electrode portions and the plurality of B electrode portions are connected to one of the pixel driving circuits, and the R electrode portions and the B electrode portions connected to the same pixel driving circuit are alternately arranged in the column direction; and the plurality of G electrode portions are connected to the other pixel driving circuit. The minimum distance S1 of the orthogonal projection of the two G electrode portions connected to the adjacent pixel driving circuit rows and connected to the same pixel driving circuit column on the substrate in the column direction is greater than the size S2 of the orthogonal projection of the R electrode portion on the substrate in the column direction or greater than the size S3 of the orthogonal projection of the B electrode portion on the substrate in the column direction. The orthogonal projection of the R electrode portion on the substrate and the orthogonal projection of the opening corresponding to the R electrode portion on the pixel definition layer on the substrate coincide with each other, the orthogonal projection of the G electrode portion on the substrate and the orthogonal projection of the opening corresponding to the G electrode portion on the pixel definition layer on the substrate coincide with each other, and the orthogonal projection of the B electrode portion on the substrate and the orthogonal projection of the opening corresponding to the B electrode portion on the pixel definition layer on the substrate coincide with each other.

[0073] In the present example embodiment, as shown in Figure 4 , 8 , the first bridge portion 41 can also be connected to the third conductive portion 23 through the via hole. As shown in Figure 3 , after the data writing stage of the pixel driving circuit ends, the first gate line G1 pulls up the potential of the second conductive portion 12, and under the parallel plate capacitive coupling effect formed by the third conductive portion and the second conductive portion 12, the third conductive portion 23 is pulled up, that is, the gate voltage of the driving transistor is pulled up, so that the display panel can realize black screen display with lower voltage data signal.

[0074] In the present example embodiment, as shown in Figure 16As shown, the orthographic projection of the second conductive part 12 on the substrate can be located on the side of the orthographic projection of the first gate line G1 on the substrate away from the orthographic projection of the first conductive part 11 on the substrate; the orthographic projection of the third conductive part 23 on the substrate can be located on the side of the orthographic projection of the first gate line G1 on the substrate away from the orthographic projection of the first conductive part 11 on the substrate. In the first direction X, the orthographic projection of the second conductive part 12 on the substrate and the orthographic projection of the third conductive part 23 on the substrate can both be located between the orthographic projection of the second active part 62 on the substrate and the orthographic projection of the fourth active part 64 on the substrate. The distance S4 between the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the fourth active part 64 on the substrate in the first direction X can be greater than the distance S5 between the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the second active part 62 on the substrate in the first direction X. Wherein, the distance between the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the fourth active part 64 on the substrate in the first direction X can refer to the distance between the adjacent edges of the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the fourth active part 64 on the substrate in the first direction X, and the distance between the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the second active part 62 on the substrate in the first direction X can refer to the distance between the adjacent edges of the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the second active part 62 on the substrate in the first direction X. Since the fourth active part 64 needs to be connected to the data line Da, the third conductive part 23 is arranged on the side away from the fourth active part 64 in the present exemplary embodiment, so that the noise influence of the data line Da or the equipotential point of the data line Da on the gate of the driving transistor can be reduced.

[0075] In the present exemplary embodiment, as Figure 7 , 8As shown in FIGS. 16, the third conductive part 23 can include a first edge 231 and a second edge 232 oppositely arranged in the first direction X, and a third edge 233 and a fourth edge 234 oppositely arranged in the second direction Y; the second conductive part 12 includes a fifth edge 125 and a sixth edge 126 oppositely arranged in the first direction X. In the first direction X, the orthogonal projection of the fifth edge 125 on the substrate substrate is between the orthogonal projection of the first edge 231 on the substrate substrate and the orthogonal projection of the second edge 232 on the substrate substrate; the orthogonal projection of the sixth edge 126 on the substrate substrate is between the orthogonal projection of the first edge 231 on the substrate substrate and the orthogonal projection of the second edge 232 on the substrate substrate; the orthogonal projection of the third edge 233 on the substrate substrate and the orthogonal projection of the fourth edge 234 on the substrate substrate both intersect with the orthogonal projection of the second conductive part 12 on the substrate substrate.

[0076] It should be understood that the second conductive part and the third conductive part can also be arranged on other conductive layers, and the second conductive part and the third conductive part can be arranged on any conductive layer between the second conductive layer and the fourth conductive layer. For example, the third conductive part can also be arranged on the second active layer or the third conductive layer. Compared with arranging the third conductive part on the second active layer, arranging the third conductive part on the second conductive layer in the present example embodiment can reduce the distance between the second conductive part and the third conductive part, thereby increasing the capacitance of the parasitic capacitor formed by the second conductive part and the third conductive part, improving the pull-up effect of the first gate line G1 on the gate of the driving transistor T3, and further reducing the data signal voltage required for the black picture of the display panel. In addition, arranging the third conductive part on the second conductive layer far from the layer level of the data line Da can reduce the noise influence of the data line on the gate of the driving transistor T3. As shown in the following table, Table 1 is the simulation data of the display panel when the third conductive part is arranged on the second active layer. Table 2 is the simulation data of the display panel when the third conductive part is arranged on the second conductive layer. Among them, Cx1 represents the parasitic capacitance between the first gate line equipotential structure and the driving transistor gate equipotential structure, Cx2 represents the parasitic capacitance between the data line equipotential structure and the driving transistor gate equipotential structure. Normal represents the normal driving mode of the display panel, HBM represents the high brightness driving mode of the display panel, Vdata@L0 represents the data signal voltage required for each sub-pixel in the black picture state, R represents the red sub-pixel, G represents the green sub-pixel, and B represents the blue sub-pixel. V_Crosstalk represents the ratio of the variable of the driving transistor output current under the noise interference of the data line to the ideal driving transistor output current.

[0077] Table 1

[0078]

[0079] Table 2

[0080]

[0081] The table above further verifies that placing the third conductive part on the second conductive layer can increase the capacitance of the parasitic capacitance formed by the second and third conductive parts, thereby reducing the data signal voltage required for a black screen on the display panel. Furthermore, the table also verifies that placing the third conductive part on the second conductive layer, which is farther from the layer containing the data line Da, can reduce the noise impact of the data line on the gate of the driving transistor T3.

[0082] It should be understood that, in other exemplary embodiments, the configuration of synchronously coupling the gate of the driving transistor via the first gate line G1 by adding a second conductive portion and a third conductive portion can also be applied to other pixel driving circuit structures or other display panel layout structures. For example, this configuration can also be applied to the circuit architecture of an N-type driving transistor, whereby the first gate line G1 can synchronously pull down the third conductive portion at the end of the data writing phase to pull down the gate voltage of the driving transistor.

[0083] It should be noted that, as Figure 4 , 19 As shown in Figure 20, the black squares drawn on the side of the fourth conductive layer away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. These black squares only indicate the location of the vias; different vias represented by black squares at different locations can penetrate different insulating layers.

[0084] like Figure 21 As shown, Figure 4A partial cross-sectional view of the display panel along the dotted line AA is shown. The display panel can further include a barrier layer 92, a first buffer layer 93, a first insulating layer 94, a second insulating layer 95, a first dielectric layer 96, a second buffer layer 97, a third insulating layer 98, a second dielectric layer 99, a passivation layer 910, a first planar layer 911, a second planar layer 912. Among them, the substrate 91, the light shielding layer, the barrier layer 92, the first buffer layer 93, the first active layer, the first insulating layer 94, the first conductive layer, the second insulating layer 95, the second conductive layer, the first dielectric layer 96, the second buffer layer 97, the second active layer, the third insulating layer 98, the third conductive layer, the second dielectric layer 99, the fourth conductive layer, the passivation layer 910, the first planar layer 911, the fifth conductive layer, the second planar layer 912, and the electrode layer are sequentially stacked. Among them, the substrate can include a first polyimide layer, a second barrier layer, a second polyimide layer, and a third barrier layer which are sequentially stacked, and the light shielding layer is located on the side of the third barrier layer away from the first polyimide layer. The thickness of the first polyimide layer can be 8-12um, for example, the thickness of the first polyimide layer can be 8um, 10um, 12um. The second barrier layer can include an amorphous silicon layer and a silicon oxide layer, the thickness of the amorphous silicon layer in the second barrier layer can be 30 angstroms-50 angstroms, for example, the thickness of the amorphous silicon layer can be 30 angstroms, 40 angstroms, 50 angstroms, the thickness of the silicon oxide layer in the second barrier layer can be 5000 angstroms-7000 angstroms, for example, the thickness of the silicon oxide layer can be 5000 angstroms, 6000 angstroms, 7000 angstroms. The thickness of the second polyimide layer can be 4um-7um, for example, the thickness of the second polyimide layer can be 4um, 5um, 5.8um, 7um. The third barrier layer can include a silicon oxide layer, the thickness of the silicon oxide layer can be 500 angstroms-1500 angstroms, for example, the thickness of the silicon oxide layer can be 500 angstroms, 1000 angstroms, 1500 angstroms. The light shielding layer can include a molybdenum layer, the thickness of the molybdenum layer can be 500 angstroms-1500 angstroms, for example, the thickness of the molybdenum layer can be 500 angstroms, 1000 angstroms, 1500 angstroms. The barrier layer 92 can include a silicon oxide layer, the thickness of the silicon oxide layer can be 3000 angstroms-5000 angstroms, for example, the thickness of the silicon oxide layer can be 3000 angstroms, 4000 angstroms, 5000 angstroms. The first buffer layer 93 can include a silicon oxide layer and a silicon nitride layer, the thickness of the silicon oxide layer can be 2000 angstroms-4000 angstroms, for example, the thickness of the silicon oxide layer can be 2000 angstroms, 3000 angstroms, 4000 angstroms, the thickness of the silicon nitride layer can be 500 angstroms-1500 angstroms, for example, the thickness of the silicon nitride layer can be 500 angstroms, 1000 angstroms, 1500 angstroms. The first active layer can include a polysilicon layer, the thickness of the polysilicon layer can be 300 angstroms-700 angstroms, for example, the thickness of the polysilicon layer can be 300 angstroms, 500 angstroms, 700 angstroms.The first insulating layer 94 can include a silicon oxide layer, and the thickness of the silicon oxide layer can be 1000-1500 angstroms, for example, the thickness of the silicon oxide layer can be 1000 angstroms, 1200 angstroms, 1500 angstroms. The first conductive layer can include a molybdenum layer, and the thickness of the molybdenum layer can be 2000-4000 angstroms, for example, the thickness of the molybdenum layer can be 2000 angstroms, 3000 angstroms, 4000 angstroms. The second insulating layer 95 can include a silicon nitride layer, and the thickness of the silicon nitride layer can be 1000-1500 angstroms, for example, the thickness of the silicon nitride layer can be 1000 angstroms, 1300 angstroms, 1500 angstroms. The structure of the second conductive layer and the first conductive layer can be the same. The first dielectric layer 96 can include a silicon nitride layer, and the thickness of the silicon nitride layer can be 500-1500 angstroms, for example, the thickness of the silicon nitride layer can be 500 angstroms, 1000 angstroms, 1500 angstroms. The second buffer layer 97 can include a silicon oxide layer, and the thickness of the silicon oxide layer can be 2000-4000 angstroms, for example, the thickness of the silicon oxide layer can be 2000 angstroms, 3000 angstroms, 4000 angstroms. The thickness of the second active layer can be 200-400 angstroms, for example, the thickness of the second active layer can be 200 angstroms, 310 angstroms, 400 angstroms. The third insulating layer 98 can include a silicon oxide layer, and the thickness of the silicon oxide layer can be 1200-1700 angstroms, for example, the thickness of the silicon oxide layer can be 1200 angstroms, 1500 angstroms, 1700 angstroms. The third conductive layer can include a molybdenum layer and a titanium nitride layer, the thickness of the molybdenum layer can be 2000-3000 angstroms, for example, the thickness of the molybdenum layer can be 2000 angstroms, 2500 angstroms, 3000 angstroms, the thickness of the titanium nitride layer can be 200-400 angstroms, for example, the thickness of the titanium nitride layer can be 200 angstroms, 300 angstroms, 400 angstroms. The second dielectric layer 99 can include a silicon nitride layer and a silicon oxide layer, the thickness of the silicon nitride layer can be 1500-2500 angstroms, for example, the thickness of the silicon nitride layer can be 1500 angstroms, 2000 angstroms, 2500 angstroms, the thickness of the silicon oxide layer can be 2500-3500 angstroms, for example, the thickness of the silicon oxide layer can be 2500 angstroms, 3000 angstroms, 3500 angstroms. The fourth conductive layer can include a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence, the thickness of the first titanium layer can be 400-700 angstroms, for example, the thickness of the first titanium layer can be 400 angstroms, 550 angstroms, 700 angstroms, the thickness of the aluminum layer can be 5000-7000 angstroms, for example, the thickness of the aluminum layer can be 5000 angstroms, 6000 angstroms, 7000 angstroms, the thickness of the second titanium layer can be 400-700 angstroms, for example, the thickness of the second titanium layer can be 400 angstroms, 500 angstroms, 700 angstroms. The passivation layer 910 can include a silicon oxide layer, and the thickness of the silicon oxide layer can be 2000-4000 angstroms, for example, the thickness of the silicon oxide layer can be 2000 angstroms, 3000 angstroms, 4000 angstroms.The first planar layer 911 can include a polyimide layer, and the thickness of the polyimide layer can be 1 um-2 um, for example, the thickness of the polyimide layer can be 1 um, 1.5 um, 2 um. The structure of the fifth conductive layer can be the same as that of the fourth conductive layer. The structure of the second planar layer 912 can be the same as that of the first planar layer 911. The electrode layer can include a first indium tin oxide layer, a silver layer, and a second indium tin oxide layer which are sequentially stacked, the thickness of the first indium tin oxide layer can be 50 angstroms-90 angstroms, for example, the thickness of the first indium tin oxide layer can be 50 angstroms, 70 angstroms, 90 angstroms, the thickness of the silver layer can be 700 angstroms-1000 angstroms, for example, the thickness of the silver layer can be 700 angstroms, 850 angstroms, 1000 angstroms, and the thickness of the second indium tin oxide layer can be 40 angstroms-80 angstroms, for example, the thickness of the second indium tin oxide layer can be 40 angstroms, 60 angstroms, 80 angstroms. The display panel can further include a pixel definition layer on the side of the electrode layer away from the substrate, and the pixel definition layer can include a polyimide layer, and the thickness of the polyimide layer can be 1.5 um-3 um, for example, the thickness of the polyimide layer can be 1.5 um, 2.1 um, 3 um.

[0085] It should be noted that the scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the figure, and the drawings described in the present disclosure are only schematic diagrams. In addition, the adjectives first, second, etc. are only used to define different structure names, and do not have the meaning of a specific order.

[0086] The present exemplary embodiment also provides a display device, comprising the display panel described above. The display device can be a mobile phone, a tablet computer, a television, etc.

[0087] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the description herein, the principles described herein are intended to be broad and to encompass any and all modifications thereof and alternative constructions thereof as falling within the scope of the present disclosure. The description and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure is indicated by the claims.

[0088] It should be understood that the present disclosure is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A display panel, the display panel including a pixel driving circuit, the pixel driving circuit including a driving transistor and a fourth transistor, the first terminal of the fourth transistor being connected to a data line, and the second terminal being connected to the first terminal of the driving transistor, the display panel further including: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes a first gate line and a first conductive portion. The orthographic projection of the first gate line on the substrate extends along a first direction, and a portion of the structure of the first gate line is used to form the gate of the fourth transistor. The first conductive portion is used to form the gate of the driving transistor. The second conductive part is connected to the first gate line; The third conductive portion is located on a different conductive layer from the second conductive portion, and the orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate. A fourth conductive layer is located on the side of the first conductive layer away from the substrate. The fourth conductive layer includes a first bridging portion, which connects the third conductive portion and the first conductive portion through vias. The pixel driving circuit also includes an eighth transistor, a first transistor, and a second transistor; The first terminal of the eighth transistor is connected to the gate of the driving transistor, the second terminal of the eighth transistor is connected to the second terminal of the first transistor, the first terminal of the first transistor is connected to the first initial signal line, the first terminal of the second transistor is connected to the second terminal of the eighth transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. The display panel also includes: The second active layer is located between the first conductive layer and the fourth conductive layer. The second active layer includes an eighth active portion, which is used to form the channel region of the eighth transistor. A third conductive layer is located between the second active layer and the fourth conductive layer. The third conductive layer includes a second gate line. The orthographic projection of the second gate line on the substrate extends along the first direction and covers the orthographic projection of the eighth active portion on the substrate. A portion of the structure of the second gate line is used to form the top gate of the eighth transistor. The display panel also includes: A second conductive layer is located between the first conductive layer and the second active layer. The second conductive layer includes a third gate line, the orthographic projection of the third gate line on the substrate extending along the first direction and covering the orthographic projection of the eighth active portion on the substrate. A portion of the structure of the third gate line is used to form the bottom gate of the eighth transistor. The third conductive layer further includes a fifth conductive portion, which is connected to the second gate line. The orthographic projection of the fifth conductive portion on the substrate is located on the side of the orthographic projection of the second gate line on the substrate facing the orthographic projection of the first gate line on the substrate. The fifth conductive portion includes a seventh edge away from the second gate line and an eighth edge connected to the seventh edge. The orthographic projection of the seventh edge on the substrate extends along the first direction and intersects with the orthographic projection of the eighth edge on the substrate. The second gate line includes a ninth edge and a tenth edge disposed opposite to each other in a second direction, the second direction intersecting the first direction, the orthographic projection of the ninth edge on the substrate and the orthographic projection of the tenth edge on the substrate both extending along the first direction, the orthographic projection of the ninth edge on the substrate is located on the side of the orthographic projection of the tenth edge on the substrate facing the orthographic projection of the first gate line on the substrate, and the ninth edge is connected to the eighth edge, the angle between the orthographic projection of the eighth edge on the substrate and the orthographic projection of the ninth edge on the substrate is less than 180°; The third gate line includes an eleventh edge and a twelfth edge disposed opposite to each other in a second direction. The orthographic projection of the eleventh edge on the substrate and the orthographic projection of the twelfth edge on the substrate both extend along the first direction. The orthographic projection of the eleventh edge on the substrate is located on the side of the orthographic projection of the twelfth edge on the substrate facing the orthographic projection of the first gate line on the substrate. The orthographic projection of the first bridging portion on the substrate intersects with the orthographic projections of the seventh edge, the tenth edge, the eleventh edge, and the twelfth edge on the substrate. The orthographic projection of a portion of the first bridging portion onto the substrate overlaps with the orthographic projections of the second gate line and the third gate line onto the substrate.

2. The display panel according to claim 1, wherein, The conductive layer containing the second conductive portion is located either in the first conductive layer or between the first conductive layer and the fourth conductive layer. The conductive layer containing the third conductive part is located between the conductive layer containing the second conductive part and the fourth conductive layer.

3. The display panel according to claim 2, wherein, The pixel driving circuit also includes a capacitor, the first electrode of which is connected to the gate of the driving transistor, the second electrode of which is connected to a power line, and the first conductive portion is also used to form the first electrode of the capacitor. The display panel further includes: a second conductive layer, the second conductive layer being located between the first conductive layer and the fourth conductive layer, the second conductive layer comprising: A fourth conductive portion, wherein the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap, the fourth conductive portion being used to form the second electrode of the capacitor; The third conductive part is located in the second conductive layer.

4. The display panel according to claim 1, wherein, The display panel also includes: The second active layer is located between the first conductive layer and the fourth conductive layer. The second active layer includes an eighth active portion, which is used to form the channel region of the eighth transistor. The third conductive part is located in the second active layer.

5. The display panel according to claim 1, wherein, The orthographic projection of the second conductive portion on the substrate is located on the side of the orthographic projection of the first gate line on the substrate that is away from the orthographic projection of the first conductive portion on the substrate; The orthographic projection of the third conductive portion on the substrate is located on the side where the orthographic projection of the first gate line on the substrate is away from the orthographic projection of the first conductive portion on the substrate.

6. The display panel according to claim 1, wherein, The pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor, and a portion of the structure of the first gate line is used to form the gate of the second transistor; The display panel also includes: A first active layer is located between the substrate and the first conductive layer. The first active layer includes a second active portion and a fourth active portion. The orthographic projection of the first gate line on the substrate covers the orthographic projection of the second active portion on the substrate and the orthographic projection of the fourth active portion on the substrate. The second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the fourth transistor. In the first direction, the orthographic projection of the second conductive portion on the substrate is located between the orthographic projection of the second active portion on the substrate and the orthographic projection of the fourth active portion on the substrate.

7. The display panel according to claim 6, wherein, In the first direction, the orthographic projection of the third conductive portion on the substrate is located between the orthographic projection of the second active portion on the substrate and the orthographic projection of the fourth active portion on the substrate. The distance between the orthographic projection of the third conductive part on the substrate and the orthographic projection of the fourth active part on the substrate in the first direction is greater than the distance between the orthographic projection of the third conductive part on the substrate and the orthographic projection of the second active part on the substrate in the first direction.

8. The display panel according to claim 5, wherein, The third conductive portion includes a first edge and a second edge disposed opposite to each other in the first direction, and a third edge and a fourth edge disposed opposite to each other in the second direction, wherein the second direction intersects the first direction; The second conductive portion includes a fifth edge and a sixth edge disposed opposite to each other in the first direction; In the first direction, the orthographic projection of the fifth edge on the substrate is located between the orthographic projection of the first edge on the substrate and the orthographic projection of the second edge on the substrate, and the orthographic projection of the sixth edge on the substrate is located between the orthographic projection of the first edge on the substrate and the orthographic projection of the second edge on the substrate. The orthographic projections of the third edge and the fourth edge on the substrate both intersect with the orthographic projection of the second conductive portion on the substrate.

9. The display panel according to claim 1, wherein, The orthographic projection of the second gate line on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first gate line on the substrate.

10. The display panel according to claim 1, wherein, The distance between the orthographic projection of the seventh edge on the substrate and the orthographic projection of the eleventh edge on the substrate in the second direction is greater than the distance between the orthographic projection of the ninth edge on the substrate and the orthographic projection of the eleventh edge on the substrate in the second direction.

11. The display panel according to claim 1 or 10, wherein, The orthographic projection of the seventh edge on the substrate is located on the orthographic projection of the first gate line on the substrate.

12. The display panel according to claim 9, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a fifth transistor, a sixth transistor, and a seventh transistor. The first electrode of the fifth transistor is connected to a power supply line, and the second electrode is connected to the first electrode of the driving transistor. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel also includes: A first active layer is located between the substrate and the first conductive layer. The first active layer includes a first active portion, a fifth active portion, a sixth active portion, and a seventh active portion. The first active portion is used to form the channel region of the first transistor, the fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor. The first conductive layer also includes: An enable signal line extends along the first direction and covers the orthogonal projection of the fifth active portion on the substrate and the orthogonal projection of the sixth active portion on the substrate. A portion of the structure of the enable signal line is used to form the gate of the fifth transistor, and another portion of the structure of the enable signal line is used to form the gate of the sixth transistor. A first reset signal line extends along the first direction and covers the orthogonal projection of the first active portion on the substrate, and a portion of the structure of the first reset signal line is used to form the gate of the first transistor. The second reset signal line extends along the first direction and covers the orthogonal projection of the seventh active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor. Wherein, the orthogonal projection of the enable signal line on the substrate is located on the side of the orthogonal projection of the first conductive portion on the substrate that is away from the orthogonal projection of the first gate line on the substrate. The orthographic projection of the second reset signal line on the substrate is located on the side of the orthographic projection of the enable signal line on the substrate that is away from the orthographic projection of the first conductive part on the substrate. The orthographic projection of the first reset signal line on the substrate is located on the side of the orthographic projection of the first gate line on the substrate that is away from the orthographic projection of the first conductive part on the substrate.

13. The display panel according to claim 12, wherein, The first direction is the row direction, and the second reset signal line in the pixel driving circuit of the adjacent previous row is multiplexed as the first reset signal line in the pixel driving circuit of this row.

14. The display panel according to claim 12, wherein, The first direction is the row direction, and the third conductive layer further includes: The first initial signal line, the orthographic projection of the first initial signal line on the substrate extends along the first direction, and is located on the side of the first reset signal line on the substrate away from the orthographic projection of the first conductive part on the substrate; The orthographic projection of the first initial signal line in the adjacent next row pixel driving circuit on the substrate is located between the orthographic projection of the second reset signal line in the current row pixel driving circuit on the substrate and the orthographic projection of the first conductive part in the current row pixel driving circuit on the substrate, and the orthographic projection of the first initial signal line in the adjacent next row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the enable signal line in the current row pixel driving circuit on the substrate.

15. The display panel according to claim 12, wherein, The first direction is the row direction, and the fourth conductive layer further includes: The second initial signal line, the orthographic projection of the second initial signal line on the substrate extends along the first direction, and is located on the side of the second reset signal line on the substrate away from the orthographic projection of the first conductive part on the substrate; The orthographic projection of the second initial signal line in the adjacent previous row pixel driving circuit onto the substrate is located between the orthographic projection of the first reset signal line in the current row pixel driving circuit onto the substrate and the orthographic projection of the first gate line in the current row pixel driving circuit onto the substrate.

16. The display panel according to claim 1, wherein, The display panel also includes: The second active layer is located between the first conductive layer and the fourth conductive layer. The second active layer includes an eighth active portion, which is used to form the channel region of the eighth transistor. The fifth conductive layer is located on the side of the fourth conductive layer away from the substrate. The fifth conductive layer includes a power line, which includes a first extension, a second extension, and a third extension. The second extension is connected between the first extension and the third extension. Wherein, the size of the orthographic projection of the second extension on the substrate in the first direction is greater than the size of the orthographic projection of the first extension on the substrate in the first direction, and the size of the orthographic projection of the second extension on the substrate in the first direction is greater than the size of the orthographic projection of the third extension on the substrate in the first direction. The orthographic projection of the second extension on the substrate covers the orthographic projection of the eighth active portion on the substrate and the orthographic projection of the first bridging portion on the substrate.

17. The display panel according to claim 1, wherein, The pixel driving circuit also includes a capacitor, the first electrode of which is connected to the gate of the driving transistor, and the second electrode of which is connected to a power supply line. The power cord includes: a first extension, a second extension, and a third extension, wherein the second extension is connected between the first extension and the third extension; The first direction is the row direction, and the display panel includes a plurality of repeating units distributed along the row and column directions. Each repeating unit includes two pixel driving circuits. The two pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit distributed along the row direction. The first pixel driving circuit and the second pixel driving circuit are arranged in a mirror symmetrical manner. Each column of pixel driving circuits is provided with a corresponding power line, and in the same repeating unit, the second extensions of the two power lines are connected to each other; The display panel further includes: a second conductive layer, the second conductive layer being located between the first conductive layer and the fourth conductive layer, the second conductive layer comprising: A fourth conductive portion, wherein the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap, the fourth conductive portion being used to form the second electrode of the capacitor; In the repeating units adjacent to each other in the row direction, the adjacent fourth conductive parts are connected.

18. The display panel according to claim 17, wherein, The second conductive layer further includes a first connection portion, in which adjacent fourth conductive portions are connected in the row direction of adjacent repeating units; The pixel driving circuit further includes a fifth transistor, the first terminal of which is connected to the power line, and the second terminal of which is connected to the first terminal of the driving transistor; The display panel further includes: a first active layer, the first active layer being located between the substrate and the first conductive layer, the first active layer comprising: The third active part is used to form the channel region of the driving transistor; The fifth active part is used to form the channel region of the fifth transistor; The ninth active unit is connected to the side of the fifth active unit away from the third active unit, and is connected between two fifth active units in the adjacent repeating units in the row direction; The fourth conductive layer further includes: The second bridging part is connected to the ninth active part and the first connecting part through vias, and the second bridging part is connected to the power line through vias.

19. The display panel according to claim 12, wherein, The first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors, and the eighth transistor is an N-type transistor.

20. A display device, wherein, Includes the display panel as described in any one of claims 1-19.

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