Display panel and display device

Abstract

A display panel includes a first pixel driving circuit and a second pixel driving circuit. Both the first and second pixel driving circuits include a capacitor, a driving transistor, and a data writing transistor; the data writing transistor is coupled to a data line and the driving transistor; the capacitor includes a first electrode. Along the extension direction of the data line, the data writing transistor and the driving transistor of the first pixel driving circuit, and the driving transistor and the data writing transistor of the second pixel driving circuit are arranged sequentially. In the first pixel driving circuit, the first electrode is coupled to the driving transistor at a first coupling position and to a first light-emitting device at a second coupling position; the second coupling position is located on the side away from the data writing transistor from the first coupling position. In the second pixel driving circuit, the first electrode is coupled to the driving transistor at a third coupling position and to the second light-emitting device at a fourth coupling position; the fourth coupling position is located between the third coupling position and the data writing transistor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Display panels, such as organic light-emitting diodes (OLEDs) Emitting Diode (OLED) display panels have advantages such as self-illumination, thinness, low power consumption, good color reproduction, high sensitivity, and wide viewing angle, and have broad development prospects. Summary of the Invention

[0003] In a first aspect, a display panel is provided, comprising a data line, a first light-emitting device, a second light-emitting device, a first pixel driving circuit, and a second pixel driving circuit. Both the first pixel driving circuit and the second pixel driving circuit include a capacitor, a driving transistor, and a data writing transistor; the data writing transistor is coupled to the data line and the driving transistor; the capacitor includes a first electrode and a second electrode disposed opposite to each other.

[0004] In this circuit, along the extension direction of the data line, the data writing transistor of the first pixel driving circuit, the driving transistor of the first pixel driving circuit, the driving transistor of the second pixel driving circuit, and the data writing transistor of the second pixel driving circuit are arranged sequentially. In the first pixel driving circuit, the first electrode plate is coupled to the driving transistor at a first coupling position and to the first light-emitting device at a second coupling position; the second coupling position is located on the side away from the data writing transistor at the first coupling position. In the second pixel driving circuit, the first electrode plate is coupled to the driving transistor at a third coupling position and to the second light-emitting device at a fourth coupling position; the fourth coupling position is located between the third coupling position and the data writing transistor.

[0005] Optionally, the driving transistor includes an active layer comprising a plurality of semiconductor segments sequentially distributed and coupled to each other along the extension direction of the data line, the extension direction of the semiconductor segments intersecting the extension direction of the data line. In the first pixel driving circuit, the second coupling position is located on the side of the plurality of semiconductor segments away from the first coupling position. In the second pixel driving circuit, the fourth coupling position is located on the side of the plurality of semiconductor segments closer to the third coupling position.

[0006] Optionally, the display panel further includes a first transition pattern, a first insulating layer, and a second insulating layer. The first insulating layer is located between the first transition pattern and the first electrode plate in the first pixel driving circuit, and has a first through-hole at a second coupling position; and the second insulating layer is located between the first transition pattern and the first light-emitting device, and has a second through-hole at a second coupling position. The first transition pattern is coupled to the first electrode plate in the first pixel driving circuit at the first through-hole, and to the first light-emitting device at the second through-hole. The first through-hole and the second through-hole are staggered along the thickness direction of the display panel.

[0007] Optionally, the display panel further includes a second transition pattern. A first insulating layer extends between the second transition pattern and the first electrode in the second pixel driving circuit, and the first insulating layer also has a third through-hole located at a fourth coupling position. A second insulating layer extends between the second transition pattern and the second light-emitting device, and the second insulating layer has a fourth through-hole located at a fourth coupling position. The second transition pattern is coupled to the first electrode in the second pixel driving circuit at the third through-hole and to the second light-emitting device at the fourth through-hole. The third and fourth through-holes are staggered along the thickness direction of the display panel.

[0008] Optionally, the center line connecting the first through hole and the second through hole intersects the center line connecting the third through hole and the fourth through hole.

[0009] Optionally, both the first and second adapter patterns are approximately rectangular in shape. The first and second through holes are arranged sequentially along the long side of the first adapter pattern; the third and fourth through holes are arranged sequentially along the long side of the second adapter pattern.

[0010] Optionally, the long side of the first adapter pattern is approximately parallel to the extension direction of the data cable; the long side of the second adapter pattern intersects the extension direction of the data cable.

[0011] Optionally, the distance between the second and fourth through holes in the direction of extension of the data line is approximately equal to the pixel size of the display panel in the direction of extension of the data line.

[0012] Optionally, the first electrode plate of the first pixel driving circuit and the first electrode plate of the second pixel driving circuit have different shapes; the facing areas of the first electrode plate and the second electrode plate are equal.

[0013] Optionally, the second electrode plate of the first pixel driving circuit and the second electrode plate of the second pixel driving circuit have different shapes.

[0014] Optionally, the gate of the data writing transistor includes two first sub-gates coupled to each other, and the data writing transistor has a first groove that separates the two first sub-gates. The openings of the first groove in the first pixel driving circuit and the first groove in the second pixel driving circuit face opposite directions.

[0015] Optionally, the driving transistor includes a gate, a first electrode, and a second electrode, with the second electrode coupled to the first plate. Both the first pixel driving circuit and the second pixel driving circuit further include a reference signal transistor; the reference signal transistor includes a gate, a first electrode, and a second electrode, wherein the first electrode is configured to write a reference signal, and the second electrode is coupled to the second plate and the gate of the driving transistor. The reference signal transistor is located on the side of the data writing transistor away from the driving transistor.

[0016] Optionally, the display panel also includes a reference signal connection line located on the side of the reference signal transistor of the second pixel driving circuit away from the data write transistor, and intersecting and insulated from the data line; the reference signal connection line is coupled to the reference signal transistor and configured to provide a write reference signal.

[0017] Optionally, the gate of the reference signal transistor includes two second sub-gates coupled to each other, and the reference signal transistor has a second groove that separates the two second sub-gates.

[0018] Optionally, when the gate of the data writing transistor has a first groove, in the first pixel driving circuit, the openings of the first groove and the second groove face opposite directions.

[0019] Alternatively, in the case where the gate of the data writing transistor has a first groove, in the second pixel driving circuit, the openings of the first groove and the second groove face opposite directions.

[0020] Alternatively, in the case where the gate of the data writing transistor has a first groove, in a pixel driving circuit, the openings of the first groove and the second groove face away from each other; in a second pixel driving circuit, the openings of the first groove and the second groove face away from each other.

[0021] Optionally, the first pixel driving circuit further includes a first light-emitting control transistor; the first light-emitting control transistor includes a gate, a first electrode, and a second electrode, wherein the first electrode of the first light-emitting control transistor is configured to write a first light-emitting signal, and the second electrode of the first light-emitting control transistor is coupled to the first electrode of the driving transistor in the first pixel driving circuit and the first electrode of the driving transistor in the second pixel driving circuit; the first light-emitting control transistor is located between the driving transistor in the first pixel driving circuit and the driving transistor in the second pixel driving circuit.

[0022] Alternatively, both the first pixel driving circuit and the second pixel driving circuit may further include a second light-emitting control transistor; the second light-emitting control transistor includes a gate, a first electrode, and a second electrode, wherein the first electrode of the second light-emitting control transistor is configured to write a second light-emitting signal, and the second electrode of the second light-emitting control transistor is coupled to the first electrode of the driving transistor; the second light-emitting control transistor is located on the side of the driving transistor away from the data writing transistor.

[0023] Optionally, the first pixel driving circuit further includes a first reset transistor; the first reset transistor includes a gate, a first electrode, and a second electrode, wherein the second electrode of the first reset transistor is configured to write a first initialization signal, and the first electrode of the first reset transistor is coupled to the first electrode of the driving transistor in the first pixel driving circuit and the first electrode of the driving transistor in the second pixel driving circuit; the first reset transistor is located between the driving transistor in the first pixel driving circuit and the driving transistor in the second pixel driving circuit.

[0024] Alternatively, both the first pixel driving circuit and the second pixel driving circuit may further include a second reset transistor; the second reset transistor includes a gate, a first electrode, and a second electrode, wherein the second electrode of the second reset transistor is configured to write a second initialization signal, and the first electrode of the second reset transistor is coupled to the second electrode of the driving transistor; the second reset transistor is located on the side of the driving transistor away from the data writing transistor.

[0025] In a second aspect, a display device is provided, comprising a display panel. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is a structural diagram of a display device provided for some embodiments of the present disclosure.

[0028] Figure 2 A circuit diagram of a pixel circuit provided for some embodiments of this disclosure.

[0029] Figure 3 This is a structural diagram of a pixel driving circuit group provided for some embodiments of the present disclosure.

[0030] Figure 4A circuit diagram of a pixel driving circuit group provided for some embodiments of this disclosure.

[0031] Figure 5 for Figure 4 A diagram illustrating the driving method of the mid-pixel driving circuit group F.

[0032] Figure 6 for Figure 4 The structural diagram.

[0033] Figure 7 This is a structural diagram of the anode and pixel definition layer of a light-emitting device provided for some embodiments of this disclosure.

[0034] Figure 8 for Figure 6 The structural diagram of the first pattern layer in the diagram.

[0035] Figure 9 for Figure 8 The structure diagram of the active layer of the driving transistor.

[0036] Figure 10 for Figure 6 The structural diagram of the second pattern layer.

[0037] Figure 11 for Figure 10 A structural diagram of the transistor through which data is written.

[0038] Figure 12 for Figure 8 A structural diagram of the active layer of the transistor in which data is written.

[0039] Figure 13 for Figure 8 and 10 A structural diagram of a transistor.

[0040] Figure 14 for Figure 6 The structural diagram of the third pattern layer.

[0041] Figure 15 for Figure 6 The structural diagram of the fourth pattern layer in the middle.

[0042] Figure 16 for Figure 7 Side view at W1-W2.

[0043] Figure 17 for Figure 6 Enlarged view of the second coupling position P2.

[0044] Figure 18 for Figure 6 Enlarged view of the fourth coupling position P4.

[0045] Figure 19 A schematic diagram of adjacent rows of pixel driving circuit groups is provided for some embodiments of this disclosure.

[0046] Figure 20 Structural diagrams of pixel units are provided for some embodiments of this disclosure.

[0047] Figure 21 Another circuit diagram of a pixel driving circuit group provided for some embodiments of this disclosure.

[0048] Figure 22 for Figure 21 The diagram shows the driving method of pixel driving circuit group F.

[0049] Figure 23 Another circuit diagram of a pixel driving circuit group provided for some embodiments of this disclosure.

[0050] Figure 24 for Figure 23 The diagram shows the driving method of pixel driving circuit group F. Detailed Implementation

[0051] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0053] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0054] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0055] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0056] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0057] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0058] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0059] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0060] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0061] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0062] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0063] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0064] Some embodiments of this disclosure provide a display device. A display device refers to a product with image display functionality; exemplary examples include: a monitor, television, billboard, digital photo frame, laser printer with display functionality, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, monitor, navigator, vehicle, large-area wall, home appliance, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), and monitors, etc.

[0065] Figure 1 This is a structural diagram of the display device.

[0066] See Figure 1 The display device 1 typically includes a display panel 10. Exemplarily, the display panel 10 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (including miniLED or microLED) display panel, etc.

[0067] The display panel 10 has a display area AA and a non-display area SA. The display area AA of the display panel 10 is the area capable of displaying images. The non-display area SA may be located on at least one side of the display area AA (e.g., one side, or multiple sides). For example, the non-display area SA may be arranged around the display area AA.

[0068] For example, the display area AA can be a rectangle, or a rounded rectangle or a similar shape. Based on this, the display area AA has two intersecting (e.g., perpendicular) sides. For ease of description, a Cartesian coordinate system is established using the extension directions of these two sides as the X-axis and Y-axis.

[0069] The display device 1 may also include other components, such as a display driver integrated circuit (DDIC) 20. The DDIC 20 is coupled to the display panel 10, for example, it may be attached to the display panel 10 and configured to provide data signals to the display panel 10.

[0070] See Figure 2 The embodiments of this disclosure provide a display panel.

[0071] The display panel 10 includes a plurality of sub-pixels SP located in the display area AA. The plurality of sub-pixels SP includes a first sub-pixel for emitting a first color light, a second sub-pixel for emitting a second color light, and a third sub-pixel for emitting a third color light. The first, second, and third colors are three primary colors (e.g., red, green, and blue). For example, the display panel 10 may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.

[0072] See also Figure 2Each subpixel SP (e.g., each) may include a pixel driving circuit Q and a light-emitting device ED coupled to the pixel driving circuit Q. The pixel driving circuit Q is configured to drive the light-emitting device ED to emit light according to a received data signal. For example, the data signal may be a voltage signal, and the brightness of the light-emitting device ED will vary depending on the voltage value of the data signal.

[0073] For example, the light-emitting device (ED) in the red sub-pixel is configured to emit red light, the light-emitting device (ED) in the blue sub-pixel is configured to emit blue light, and the light-emitting device (ED) in the green sub-pixel is configured to emit green light. Alternatively, the light-emitting devices (ED) in the red, green, and blue sub-pixels are all configured to emit white light; in this case, the display panel 10 also includes a red filter located in the red sub-pixel, a green filter located in the green sub-pixel, and a blue filter located in the blue sub-pixel.

[0074] The light-emitting device (ED) can be one or more of organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes.

[0075] A light-emitting device (ED) includes a cathode and an anode, and a light-emitting functional layer located between the cathode and the anode. The light-emitting functional layer may include, for example, a light-emitting layer (EL), a hole transport layer (HTL) located between the light-emitting layer and the anode, and an electron transport layer (ETL) located between the light-emitting layer and the cathode. Of course, depending on the requirements, in some embodiments, a hole injection layer (HIL) may be disposed between the hole transport layer (HTL) and the anode, and an electron injection layer (EIL) may be disposed between the electron transport layer (ETL) and the cathode. Furthermore, an electron blocking layer (EBL) may be disposed between the hole transport layer (HTL) and the light-emitting layer (EL), and a hole blocking layer (HBL) may be disposed between the electron transport layer (ETL) and the light-emitting layer (EL).

[0076] For example, the anode may be formed of a transparent conductive material with a high work function, and its electrode material may include one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc gallium oxide (GZO), zinc oxide (ZnO), indium oxide (In2O3), zinc aluminum oxide (AZO), and carbon nanotubes. The cathode may be formed of a material with high conductivity and low work function, and its electrode material may include alloys such as magnesium-aluminum alloy (MgAl) or lithium-aluminum alloy (LiAl), or elemental metals such as magnesium (Mg), aluminum (Al), lithium (Li), or silver (Ag). The material of the light-emitting layer can be selected according to the different colors of the emitted light. For example, the material of the light-emitting layer includes fluorescent or phosphorescent materials. Alternatively, the light-emitting layer may employ a doping system, i.e., dopant materials are mixed into the host light-emitting material to obtain a usable light-emitting material. For example, the main luminescent material can be one of the following: metal compound material, anthracene derivative, aromatic diamine compound, triphenylamine compound, aromatic triamine compound, benzidine diamine derivative, and triarylamine polymer.

[0077] Multiple pixel driving circuits Q can be arranged in an array. For example, multiple pixel driving circuits can form an array of 2n rows and m columns. Here, n is greater than or equal to 1; m is greater than or equal to 1, for example, m is greater than or equal to 2. For example, a row of pixel driving circuits Q distributed along a first direction X (e.g., the direction shown by the X-axis) is called the same row of pixel driving circuits Q. A row of pixel driving circuits Q distributed along a second direction Y (e.g., the direction shown by the Y-axis) is called the same column of pixel driving circuits Q.

[0078] The pixel driving circuit Q can include multiple electronic components such as transistors and capacitors. For example, a pixel driving circuit can typically include three transistors and one capacitor, forming a 3T1C (i.e., one driving transistor, two switching transistors, and one capacitor). It can also include more than three transistors and at least one capacitor, such as 4T1C (i.e., one driving transistor, three switching transistors, and one capacitor), 5T1C (i.e., one driving transistor, four switching transistors, and one capacitor), or 7T2C (i.e., one driving transistor, six switching transistors, and two capacitors), etc.

[0079] The transistor can be a thin film transistor (TFT), a metal oxidized semiconductor transistor (MOS), or other switching devices with the same characteristics. In the embodiments of this disclosure, thin film transistors are used as an example for illustration.

[0080] A thin-film transistor (TFT) includes a gate, a first electrode, and a second electrode. The first electrode is one of the source and the drain, and the second electrode is the other of the source and the drain. Since the source and drain of a TFT have the same function, they do not need to be specifically distinguished.

[0081] In the pixel driving circuit provided in the embodiments of this disclosure, each transistor can be an N-type transistor. It should be noted that the embodiments of this disclosure include, but are not limited to, this. For example, one or more transistors in the pixel driving circuit provided in the embodiments of this disclosure can also be P-type transistors, simply by connecting the terminals of the P-type transistors in accordance with the terminals of the corresponding N-type transistors in the embodiments of this disclosure, and applying a corresponding high or low level to the corresponding gate.

[0082] See also Figure 2 The display panel may also include a variety of signal lines coupled to multiple pixel driving circuits.

[0083] For example, multiple signal lines include multiple data lines DL(1) to DL(m). If the pixel driving circuit of column k (representing any column) is coupled to data line DL(k), the data line DL(k) is configured to provide data signals to the pixel driving circuit of column k. Here, k is greater than or equal to 1 and less than or equal to m.

[0084] For example, the various signal lines also include multiple first scan signal lines GL1(1) to GL1(2n). If the pixel driving circuit of the i-th row (representing any row) is coupled to the first scan signal line GL1(i), the first scan signal line GL1(i) is configured to provide a first scan signal to the pixel driving circuit of the i-th row. Here, i is greater than or equal to 1 and less than or equal to 2n-1.

[0085] For example, the various signal lines also include multiple second scan signal lines GL2(1) to GL2(2n). If the pixel driving circuit of the i-th row is coupled to the second scan signal line GL2(i), the second scan signal line GL2(i) is configured to provide a second scan signal to the pixel driving circuit of the i-th row.

[0086] For example, the various signal lines also include multiple first light emission control signal lines EML1(1) to EML1(n). If the pixel driving circuits of the i-th and j-th rows are coupled to the first light emission control signal line EML1(h), the first light emission control signal line EML1(h) is configured to provide first light emission control signals to the pixel driving circuits of the i-th and j-th rows. Here, j is greater than or equal to 2, less than or equal to 2n, and j is not equal to i.

[0087] For example, the various signal lines also include multiple second light emission control signal lines EML2(1) to EML2(n). If the pixel driving circuits of the i-th and j-th rows are coupled to the second light emission control signal line EML2(h), the second light emission control signal line EML2(h) is configured to provide a second light emission control signal to the pixel driving circuits of the i-th and j-th rows.

[0088] The following section will describe in detail the driving circuits for two pixels located in the same column and adjacent rows. See also Figure 3 These two pixel driving circuits are referred to as the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(j,k), respectively, and can be coupled to the same data line DL(k). Furthermore, the light-emitting device ED coupled to the first pixel driving circuit Q(i,k) is called the first light-emitting device ED(i,k), and the light-emitting device ED coupled to the second pixel driving circuit Q(j,k) is called the second light-emitting device ED(j,k). Other pixel driving circuits can also refer to the relevant descriptions of the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(j,k) here.

[0089] Figure 4 yes Figure 3 A specific circuit diagram. Figure 5 yes Figure 4 The signal timing diagram of the circuit shown is shown.

[0090] See Figure 4 Both the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(j,k) include multiple electronic components (i.e., parts), such as a capacitor Cst, a driving transistor T3, and a data writing transistor T1. Figure 4 In this diagram, if the reference numeral of an electronic component contains (i, k), it indicates that the electronic component belongs to the first pixel driving circuit; if the reference numeral of an electronic component contains (j, k), it indicates that the electronic component belongs to the second pixel driving circuit. As an example, if i is an odd number, then i+1=j=2h.

[0091] The following describes the functions of capacitor Cst(i,k), driving transistor T3(i,k), and data writing transistor T1(i,k) in the first pixel driving circuit Q(i,k), as well as their interconnections.

[0092] The driving transistor T3(i,k) includes a gate T3g, a first electrode T31, and a second electrode T32, and is configured to control the current flowing through the first electrode T31 and the second electrode T32 in response to a signal applied to the gate T3g. Exemplarily, the signal applied to the gate T3g can be a data signal Vdate or a compensated data signal Vdate+Vth, where Vth is the threshold voltage of the driving transistor T3(i,k). Exemplarily, the first electrode T31, the second electrode T32 of the driving transistor T3(i,k), and the first light-emitting device ED(i,k) are connected in series between the first power supply voltage terminal VDD and the second power supply voltage terminal VSS, such that the driving transistor T3(i,k) can control the magnitude of the current flowing through the first light-emitting device ED(i,k).

[0093] A data write transistor T1(i,k) is coupled to a data line DL(k) and a drive transistor T3(i,k) and is configured to transmit a data signal applied to the data line DL(k) to the drive transistor T3(i,k). The data write transistor T1(i,k) includes a gate T1g, a first terminal T11, and a second terminal T12. Exemplarily, the first terminal T11 of the data write transistor T1(i,k) is coupled to the data line DL(k), the second terminal T12 of the data write transistor T1(i,k) is coupled to the gate T3g of the drive transistor T3(i,k), and the gate T1g of the data write transistor T1(i,k) is coupled to a first scan signal line GL1(i). The data write transistor T1(i,k) is configured to transmit a data signal applied to the data line DL(k) to the gate T3g of the drive transistor T3(i,k) in response to a first scan signal from the first scan signal line GL1(i).

[0094] The capacitor Cst(i,k) has a first plate C11 and a second plate C12 facing each other; wherein, the first plate C11 of the capacitor Cst(i,k) is coupled to both the second plate T32 of the driving transistor T3(i,k) and the first light-emitting device ED(i,k). For example, the first plate C11 of the capacitor Cst(i,k) is coupled to the anode of the first light-emitting device ED(i,k). The second plate C12 of the capacitor Cst(i,k) is coupled to the gate T3g of the driving transistor T3(i,k).

[0095] Similarly, in the second pixel driving circuit Q(j,k), the first terminal T31 and the second terminal T32 of the driving transistor T3(j,k) and the second light-emitting device ED(j,k) can be connected in series, so that the driving transistor T3(j,k) can control the magnitude of the current flowing through the second light-emitting device ED(j,k). For a detailed description of the driving transistor T3(j,k), please refer to the relevant introduction of the driving transistor T3(i,k) in the first pixel driving circuit Q(i,k) above.

[0096] The data write transistor T1(j,k) is configured to transmit the data signal applied to the data line DL(k) to the gate T3g of the driving transistor T3(j,k) in response to the first scan signal of the first scan signal line GL1(j). For a detailed description of the data write transistor T1(j,k), please refer to the relevant introduction of the data write transistor T1(i,k) of the first pixel driving circuit Q(i,k) above.

[0097] Furthermore, in the second pixel driving circuit Q(j,k), the capacitor Cst(j,k) has a first plate C11 and a second plate C12 facing each other; wherein, the first plate C11 of the capacitor Cst(j,k) is coupled to both the second plate T32 of the driving transistor T3(j,k) and the second light-emitting device ED(j,k). For example, the first plate C11 of the capacitor Cst(j,k) is coupled to the anode of the second light-emitting device ED(j,k). The second plate C12 of the capacitor Cst(j,k) is coupled to the gate T3g of the driving transistor T3(j,k).

[0098] In some embodiments, the first pixel driving circuit Q(i,k) further includes a reference signal transistor T2(i,k). The reference signal transistor T2(i,k) includes a gate T2g, a first terminal T21, and a second terminal T22. Exemplarily, the first terminal T21 of the reference signal transistor T2(i,k) is coupled to a reference signal line VIN2 and is configured to write a reference signal. The second terminal T21 of the reference signal transistor T2(i,k) is coupled to the second plate C12 of the capacitor Cst and the gate T3g of the driving transistor T3(i,k); the gate T2g of the reference signal transistor T2 is coupled to a second scan signal line GL2(i). The reference signal transistor T2(i,k) is configured to transmit a reference signal applied to the reference signal line VIN2 to the gate T3g of the driving transistor T3(i,k) and the second plate C12 of the capacitor Cst(i,k) in response to a second scan signal applied to the second scan signal line GL2(i).

[0099] In the second pixel driving circuit Q(j,k), the reference signal transistor T2(j,k) is configured to transmit the reference signal applied to the reference signal line VIN2 to the gate T3g of the driving transistor T3(j,k) and the second plate C12 of the capacitor Cst(j,k) in response to the second scan signal applied to the second scan signal line GL2(j). For a detailed description of the reference signal transistor T2(j,k), please refer to the relevant introduction of the reference signal transistor T2(i,k) in the first pixel driving circuit Q(i,k) above.

[0100] In some embodiments, the first pixel driving circuit Q(i,k) further includes a first reset transistor T4(h,k). The first reset transistor T4(h,k) can be shared by the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(j,k), and includes a gate T4g, a first electrode T41, and a second electrode T42.

[0101] For example, the second terminal T42 of the first reset transistor T4(h,k) is configured to write an initialization signal; for example, the second terminal T42 of the first reset transistor T4(h,k) is coupled to the initial signal line VIN1. The first terminal T41 of the first reset transistor T4(h,k) is coupled to the first terminal T31 of the driving transistor T3(i,k) of the first pixel driving circuit Q(i,k) and the first terminal T31 of the driving transistor T3(j,k) of the second pixel driving circuit Q(j,k). The gate T4g of the first reset transistor T4(h,k) is coupled to the second light emission control signal line EML2(h). The first reset transistor T4(h,k) is configured to transmit the initialization signal applied to the initial signal line VIN1 to the first terminal T31 of the driving transistor T3(i,k) of the first pixel driving circuit Q(i,k) and the first terminal T31 of the driving transistor T3(j,k) of the second pixel driving circuit Q(j,k) in response to the second light emission control signal applied to the second light emission control signal line EML2(h).

[0102] In some embodiments, the first pixel driving circuit Q(i,k) further includes a first light-emitting transistor T5(h,k). The first light-emitting transistor T5(h,k) can be shared by the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(j,k), and includes a gate T5g, a first electrode T51, and a second electrode T52.

[0103] For example, the first terminal T51 of the first light-emitting control transistor T5(h,k) is configured to write a light-emitting signal; for example, the first terminal T51 of the first light-emitting control transistor T5(h,k) is coupled to the first power supply voltage terminal VDD. The second terminal T52 of the first light-emitting control transistor T5(h,k) is coupled to the first terminal T31 of the driving transistor T3(i,k) of the first pixel driving circuit Q(i,k) and the first terminal T31 of the driving transistor T3(j,k) of the second pixel driving circuit Q(j,k). The gate T5g of the first light-emitting control transistor T5(h,k) is coupled to the first light-emitting control signal line EML1(h). The first light-emitting control transistor T5(h,k) is configured to, in response to the first light-emitting control signal applied to the first light-emitting control signal line EML1(h), transmit the voltage applied to the first power supply voltage terminal VDD to the first terminal T31 of the driving transistor T3(i,k) of the first pixel driving circuit Q(i,k) and the first terminal T31 of the driving transistor T3(j,k) of the second pixel driving circuit Q(j,k). That is, the first light-emitting control transistor T5(h,k) can control the on / off state of the path from the first power supply voltage terminal VDD, through the first light-emitting device ED(i,k), to the second power supply voltage terminal VSS, thereby controlling the light-emitting duration of the first light-emitting device ED(i,k), and thus controlling the brightness of the first light-emitting device ED(i,k) (the brightness of the sub-pixel to which the first light-emitting device (i,k) belongs) during the display panel displaying one frame of image. Similarly, the first light-emitting control transistor T5(h,k) can also control the light-emitting duration of the second light-emitting device ED(j,k).

[0104] The following is an introduction Figure 4 A driving method for a pixel driving circuit group F (including a first pixel driving circuit and a second pixel driving circuit). Exemplarily, this driving method may include several stages to compensate for the written data signal. See [link to relevant documentation]. Figure 4 and Figure 5 The driving methods for pixel driving circuit group F include:

[0105] In the first stage S1, the pixel driving circuit group F resets the second terminals T32 of driving transistors T3(i,k) and T3(j,k). Furthermore, the pixel driving circuit group F writes reference signals to the gates T3g of both driving transistors T3(i,k) and T3g of T3(j,k).

[0106] Specifically, the first stage S1 includes the first sub-stage S1(i) and the second sub-stage S1(j).

[0107] In the first sub-stage S1(i), in the first pixel driving circuit Q(i,k), the reference signal transistor T2(i,k) and the first reset transistor T4(h,k) are both turned on; the data writing transistor T1(i,k) and the first light-emitting transistor T5(h,k) can be turned off.

[0108] The reference signal transistor T2(i,k) responds to the second scan signal G2(i) provided by the second scan signal line GL2(i) being at an effective voltage (e.g., high level), and transmits the reference signal Vref applied to the reference signal line VIN2 to the gate T3g of the driving transistor T3(i,k), causing the driving transistor T3(i,k) to turn on. The first reset transistor T4(h,k) responds to the second light emission control signal EM2(h) transmitted by the second light emission control signal line EML2(h) being at an effective voltage (e.g., high level), and transmits the initialization signal applied to the initialization signal line VIN1 to the first terminal T31 of the driving transistor T3(i,k), causing the second terminal T32 of the driving transistor T3(i,k) to be reset.

[0109] In the second sub-stage S1(j), in the second pixel driving circuit Q(j,k), the reference signal transistor T2(j,k) is turned on; the data writing transistor T1(j,k) and the first light-emitting transistor T5(h,k) can be turned off. In response to the second scan signal G2(j) provided by the second scan signal line GL2(j) being an effective voltage (e.g., high level), the reference signal transistor T2(j,k) transmits the reference signal Vref applied to the reference signal line VIN2 to the gate T3g of the driving transistor T3(j,k), causing the driving transistor T3(j,k) to turn on. Furthermore, the first reset transistor T4(h,k) remains on, causing the initialization signal to be transmitted to the second terminal T32 of the driving transistor T3(j,k), thus resetting the second terminal T32 of the driving transistor T3(j,k).

[0110] Second stage S2: The pixel driving circuit group F performs threshold voltage compensation on the second terminals of driving transistors T3(i,k) and T3(j,k).

[0111] Specifically, the second phase S2 may include the first sub-phase S21 and the second sub-phase S22.

[0112] In the first sub-stage S21, the reference signal transistor T2(i,k), the driving transistor T3(i,k), the reference signal transistor T2(j,k), and the driving transistor T3(j,k) remain on; the first light-emitting transistor T5(h,k) is on; and the first reset transistor T4(h,k), the data writing transistor T1(j,k), and the data writing transistor T1(i,k) are off.

[0113] In response to the first light-emitting transistor T5(h,k) receiving a valid voltage (e.g., a high level) from the first light-emitting control signal line EML1(h), the first light-emitting transistor T5(h,k) transmits the voltage applied to the first power supply voltage terminal VDD to the first terminals T31 of the driving transistors T3(i,k) and T3(j,k), causing both capacitors Cst(i,k) and Cst(j,k) to charge. This results in the voltage at the second terminal T32 of the driving transistor T3(i,k) (which can also be considered the first plate C11 of capacitor Cst(i,k), or the anode of the first light-emitting device ED(i,k)) reaching Vref. Vth (Vth is the threshold voltage of the third transistor T3(i,k)). Similarly, the voltage at the second terminal T32 driving T3(j,k) reaches Vref. Vth (Vth is the threshold voltage of the third transistor T3(j,k)).

[0114] In the second sub-stage S22, the first light-emitting transistor T5(h,k) and the driving transistor T3(i,k) remain on; the reference signal transistor T2(i,k), the first reset transistor T4(h,k), and the data writing transistor T1(i,k) are off.

[0115] Since the voltage across capacitor Cst(i,k) does not change abruptly, the voltage at the second terminal T32 of driving transistor T3(i,k) remains at Vref. Vth.

[0116] In the third stage S3, the pixel driving circuit group F writes data signals to the gate T3g of the driving transistor T3(i,k) and the gate T3g of the driving transistor T3(j,k).

[0117] Specifically, the third stage S3 includes the first sub-stage S3(i) and the second sub-stage S3(j).

[0118] In the first sub-stage S3(i), the data writing transistor T1(i,k) and the driving transistor T3(i,k) are turned on, while the reference signal transistor T2(i,k), the first light-emitting transistor T5(h,k), and the first reset transistor T4(h,k) can be turned off.

[0119] In response to the first scan signal G1(i) provided by the first scan signal line GL1(i) being an effective voltage (e.g., high level), the data write transistor T1(i,k) transmits the data signal Vdata(i,k) applied to the data line DL(k) to the gate T3g of the driving transistor T3(i,k). The voltage difference (e.g., the gate-source voltage) between the gate T3g of the driving transistor T3(i,k) and the second terminal T32 of the driving transistor T3(i,k) is Vdata(i,k) - (Vref) Vth), which is the voltage difference across capacitor Cst(i,k).

[0120] In the second sub-stage S3(j), the data writing transistor T1(j,k) and the driving transistor T3(j,k) are turned on, while the reference signal transistor T2(j,k), the first light-emitting transistor T5(h,k), and the first reset transistor T4(h,k) are turned off.

[0121] The data writing transistor T1(j,k) responds to the first scan signal G1(j) provided by the first scan signal line GL1(j) being an effective voltage (e.g., high level), and transmits the data signal Vdata(j,k) applied to the data line DL(k) to the gate T3g of the driving transistor T3(j,k). The voltage difference between the gate T3g of the driving transistor T3(j,k) and the second terminal T32 of the driving transistor T3(j,k) is Vdata(j,k) - (Vref) Vth), which is the voltage difference across capacitor Cst(j,k).

[0122] Fourth stage S4: In this stage, only the driving transistor T3 and the first light-emitting transistor T5(h,k) are turned on. The first light-emitting transistor T5(h,k) responds to the first light-emitting signal EM1(h) provided by the first light-emitting control signal line EML1(h) being an effective voltage (e.g., high level), and transmits the voltage applied to the first power supply voltage terminal VDD to the first terminals T31 of the driving transistors T3(i,k) and T3(j,k), causing both the first light-emitting device ED(i,k) and the second light-emitting device ED(j,k) to emit light.

[0123] Since the voltage across capacitor Cst does not change abruptly, the voltage difference between the gate T3g of driving transistor T3 and the second terminal T32 of driving transistor T3 remains in the third stage state, so that the magnitude of the current flowing through the first light-emitting device ED(i,k) and the second light-emitting device ED(j,k) is independent of their respective threshold voltages.

[0124] Figure 6 for Figure 4 The diagram shows the structure of pixel driving circuit group F.

[0125] In some embodiments, see Figure 6 The display panel may include a substrate and multiple layers disposed on the substrate. For example, the multiple layers may include: a first pattern layer 100, a second pattern layer 200, a third pattern layer 300, a first insulating layer YJ1, a fourth pattern layer 400, and a second insulating layer YJ2 disposed along a direction away from the substrate. These layers are used to form... Figure 4 The pixel driving circuit group F is shown.

[0126] In embodiments of this disclosure, a "patterned layer" may be a layer structure containing a specific pattern formed by forming at least one film layer using the same film deposition process and then performing a patterning process on the at least one film layer. Depending on the specific pattern, the patterning process may include multiple coating, exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights (or thicknesses).

[0127] See also Figure 6 Along the extension direction of the data line DL(k), the data writing transistor T1(i,k) of the first pixel driving circuit, the driving transistor T3(i,k) of the first pixel driving circuit, the driving transistor T3(j,k) of the second pixel driving circuit, and the data writing transistor T1(j,k) of the second pixel driving circuit are arranged in sequence.

[0128] For example, the extension direction of the data line DL(k) can be the second direction Y; it can also be the first direction X; or it can be an inclined direction, such as a 45° direction. The attached figure illustrates the extension direction of the data line DL(k) as the second direction Y. Specifically, the data writing transistor T1(i,k) of the first pixel driving circuit, the driving transistor T3(i,k) of the first pixel driving circuit, the driving transistor T3(j,k) of the second pixel driving circuit, and the data writing transistor T1(j,k) of the second pixel driving circuit can be arranged sequentially along the positive direction of the second direction Y (the side indicated by the arrow), or they can be arranged sequentially along the negative direction of the second direction Y (opposite to the positive direction). This arrangement ensures that, in the first and second pixel driving circuits, driving transistors T3(i,k) and T3(j,k) are located between data writing transistors T1(i,k) and T1(j,k); it can be said that the positions of data writing transistors T1(i,k) and T1(j,k) are approximately symmetrical relative to driving transistors T3(i,k) and T3(j,k). Because driving transistors T3(i,k) and T3(j,k) are close to each other, if they need to be coupled, they do not need to cross or bypass other transistors, thus facilitating their coupling and helping to reduce the space occupied by a single pixel driving circuit.

[0129] See also Figure 6 In the first pixel driving circuit Q(i,k), the first plate C11 of capacitor Cst(i,k) is coupled to the second plate T32 of driving transistor T3(i,k) at the first coupling position P1, and is coupled to the first light-emitting device at the second coupling position P2; the second coupling position P2 is located on the side away from the data writing transistor T1(i,k) at the first coupling position P1. In the second pixel driving circuit Q(j,k), the first plate C11 of capacitor Cst(j,k) is coupled to the second plate T32 of driving transistor T3(j,k) at the third coupling position P3; the first plate C11 of capacitor Cst(j,k) is coupled to the second light-emitting device at the fourth coupling position P4. The fourth coupling position P4 is located between the third coupling position P3 and the data writing transistor T1(j,k).

[0130] For example, along the positive direction of the second direction Y, the first coupling position P1 and the second coupling position P2 are arranged sequentially; along the positive direction of the second direction Y, the third coupling position P3 and the fourth coupling position P4 are also arranged sequentially. It can be said that the relative positions of the first coupling position P1 and the second coupling position P2 in the extension direction of the data line (e.g., the second direction Y) (e.g., the second coupling position P2 is located positively upwards in the second direction Y of the first coupling position P1) are the same as the relative positions of the third coupling position P3 and the fourth coupling position P4 in the extension direction of the data line (e.g., the fourth coupling position P4 is located positively upwards in the second direction Y of the third coupling position P3). It can also be said that the second coupling position P2 and the fourth coupling position P4 are asymmetrically arranged relative to the first coupling position P1 and the third coupling position P3.

[0131] Based on the premise that the positions of the two data write transistors T1(i,k) and T1(j,k) are roughly symmetrical relative to the driving transistors T3(i,k) and T3(j,k), an easy-to-think solution is to also symmetrically arrange the second coupling position P2 and the fourth coupling position P4 relative to the first coupling position P1 and the third coupling position P3 (for example, the second coupling position P2 and the fourth coupling position P4 are located between the first coupling position P1 and the third coupling position P3). In contrast to this solution, in this embodiment, the second coupling position P2 and the fourth coupling position P4 are asymmetrically arranged, which helps to ensure the distance between the second coupling position P2 and the fourth coupling position P4 in the pixel driving circuit group F.

[0132] For a column of pixel driving circuits, the second coupling position P2 and the fourth coupling position P4 can be alternately set. Then the distance between any two adjacent positions used for coupling the light-emitting device (the second coupling position P2 and the fourth coupling position P4) in the second direction Y can be approximately equal. The distance between two coupling positions (the second coupling position P2 and the fourth coupling position P4) in the second direction Y means the distance between the geometric center (or geometric centroid) of the two coupling positions (the second coupling position P2 and the fourth coupling position P4) in the second direction Y. For example, if the number of a column of pixel driving circuits is 2n, then 2n-1 of the above distances can be obtained, denoted as L(1) to L(2n-1). The ratio of the difference between the maximum and minimum values ​​of these distances to the average value of these distances is, for example, less than or equal to 10%, 8%, 5%, 4%, or 2%, etc.

[0133] Figure 7 In order to be in Figure 6 Based on this, a structural diagram of the anode of the light-emitting device has been added.

[0134] In some embodiments, see Figure 7The display panel may further include a fifth pattern layer 500 and a pixel definition layer PDL disposed on the side of the second insulating layer YJ2 away from the substrate. For example, the pixel definition layer PDL is located on the side of the fifth pattern layer 500 away from the substrate. Of course, it is also possible to form the pixel definition layer PDL first and then the fifth pattern layer 500.

[0135] The fifth pattern layer 500 includes electrodes (e.g., anodes) for multiple light-emitting devices (EDs). For example, Figure 7 In the middle, the fifth pattern layer 500 includes the anode of the first light-emitting device ED(i,k) and the anode of the second light-emitting device ED(j,k).

[0136] The pixel definition layer (PDL) has multiple pixel openings K, wherein each sub-pixel may have one pixel opening K to expose at least a portion of the electrode (e.g., anode) of the light-emitting device (ED) in that sub-pixel. In each pixel opening K, the light-emitting functional layer described above can be formed by processes such as vapor deposition; thereafter, an electrode layer covering these light-emitting functional layers can be formed to serve as another electrode (e.g., cathode) for all light-emitting devices.

[0137] The pixel opening of a sub-pixel (e.g., a sub-pixel containing a second pixel driving circuit) can be located between the second coupling position P2 and the fourth coupling position P4, thus avoiding the recesses at these coupling positions. In conjunction with the above description, this embodiment can reduce the space occupied by a single pixel driving circuit while ensuring the distance between the second coupling position P2 and the fourth coupling position P4, thereby minimizing the impact on the pixel opening of the sub-pixel.

[0138] In some embodiments, see continue to see Figure 6 The first light-emitting control transistor T5(h,k) is located on the side of the driving transistor T3(i,k) away from the data writing transistor T1(i,k), and similarly, the driving transistor T3(j,k) is also located on the side of the driving transistor T3(j,k) away from the data writing transistor T1(j,k). Alternatively, it can be said that the first light-emitting control transistor T5(h,k) is located between the driving transistors T3(i,k) and T3(j,k). Since the first light-emitting control transistor T5(h,k) is shared by the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(i,k), this placement minimizes the number of lines crossed and simplifies the structure.

[0139] In some embodiments, see continue to see Figure 6The first reset transistor T4(h,k) is located on the side of the driving transistor T3(i,k) away from the data writing transistor T1(i,k), and similarly, the driving transistor T3(j,k) is also located on the side of the driving transistor T3(j,k) away from the data writing transistor T1(j,k). Alternatively, the first reset transistor T4(h,k) can be described as being located between the driving transistors T3(i,k) and T3(j,k). Since the first reset transistor T4(h,k) is shared by the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(i,k), this placement minimizes the number of cross-line connections and simplifies the structure.

[0140] It should be noted that the first light-emitting control transistor T5(h,k) and the first reset transistor T4(h,k) can both be located between the driving transistors T3(i,k) and T3(j,k). In some possible implementations, the first light-emitting control transistor T5(h,k) and the first reset transistor T4(h,k) are arranged sequentially along the extension direction of the data line (e.g., the positive direction of the second direction Y); that is, the first reset transistor T4(h,k) is closer to the driving transistor T3(j,k) than the first light-emitting control transistor T5(h,k). In other possible implementations, the first reset transistor T4(h,k) and the first light-emitting control transistor T5(h,k) are arranged sequentially along the extension direction of the data line (e.g., the positive direction of the second direction Y).

[0141] In some embodiments, see continue to see Figure 6 In both the first and second pixel driving circuits, the reference signal transistor T2 is located on the side of the data writing transistor T1 away from the driving transistor T3. Specifically, in the first pixel driving circuit, the reference signal transistor T2(i,k) is located on the side of the data writing transistor T1(i,k) away from the driving transistor T3(i,k). In the second pixel driving circuit, the reference signal transistor T2(j,k) is located on the side of the data writing transistor T1(j,k) away from the driving transistor T3(j,k). In other words, the reference signal transistors T2(i,k) and T2(j,k) are located outside the data writing transistors T1(i,k) and T1(j,k), not between them. Therefore, it can be said that the reference signal transistors T2(i,k) and T2(j,k) are also symmetrically arranged compared to the data writing transistors T1(i,k) and T1(j,k).

[0142] In the display panel, the reference signal line VIN2 and the data line DL(k) can extend in the same direction, that is, both can extend along the second direction Y. Since the first terminals T21(i,k) and T21(i,k) of the reference signal transistors T2(i,k) and T21(j,k) are both coupled to the reference signal line VIN2, a connecting line (hereinafter referred to as reference signal connecting line 111) is needed to transmit the signal between them. Therefore, two reference signal transistors T2 that are close to each other in two adjacent pixel driving circuit groups F can be coupled to the reference signal line VIN2 through a single reference signal connecting line 111. For example, reference signal transistors T2(i+1,k) and T2(j,k) can be coupled to a single reference signal connection line 111; wherein, reference signal transistor T2(i+1,k) is the reference signal transistor in the (i+1)th row and kth column pixel driving circuit; or, in other words, along the positive direction of the second direction Y, reference signal transistor T2(i+1,k) is located in the row below reference signal transistor T2(j,k). Similarly, reference signal transistors T2(i,k) and T2(j-1,k) can be coupled to a single reference signal connection line 111; wherein, reference signal transistor T2(j-1,k) is the reference signal transistor in the (j-1)th row and kth column pixel driving circuit. This reduces the number of reference signal connection lines 111, helping to reduce the space occupied by a single pixel driving circuit, thereby increasing the pixel density unit (Pixels Per Inch, PPI) of the display panel.

[0143] For example, the reference signal line 111 extends in the first direction X, that is, the reference signal line 111 can be a straight line.

[0144] Figure 8 , Figure 10 , Figure 14 and Figure 15 for Figure 7 A schematic diagram of a portion of the layers contained herein. Below, we will combine... Figure 8 , Figure 10 , Figure 14 and Figure 15 right Figure 7 The layers in the display panel are described in detail.

[0145] The substrate can be a flexible substrate, such as polyimide (PI). Alternatively, the substrate can be a rigid substrate. Rigid substrates are made of materials such as glass, sapphire, or hard resin materials.

[0146] Formed on the substrate Figure 8 The first pattern layer 100 shown and Figure 10After the second pattern layer 200 shown, it is possible to obtain Figure 13 The structure shown can at least form Figure 7 In addition to the multiple transistors in the circuit, auxiliary patterns can also be formed (such as reference signal connection line 111, etc.).

[0147] To simplify the description, if special explanations are needed for different devices or signal lines, serial numbers are added; otherwise, no serial numbers are added. For example, data write transistor T1(i,k) and data write transistor T1(j,k) are different devices, but in the following text, data write transistor T1 can refer to either data write transistor T1(i,k) or data write transistor T1(j,k). Similarly, the driving transistor T3, reference signal transistor T2, first reset transistor T4, first light-emitting transistor T5, capacitor Cst, first scan signal line GL1, second scan signal line GL2, second reset transistor T6, and second light-emitting transistor T7 are also described in a simplified manner.

[0148] See Figure 8 The first pattern layer 100 has multiple active regions and multiple conductive regions; wherein, the conductive regions may include areas on both sides of each active region; or they may be areas of other patterns (e.g., reference signal connection lines 111). The active regions are made of semiconductors, such as polysilicon. The conductive regions are made of ion-doped semiconductors, such as polysilicon doped with P (phosphorus) ions, or polysilicon doped with B (boron) ions. Figure 8 In the first pattern layer 100 shown, with Figure 10 The area of ​​the second pattern layer 200 shown that faces the thickness direction of the display panel is the active area, and the other areas are the conductive areas.

[0149] The first patterned layer 100 may include active layers of multiple transistors, and first and second electrodes located on both sides of the active layers. The active layer of each transistor corresponds to at least one (e.g., one, or two) active region. The first or second electrode of each transistor corresponds to at least one (e.g., one) conductive region.

[0150] For example, see [link to previous article] Figure 8 The first pattern layer 100 may include: an active layer T3a, a first electrode T31, and a second electrode T32 for the driving transistor T3; an active layer T1a, a first electrode T11, and a second electrode T12 for the data writing transistor T1. The first pattern layer 100 may also include an active layer T2a, a first electrode T21, and a second electrode T22 for the reference signal transistor T2; an active layer T4a, a first electrode T41, and a second electrode T42 for the first reset transistor T4; an active layer T5a, a first electrode T51, and a second electrode T52 for the first light-emitting transistor T5; and a reference signal connection line 111.

[0151] For example, the reference signal connection line 111 and the first terminal T21 of the reference signal transistor T2 are in the same conductive region. The second terminal T22 of the reference signal transistor T2 and the second terminal T12 of the signal writing transistor T1 are in the same conductive region. The first terminal T41 of the first reset transistor T4(h,k) and the first terminal T31 of the drive transistor T3(j,k) are in the same conductive region.

[0152] For example, see Figure 9 The active layer T3a of the driving transistor T3 includes a plurality of semiconductor segments that are sequentially spaced and coupled to each other along the extension direction of the data line DL(k). The semiconductor segments are generally parallel. The semiconductor segments are coupled to each other via connecting conductive segments. In some examples, the extension direction of the semiconductor segments is along a first direction X; wherein the angle between the extension direction of the semiconductor segments and the first direction X can be 0° to 5°. In other examples, the number of semiconductor segments can be two, or at least two.

[0153] In one possible implementation, in the first pixel driving circuit Q(i,k), the second coupling position P2 is located on the side of the plurality of semiconductor segments away from the first coupling position P1. In the second pixel driving circuit Q(j,k), the fourth coupling position P4 is located on the side of the plurality of semiconductor segments closer to the third coupling position P3. In some examples, in the first pixel driving circuit Q(i,k), the plurality of semiconductor segments are located between the first coupling position P1 and the second coupling position P2. In the second pixel driving circuit Q(j,k), the third coupling position P3 is located between the fourth coupling position P4 and the plurality of semiconductor segments.

[0154] See Figure 10 The material of the second pattern layer 200 is a conductive material; for example, it can be a metal; the metal material can be a single metal such as gold, silver, or copper, or its alloys. It can also be a non-metallic material; the non-metallic material can be graphite, etc.

[0155] The second pattern layer 200 may include: the gate T3g of the driving transistor T3 and the gate T1g of the data writing transistor T1. The second pattern layer 200 may also include: the gate T2g of the reference signal transistor T2, the gate T4g of the first reset transistor T4(h,k), the gate T5g of the first light-emitting transistor T5(h,k), and a connecting line (first connecting line 210).

[0156] Figure 11 The gate structure diagram of the transistor T1(i,k) for writing data. Figure 12 The active layer structure diagram for writing data to transistor T1(i,k).

[0157] For example, see Figure 11The data write transistor T1 has a dual-gate structure to reduce leakage current. The gate T1g of the data write transistor T1 includes two first sub-gates coupled to each other, and the data write transistor T1 has a first groove T1g3 that separates the two first sub-gates.

[0158] Specifically, see Figure 11 and Figure 12 The active layer of the data writing transistor T1 has two active regions (denoted as the first active region T1a1 and the second active region T1a2), which are connected by a conductive region (denoted as the first conductive region 112) between them. The gate T1g of the data writing transistor T1 includes two first sub-gates (denoted as the first sub-gate T1g1 and the first sub-gate T1g2) distributed along the arrangement direction of the two active regions, and a connecting portion T1g4 connecting the two first sub-gates (the first sub-gate T1g1 and the first sub-gate T1g2) together. Along the thickness direction of the display panel, the two active regions and the two first sub-gates are respectively directly opposite each other (i.e., the first active region T1a1 is directly opposite the first sub-gate T1g1, and the second active region T1a2 is directly opposite the first sub-gate T1g2), thereby forming a dual-gate structure. For example, the gate T1g of the data writing transistor T1 may have a first groove T1g3, which can separate the two first sub-gates (first sub-gate T1g1 and first sub-gate T1g2).

[0159] It should be noted that, Figure 11 The dashed line is to distinguish the first sub-gate from the conductive part T1g4, which can be integrally formed.

[0160] For example, both the reference signal transistor T2 and the first reset transistor T4(h,k) can be dual-gate structures. The gate T2g of the reference signal transistor T2 includes two mutually coupled second sub-gates, and the reference signal transistor T2 has a second groove that separates the two second sub-gates. The gate T2g of the first reset transistor T4(h,k) includes two mutually coupled third sub-gates, and the first reset transistor T4(h,k) has a third groove that separates the two third sub-gates.

[0161] The structures of the reference signal transistor T2 and the first reset transistor T4(h,k) are similar to those of the data writing transistor T1. Therefore, the structures of the reference signal transistor T2 and the first reset transistor T4(h,k) can be found in the relevant description of the data writing transistor T1.

[0162] For example, when the gate T1g of the data writing transistor T1 has a first groove T1g3, in the first pixel driving circuit, the openings of the first groove T1g3 and the second groove face opposite directions. This facilitates the arrangement of the first scan signal line GL1 and the second scan signal line GL2 in the same pixel driving circuit, preventing them from being too close to each other.

[0163] For example, when the gate T1g of the data writing transistor T1 has a first groove T1g3, in the second pixel driving circuit, the openings of the first groove T1g3 and the second groove face opposite directions.

[0164] For example, when the gate T1g of the data writing transistor T1 has a first groove T1g3, in the first pixel driving circuit, the openings of the first groove T1g3 and the second groove face opposite directions; in the second pixel driving circuit, the openings of the first groove T1g3 and the second groove face opposite directions.

[0165] For example, the openings of the first groove T1g3 in the first pixel driving circuit Q(i,k) and the first groove T1g3 in the second pixel driving circuit Q(j,k) face opposite directions.

[0166] For example, the second grooves of the reference signal transistor T2(i,k) and the second grooves of the reference signal transistor T2(j,k) have openings facing opposite directions.

[0167] For example, the second plate C12 of capacitor Cst has the same pattern as the gate T3g of driving transistor T3. However, the second plate C12 of capacitor Cst(i,k) is different from the second plate C12 of capacitor Cst(j,k).

[0168] For example, see Figure 13 Based on the extension direction of the data line DL(k) mentioned above, the data write transistor T1(i,k), driving transistor T3(i,k), first light-emitting transistor T5(h,k), first reset transistor T4(h,k), driving transistor T3(j,k), and data write transistor T1(j,k) are arranged in sequence. The active layer and gate that constitute these transistors are also arranged in sequence according to their positions, and will not be described here.

[0169] For example, the first connection line 210 is coupled to the first terminal T31 of the driving transistor T3(i,k), the second terminal T52 of the first light-emitting transistor T5(h,k), the first terminal T41 of the first reset transistor T4(h,k), and the first terminal T31 of the driving transistor T3(i,k).

[0170] See Figure 14The material of the third pattern layer 300 is a conductive material, and you can refer to the relevant description of the second conductive pattern layer 200 for details.

[0171] The third pattern layer 300 includes the first plate C11 of the capacitor Cst. It also includes a first power supply voltage line 330. The first power supply voltage line 330 may extend along a second direction Y.

[0172] For example, the overlapping areas of the first plate C11 and the second plate C12 of capacitor Cst(i,k) and the first plate C11 and the second plate C12 of capacitor Cst(j,k) are equal, that is, the capacitance value of capacitor Cst(i,k) and the capacitance value of capacitor Cst(j,k) are equal.

[0173] For example, the first plate C11 of capacitor Cst(i,k) is not the same as the first plate C11 of capacitor Cst(J,k).

[0174] See Figure 15 The material of the fourth pattern layer 400 is a conductive material, and you can refer to the relevant description of the second conductive pattern layer 200 for details.

[0175] For example, the fourth pattern layer 400 includes a first transition pattern 410 and a second transition pattern 420. The fourth pattern layer 400 also includes a first scan signal line GL1, a second scan signal line GL2, a second power supply voltage line 430, an initialization signal line VIN1, a first light emission control signal line EML1, and a second light emission control signal line EML2. The second power supply voltage line 430 is coupled to the first power supply voltage line GL2 and is configured to provide a power supply voltage to the first power supply voltage terminal VDD.

[0176] For example, along the data line extension direction (the positive direction of the second direction Y), the second scan signal line GL2(i), the first scan signal line GL1(i), the first adapter pattern 410, the first light emission control signal line EML1(h), the second power supply voltage line 430, the initialization signal line VIN1, the second light emission control signal line EML2(h), the second adapter pattern 420, the first scan signal line GL1(j), and the second scan signal line GL2(j) are arranged in sequence.

[0177] For example, the first scan signal line GL1, the second scan signal line GL2, the second power supply voltage line 430, the initialization signal line VIN1, the first light emission control signal line EML1(h), and the second light emission control signal line EML2(h) all extend along the first direction X.

[0178] See Figure 6 and Figure 16The first insulating layer YJ1 is located between the third pattern layer 300 and the fourth pattern layer 400. The second insulating layer YJ2 is located between the fourth pattern layer 400 and the light-emitting device ED. The display panel also includes a fourth insulating layer YJ4 located between the first pattern layer 100 (e.g., the gate T3a of the driving transistor (i,k)) and the substrate 600, and a third insulating layer YJ3 located between the first pattern layer 100 and the second pattern layer 200.

[0179] For example, the second insulating layer YJ2 includes a stacked inorganic insulating layer YJ10 and an organic insulating layer YJ20, the organic insulating layer YJ20 being in contact with a light-emitting device ED (e.g., the anode of the light-emitting device ED), and the inorganic insulating layer YJ10 being in contact with a fourth layer 400.

[0180] For example, the first insulating layer YJ1 has a first through hole YJ11 located at the second coupling position P2, and also has a third through hole YJ12 located at the fourth coupling position P4.

[0181] For example, in the first pixel driving circuit Q(i,k), the first insulating layer YJ1 is located between the first transition pattern 410 and the first plate C11 of the capacitor Cst(i,k). In the second pixel driving circuit Q(j,k), the first insulating layer YJ1 is located between the second transition pattern 420 and the first plate C11 of the capacitor Cst(j,k).

[0182] For example, the second insulating layer YJ2 has a second through hole YJ21 located at the second coupling position P2, and also has a fourth through hole YJ22 located at the fourth coupling position P4.

[0183] For example, the second insulating layer YJ2 is located between the first transition pattern 410 and the first light-emitting device ED(i,k). The second insulating layer YJ2 is also located between the second transition pattern 420 and the second light-emitting device ED(j,k). For example, the second insulating layer YJ2 is located between the first transition pattern 410 and the anode of the first light-emitting device ED(i,k). The second insulating layer YJ2 is also located between the second transition pattern 420 and the anode of the second light-emitting device ED(j,k).

[0184] In one feasible example, the first transition pattern 410 is coupled to the first plate C11 of the capacitor Cst(i,k) at a first through-hole (YJ11) and to the anode of the first light-emitting device ED(i,k) at a second through-hole (YJ21). The second transition pattern 420 is coupled to the first plate C11 of the capacitor Cst(j,k) at a third through-hole (YJ12) and to the anode of the second light-emitting device ED(j,k) at a fourth through-hole (YJ22).

[0185] In one feasible example, in the thickness direction of the display panel (i.e., the plane perpendicular to the second direction Y and the first direction X), the first through-hole YJ11 and the second through-hole YJ21 are staggered; meaning that the orthographic projections of the first through-hole YJ11 and the second through-hole YJ21 on the substrate do not overlap. The third through-hole YJ12 and the fourth through-hole YJ22 are also staggered; meaning that the orthographic projections of the third through-hole YJ12 and the fourth through-hole YJ22 on the substrate do not overlap.

[0186] In one feasible example, the first transition pattern 410 and the second transition pattern 420 are both approximately rectangular in shape, such as rectangles and rounded rectangles.

[0187] The long side of the first adapter pattern 410 is approximately parallel to the extension direction (second direction Y) of the data line DL(k), for example, the long side of the first adapter pattern 410 is parallel to the extension direction (second direction Y) of the data line DL(k); or, for example, the long side of the first adapter pattern 410 has an angle of 0~5° with the extension direction (second direction Y) of the data line DL(k). The first through hole YJ11 and the second through hole YJ21 are arranged sequentially along the long side of the first adapter pattern 410. At this time, there is a gap between the first through hole YJ11 and the second through hole YJ21 along the extension direction of the long side of the first adapter pattern 410. For example, in the positive direction of the second direction Y (the direction of arrow extension), the second through hole YJ21 and the first through hole YJ11 are arranged sequentially. For example, in the opposite direction of the second direction Y (the direction opposite to the positive direction), the second through hole YJ21 and the first through hole YJ11 are arranged sequentially.

[0188] The long side of the second adapter pattern 420 intersects the extension direction (second direction Y) of the data line DL(k). For example, the long side of the second adapter pattern 420 is perpendicular to the extension direction (second direction Y) of the data line DL(k), i.e., perpendicular to the first direction X. The fourth through hole YJ22 and the third through hole YJ12 are arranged sequentially along the long side of the second adapter pattern 420. At this time, there is a gap between the fourth through hole YJ22 and the third through hole YJ12 along the extension direction of the long side of the second adapter pattern 420. For example, in the positive direction of the first direction X (the direction of arrow extension), the fourth through hole YJ22 and the third through hole YJ12 are arranged sequentially. As another example, in the negative direction of the first direction X (the direction opposite to the positive direction), the fourth through hole YJ22 and the third through hole YJ12 are arranged sequentially. The projected areas of the first adapter pattern 410 and the second adapter pattern 420 in the thickness direction of the display panel are equal.

[0189] See Figure 17 and Figure 18In one feasible example, the line connecting the centers of the first through hole YJ11 and the second through hole YJ21 intersects the line connecting the centers of the third through hole YJ21 and the fourth through hole YJ22. For example, the angle α between the line connecting the centers of the second through hole YJ21 and the first through hole YJ11 and the positive direction of the first direction X is 0°~180° (e.g., 10°, 30°, 45°, 60°, 90°, 120°, 150°, etc.). The angle β between the line connecting the centers of the third through hole YJ21 and the fourth through hole YJ22 and the opposite direction of the first direction X is 0°~180° (e.g., 10°, 30°, 45°, 60°, 90°, 120°, 150°, etc.). α and β can be complementary or non-complementary.

[0190] See Figure 19 In one feasible example, the distance between the second via YJ21 and the fourth via YJ22 in the extension direction of the data line DL(k) is approximately equal to the pixel size of the display panel in the extension direction of the data line DL(k) (wherein the pixel size is determined by the resolution of the display panel, i.e., the width of the display panel divided by the number of rows of the pixel circuit). For example, in the same pixel driving circuit group F, in the extension direction of the data line DL(k) (the positive direction of the second direction Y), the distance between the second via YJ21 and the fourth via YJ22 is 95%~100% (e.g., 95%, 96%, 97%, 98%, 99%, 100%, etc.) of the pixel size of the display panel. Exemplarily, in the positive direction of the second direction Y (the direction of arrow extension), the distance H1 between the second via YJ21 and the fourth via YJ22 in the same pixel driving circuit group F; the distance H2 between the fourth via YJ22 and the second via YJ21 between two adjacent rows of pixel driving circuit groups F. If the number of pixel driving circuits is 2n, then n distances H1 and n-1 distances H2 can be obtained. The ratio of the average of the n distances H1 to the average of the n-1 distances H2 is, for example, less than or equal to 10%, 8%, 5%, 4%, or 2%.

[0191] Figure 20 This is a structural diagram of a group F of multiple pixel driving circuits arranged along the first direction X.

[0192] See Figure 20 Along the positive direction of the first direction X (the direction of arrow extension), multiple pixel driving circuit groups F constitute a display unit, denoted as F(1) to F(m). For example, along the positive direction of the first direction X (the direction of arrow extension), a display unit includes six pixel driving circuit groups F arranged sequentially, denoted as F(1) to F(6). Among them, pixel driving circuit groups F(1) and F(4) are... Figure 6In the diagram shown, pixel driving circuit groups F(2), F(3), F(5), and F(6) are mirror images of pixel driving circuit group F(1). The reference signal line VIN1 is located between pixel driving circuit groups F(3) and F(4). The power supply voltage line 330 is located on the side of pixel driving circuit group F(1) away from pixel driving circuit group F(2).

[0193] Figure 21 To be Figure 4 The circuit diagram in which the first reset transistor T4 is replaced with the second reset transistor T6.

[0194] In some embodiments, see Figure 21 Both the first pixel driving circuit and the second pixel driving circuit include a second reset transistor T6. The second reset transistor T6 includes a gate T6g, a first electrode T61, and a second electrode T62.

[0195] For example, the first terminal T61 of the second reset transistor T6 is coupled to the second terminal T32 of the driving transistor T3. For instance, the first terminal T61 of the second reset transistor T6(i,k) is coupled to the second terminal T32 of the driving transistor T3(i,k). The first terminal T61 of the second reset transistor T6(j,k) is coupled to the second terminal T32 of the driving transistor T3(j,k). The second terminal T62 of the second reset transistor T6 is coupled to the initialization signal line VIN1. The gate T6g of the second reset transistor T6 is coupled to the third scan signal line GL3. For instance, the gate T6g of the second reset transistor T6(i,k) is coupled to the third scan signal line GL3(i). The gate T6g of the second reset transistor T6(j,k) is coupled to the third scan signal line GL3(j).

[0196] See Figure 22 for Figure 21 The driving method of the pixel driving circuit group F.

[0197] The following is an introduction Figure 21 A driving method for a pixel driving circuit group (including a first pixel driving circuit and a second pixel driving circuit). Exemplarily, this driving method may include several stages to compensate for the written data signal. See [link to relevant documentation]. Figure 21 and Figure 22 The driving methods for pixel driving circuit group F include:

[0198] In the first stage S1, the pixel driving circuit group F resets the second terminals T32 of driving transistors T3(i,k) and T3(j,k). Furthermore, the pixel driving circuit group F writes reference signals to the gates T3g of both driving transistors T3(i,k) and T3g of T3(j,k).

[0199] Specifically, the first stage S1 includes the first sub-stage S1(i) and the second sub-stage S1(j).

[0200] In the first sub-stage S1(i), in the first pixel driving circuit Q(i,k), both the reference signal transistor T2(i,k) and the second reset transistor T6(i,k) are turned on; the data writing transistor T1(i,k) and the first light-emitting transistor T5(h,k) are turned off. In response to the second scan signal G2(i) provided by the second scan signal line GL2(i) being an effective voltage (e.g., high level), the reference signal transistor T2(i,k) transmits the reference signal Vref applied to the reference signal line VIN2 to the gate T3g of the driving transistor T3(i,k), causing the driving transistor T3(i,k) to turn on. In response to the third point scan signal G3(i) transmitted by the third scan signal line GL3(i) being an effective voltage (e.g., high level), the second reset transistor T6(i,k) transmits the initialization signal applied to the initialization signal line VIN1 to the second terminal T32 of the driving transistor T3(i,k) for reset.

[0201] In the second sub-stage S1(j), in the second pixel driving circuit Q(j,k), the reference signal transistor T2(j,k) and the second reset transistor T6(i,k) are turned on; the data writing transistor T1(j,k) and the first light-emitting transistor T5(h,k) are turned off. In response to the second scan signal G2(j) provided by the second scan signal line GL2(j) being an effective voltage (e.g., high level), the reference signal transistor T2(j,k) transmits the reference signal Vref applied to the reference signal line VIN2 to the gate T3g of the driving transistor T3(j,k), causing the driving transistor T3(j,k) to turn on. In response to the third point scan signal G3(j) transmitted by the third scan signal line GL3(j) being an effective voltage (e.g., high level), the second reset transistor T6(j,k) transmits the initialization signal applied to the initialization signal line VIN1 to the second terminal T32 of the driving transistor T3(j,k), thus resetting the second terminal T32 of the driving transistor T3(j,k).

[0202] Second stage S2: The pixel driving circuit group F performs threshold voltage compensation on the second terminals of driving transistors T3(i,k) and T3(j,k).

[0203] Specifically, the second phase S2 may include the first sub-phase S21 and the second sub-phase S22.

[0204] In the first sub-stage S21, the reference signal transistor T2(i,k), the driving transistor T3(i,k), the reference signal transistor T2(j,k), and the driving transistor T3(j,k) remain on; the first light-emitting transistor T5(h,k) is on; and the second reset transistor T6(i,k), the second reset transistor T6(j,k), the data writing transistor T1(j,k), and the data writing transistor T1(i,k) are off.

[0205] In response to the first light-emitting transistor T5(h,k) receiving a valid voltage (e.g., a high level) from the first light-emitting control signal line EML1(h), the first light-emitting transistor T5(h,k) transmits the voltage applied to the first power supply voltage terminal VDD to the first terminals T31 of the driving transistors T3(i,k) and T3(j,k), causing both capacitors Cst(i,k) and Cst(j,k) to charge. This results in the voltage at the second terminal T32 of the driving transistor T3(i,k) (which can also be considered the first plate C11 of capacitor Cst(i,k), or the anode of the first light-emitting device ED(i,k)) reaching Vref. Vth (Vth is the threshold voltage of the third transistor T3(i,k)). Similarly, the voltage at the second terminal T32 driving T3(j,k) reaches Vref. Vth (Vth is the threshold voltage of the third transistor T3(j,k)).

[0206] In the second sub-stage S22, the first light-emitting transistor T5(h,k) and the driving transistor T3(i,k) remain on; the reference signal transistor T2(i,k), the first reset transistor T4(h,k), and the data writing transistor T1(i,k) are off.

[0207] Since the voltage across capacitor Cst(i,k) does not change abruptly, the voltage at the second terminal T32 of driving transistor T3(i,k) remains at Vref. Vth.

[0208] In the third stage S3, the pixel driving circuit group F writes data signals to the gate T3g of the driving transistor T3(i,k) and the gate T3g of the driving transistor T3(j,k).

[0209] In the first sub-stage S3(i), the data writing transistor T1(i,k) and the driving transistor T3(i,k) are turned on, while the reference signal transistor T2(i,k), the first light-emitting transistor T5(h,k), and the first reset transistor T4(h,k) can be turned off.

[0210] In response to the first scan signal G1(i) provided by the first scan signal line GL1(i) being an effective voltage (e.g., high level), the data write transistor T1(i,k) transmits the data signal Vdata(i,k) applied to the data line DL(k) to the gate T3g of the driving transistor T3(i,k). The voltage difference (e.g., the gate-source voltage) between the gate T3g of the driving transistor T3(i,k) and the second terminal T32 of the driving transistor T3(i,k) is Vdata(i,k) - (Vref) Vth), which is the voltage difference across capacitor Cst(i,k).

[0211] In the second sub-stage S3(j), the data writing transistor T1(j,k) and the driving transistor T3(j,k) are turned on, while the reference signal transistor T2(j,k), the first light-emitting transistor T5(h,k), and the first reset transistor T4(h,k) are turned off.

[0212] The data writing transistor T1(j,k) responds to the first scan signal G1(j) provided by the first scan signal line GL1(j) being an effective voltage (e.g., high level), and transmits the data signal Vdata(j,k) applied to the data line DL(k) to the gate T3g of the driving transistor T3(j,k). The voltage difference between the gate T3g of the driving transistor T3(j,k) and the second terminal T32 of the driving transistor T3(j,k) is Vdata(j,k) - (Vref) Vth), which is the voltage difference across capacitor Cst(j,k).

[0213] Fourth stage S4: In this stage, only the driving transistor T3 and the first light-emitting transistor T5(h,k) are turned on. The first light-emitting transistor T5(h,k) responds to the first light-emitting signal EM1(h) provided by the first light-emitting control signal line EML1(h) being an effective voltage (e.g., high level), and transmits the voltage applied to the first power supply voltage terminal VDD to the first terminals T31 of the driving transistors T3(i,k) and T3(j,k), causing both the first light-emitting device ED(i,k) and the second light-emitting device ED(j,k) to emit light.

[0214] Since the voltage across capacitor Cst does not change abruptly, the voltage difference between the gate T3g of driving transistor T3 and the second terminal T32 of driving transistor T3 remains in the third stage state, so that the magnitude of the current flowing through the first light-emitting device ED(i,k) and the second light-emitting device ED(j,k) is independent of their respective threshold voltages.

[0215] In this embodiment, Figure 21The locations and connections of the data writing transistor T1, driving transistor T3, and reference signal transistor T2 in the corresponding block diagram can be found in the reference diagram. Figure 6 Related descriptions. Figure 18 Corresponding structural diagram and Figure 6 The structural diagram shows several differences between driving transistor T3(i,k) and driving transistor T3(j,k): for example, along the positive direction of the second direction Y (the direction of arrow extension), the second reset transistor T6(i,k), the first light-emitting transistor T5(h,k) and the second reset transistor T6(j,k) are arranged in sequence.

[0216] Figure 23 To be Figure 21 The circuit diagram in which the first light-emitting transistor T5 is replaced with the second light-emitting transistor T7.

[0217] In some embodiments, see Figure 23 Both the first pixel driving circuit Q(i,k) and the second pixel driving circuit Q(j,k) include a second light-emitting transistor T7. The second light-emitting transistor T7 includes a gate T7g, a first electrode T71, and a second electrode T72.

[0218] For example, the second terminal T72 of the second light-emitting transistor T7 is coupled to the first terminal T31 of the driving transistor T3. For instance, the second terminal T71 of the second light-emitting transistor T7(i,k) is coupled to the first terminal T31 of the driving transistor T3(i,k). The second terminal T71 of the second light-emitting transistor T7(j,k) is coupled to the first terminal T31 of the driving transistor T3(j,k). The first terminal T71 of the second light-emitting transistor T7 is coupled to the first power supply voltage line VDD. The gate T7g of the second light-emitting transistor T7 is coupled to the third light-emitting control line EML3. For instance, the gate T7g of the second light-emitting transistor T7(i,k) is coupled to the third light-emitting control line EML3(i). The gate T7g of the second light-emitting transistor T7(j,k) is coupled to the third light-emitting control line EML3(j).

[0219] See Figure 24 for Figure 23 The driving method of the pixel driving circuit group F.

[0220] The following is an introduction Figure 23 A driving method for a pixel driving circuit group F (including a first pixel driving circuit and a second pixel driving circuit). Exemplarily, this driving method may include several stages to compensate for the written data signal. See [link to relevant documentation]. Figure 23 and Figure 24 The driving methods for pixel driving circuit group F include:

[0221] In the first stage S1: In the first pixel driving circuit Q(i,k), both the reference signal transistor T2(i,k) and the second reset transistor T6(i,k) are turned on; the data writing transistor T1(i,k) and the second light-emitting transistor T7(i,k) can be turned off. In response to the second scan signal G2(i) provided by the second scan signal line GL2(i) being an effective voltage (e.g., high level), the reference signal transistor T2(i,k) transmits the reference signal Vref applied to the reference signal line VIN2 to the gate T3g of the driving transistor T3(i,k), causing the driving transistor T3(i,k) to turn on. In response to the third point scan signal G3(i) transmitted by the third scan signal line GL3(i) being an effective voltage (e.g., high level), the second reset transistor T6(i,k) transmits the initialization signal applied to the initialization signal line VIN1 to the second terminal T32 of the driving transistor T3(i,k). The second terminal T32 of the driving transistor T3(i,k) is reset.

[0222] Second stage S2: In the first sub-stage, the reference signal transistor T2(i,k) and the driving transistor T3(i,k) continue to be turned on; the second light-emitting transistor T7(i,k) is turned on; the second reset transistor T6(i,k) and the data writing transistor T1(i,k) are turned off.

[0223] In response to the third light-emitting signal EM3(i) provided by the third light-emitting control signal line EML3(i) being an effective voltage (e.g., high level), the second light-emitting transistor T7(i,k) transmits the voltage applied to the first power supply voltage terminal VDD to the first terminal T31 of the driving transistor T3(i,k), causing the capacitor Cst(i,k) to charge. This results in the voltage at the second terminal T32 of the driving transistor T3(i,k) (which can also be considered the first plate C11 of the capacitor Cst(i,k), or the anode of the first light-emitting device ED(i,k)) reaching Vref. Vth (Vth is the threshold voltage of the third transistor T3(i,k)).

[0224] In the second sub-stage, the second light-emitting transistor T7(i,k) and the driving transistor T3(i,k) remain on; the reference signal transistor T2(i,k), the first reset transistor T4(h,k), and the data writing transistor T1(i,k) are off.

[0225] Since the voltage across capacitor Cst(i,k) does not change abruptly, the voltage at the second terminal T32 of driving transistor T3(i,k) remains at Vref. Vth.

[0226] In the third stage S3: the data writing transistor T1(i,k) and the driving transistor T3(i,k) are turned on, while the reference signal transistor T2(i,k), the second light-emitting transistor T7(i,k), and the second reset transistor T6(i,k) are turned off. In response to the first scan signal G1(i) provided by the first scan signal line GL1(i) being an effective voltage (e.g., high level), the data writing transistor T1(i,k) transmits the data signal applied to the data line DL(k) to the gate T3g of the driving transistor T3(i,k), causing the driving transistor T3(i,k) to turn on. The voltage difference (e.g., the gate-source voltage) between the gate T3g of the driving transistor T3(i,k) and the second terminal T32 of the driving transistor T3(i,k) is Vdata(i,k) - (Vref) Vth), which is the voltage difference across capacitor Cst(i,k).

[0227] Phase 4 (S4): In this phase, only the driving transistor T3 and the first light-emitting transistor T5(h,k) are turned on. The second light-emitting transistor T7(i,k), in response to the effective voltage (e.g., high level) of the third light-emitting signal EM3(i) provided by the third light-emitting control signal line EML3(i), transmits the voltage applied to the first power supply voltage terminal VDD to the first terminal T31 of the driving transistor T3(i,k), causing the first light-emitting device ED(i,k) to emit light.

[0228] Since the voltage across capacitor Cst does not change abruptly, the voltage difference between the gate T3g of driving transistor T3 and the second terminal T32 of driving transistor T3 remains in the third stage state, so that the magnitude of the current flowing through the first light-emitting device ED(i,k) is independent of their respective threshold voltages.

[0229] It should be noted that, in Figure 21 In the illustrated embodiment, since the electrical components in the first pixel driving circuit and the second pixel driving circuit are coupled at identical positions, the driving method of this second pixel driving circuit can be referred to the relevant description of the first pixel driving circuit.

[0230] In this embodiment, Figure 23 The locations and connections of the data writing transistor T1, driving transistor T3, and reference signal transistor T2 in the corresponding block diagram can be found in the reference diagram. Figure 6 Related descriptions. Figure 19 Corresponding structural diagram and Figure 6The structural diagram shows several differences between driving transistors T3(i,k) and T3(j,k): for example, along the positive direction of the second direction Y (the direction of arrow extension), the second reset transistor T6(i,k), the second light-emitting transistor T7(i,k), the second light-emitting transistor T7(j,k), and the second reset transistor T6(j,k) are arranged in sequence. For instance, there is no first connection line between the first terminals T31 of driving transistor T3(i,k) and T31 of driving transistor T3(j,k) (i.e., they are not coupled).

[0231] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: Data cable; First light-emitting device and second light-emitting device; as well as The first pixel driving circuit and the second pixel driving circuit both include a capacitor, a driving transistor, and a data writing transistor; the data writing transistor is coupled to the data line and the driving transistor; the capacitor includes a first electrode and a second electrode disposed opposite to each other; wherein... Along the extension direction of the data line, the data writing transistor of the first pixel driving circuit, the driving transistor of the first pixel driving circuit, the driving transistor of the second pixel driving circuit, and the data writing transistor of the second pixel driving circuit are arranged in sequence. In the first pixel driving circuit, the first electrode plate is coupled to the driving transistor at a first coupling position and to the first light-emitting device at a second coupling position; the second coupling position is located on the side of the first coupling position away from the data writing transistor. In the second pixel driving circuit, the first electrode plate is coupled to the driving transistor at a third coupling position; and coupled to the second light-emitting device at a fourth coupling position; the fourth coupling position is located between the third coupling position and the data writing transistor.

2. The display panel according to claim 1, wherein, The driving transistor includes an active layer, which includes a plurality of semiconductor segments that are sequentially distributed and coupled to each other along the extension direction of the data line, and the extension direction of the semiconductor segments intersects the extension direction of the data line. In the first pixel driving circuit, the second coupling position is located on the side of the plurality of semiconductor segments away from the first coupling position; In the second pixel driving circuit, the fourth coupling position is located on the side of the plurality of semiconductor segments close to the third coupling position.

3. The display panel according to claim 1, further comprising: First adapter pattern; A first insulating layer is located between the first adapter pattern and the first electrode plate in the first pixel driving circuit, and has a first through hole located at the second coupling position; as well as, The second insulating layer is located between the first transition pattern and the first light-emitting device, and has a second through hole located at the second coupling position; Wherein, the first adapter pattern is coupled to the first electrode plate in the first pixel driving circuit at the first through hole, and coupled to the first light-emitting device at the second through hole; Along the thickness direction of the display panel, the first through hole and the second through hole are staggered.

4. The display panel according to claim 3, further comprising: Second transition pattern; The first insulating layer extends between the second transition pattern and the first electrode plate in the second pixel driving circuit, and the first insulating layer also has a third through hole located at the fourth coupling position. The second insulating layer extends between the second transition pattern and the second light-emitting device, and the second insulating layer has a fourth through-hole located at the fourth coupling position; The second adapter pattern is coupled to the first electrode plate in the second pixel driving circuit at the third through hole, and coupled to the second light-emitting device at the fourth through hole; Along the thickness direction of the display panel, the third through hole and the fourth through hole are staggered.

5. The display panel according to claim 4, wherein, The line connecting the centers of the first and second through holes intersects the line connecting the centers of the third and fourth through holes.

6. The display panel according to claim 4, wherein, Both the first and second transition patterns are approximately rectangular in shape. The first through hole and the second through hole are arranged sequentially along the long side of the first transition pattern; the third through hole and the fourth through hole are arranged sequentially along the long side of the second transition pattern.

7. The display panel according to claim 6, wherein, The long side of the first adapter pattern is approximately parallel to the extension direction of the data line; the long side of the second adapter pattern intersects the extension direction of the data line.

8. The display panel according to claim 4, wherein, The distance between the second through hole and the fourth through hole in the direction of extension of the data line is approximately equal to the pixel size of the display panel in the direction of extension of the data line.

9. The display panel according to claim 1, wherein, The first electrode plate of the first pixel driving circuit and the first electrode plate of the second pixel driving circuit have different shapes; the facing areas of the first electrode plate and the second electrode plate are equal.

10. The display panel according to claim 1, wherein, The second electrode plates of the first pixel driving circuit and the second pixel driving circuit have different shapes.

11. The display panel according to claim 1, wherein, The gate of the data writing transistor includes two first sub-gates coupled to each other, and the data writing transistor has a first groove that separates the two first sub-gates. The openings of the first groove in the first pixel driving circuit and the first groove in the second pixel driving circuit face opposite directions.

12. The display panel according to claim 1, wherein, The driving transistor includes a gate, a first electrode, and a second electrode, wherein the second electrode of the driving transistor is coupled to the first electrode plate. Both the first pixel driving circuit and the second pixel driving circuit further include a reference signal transistor; the reference signal transistor includes a gate, a first electrode, and a second electrode, wherein the first electrode is configured to write a reference signal, and the second electrode is coupled to the second electrode plate and the gate of the driving transistor; The reference signal transistor is located on the side of the data write transistor away from the drive transistor.

13. The display panel according to claim 12, further comprising: A reference signal connection line is located on the side of the reference signal transistor of the second pixel driving circuit away from the data write transistor, and intersects with and is insulated from the data line; the reference signal connection line is coupled to the reference signal transistor and is configured to provide the write reference signal.

14. The display panel according to claim 12, wherein, The gate of the reference signal transistor includes two second sub-gates coupled to each other, and the reference signal transistor has a second groove that separates the two second sub-gates.

15. The display panel according to claim 14, wherein, When the gate of the data writing transistor has a first groove, In the first pixel driving circuit, the openings of the first groove and the second groove face opposite directions; and / or, In the second pixel driving circuit, the openings of the first groove and the second groove face opposite directions.

16. The display panel according to claim 1, wherein, The first pixel driving circuit further includes a first light-emitting control transistor; the first light-emitting control transistor includes a gate, a first electrode, and a second electrode, wherein the first electrode of the first light-emitting control transistor is configured to write a first light-emitting signal, and the second electrode of the first light-emitting control transistor is coupled to the first electrode of the driving transistor in the first pixel driving circuit and the first electrode of the driving transistor in the second pixel driving circuit; the first light-emitting control transistor is located between the driving transistor in the first pixel driving circuit and the driving transistor in the second pixel driving circuit. or, Both the first pixel driving circuit and the second pixel driving circuit further include a second light-emitting control transistor; the second light-emitting control transistor includes a gate, a first electrode, and a second electrode, wherein the first electrode of the second light-emitting control transistor is configured to write a second light-emitting signal, and the second electrode of the second light-emitting control transistor is coupled to the first electrode of the driving transistor; the second light-emitting control transistor is located on the side of the driving transistor away from the data writing transistor.

17. The display panel according to any one of claims 1 to 16, wherein, The first pixel driving circuit further includes a first reset transistor; the first reset transistor includes a gate, a first electrode, and a second electrode, wherein the second electrode of the first reset transistor is configured to write a first initialization signal, and the first electrode of the first reset transistor is coupled to the first electrode of the driving transistor in the first pixel driving circuit and the first electrode of the driving transistor in the second pixel driving circuit; the first reset transistor is located between the driving transistor in the first pixel driving circuit and the driving transistor in the second pixel driving circuit. or, Both the first pixel driving circuit and the second pixel driving circuit further include a second reset transistor; the second reset transistor includes a gate, a first terminal and a second terminal, wherein the second terminal of the second reset transistor is configured to write a second initialization signal, and the first terminal of the second reset transistor is coupled to the second terminal of the driving transistor; the second reset transistor is located on the side of the driving transistor away from the data writing transistor.

18. A display device, comprising, The display panel according to any one of claims 1 to 17.

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