Display panel, terminal device

Abstract

The embodiment of the application discloses a display panel and a terminal device. The display panel comprises a scanning line and a pixel unit. The pixel unit comprises P(1)...P(n) and P(n+1). The scanning line comprises G(0)...G(n-1), G(n) and G(n+1). The pixel unit P(n) is electrically connected with the scanning line G(n+1). At least one of the G(n-1) and the G(n) is arranged to overlap the pixel electrode of the pixel unit P(n). Through cross-line charging, a shielding electrode is not arranged between adjacent pixel electrodes, the distance between adjacent pixel electrodes is reduced, the transmittance of the pixel unit is increased, at least one of the G(n-1) and the G(n) is arranged to overlap the pixel electrode of the pixel unit P(n) in a different plane to form a compensation capacitor, the coupling voltage Vft(n+1) is reduced, the dark lines are reduced, and the display quality is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a terminal device. Background Technology

[0002] Please see Figure 1 In existing display panels, the pixel unit P(n) is electrically connected to the scan line G(n), and a shielding electrode is provided between adjacent pixel electrodes of the existing display panel. The shielding electrode is used to shield the influence of the signal between the scan line and the pixel electrode. However, there is a certain gap between the shielding electrode and the pixel electrodes on both sides, which makes the spacing between adjacent pixel electrodes large, the transmittance of the pixel unit low, and the display has dark lines.

[0003] Therefore, existing display panels have technical problems such as dark patterns and low transmittance. Summary of the Invention

[0004] This application provides a display panel and a terminal device that can alleviate the technical problems of existing display panels having dark patterns and low transmittance.

[0005] This application provides a display panel including scan lines and pixel units. A pixel unit is disposed between adjacent scan lines. The pixel unit includes a pixel electrode. A scan line is connected to a pixel unit. The pixel unit includes P(1)...P(n) and P(n+1). The scan line includes G(0)...G(n-1), G(n), and G(n+1). The pixel unit P(n) is electrically connected to the scan line G(n+1). At least one of G(n-1), G(n-1), and G(n) overlaps with the pixel electrode of the pixel unit P(n). n is a positive integer greater than or equal to 2.

[0006] Optionally, in some embodiments of this application, the pixel unit further includes a TFT device, the pixel unit P(n) includes an nth TFT device and an nth pixel electrode, and the pixel unit P(n+1) includes an (n+1)th TFT device and an (n+1)th pixel electrode, wherein the nth pixel electrode is connected to the (n+1)th TFT device.

[0007] Optionally, in some embodiments of this application, when the scan line G(n+1) provides a scan signal to the pixel unit (n), a compensation capacitor Cco is formed between G(n-1), G(n), and the pixel electrode of the pixel unit P(n).

[0008] Optionally, in some embodiments of this application, the display panel is a liquid crystal display panel, the TFT device includes a gate, a source, and a drain, the voltage change of the gate is Vgh-Vgl, the capacitance between the drain and the gate is Cgs, the liquid crystal capacitor is Clc, and the storage capacitor is Cst, wherein the coupling voltage Vft(n+1)=(Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco).

[0009] Optionally, in some embodiments of this application, the nth pixel electrode is connected to the source of the (n+1)th TFT device through a via.

[0010] Optionally, in some embodiments of this application, when G(n-1) is turned off, G(n-1) generates a first coupling deviation Vft(n-1) to G(n+1), and when G(n) is turned off, G(n) generates a second coupling deviation Vft(n) to G(n+1), wherein Vft(n) is less than Vft(n-1).

[0011] Optionally, in some embodiments of this application, the voltage value after the scan line G(n+1) is turned on is V, where V > Vft(n+1) > Vft(n-1) > Vft(n).

[0012] Optionally, in some embodiments of this application, when G(n-1) is off, G(n+1) is on, the scanning time of the scan line is 5 microseconds, and the interval between the opening of adjacent scan lines is 2.5 microseconds.

[0013] Optionally, in some embodiments of this application, the spacing between adjacent pixel electrodes ranges from 4 micrometers to 5 micrometers.

[0014] This application provides a terminal device, which includes the display panel described in any of the above embodiments.

[0015] Beneficial effects: By electrically connecting the pixel unit P(n) to the scan line G(n+1), cross-line charging is achieved, eliminating the need for shielding electrodes between adjacent pixel electrodes. This reduces the spacing between adjacent pixel electrodes, thereby increasing the transmittance of the pixel unit. Simultaneously, G(n-1), G(n), and the pixel electrodes of the pixel unit P(n) are arranged in an overlapping manner. When the scan line G(n+1) scans and drives the pixel unit P(n), at least one of G(n-1) and G(n) forms a compensation capacitor with the pixel electrode of the pixel unit P(n), thereby reducing the coupling voltage, reducing dark lines, improving the display quality, and alleviating the technical problems of dark lines and low transmittance in existing display panels. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a cross-sectional schematic diagram of a display panel provided by existing technology;

[0018] Figure 2 It is a timing diagram of a display panel provided by existing technology;

[0019] Figure 3 This is a cross-sectional schematic diagram of the display panel provided in this application;

[0020] Figure 4 This is a timing diagram of the display panel provided in this application;

[0021] Figure 5 This application Figure 3 The diagram shows the spacing d in a specific area 2 of the display panel provided.

[0022] Explanation of reference numerals in the attached figures:

[0023] Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0025] Please see Figure 3The display panel 1 provided in this application includes scan lines and pixel units. A pixel unit is disposed between adjacent scan lines. The pixel unit includes a pixel electrode. A scan line is connected to a pixel unit. The pixel unit includes P(1)...P(n) and P(n+1). The scan line includes G(0)...G(n-1), G(n), and G(n+1). The pixel unit P(n)10 is electrically connected to the scan line G(n+1)50. At least one of G(n-1) and G(n) is disposed opposite to the pixel electrode of the pixel unit P(n)10. n is a positive integer greater than or equal to 2.

[0026] In this embodiment, cross-line charging is achieved by electrically connecting the pixel unit P(n)10 to the scan line G(n+1)50, thereby eliminating the need to set shielding electrodes 60 between adjacent pixel electrodes, reducing the spacing d between adjacent pixel electrodes, and increasing the transmittance of the pixel unit. At the same time, G(n-1), G(n), and the pixel electrode of the pixel unit P(n)10 are overlapped. When the scan line G(n+1)50 scans and drives the pixel unit P(n), at least one of G(n-1) and G(n) forms a compensation capacitor with the pixel electrode of the pixel unit P(n)10, thereby reducing the coupling voltage, reducing dark lines, improving the display quality, and alleviating the technical problem of dark lines and low transmittance in the existing display panel 1.

[0027] The technical solution of this application will now be described in conjunction with specific embodiments.

[0028] This application only illustrates the example of cross-line charging achieved by electrically connecting the pixel unit P(n)10 and the scan line G(n+1)50. Other implementation methods that satisfy cross-line charging between the pixel unit and the scan line are also within the protection scope of this application.

[0029] This application increases the area of ​​the pixel electrodes by charging the pixel units across the scan lines, thereby eliminating the need for shielding electrodes 60 between adjacent pixel electrodes and increasing the transmittance. At the same time, the increased area of ​​the pixel electrodes of the pixel unit P(n)10 also forms a compensation capacitor with the scan lines G(n)40 and G(n-1). The compensation capacitor can reduce the coupling voltage of G(n+1), thereby increasing the pixel unit's resistance to process fluctuations and improving the display quality.

[0030] In one embodiment, both G(n-1) and G(n) form a compensation capacitor with the pixel electrode of the pixel unit P(n)10.

[0031] In this embodiment, by forming a compensation capacitor between G(n-1) and G(n) and the pixel electrode of the pixel unit P(n)10, the compensation capacitor is increased, the coupling voltage of G(n+1) is further reduced, the pixel unit's ability to resist process fluctuations is increased, and the display quality is improved.

[0032] In one embodiment, please refer to Figure 3 The pixel unit further includes a TFT device. The pixel unit P(n)10 includes an nth TFT device 102 and an nth pixel electrode 101. The pixel unit P(n+1)20 includes an (n+1)th TFT device 202 and an (n+1)th pixel electrode 201. The nth pixel electrode 101 is connected to the (n+1)th TFT device 202.

[0033] It is understood that the pixel unit P(n)10 is electrically connected to the scan line G(n+1)50 by connecting the nth pixel electrode 101 of the pixel unit P(n)10 to the (n+1)th TFT device 202 of the pixel unit P(n+1)20, and the (n+1)th TFT device 202 is connected to the scan line G(n+1)50.

[0034] In one embodiment, please refer to Figure 3 When the scan line G(n+1)50 provides a scan signal to the pixel unit (n), a compensation capacitor Cco is formed between G(n-1), G(n) and the pixel electrode of the pixel unit P(n)10.

[0035] It is understandable that, since scan lines G(n-1)30 and G(n)40 overlap with the pixel electrode of pixel unit P(n)10 in the film thickness direction, in the overlapping area, scan lines G(n-1)30 and G(n)40 and the pixel electrode of pixel unit P(n)10 will form a compensation capacitor, which can increase the size of the storage capacitor.

[0036] It is understood that, for the cross-line charging structure of this application, the coupling voltage Vft(n+1) is inversely proportional to Cst. That is, when the storage capacitance Cst increases, the coupling voltage Vft(n+1) can be reduced, thereby improving the quality. Therefore, this application forms a compensation capacitor with the pixel electrode of the pixel unit P(n)10 through the scan line G(n-1)30, the scan line G(n)40, and increases the storage capacitance Cst, thereby reducing the coupling voltage Vft(n+1).

[0037] In this embodiment, by forming a compensation capacitor Cco between G(n-1), G(n), and the pixel electrode of the pixel unit P(n)10, the storage capacitor Cst can be increased, thereby reducing the coupling voltage Vft(n+1) and improving the display quality.

[0038] In one embodiment, please refer to Figure 3 The display panel 1 is a liquid crystal display panel 1. The TFT device includes a gate 70, a source 80, and a drain. The voltage change of the gate 70 is Vgh-Vgl. The capacitance between the drain and the gate 70 is Cgs. The liquid crystal capacitor is Clc. The storage capacitor is Cst. The coupling voltage Vft(n+1) = (Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco).

[0039] The formula for the coupling voltage Vft(n+1) further illustrates that by forming the compensation capacitor, the coupling voltage Vft(n+1) can be reduced, thereby increasing the pixel unit's resistance to process fluctuations and improving its quality.

[0040] It is understandable that the coupling voltage Vft(n+1) can be reduced by increasing the liquid crystal capacitance Clc or by increasing Cgs.

[0041] It is understood that the coupling voltage Vft(n+1) can also be reduced by increasing the voltage change (Vgh-Vgl) of the gate 70.

[0042] In this embodiment, by adjusting at least one of Clc, Cgs, Cst, (Vgh-Vgl), and Cco, the coupling voltage Vft(n+1) can be reduced, thereby improving the pixel unit's resistance to process fluctuations and enhancing its quality.

[0043] In one embodiment, the nth pixel electrode 101 is connected to the source 80 of the (n+1)th TFT device 202 through a via.

[0044] In one embodiment, please refer to Figure 3 , Figure 4 When G(n-1) is turned off, G(n-1) generates a first coupling deviation Vft(n-1) to G(n+1). When G(n) is turned off, G(n) generates a second coupling deviation Vft(n) to G(n+1), wherein Vft(n) is less than Vft(n-1).

[0045] Understandably, please refer to Figure 3In this application, due to cross-line charging, scan line G(n+1)50 drives pixel unit P(n)10, while scan lines G(n-1)30 and G(n)40 both couple to scan line G(n+1)50 once when closed, resulting in two coupling deviations. In contrast, in the prior art, scan line G(n)40 drives pixel unit P(n)10. (See [link to previous text]). Figure 2 When scan line G(n-1)30 is turned off, a coupling deviation Vft'(n-1) will be generated on scan line G(n)40. That is, the prior art has only one coupling deviation. When scan line G(n)40 is turned off, the generated coupling voltage Vft'(n) = (Vgh-Vgl)×Cgs / (Cst+Cgs+Clc). Obviously, Vft'(n) is greater than Vft(n+1), that is, the coupling voltage of this application is smaller, thereby increasing the pixel unit's ability to resist process fluctuations and the quality will be better.

[0046] It should be noted that although there are two coupling deviations in the scan line G(n+1)50 due to cross-line charging in this application, when the scan line G(n+1)50 is turned off, the magnitude of the coupling voltage Vft(n+1) can be obtained as shown in the above formula Vft(n+1)=(Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco). Since this application has a compensation capacitor Cco, and there is no overlap between the pixel electrode and the scan line in the prior art, the coupling voltage Vft(n+1) of this application is smaller, thus improving the display quality.

[0047] In one embodiment, please refer to Figure 4 When G(n-1) is closed, G(n+1) is open, the scanning time of the scan line is 5 microseconds, and the interval between the opening of adjacent scan lines is 2.5 microseconds.

[0048] The following description uses a scan time of 5 microseconds and a scan interval of 2.5 microseconds as an example. Other scan times and scan intervals should also be within the scope of protection of this application.

[0049] It is understandable that the interval between the opening of adjacent scan lines is 2.5 microseconds, making the scan interval time equal, and the multiple scan lines scan periodically, which improves stability.

[0050] It is understandable that when scan line G(n-1)30 is turned off, it couples with scan line G(n+1)50, resulting in a voltage drop of Vft(n-1). Similarly, when scan line G(n)40 is turned off, it couples with scan line G(n+1)50, resulting in a voltage drop of Vft(n). Since the voltage drops of Vft(n-1) and Vft(n) only last for 2.5µs, they are imperceptible to the human eye and therefore do not affect the display effect. By limiting the scanning time and interval time, the display quality can be improved, and the voltage drops of coupling deviation Vft(n-1) and Vft(n) can be avoided from being seen by the human eye and affecting the display effect.

[0051] In one embodiment, please refer to Figure 4 The voltage value after the scan line G(n+1)50 is turned on is V, where V > Vft(n+1) > Vft(n-1) > Vft(n).

[0052] In one embodiment, please refer to Figure 5 The spacing d between adjacent pixel electrodes ranges from 4 micrometers to 5 micrometers.

[0053] Understandably, please refer to Figure 5 , Figure 5 for Figure 3 An enlarged schematic diagram of a specific region 2 in the middle. Figure 5 To illustrate the spacing d between adjacent pixels, this application uses cross-row charging without the need for an additional shielding electrode 60; see [link / reference]. Figure 1 In existing designs, the width of the shielding electrode 60 is typically about 11 micrometers. The shielding electrode 60 is usually disposed between adjacent pixel electrodes, and the distance between the shielding electrode 60 and the pixel electrodes on both sides ranges from 4 to 5 micrometers. Therefore, in the prior art, the spacing d between adjacent pixel electrodes = the width of the shielding electrode 60 + the distance between the shielding electrode 60 and one side pixel electrode + the distance between the shielding electrode 60 and the other side pixel electrode. Taking the above value range as an example, the spacing d between adjacent pixel electrodes in the prior art is typically 19 to 21 micrometers. However, this application does not require the shielding electrode 60, thus reducing the width of the shielding electrode 60 itself and the width between the shielding electrode 60 and one side pixel electrode. This application only needs to reserve a certain width between adjacent pixel units to prevent short circuits caused by process errors. This width can be 4 to 5 micrometers.

[0054] It should be noted that this embodiment is only illustrated with an example of a spacing of 4 to 5 micrometers and a width of 11 micrometers for the shielding electrode 60. Provided that the process conditions and display requirements are met, other spacing ranges should also fall within the protection scope of this application.

[0055] This application achieves cross-line charging by electrically connecting the pixel unit P(n) to the scan line G(n+1). Cross-line charging eliminates the need for shielding electrodes between adjacent pixel electrodes, thereby reducing the spacing between adjacent pixel electrodes and improving transmittance.

[0056] Furthermore, due to the reduced spacing between adjacent pixel electrodes, the pixel electrodes and scan lines can be overlapped. Specifically, G(n-1), G(n), and the pixel electrodes of the pixel unit P(n) are overlapped. When the scan line G(n+1) drives the pixel unit P(n) to scan, at least one of the scan line G(n-1) and the scan line G(n) forms a compensation capacitor with the pixel electrode of the pixel unit P(n), thereby reducing the coupling voltage, reducing dark lines, and improving the display quality.

[0057] This application also proposes a display module and a terminal device, both of which include the aforementioned display panel, which will not be described in detail here.

[0058] The display panel provided in this embodiment includes scan lines and pixel units. A pixel unit is disposed between adjacent scan lines. The pixel unit includes a pixel electrode. A scan line is correspondingly connected to a pixel unit. The pixel unit includes P(1)...P(n), P(n+1), and the scan line includes G(0)...G(n-1), G(n), G(n+1). The pixel unit P(n) is electrically connected to the scan line G(n+1). The pixel electrodes of G(n-1), G(n), and the pixel unit P(n) are overlapped. n is a positive integer greater than or equal to 2. By connecting the pixel unit P(n)...P(n+1)...P(n+1), the pixel unit P(n)...P(n+1), the pixel electrode G ... The sensor is electrically connected to the scan line G(n+1) to achieve cross-line charging, thus eliminating the need for shielding electrodes between adjacent pixel electrodes. This reduces the spacing between adjacent pixel electrodes, thereby increasing the transmittance of the pixel unit. Simultaneously, G(n-1), G(n), and the pixel electrodes of the pixel unit P(n) are arranged in an overlapping manner. When the scan line G(n+1) scans and drives the pixel unit P(n), a compensation capacitor is formed between G(n-1), G(n), and the pixel electrodes of the pixel unit P(n), thereby reducing the coupling voltage, reducing dark lines, improving the display quality, and alleviating the technical problems of dark lines and low transmittance in existing display panels.

[0059] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0060] The display panel provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, comprising scan lines and pixel units, wherein a pixel unit is disposed between adjacent scan lines, the pixel unit comprising a pixel electrode, and a scan line is correspondingly connected to a pixel unit, characterized in that, The pixel unit includes P(1)...P(n), P(n+1), and the scan line includes G(0)...G(n-1), G(n), G(n+1), wherein the pixel unit P(n) is electrically connected to the scan line G(n+1), and at least one of G(n-1) and G(n) is disposed opposite to the pixel electrode of the pixel unit P(n), and n is a positive integer greater than or equal to 2; The pixel unit further includes a TFT device. The pixel unit P(n) includes an nth TFT device and an nth pixel electrode. The pixel unit P(n+1) includes an (n+1)th TFT device and an (n+1)th pixel electrode. The nth pixel electrode is connected to the (n+1)th TFT device. When the scan line G(n+1) provides a scan signal to the pixel unit (n), a compensation capacitor Cco is formed between G(n-1), G(n), and the pixel electrode of the pixel unit P(n).

2. The display panel as described in claim 1, characterized in that, The display panel is a liquid crystal display panel. The TFT device includes a gate, a source, and a drain. The voltage change of the gate is Vgh-Vgl. The capacitance between the drain and the gate is Cgs. The liquid crystal capacitor is Clc. The storage capacitor is Cst. The coupling voltage Vft(n+1) = (Vgh-Vgl)×Cgs / (Cst+Cgs+Clc+Cco).

3. The display panel as described in claim 2, characterized in that, The nth pixel electrode is connected to the source of the (n+1)th TFT device through a via.

4. The display panel as described in claim 2, characterized in that, When G(n-1) is turned off, G(n-1) generates a first coupling deviation Vft(n-1) to G(n+1). When G(n) is turned off, G(n) generates a second coupling deviation Vft(n) to G(n+1), wherein Vft(n) is less than Vft(n-1).

5. The display panel as described in claim 4, characterized in that, The voltage value after the scan line G(n+1) is turned on is V, where V > Vft(n+1) > Vft(n-1) > Vft(n).

6. The display panel as described in claim 2, characterized in that, When G(n-1) is closed, G(n+1) is open, the scanning time of the scan line is 5 microseconds, and the interval between the opening of adjacent scan lines is 2.5 microseconds.

7. The display panel as described in claim 1, characterized in that, The spacing between adjacent pixel electrodes ranges from 4 micrometers to 5 micrometers.

8. A terminal device, characterized in that, The terminal device includes a display panel as described in any one of claims 1 to 7.

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