output stage circuit

Abstract

The application discloses an output stage circuit, comprising: an output stage. The output stage comprises: a first following unit, a first output tube, a sampling unit, a second following unit and a second output tube. The first following unit generates a first control voltage following a first input current variation; a control end of the first output tube is used for receiving the first control voltage; the sampling unit generates a sampling current proportional to a current on the first output tube; the second following unit generates a second control voltage following a second input current and the sampling current variation; and a control end of the second output tube is used for receiving the second control voltage. According to the output stage circuit of the application, when a power supply voltage is disturbed, the control end of the first output tube is not easily disturbed, the high-frequency power supply rejection ratio performance can be optimized, and the rail-to-rail output swing is maintained; the output stage circuit of the embodiment of the application can support the use of a high-voltage environment, and compared with the traditional Class AB, there is no obvious cost increase, the structure conversion is relatively strong, and the power consumption is not additionally increased.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an output stage circuit. Background Technology

[0002] Class AB output structure is widely used in operational amplifier products because it can achieve rail-to-rail output. With the increase in chip integration and the higher requirements for transmission speed, high-frequency disturbances on the power supply are receiving more and more attention, and there are higher requirements for the high-frequency power rejection ratio (PSRR@High Frequency) of the products.

[0003] In traditional Class AB output structures, the power supply rejection ratio (PSRR) of operational amplifiers or comparators begins to decrease from the position of the dominant pole. It is difficult to make the frequency of the dominant pole high in the design, so the PSRR at high frequencies is generally not very high. Choosing other output structures will lose the rail-to-rail advantage of Class AB output. Therefore, it is more valuable to design a Class AB structure with excellent high-frequency PSRR performance.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide an output stage circuit that, while retaining the characteristics of Class AB output, achieves a power supply rejection ratio (PSRR) at a frequency much higher than the main pole frequency of the operational amplifier or comparator, thereby obtaining a higher high-frequency PSRR.

[0006] To achieve the above objectives, embodiments of the present invention provide an output stage circuit, comprising: an output stage, the output stage including:

[0007] The first follower unit is used to generate a first control voltage that follows the change of the first input current based on the first input current;

[0008] The first output transistor, the control terminal of the first output transistor is used to receive the first control voltage;

[0009] A sampling unit is used to generate a sampling current that is proportional to the current on the first output transistor based on a first control voltage;

[0010] The second follower unit is used to generate a second control voltage that follows the changes in the second input current and the sampled current; and

[0011] The second output transistor has a control terminal for receiving a second control voltage. The first terminal of the second output transistor is connected to the first terminal of the first output transistor to form the output terminal of the output stage circuit. The second terminals of the first and second output transistors are respectively connected to the power supply voltage and the ground voltage.

[0012] In one or more embodiments of the present invention, the first follower unit includes a first current source, a first transistor and a second current source, the second terminal of the first transistor is used to receive a first input current and is simultaneously connected to the second current source, and the first terminal of the first transistor is connected to the first current source and is used to generate a first control voltage.

[0013] In one or more embodiments of the present invention, the sampling unit includes a second transistor, the control terminal of the second transistor being used to receive a first control voltage to generate a sampling current on the second transistor.

[0014] In one or more embodiments of the present invention, the second follower unit includes a current mirror unit and a current follower circuit. The current mirror unit is connected to the sampling unit to mirror the sampled current to generate a first current. The current follower circuit generates a second current that follows the change of the second input current based on the second input current. The current mirror unit and the current follower circuit are simultaneously connected to the control terminal of the second output transistor to generate a second control voltage based on the first current and the second current.

[0015] In one or more embodiments of the present invention, the current mirror unit includes a first current mirror, or a first current mirror and a bias unit. The first current mirror is connected to the sampling unit, the current follower circuit, and the control terminal of the second output transistor to mirror the sampled current to generate a first current and cooperate with the second current to generate a second control voltage. The bias unit is connected to the first current mirror.

[0016] In one or more embodiments of the present invention, the first current mirror includes a third transistor and a fourth transistor, the bias unit includes a fifth transistor and a sixth transistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, the control terminal of the third transistor is connected to the first terminal of the third transistor and is connected to the control terminal of the current follower circuit and the second output transistor, the first terminal of the fourth transistor is connected to the sampling unit, the control terminal of the fifth transistor is connected to the control terminal of the sixth transistor, the control terminal of the sixth transistor is connected to the first terminal of the fourth transistor or to the first terminal of the sixth transistor, the first terminal of the fifth transistor is connected to the second terminal of the third transistor, and the first terminal of the sixth transistor is connected to the second terminal of the fourth transistor.

[0017] In one or more embodiments of the present invention, the first current mirror includes a third transistor and a fourth transistor, the bias unit includes a first resistor and a second resistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, the control terminal of the fourth transistor is connected to the first terminal of the fourth transistor and connected to the sampling unit, the first terminal of the third transistor is connected to the control terminal of the current follower circuit and the second output transistor, the second terminal of the third transistor is connected to the first resistor, and the second terminal of the fourth transistor is connected to the second resistor.

[0018] In one or more embodiments of the present invention, the current follower circuit includes a seventh transistor and a third current source, the second terminal of the seventh transistor is used to receive a second input current and is connected to the third current source, and the first terminal of the seventh transistor is connected to the control terminal of the current mirror unit and the second output transistor.

[0019] In one or more embodiments of the present invention, the second follower unit further includes a second high-voltage isolation unit disposed between the current mirror unit and the current follower circuit and between the current mirror unit and the sampling unit.

[0020] In one or more embodiments of the present invention, the first follower unit further includes a first high-voltage isolation unit disposed between the first current source and the first transistor.

[0021] Compared with the prior art, the output stage circuit of the present invention, by connecting the control terminals of the first output transistor and the second output transistor to two points respectively, and isolating the two points by a high-impedance structure, makes the control terminal of the first output transistor less susceptible to interference when the power supply voltage is disturbed, thereby optimizing the high-frequency power supply rejection ratio performance and maintaining the rail-to-rail output swing. The output stage circuit of the present invention can support the use of high-voltage environments, and compared with the traditional Class AB, there is no significant increase in cost, strong structural convertibility, and no additional increase in power consumption. Attached Figure Description

[0022] Figure 1 This is a circuit schematic diagram of an output stage circuit according to an embodiment of the present invention. Detailed Implementation

[0023] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0024] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0025] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0026] like Figure 1 As shown, an output stage circuit includes: a first follower unit 10, a sampling unit 20, a second follower unit, a first output transistor MN, and a second output transistor MP. In one embodiment, the output stage circuit is the output stage circuit of an operational amplifier, or it can be the output stage circuit of a comparator.

[0027] The first follower unit 10 is used to generate a first control voltage Va that follows the change of the first input current Ia based on the first input current Ia; the control terminal of the first output transistor MN is used to receive the first control voltage Va; the sampling unit 20 is used to generate a sampling current that is proportional to the current on the first output transistor MN based on the first control voltage Va. The second follower unit is used to generate a second control voltage Vb that follows the change of the second input current Ib and the sampling current based on the second input current Ib and the sampling current; the control terminal of the second output transistor MP is used to receive the second control voltage Vb; the first terminal of the second output transistor MP and the first terminal of the first output transistor MN are connected to form the output terminal OUT of the output stage circuit; the second terminal of the first output transistor MN and the second terminal of the second output transistor MP are connected to the power supply voltage and the ground voltage, respectively.

[0028] The first output transistor MN is an N-channel MOSFET, with its control terminal being the gate, its first terminal being the drain, and its second terminal being the source. The second output transistor MP is a P-channel MOSFET, with its control terminal being the gate, its first terminal being the drain, and its second terminal being the source.

[0029] In one embodiment, the operational amplifier with an output stage circuit further includes an input stage having two positive input terminals that generate simultaneously varying first input currents Ia and Ib, respectively. The input stage also has a negative input terminal, the current generated at the negative input terminal being equal to the sum of the first input current Ia and the second input current Ib. In other embodiments, the comparator with an output stage circuit also includes an input stage having two positive input terminals and one negative input terminal. The first input current Ia at the two positive input terminals is equal to the second input current Ib, and the current at the negative input terminal, along with the sum of the first input current Ia and the second input current Ib, is a fixed value.

[0030] Specifically, the first follower unit 10 includes a first current source A1, a first high-voltage isolation unit, a first transistor M1, and a second current source A2. The first high-voltage isolation unit includes a first high-voltage transistor MV1. The second terminal of the first transistor M1 is used to receive a first input current Ia and is simultaneously connected to the first terminal of the second current source A2, which is connected to ground. The first terminal of the first transistor M1 is connected to the first terminal of the first high-voltage transistor MV1 and is used to generate a first control voltage Va. The second terminal of the first high-voltage transistor MV1 is connected to the first terminal of the first current source A1, which is connected to the power supply voltage VDD.

[0031] In other embodiments, if not applied to high-voltage scenarios, the first high-voltage isolation unit may be omitted.

[0032] The output stage also includes a branch for receiving the current generated at the negative terminal of the input stage. This branch includes a fourth current source A4, a third high-voltage isolation unit, an eighth transistor M8, and a fifth current source A5. The third high-voltage isolation unit includes a second high-voltage transistor MV2.

[0033] The first terminal of the fourth current source A4 is connected to the power supply voltage VDD. The second terminal of the fourth current source A4 is connected to the second terminal of the second high-voltage transistor MV2. The first terminal of the second high-voltage transistor MV2 is connected to the first terminal of the eighth transistor M8. The second terminal of the eighth transistor M8 is connected to the first terminal of the fifth current source A5 and receives the current generated by the negative terminal of the input stage. The second terminal of the fifth current source A5 is connected to the ground voltage.

[0034] In other embodiments, if not applied to high-voltage scenarios, a third high-voltage isolation unit may not be required.

[0035] It should be noted that each of the first current source A1, the fourth current source A4, and the additionally provided sixth current source A6 can be a current source composed of a single current mirror; alternatively, each current source can be composed of a single MOSFET, thereby connecting the first current source A1, the fourth current source A4, and the additionally provided sixth current source A6 via a common gate to form a current mirror. The sixth current source A6 is also connected to the bias current Ibias provided by the previous stage, thereby mirroring two currents flowing to the first transistor M1 and the eighth transistor M8 respectively on the first current source A1 and the fourth current source A4 based on the bias current Ibias. In this embodiment, preferably, the first current source A1, the fourth current source A4, and the sixth current source A6 are each composed of a single MOSFET.

[0036] like Figure 1 As shown, the sampling unit 20 includes a second transistor M2. The control terminal of the second transistor M2 is connected to the first terminal of the first transistor M1. The second transistor M2 receives a first control voltage Va to generate a sampling current on the second transistor M2. Since the control terminal of the first output transistor MN also receives the first control voltage Va, and the second terminals of both the first output transistor MN and the second transistor M2 are connected to ground, by adjusting the width-to-length ratio of the first output transistor MN and the second transistor M2, a sampling current proportional to the current on the first output transistor MN can be generated on the second transistor M2.

[0037] like Figure 1 As shown, the second follower unit includes a current mirror unit 31 and a current follower circuit 32. The current mirror unit 31 is connected to the sampling unit 20 to generate a first current by mirroring the sampled current. The current follower circuit 32 generates a second current that follows the changes of the second input current Ib. The current mirror unit 31 and the current follower circuit 32 are simultaneously connected to the control terminal of the second output transistor MP to generate a second control voltage Vb based on the first current and the second current.

[0038] The current mirror unit 31 includes a first current mirror 311 and a bias unit 312. The first current mirror 311 is connected to the sampling unit 20, the current follower circuit 32, and the control terminal of the second output transistor MP to mirror the sampled current to generate a first current and, in conjunction with the second current, generate a second control voltage Vb. The bias unit 312 is connected to the first current mirror 311 and is used to ensure that each MOS transistor of the first current mirror 311 operates in the linear region. In other embodiments, the bias unit 312 may be omitted in different application scenarios.

[0039] The first current mirror 311 includes a third transistor M3 and a fourth transistor M4, and the biasing unit includes a fifth transistor M5 and a sixth transistor M6. The control terminal of the third transistor M3 is connected to the control terminal of the fourth transistor M4. The control terminal of the third transistor M3 is connected to its first terminal to generate a first current. After the control terminal of the third transistor M3 is connected to its first terminal, it is connected to the current follower circuit 32 to generate a second control voltage Vb to the control terminal of the second output transistor MP. The first terminal of the fourth transistor M4 is connected to the sampling unit 20. The control terminal of the fifth transistor M5 is connected to the control terminal of the sixth transistor M6 and is also connected to the first terminal of the fourth transistor M4. The first terminal of the fifth transistor M5 is connected to the second terminal of the third transistor M3, and the first terminal of the sixth transistor M6 is connected to the second terminal of the fourth transistor M4. In other embodiments, the control terminals of the fifth transistor M5 and the sixth transistor M6 can also be connected together before being connected to the first terminal of the sixth transistor M6.

[0040] In other embodiments, the fifth transistor M5 can be replaced with the first resistor, and the sixth transistor M6 can be replaced with the second resistor. In this case, the control terminal of the third transistor M3 is connected to the control terminal of the fourth transistor M4, the control terminal of the fourth transistor M4 is connected to the first terminal of the fourth transistor M4 and connected to the sampling unit 20, the first terminal of the third transistor M3 is connected to the current follower circuit 32 and the control terminal of the second output transistor MP, the second terminal of the third transistor M3 is connected to the first terminal of the first resistor, the second terminal of the fourth transistor M4 is connected to the first terminal of the second resistor, and the second terminals of the first and second resistors are connected to the power supply voltage VDD.

[0041] like Figure 1 As shown, the current follower circuit 32 includes a seventh transistor M7 and a third current source A3. The second terminal of the seventh transistor M7 receives the second input current Ib and is connected to the first terminal of the third current source A3. The second terminal of the third current source A3 is connected to ground. The first terminal of the seventh transistor M7 is connected to the control terminal of the current mirror unit 31 and the second output transistor MP. A second current is generated on the seventh transistor M7.

[0042] In one embodiment, the second current source A2, the third current source A3, and the fifth current source A5 can be three separate current sources, or they can be a current mirror composed of three connected MOS transistors.

[0043] like Figure 1 As shown, the second follower unit also includes a second high-voltage isolation unit 40 disposed between the current mirror unit 31 and the current follower circuit 32, and between the current mirror unit 31 and the sampling unit 20.

[0044] The second high-voltage isolation unit 40 includes a third high-voltage transistor MV3 and a fourth high-voltage transistor MV4. The first terminal of the third high-voltage transistor MV3 is connected to the first terminal of the third transistor M3 and the control terminal of the MP of the second output transistor. The first terminal of the fourth high-voltage transistor MV4 is connected to the first terminal of the fourth transistor M4. The second terminal of the third high-voltage transistor MV3 is connected to the first terminal of the seventh transistor M7, and the first terminal of the fourth high-voltage transistor MV4 is connected to the first terminal of the second transistor M2. In other embodiments, in low-voltage applications, the second high-voltage isolation unit 40 may not be required.

[0045] like Figure 1 As shown, the output stage circuit also includes a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 is connected to the control terminal of the first output transistor MN, and the second terminal of the first capacitor C1 is connected to the first terminal of the first output transistor MN. The first terminal of the second capacitor C2 is connected to the control terminal of the second output transistor MP, and the second terminal of the second capacitor C2 is connected to the first terminal of the second output transistor MP. The output of the output stage circuit can be stabilized through the first capacitor C1 and the second capacitor C2.

[0046] In one embodiment, the first transistor M1, the second transistor M2, the seventh transistor M7, and the second transistor M8 are N-channel MOSFETs, and the third high-voltage transistor MV3 and the fourth high-voltage transistor MV4 are N-channel high-voltage MOSFETs.

[0047] The first terminals of the first transistor M1, the second transistor M2, the seventh transistor M7, and the second transistor M8 are the drains. The second terminals of the first transistor M1, the second transistor M2, the seventh transistor M7, and the second transistor M8 are the sources. The control terminals of the first transistor M1, the second transistor M2, the seventh transistor M7, and the second transistor M8 are the gates. The control terminals of the first transistor M1, the seventh transistor M7, and the second transistor M8 receive corresponding control voltages.

[0048] The first terminal of the third high-voltage transistor MV3 and the first terminal of the fourth high-voltage transistor MV4 are the drains, the second terminal of the third high-voltage transistor MV3 and the second terminal of the fourth high-voltage transistor MV4 are the sources, and the control terminal of the third high-voltage transistor MV3 and the control terminal of the fourth high-voltage transistor MV4 are the gates.

[0049] The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are P-channel MOSFETs, and the first high-voltage transistor MV1 and the second high-voltage transistor MV2 are P-channel high-voltage MOSFETs.

[0050] The first terminals of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are the drains; the second terminals of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are the sources; and the control terminals of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are the gates.

[0051] The first end of the first high-voltage transistor MV1 and the first end of the second high-voltage transistor MV2 are the drains, the second end of the first high-voltage transistor MV1 and the second end of the second high-voltage transistor MV2 are the sources, and the control terminals of the first high-voltage transistor MV1 and the second high-voltage transistor MV2 are the gates.

[0052] The second current source A2, the fifth current source A5, and the third current source A3 are composed of N-channel MOSFETs. The first terminal of the second current source A2, the first terminal of the fifth current source A5, and the first terminal of the third current source A3 are the drains. The second terminal of the second current source A2, the second terminal of the fifth current source A5, and the second terminal of the third current source A3 are the sources. The control terminals of the second current source A2, the fifth current source A5, and the third current source A3 are the gates.

[0053] The first current source A1, the fourth current source A4, and the sixth current source A6 are composed of P-channel MOSFETs. The first terminal of the first current source A1, the first terminal of the fourth current source A4, and the first terminal of the sixth current source A6 are the drains, the second terminals of the first current source A1, the second terminals of the fourth current source A4, and the second terminals of the sixth current source A6 are the sources, and the control terminals of the first current source A1, the fourth current source A4, and the sixth current source A6 are the gates.

[0054] In other embodiments, the N-channel MOSFET can be replaced with a P-channel MOSFET, and the P-channel MOSFET can be replaced with an N-channel MOSFET; or the MOSFET can be replaced with a corresponding transistor.

[0055] like Figure 1 As shown, the set of output transistors (the first output transistor MN and the second output transistor MP) located at the output terminal OUT of the output stage circuit are the same as the traditional Class AB output structure, and the output still has a large swing.

[0056] The magnitude of the current on the first output transistor MN is determined by the first control voltage Va, which is mainly determined by the first input current Ia and the current on the first transistor M1.

[0057] The magnitude of the current on the second output transistor MP is determined by the second control voltage Vb. The magnitude of the second control voltage Vb is mainly determined by the current in the current mirror unit 31 and the current in the seventh transistor M7. The current in the seventh transistor M7 is mainly determined by the second input current Ib, and the current in the current mirror unit 31 is mainly determined by the current in the second transistor M2. The current in the second transistor M2 is determined by the first control voltage Va. By setting the width-to-length ratio of the second transistor M2 and the first output transistor MN, a sampling current can be obtained on the second transistor M2 that is proportional to and follows the change of the current in the first output transistor MN.

[0058] In summary, this invention optimizes the structure while retaining a large output swing, and fixes the quiescent current of the output stage. The control terminal of the first output transistor MN is connected to the first terminal of the first transistor M1 of the first follower unit 10, and the control terminal of the second output transistor MP is connected to the first terminal of the third transistor M3 of the first current mirror 311. The control terminals of the first output transistor MN and the second output transistor MP are respectively connected to two points, and the two points are isolated by a high-impedance structure such as the current mirror unit 31. When the power supply voltage VDD is disturbed, the control terminal of the first output transistor MN is not easily disturbed, thereby optimizing the power supply rejection ratio at high frequencies (such as 100KHz).

[0059] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. An output stage circuit, characterized in that, include: The first follower unit is used to generate a first control voltage that follows the change of the first input current based on the first input current; The first output transistor, the control terminal of the first output transistor is used to receive the first control voltage; A sampling unit is used to generate a sampling current that is proportional to the current on the first output transistor based on a first control voltage; The second follower unit is used to generate a second control voltage that follows the changes of the second input current and the sampled current based on the second input current and the sampled current; as well as The second output transistor has a control terminal for receiving a second control voltage. The first terminal of the second output transistor is connected to the first terminal of the first output transistor to form the output terminal of the output stage circuit. The second terminal of the first output transistor and the second terminal of the second output transistor are respectively connected to the power supply voltage and the ground voltage. The second follower unit includes a current mirror unit and a current follower circuit. The current mirror unit is connected to the sampling unit to generate a first current by mirroring the sampled current. The current follower circuit generates a second current that follows the change of the second input current based on the second input current. The current mirror unit and the current follower circuit are simultaneously connected to the control terminal of the second output transistor to generate a second control voltage based on the first current and the second current.

2. The output stage circuit as described in claim 1, characterized in that, The first follower unit includes a first current source, a first transistor, and a second current source. The second terminal of the first transistor is used to receive a first input current and is simultaneously connected to the second current source. The first terminal of the first transistor is connected to the first current source and is used to generate a first control voltage.

3. The output stage circuit as described in claim 1, characterized in that, The sampling unit includes a second transistor, the control terminal of which is used to receive a first control voltage to generate a sampling current on the second transistor.

4. The output stage circuit as described in claim 1, characterized in that, The current mirror unit includes a first current mirror, or a first current mirror and a bias unit. The first current mirror is connected to the sampling unit, the current follower circuit, and the control terminal of the second output transistor to mirror the sampled current to generate a first current and cooperate with the second current to generate a second control voltage. The bias unit is connected to the first current mirror.

5. The output stage circuit as described in claim 4, characterized in that, The first current mirror includes a third transistor and a fourth transistor, and the bias unit includes a fifth transistor and a sixth transistor. The control terminal of the third transistor is connected to the control terminal of the fourth transistor. The control terminal of the third transistor is connected to the first terminal of the third transistor and to the control terminal of the current follower circuit and the second output transistor. The first terminal of the fourth transistor is connected to the sampling unit. The control terminal of the fifth transistor is connected to the control terminal of the sixth transistor. The control terminal of the sixth transistor is connected to the first terminal of the fourth transistor or to the first terminal of the sixth transistor. The first terminal of the fifth transistor is connected to the second terminal of the third transistor. The first terminal of the sixth transistor is connected to the second terminal of the fourth transistor.

6. The output stage circuit as described in claim 4, characterized in that, The first current mirror includes a third transistor and a fourth transistor. The bias unit includes a first resistor and a second resistor. The control terminal of the third transistor is connected to the control terminal of the fourth transistor. The control terminal of the fourth transistor is connected to the first terminal of the fourth transistor and is connected to the sampling unit. The first terminal of the third transistor is connected to the current follower circuit and the control terminal of the second output transistor. The second terminal of the third transistor is connected to the first resistor. The second terminal of the fourth transistor is connected to the second resistor.

7. The output stage circuit as described in claim 1, characterized in that, The current follower circuit includes a seventh transistor and a third current source. The second terminal of the seventh transistor is used to receive a second input current and is connected to the third current source. The first terminal of the seventh transistor is connected to the control terminal of the current mirror unit and the second output transistor.

8. The output stage circuit as described in claim 1, characterized in that, The second follower unit also includes a second high-voltage isolation unit disposed between the current mirror unit and the current follower circuit, and between the current mirror unit and the sampling unit.

9. The output stage circuit as described in claim 2, characterized in that, The first follower unit further includes a first high-voltage isolation unit disposed between the first current source and the first transistor.

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