Brightness compensation method of display panel, display panel and storage medium

Abstract

The application discloses a brightness compensation method of a display panel, the display panel and a storage medium, wherein the display panel comprises a substrate, a first metal layer, a gate insulating layer and a second metal layer; wherein the source and the gate of the same thin film transistor have a first overlapping area in the orthographic projection of the substrate, and the area of the first overlapping area corresponding to a plurality of TFTs connected to the same scan line gradually decreases from the center to the side edge of the substrate; and / or the orthographic projection of the source and the orthographic projection of the common electrode of the same thin film transistor have a second overlapping area, and the area of the second overlapping area corresponding to a plurality of TFTs connected to the same scan line gradually increases from the center to the side edge of the substrate; and the application aims to solve the problem that the display image is unevenly bright and dark due to the mura change of the TFT device in the display.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a brightness compensation method for a display panel, a display panel, and a storage medium. Background Technology

[0002] Currently, demura technology can improve the brightness difference caused by different RC loading in large-size displays. However, after the display panel undergoes high temperature and high humidity resistance test, the TFT device begins to produce brightness drift due to the effects of light, heat and electricity, causing mura change. This results in a mismatch between the brightness change after the test and the demura data, leading to uneven brightness of the displayed image. Summary of the Invention

[0003] The main objective of this invention is to provide a brightness compensation method for a display panel, a display panel, and a storage medium, aiming to solve the problem of uneven brightness in the displayed image due to mura change in the TFT devices in the display.

[0004] To achieve the above objectives, the display panel proposed in this invention includes:

[0005] substrate;

[0006] A first metal layer is disposed above the substrate, and the first metal layer includes a gate electrode and a common electrode.

[0007] A gate insulating layer is disposed above the first metal layer;

[0008] A second metal layer is disposed above the gate insulating layer, and the second metal layer includes a source and a drain.

[0009] Wherein, the source and gate of the same thin-film transistor have a first overlapping region in their orthogonal projection onto the substrate, and the area of ​​the first overlapping region corresponding to multiple TFTs connected to the same scan line gradually decreases from the center to the side of the substrate; and / or,

[0010] The source and common electrode of the same thin-film transistor have a second overlapping region in their orthogonal projection on the substrate, and the area of ​​the second overlapping region corresponding to the plurality of thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate.

[0011] In some embodiments, in the same thin-film transistor, there is a first distance between the source and the drain, and the first distance between a plurality of thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate; and / or,

[0012] Each source electrode has a first metal region corresponding to the first part of the same TFT, and the area of ​​the first metal region corresponding to the plurality of thin film transistors connected to the same scan line gradually decreases from the center to the side of the substrate.

[0013] In some embodiments, each source electrode has a second metal region corresponding to the second portion of the same TFT, and the area of ​​the second metal region corresponding to the plurality of thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate.

[0014] The present invention also proposes a brightness compensation method for a display panel, the display panel comprising a plurality of scan lines and a plurality of thin-film transistors arranged at intervals on each of the scan lines; the brightness compensation method for the display panel includes:

[0015] The feed-through voltage of the multiple thin-film transistors connected to each scan line is obtained to obtain the feed-through voltage curve of the multiple thin-film transistors corresponding to the same scan line;

[0016] Based on each feedthrough voltage curve and the preset target feedthrough voltage, the corresponding compensation curve is obtained;

[0017] The first overlap area of ​​the gate and source of the thin-film transistor, and / or the second overlap area of ​​the common electrode and source of the thin-film transistor, are adjusted according to each of the compensation curves.

[0018] In some embodiments, the scan has two sides symmetrical about a centerline, and acquiring the feed-through voltage of the thin-film transistor connected to each scan line and obtaining the feed-through voltage curve corresponding to the same scan line includes:

[0019] Multiple thin-film transistors are selected on one side of each scan line, and the holding voltage and peak voltage of each thin-film transistor during operation are collected.

[0020] Based on the holding voltage and the peak voltage, the feed-through voltage corresponding to the thin-film transistor is obtained;

[0021] Based on the symmetry of the feedthrough voltage curve and the feedthrough voltage of the plurality of thin-film transistors, the feedthrough voltage curve of the plurality of thin-film transistors corresponding to each scan line is obtained.

[0022] In some embodiments, obtaining the corresponding compensation curve based on each feedthrough voltage curve and a preset target feedthrough voltage includes:

[0023] The difference between each feedthrough voltage curve and the target feedthrough voltage is used to obtain the compensation curve corresponding to the multiple thin-film transistors connected to each scan line.

[0024] In some embodiments, adjusting the alignment deviation of the metal layer corresponding to the gate and the metal layer corresponding to the source of the thin-film transistor according to each compensation curve specifically includes:

[0025] The target compensation voltage of each thin-film transistor in the corresponding scan line is obtained according to the compensation curve;

[0026] Adjust the first overlapping region of the source and gate in the substrate of each thin-film transistor, and / or the area of ​​the second overlapping region of the source and common electrode in the substrate, so that the current compensation voltage corresponding to each thin-film transistor reaches the target compensation voltage.

[0027] In some embodiments, adjusting the first overlapping region of the source and gate in the orthographic projection of each thin-film transistor onto the substrate, and / or the area of ​​the second overlapping region of the source and common electrode in the orthographic projection of the substrate specifically includes:

[0028] The source of each of the thin-film transistors in the display panel under test is translated; and / or,

[0029] Reduce the area of ​​the first portion of the source of each of the thin-film transistors in the display panel under test; and / or,

[0030] Increase the area of ​​the second portion of the source of each of the thin-film transistors in the display panel under test.

[0031] In some embodiments, after adjusting the first overlap area of ​​the gate and source of the thin-film transistor according to each of the compensation curves, the method further includes:

[0032] The feed-through voltage of each thin-film transistor in the display panel under test is supplemented to the target feed-through voltage.

[0033] The present invention also proposes a storage medium, the storage medium including the above-described brightness compensation method for a display panel.

[0034] The technical solution of the present invention reduces the feed-through voltage difference between multiple thin-film transistors in the same scan line by setting the area of ​​the first overlapping region corresponding to multiple TFTs connected to the same scan line to gradually decrease from the center to the side of the substrate; and / or setting the area of ​​the second overlapping region corresponding to multiple TFTs connected to the same scan line to gradually increase from the center to the side of the substrate. This reduces the brightness difference of the display panel when emitting light, thereby achieving the uniformity of the display panel. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0036] Figure 1 This is a side view of an embodiment of the display panel of the present invention;

[0037] Figure 2 This is a top view of an embodiment of the display panel of the present invention;

[0038] Figure 3 This is a schematic flowchart of an embodiment of the brightness compensation method for the display panel of the present invention;

[0039] Figure 4 This is a flowchart illustrating an embodiment of step S200 in this invention;

[0040] Figure 5 This is a flowchart illustrating an embodiment of step S300 in this invention;

[0041] Figure 6 This is a schematic diagram of signal deformation at both ends and the middle part of a scan line in the prior art;

[0042] Figure 7 This is a schematic diagram of the parameters of the mura of the present invention in different scenarios.

[0043] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0045] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0046] This invention proposes a display panel.

[0047] Reference Figures 1 to 2 In one embodiment, the display panel includes:

[0048] substrate 110;

[0049] A first metal layer 120 is disposed above the substrate 110, and the first metal layer 120 includes a gate 121 and a common electrode 122.

[0050] A gate insulating layer 130 is disposed above the first metal layer 120;

[0051] A second metal layer 140 is disposed above the gate insulating layer 130, and the second metal layer 140 includes a source and a drain 143.

[0052] In this embodiment, the source and gate 121 of the same thin-film transistor have a first overlapping region in their orthogonal projection onto the substrate 110, and the area of ​​the first overlapping region corresponding to multiple TFTs connected to the same scan line gradually decreases from the center to the side of the substrate 110; and / or,

[0053] The drain 143 and the common electrode 122 of the same thin-film transistor have a second overlapping region in the orthographic projection of the substrate 110. The area of ​​the second overlapping region corresponding to the multiple TFTs connected to the same scan line gradually increases from the center to the side of the substrate 110.

[0054] It should be noted that in the display panel, each scan line is connected to multiple thin-film transistors at equal intervals, such as... Figure 6 As shown, due to the impedance of the conductor itself, there is a difference in RCloading (capacitive-resistive load) between the two ends and the middle part of the same conductor. This causes the feedthrough voltage of the thin-film transistors at the two ends of the scan line to be greater than that in the middle part when the scan line is connected to the scan signal, because the RCloading at the two ends of the scan line is smaller than that in the middle. This results in a difference in brightness when the display panel emits light.

[0055] like Figure 7 As shown, this situation can usually be improved using demura technology. However, the display panel also needs to undergo high temperature and humidity resistance tests during the manufacturing process. After being subjected to light, electricity, and heat interference, the demura data of multiple thin-film transistors will change after the test, making it impossible for demura to improve the situation based on the original data.

[0056] In this embodiment, the present invention directly adjusts the parameters (such as position, size, or height) of the metal layer inside the thin-film transistor according to the feedthrough voltage formula. Since in the feedthrough voltage formula ΔV=(Vgh-Vgl)Cgs / (Cgs+Clc+Cst), where Vgh is the turn-on voltage of the thin-film transistor, Vgl is the turn-off voltage of the thin-film transistor, Cgs is the parasitic capacitance between the source and gate of the thin-film transistor, Clc is the parallel plate capacitance formed by the liquid crystal, and Cst is the storage capacitance of the thin-film transistor, it can be seen that the magnitude of the feedthrough voltage is related to Vgh, Vgl, Cgs, Clc, and Cst. Vgh and Vgl, as the control voltage of the TFT, are usually constant, while Clc is only related to the liquid crystal. Therefore, it is known that the feedthrough voltage of the thin-film transistor can be changed by changing Cgs and Cst.

[0057] The parasitic capacitance Cgs between the source and gate 121 of the thin-film transistor is generated due to the first overlapping region of the source and the gate 121 of the same thin-film transistor projected onto the substrate 110. The storage capacitance Cst of the thin-film transistor is generated due to the second overlapping region of the source and the common electrode 122 of the same thin-film transistor projected onto the substrate 110. Therefore, in this embodiment of the invention, by setting the area of ​​the first overlapping region corresponding to the plurality of TFTs connected to the same scan line to gradually decrease from the center to the side of the substrate 110; and / or setting the area of ​​the second overlapping region corresponding to the plurality of TFTs connected to the same scan line to gradually increase from the center to the side of the substrate 110, the feed-through voltage difference between the plurality of thin-film transistors in the same scan line can be reduced.

[0058] Taking the adjustment of the feed-through voltage of all thin-film transistors on a scan line to make it close to the feed-through voltage of the thin-film transistor in the middle position as an example:

[0059] In one embodiment, the area of ​​the first overlapping region corresponding to multiple TFTs connected to the same scan line gradually decreases from the center to the side of the substrate 110. At this time, the parasitic capacitance Cgs between the source and gate 121 of each thin film transistor on the scan line gradually decreases from the center to the side of the substrate 110, thereby achieving a greater reduction in feed-through voltage at the left and right ends than in the middle, compensating for the difference in feed-through voltage caused by RC loading.

[0060] In one embodiment, the area of ​​the second overlapping region corresponding to multiple TFTs connected to the same scan line gradually increases from the center to the side of the substrate 110. At this time, the storage capacitance Cst between the source of each thin film transistor on the scan line and the common electrode 122 of the same thin film transistor gradually increases from the center to the side of the substrate 110, thereby realizing that the feed-through voltage at the left and right ends is reduced more than that in the middle, which makes up for the difference in feed-through voltage caused by RC loading.

[0061] In one embodiment, the area of ​​the first overlapping region corresponding to the plurality of TFTs connected to the same scan line gradually decreases from the center to the side of the substrate 110, and the area of ​​the second overlapping region corresponding to the plurality of TFTs connected to the same scan line gradually increases from the center to the side of the substrate 110. At this time, the parasitic capacitance Cgs between the source and gate 121 of each thin film transistor on the scan line gradually decreases from the center to the side of the substrate 110, and the storage capacitance Cst between the source and common electrode 122 of each thin film transistor on the scan line gradually increases from the center to the side of the substrate 110. This results in a greater reduction in feedthrough voltage at the left and right ends than in the middle, compensating for the difference in feedthrough voltage caused by RC loading.

[0062] The technical solution of the present invention reduces the feed-through voltage difference between multiple thin-film transistors in the same scan line by setting the area of ​​the first overlapping region corresponding to multiple TFTs connected to the same scan line to gradually decrease from the center to the side of the substrate 110; and / or setting the area of ​​the second overlapping region corresponding to multiple TFTs connected to the same scan line to gradually increase from the center to the side of the substrate 110. This reduces the brightness difference of the display panel when emitting light, thereby achieving the uniformity of the display panel.

[0063] Reference Figures 1 to 2 In one embodiment, within the same thin-film transistor, a first distance exists between the source and drain 143, and the first distance between multiple thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate; and / or,

[0064] Each source has a first metal region 141 corresponding to the gate 121 of the same thin-film transistor. The area of ​​the first metal region 141 corresponding to the multiple thin-film transistors connected to the same scan line gradually decreases from the center to the side of the substrate 110.

[0065] In embodiments of the present invention, such as Figure 2 As shown, the first distance is in the direction of the x-axis.

[0066] In a thin-film transistor, its source has overlapping areas with the gate 121 and the common electrode 121 of the same thin-film transistor. When manufacturing a display panel, if it is necessary to reduce the feed-through voltage of the thin-film transistor at this point, the first distance between the source of the thin-film transistor and the drain 143 along the x-axis direction can be increased, thereby reducing the area of ​​the first overlapping region and increasing the area of ​​the second overlapping region, thereby reducing the Cgs of the thin-film transistor and increasing its Cst.

[0067] Alternatively, the area of ​​the first metal region 141 of the source of the thin-film transistor can be reduced, thereby reducing the first overlapping region generated by the orthogonal projection of its source and gate 121 onto the substrate 110, thus reducing the Cgs of the thin-film transistor and reducing the feed-through voltage of the thin-film transistor.

[0068] Therefore, by gradually increasing the first distance between multiple TFTs connected to the same scan line from the center to the side of the substrate 110; and / or by gradually decreasing the first metal region 141 between multiple TFTs connected to the same scan line from the center to the side of the substrate 110, it is possible to achieve a greater reduction in feed-through voltage at the left and right ends than in the middle, thus compensating for the difference in feed-through voltage caused by RC loading.

[0069] Reference Figures 1 to 2 In one embodiment, each source electrode has a second metal region 142 corresponding to the common electrode 121 of the same thin-film transistor, and the area of ​​the second metal region 142 corresponding to the plurality of thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate 110.

[0070] In this embodiment, the area of ​​the second metal region 142 of the source of a thin-film transistor is increased, thereby increasing the area of ​​the second overlapping region of the thin-film transistor, which in turn increases the Cst of the thin-film transistor and reduces its feed-through voltage.

[0071] Therefore, by gradually increasing the area of ​​the second metal region 142 of the source electrodes of multiple TFTs connected to the same scan line from the center to the side of the substrate 110, the feed-through voltage at the left and right ends can be reduced more than that in the middle, thus compensating for the difference in feed-through voltage caused by RC loading.

[0072] Reference Figures 1 to 3 In one embodiment, the present invention also proposes a brightness compensation method for a display panel, the display panel including a plurality of scan lines and a plurality of thin-film transistors arranged at intervals on each scan line; the brightness compensation method for the display panel includes:

[0073] S200. Obtain the feed-through voltage of multiple thin-film transistors connected to each scan line to obtain the feed-through voltage curve of multiple thin-film transistors corresponding to the same scan line.

[0074] In this embodiment of the invention, each scan line corresponds to a feedthrough voltage curve. When plotting the feedthrough voltage curve, multiple thin-film transistors can be selected at different positions on the same scan line, such as the two ends, the middle end and the middle position. Then, the simulation software controls the display panel under test to perform simulation work to collect data from the selected multiple thin-film transistors, thereby obtaining the corresponding feedthrough voltage parameters. Based on the parameters, a smooth curve corresponding to the scan line, i.e., the feedthrough voltage curve, is plotted.

[0075] S300: Obtain the corresponding compensation curve based on each feed-through voltage curve and the preset target feed-through voltage;

[0076] In this embodiment of the invention, the target feedthrough voltage is the desired feedthrough voltage for each thin-film transistor (TFT) in the display panel under test. It is related to the charging rate of the display panel. Therefore, when the tester inputs the TFT data of the panel under test into the simulation system, a target feedthrough voltage corresponding to its charging rate can be generated. Based on the required reduction in different parts of the feedthrough voltage, a compensation value between the feedthrough voltage curve and the target feedthrough voltage is obtained, serving as a compensation curve. Thus, the required compensation value for the feedthrough voltage of each TFT can be obtained based on the compensation curve.

[0077] S400, Adjust the first overlap area of ​​the gate 121 and source of the thin-film transistor and / or the second overlap area of ​​the common electrode 122 and source of the thin-film transistor according to each of the compensation curves.

[0078] In this embodiment of the invention, according to the feed-through voltage formula, the feed-through voltage of the thin-film transistor is related to Vgh, Vgl, Cgs, Clc, and Cst. Here, Vgh is the turn-on voltage of the thin-film transistor, Vgl is the turn-off voltage of the thin-film transistor, Cgs is the parasitic capacitance between the source and gate of the thin-film transistor, Clc is the parallel plate capacitance formed by the liquid crystal, and Cst is the storage capacitance of the thin-film transistor. Vgh and Vgl, as the control voltages of the TFT, are usually constant, while Clc is only related to the liquid crystal. Therefore, the feed-through voltage of the thin-film transistor can be changed by changing Cgs and Cst.

[0079] Therefore, in this embodiment of the invention, the overlap area between the source and gate 121 and the common electrode 122 of the thin-film transistor can be adjusted. When it is necessary to increase the feed-through voltage of the thin-film transistor, the overlap area between the source and gate 121 can be increased, and the overlap area between the source and common electrode 122 can be decreased to increase the Cgs and decrease the Cst of the thin-film transistor. Thus, according to the feed-through voltage formula ΔV = (Vgh - Vgl)Cgs / (Cgs + Clc + Cst), the feed-through voltage of the thin-film transistor can be increased. When it is necessary to decrease the feed-through voltage of the thin-film transistor, the overlap area between the source and gate 121 can be decreased, and the overlap area between the source and common electrode 122 can be increased to decrease the Cgs and increase the Cst of the thin-film transistor. Thus, according to the feed-through voltage formula ΔV = (Vgh - Vgl)Cgs / (Cgs + Clc + Cst), the feed-through voltage of the thin-film transistor can be decreased.

[0080] The technical solution of this invention obtains the target feedthrough voltage and the feedthrough voltage curve for each scan line by inputting the data of the display panel under test into a simulation program. Based on the target feedthrough voltage curve, the compensation curve for the thin-film transistors of each scan line is obtained. Thus, the overlapping area of ​​multiple thin-film transistors on each scan line can be adjusted according to the compensation curve, reducing the feedthrough voltage difference between multiple thin-film transistors in the same scan line, thereby reducing the brightness difference of the display panel when emitting light and achieving the uniformity of the display panel.

[0081] Reference Figures 1 to 4 In one embodiment, the scan has two sides symmetrical about the center line, and the feed-through voltage of the thin-film transistor connected to each scan line is obtained to obtain feed-through voltage curves of multiple thin-film transistors corresponding to the same scan line, including:

[0082] S210. Select multiple thin-film transistors on one side of each scan line and collect the holding voltage and peak voltage of each thin-film transistor during operation.

[0083] S220. Based on the holding voltage and peak voltage, obtain the feed-through voltage of the corresponding thin-film transistor;

[0084] S230. Based on the symmetry of the feed-through voltage curve and the feed-through voltage of multiple thin-film transistors, obtain the feed-through voltage curve of multiple thin-film transistors corresponding to each scan line.

[0085] In this embodiment of the invention, since the method of the present invention is a simulation method, when the thin-film transistor data of the panel under test is input into the simulation system, the peak voltage and holding voltage of the selected thin-film transistor can be automatically obtained. The feed-through voltage of a thin-film transistor is the difference between its peak voltage and holding voltage. Therefore, its feed-through voltage can be obtained based on the holding voltage and peak voltage of the thin-film transistor.

[0086] Since the scanning signal of the scan line is transmitted from both ends to the middle, the feedthrough voltage curve is symmetrical along the central axis. Therefore, when acquiring data from a scanned thin-film transistor, a thin-film transistor can be selected on one side of the scan line. After plotting the curve on one side based on the feedthrough voltage of the thin-film transistor selected on one side, the curve can be symmetrically plotted along the central axis to obtain the complete feedthrough voltage curve.

[0087] Reference Figures 1 to 3 In one embodiment, obtaining the corresponding compensation curve based on each feedthrough voltage curve and a preset target feedthrough voltage includes:

[0088] S310. Subtract the target feed-through voltage from each feed-through voltage curve to obtain the compensation curves corresponding to the multiple thin-film transistors connected to each scan line.

[0089] In this embodiment of the invention, since the feed-through voltage of the thin-film transistors at both ends of a scan line is greater than that of the thin-film transistor in the middle, and when adjusting the feed-through voltage of the multiple thin-film transistors in the scan line, the feed-through voltage of the thin-film transistor in the middle is usually used as a reference. This makes the feed-through voltage represented by the feed-through voltage curve usually higher than the target feed-through voltage. Thus, by subtracting the feed-through voltage curve from the target feed-through voltage, the compensation curve corresponding to the multiple thin-film transistors connected to the scan line can be obtained.

[0090] Reference Figures 1 to 5 In one embodiment, adjusting the alignment deviation of the metal layer corresponding to the gate and the metal layer corresponding to the source of the thin-film transistor according to each compensation curve, so as to compensate the feed-through voltage of each thin-film transistor in the display panel under test to the target feed-through voltage, specifically includes:

[0091] S410. Obtain the target compensation voltage of each thin-film transistor in the corresponding scan line according to the compensation curve;

[0092] S420, Adjust the first overlapping area of ​​the source and gate 121 in each thin film transistor projected onto the substrate 110, and / or the area of ​​the source and common electrode 122 projected onto the substrate 110 having a second overlapping area, so that the current compensation voltage corresponding to each thin film transistor reaches the target compensation voltage.

[0093] In this embodiment of the invention, the data in the compensation curve corresponding to a scan line is matched with each thin-film transistor in the scan line to obtain the compensation data of multiple thin-film transistors on the scan line. Since the compensation curve is obtained based on the corresponding feedthrough voltage curve, and the feedthrough voltage curve is drawn by the selected thin-film transistors of each scan line, it is possible to obtain the compensation value of each thin-film transistor on the scan line by collecting a small amount of data from the thin-film transistors.

[0094] When adjusting a thin-film transistor (TFT) according to a compensation curve, adjusting the first overlapping region of the source and gate 121 of a TFT projected onto the substrate 110 can change the Cgs of the TFT. Adjusting the second overlapping region of the source and common electrode 122 of a TFT projected onto the substrate 110 can change the Cst of the TFT. According to the feedthrough voltage formula ΔV=(Vgh-Vgl)Cgs / (Cgs+Clc+Cst), if the feedthrough voltage of a TFT is to be reduced, the Cgs of the TFT can be reduced and / or the Cst can be increased according to its compensation value. That is, the area of ​​the first overlapping region of the TFT can be reduced alone, the area of ​​the second overlapping region of the TFT can be increased alone, or the area of ​​the first overlapping region of the TFT can be reduced and the area of ​​the second overlapping region of the TFT can be increased at the same time.

[0095] To increase the feed-through voltage of a thin-film transistor (TFT), the Cgs of the TFT can be increased and / or the Cst can be decreased according to its compensation value. That is, the area of ​​the first overlapping region of the TFT can be increased alone, the area of ​​the second overlapping region of the TFT can be decreased alone, or the area of ​​the first overlapping region of the TFT can be increased while the area of ​​the second overlapping region of the TFT is decreased.

[0096] Reference Figures 1 to 5 In one embodiment, adjusting the first overlapping region of the orthographic projection of the source and gate 121 in each thin-film transistor onto the substrate 110, and / or the area of ​​the second overlapping region of the orthographic projection of the source and common electrode 122 onto the substrate 110 specifically includes:

[0097] The source of each thin-film transistor in the display panel under test is translated; and / or,

[0098] Reduce the area of ​​the first metal region 141 of the source of each thin-film transistor in the display panel under test; and / or,

[0099] Increase the area of ​​the second metal region 142 of the source of each thin-film transistor in the display panel under test.

[0100] In this embodiment of the invention, the source of the thin-film transistor is translated along the X-axis with the drain of the same thin-film transistor as a reference.

[0101] When manufacturing a display panel, if it is necessary to reduce the feed-through voltage of the thin-film transistor, the first distance between the source and drain 143 of the thin-film transistor can be reduced, thereby reducing the first overlapping area and increasing the second overlapping area, thus reducing the Cgs of the thin-film transistor and increasing its Cst.

[0102] Alternatively, the area of ​​the first metal region 141 of the source of the thin-film transistor can be reduced, thereby reducing the first overlapping region and thus reducing the Cgs of the thin-film transistor. Or, the area of ​​the second metal region 142 of the source of the thin-film transistor can be increased, thereby increasing the second overlapping region and thus increasing the Cst of the thin-film transistor, thereby reducing the feed-through voltage of the thin-film transistor.

[0103] If it is necessary to increase the feed-through voltage of the thin-film transistor here, the first distance between the source and drain 143 of the thin-film transistor can be increased, thereby increasing the first overlapping area and decreasing the second overlapping area, thus increasing the Cgs of the thin-film transistor and decreasing its Cst.

[0104] Alternatively, the area of ​​the first metal region 141 of the source of the thin-film transistor can be increased, thereby increasing the first overlapping region and thus increasing the Cgs of the thin-film transistor. Or, the area of ​​the first metal region 141 of the source of the thin-film transistor can be reduced, thereby reducing the second overlapping region and thus reducing the Cst of the thin-film transistor, thereby reducing the feed-through voltage of the thin-film transistor.

[0105] Reference Figures 1 to 5 In one embodiment, after adjusting the first overlap area of ​​the gate and source of the thin-film transistor according to each of the compensation curves, the method further includes:

[0106] S500, The feed-through voltage of each thin-film transistor in the display panel under test is supplemented to the target feed-through voltage.

[0107] In this embodiment, since the area of ​​the first overlapping region corresponding to the plurality of TFTs connected to the same scan line gradually decreases from the center to the side of the substrate 110; and / or, the area of ​​the second overlapping region corresponding to the plurality of TFTs connected to the same scan line gradually increases from the center to the side of the substrate 110, the feed-through voltage difference between each thin-film transistor in the same scan line can be reduced. Ideally, when the feed-through voltage difference is adjusted to 0, the feed-through voltage of each thin-film transistor can be compensated to the target feed-through voltage.

[0108] The present invention also proposes a storage medium including the above-described brightness compensation method for a display panel. The specific structure of the brightness compensation method for the display panel is as described in the above embodiments. Since this storage medium adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0109] The above are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes multiple scan lines and multiple thin-film transistors connected to each scan line. The display panel also includes: substrate; A first metal layer is disposed above the substrate, and the first metal layer includes a gate electrode and a common electrode. A gate insulating layer is disposed above the first metal layer; A second metal layer is disposed above the gate insulating layer, and the second metal layer includes a source and a drain. Wherein, the source and gate of the same thin-film transistor have a first overlapping region in their orthogonal projection onto the substrate, and the area of ​​the first overlapping region corresponding to multiple thin-film transistors connected to the same scan line gradually decreases from the center to the side of the substrate; and / or, The source and common electrode of the same thin-film transistor have a second overlapping region in their orthogonal projection on the substrate, and the area of ​​the second overlapping region corresponding to the plurality of thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate; In the same thin-film transistor, there is a first distance between the source and the drain, and the first distance between a plurality of thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate; and / or, Each of the source transistors has a first metal region corresponding to the first portion of the same thin-film transistor, and the area of ​​the first metal region corresponding to the plurality of thin-film transistors connected to the same scan line gradually decreases from the center to the side of the substrate; and / or Each of the source transistors has a second metal region corresponding to the second portion of the same thin-film transistor, and the area of ​​the second metal region corresponding to the plurality of thin-film transistors connected to the same scan line gradually increases from the center to the side of the substrate.

2. A brightness compensation method for a display panel, the display panel comprising a plurality of scan lines and a plurality of thin-film transistors spaced apart on each of the scan lines; characterized in that, The brightness compensation method for the display panel includes: The feed-through voltage of the multiple thin-film transistors connected to each scan line is obtained to obtain the feed-through voltage curve of the multiple thin-film transistors corresponding to the same scan line; Based on each feedthrough voltage curve and the preset target feedthrough voltage, the corresponding compensation curve is obtained; The first overlap area of ​​the gate and source of the thin-film transistor, and / or the second overlap area of ​​the common electrode and source of the thin-film transistor, are adjusted according to each of the compensation curves. The adjustment of the alignment deviation of the metal layer corresponding to the gate and the metal layer corresponding to the source of the thin-film transistor according to each of the compensation curves specifically includes: The target compensation voltage of each thin-film transistor in the corresponding scan line is obtained according to the compensation curve; Adjust the first overlapping region of the source and gate in the substrate in each thin film transistor, and / or the area of ​​the second overlapping region of the source and common electrode in the substrate, so that the current compensation voltage corresponding to each thin film transistor reaches the target compensation voltage. The adjustment of the area of ​​the first overlapping region of the source and gate of each thin-film transistor in the orthogonal projection onto the substrate, and / or the area of ​​the second overlapping region of the source and common electrode in the orthogonal projection onto the substrate, so that the current compensation voltage corresponding to each thin-film transistor reaches the target compensation voltage, specifically includes: The source of each of the thin-film transistors in the display panel under test is translated; and / or, Reduce the area of ​​the first metal region of the source electrode of each of the thin-film transistors in the display panel under test; and / or, Increase the area of ​​the second metal region of the source electrode of each of the thin-film transistors in the display panel under test.

3. The brightness compensation method for a display panel as described in claim 2, characterized in that, The scan line has two sides symmetrical about the center line axis. The step of obtaining the feed-through voltage of the thin-film transistor connected to each scan line to obtain feed-through voltage curves of multiple thin-film transistors corresponding to the same scan line includes: Multiple thin-film transistors on one side of each scan line are selected, and the holding voltage and peak voltage of each thin-film transistor during operation are collected. Based on the holding voltage and the peak voltage, the feed-through voltage corresponding to the thin-film transistor is obtained; Based on the symmetry of the feedthrough voltage curve and the feedthrough voltage of the plurality of thin-film transistors, the feedthrough voltage curve of the plurality of thin-film transistors corresponding to each scan line is obtained.

4. The brightness compensation method for a display panel as described in claim 2, characterized in that, The step of obtaining the corresponding compensation curve based on each feedthrough voltage curve and a preset target feedthrough voltage includes: The difference between each feedthrough voltage curve and the target feedthrough voltage is used to obtain the compensation curve corresponding to the plurality of thin-film transistors connected to each scan line.

5. The brightness compensation method for a display panel as described in claim 2, characterized in that, The step of adjusting the first overlap area of ​​the gate and source of the thin-film transistor according to each of the compensation curves, and / or the second overlap area of ​​the common electrode and source of the thin-film transistor, further includes: The feed-through voltage of each thin-film transistor in the display panel under test is supplemented to the target feed-through voltage.

6. A storage medium, characterized in that, The storage medium includes the brightness compensation method for the display panel as described in any one of claims 2-5.

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