Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a first substrate, a second substrate, a spacer and a liquid crystal layer arranged between the first substrate and the second substrate; the second substrate comprises a substrate, a driving circuit layer arranged on the substrate and comprising at least one driving device, a passivation layer arranged on the driving circuit layer, the passivation layer being provided with a first opening for exposing an electrode of the at least one driving device, a first electrode comprising a first part and a second part, the first part being arranged in the first opening and electrically connected with the electrode of the driving device, and the second part being arranged on the passivation layer, a conductive part arranged on the second part of the first electrode, and a second electrode arranged on the passivation layer, a part of the second electrode covering the second part and the conductive part, wherein the conductive part is electrically connected with the second part of the first electrode and the second electrode respectively.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] VR (Virtual Reality) technology is developing towards higher PPI (Pixels Per Inch) and higher brightness as market demands; at the same time, the market also has higher requirements for VR products in terms of color distortion, crosstalk and other issues.

[0003] Therefore, there is an urgent need for a new type of LCD (Liquid-Crystal Display) VR design to solve the above problems. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device to solve the technical problem in the related art where the large overlap area between two electrodes leads to light leakage in the overlapping part and a deterioration in optical quality.

[0005] To solve the above problems, the technical solution provided by the present invention is as follows:

[0006] This invention provides a display panel, including a first substrate and a second substrate, with a liquid crystal layer and a spacer disposed between the first substrate and the second substrate. The second substrate includes:

[0007] Substrate;

[0008] A driving circuit layer, disposed on the substrate, includes at least one driving device;

[0009] A passivation layer is disposed on the driving circuit layer, and the passivation layer has a first opening that exposes the electrode of the at least one driving device;

[0010] The first electrode includes a first part and a second part, the first part being located within the first opening and electrically connected to the electrode of the driving device, and the second part being located on the passivation layer;

[0011] A conductive portion is disposed on the second portion of the first electrode, and the orthogonal projection of the conductive portion on the passivation layer is located within the orthogonal projection range of the spacer on the passivation layer. The spacer is correspondingly disposed on the conductive portion to jointly support the first substrate.

[0012] A second electrode is disposed on the passivation layer, and at least a portion of the second electrode covers the second part and the conductive part;

[0013] The conductive portion is electrically connected to the second portion of the first electrode and the second electrode, respectively.

[0014] In one embodiment, the display panel includes a light-shielding portion, the first opening being located within the range of the light-shielding portion, and the second portion being located on the passivation layer and within the range of the light-shielding portion.

[0015] In one embodiment, the second substrate further includes a color resist layer and a first light-shielding layer. The color resist layer is disposed between the driving circuit layer and the passivation layer. The color resist layer includes a plurality of color resists spaced apart. The first light-shielding layer is disposed on one side of the color resist layer near the first substrate. The first light-shielding layer includes a first light-shielding portion. At least a portion of the orthographic projection of the first light-shielding portion on the driving circuit layer is located between the orthographic projections of two adjacent color resists on the driving circuit layer.

[0016] In one embodiment, the at least one driving device includes a first transistor, the first transistor including a first source and a first drain, the first source being electrically connected to the first electrode through the first opening, and the orthographic projection of the first drain on the substrate at least partially coinciding with the orthographic projection of the first light-shielding portion on the substrate.

[0017] In one embodiment, the driving circuit layer includes a first source-drain layer, the first source-drain layer includes a first drain and a first trace portion, the first light-shielding layer further includes a second light-shielding portion, the third electrode further includes a second portion, and the second portion of the third electrode is electrically connected to the second light-shielding portion and the first trace portion.

[0018] In one embodiment, the second substrate includes a display area and a non-display area surrounding the display area, and the at least one driving device further includes a second transistor; wherein the first transistor is an indium gallium zinc oxide transistor, the second transistor is a polysilicon transistor, the first transistor is located in the non-display area, and the second transistor is located in the display area.

[0019] In one embodiment, a second light-shielding layer is provided on the first substrate, the second light-shielding layer is located within the range of the light-shielding portion, and the second light-shielding layer is located on the side of the first substrate facing the second substrate;

[0020] The material of the first light-shielding layer includes metal, and the material of the second light-shielding layer includes at least one of light-shielding metal and light-shielding resin.

[0021] In one embodiment, the second substrate further includes a filling portion disposed within the first opening and located on the first portion of the first electrode, the filling portion being supported by the conductive portion.

[0022] In one embodiment, the filling portion comprises a black light-blocking material.

[0023] In one embodiment, the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer is located on the color resist layer, the first light-shielding layer is disposed on the first passivation layer, the second passivation layer is located on the first light-shielding layer, and the first opening is formed in the first passivation layer and the second passivation layer, wherein the first opening is located between two adjacent color resist layers.

[0024] In a second aspect, embodiments of the present invention provide a display device, including a display panel as described in any of the embodiments of the first aspect and a housing, wherein the display panel is mounted on the housing.

[0025] The beneficial effects of the present invention are as follows: by providing a conductive part on the second part of the first electrode and electrically connecting the first electrode and the second electrode through the conductive part, the contact area of ​​the first electrode and the second electrode at the conductive part is increased. Therefore, the overlapping part of the first electrode and the second electrode in other parts can be reduced, thereby reducing the area affecting the light emission of the display panel, ensuring optical quality, and improving the technical problem in related technologies where the overlapping area between the two electrodes is large, thereby reducing the light emission of the overlapping part and causing the optical quality to deteriorate. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Appendix Figure 1 This is a schematic diagram of the structure of the second substrate in the related technology of the present invention;

[0028] Appendix Figure 2 This is a schematic diagram of the structure of the second substrate in one embodiment of the present invention;

[0029] Appendix Figure 3 This is a top view of the second substrate in one embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0031] In related technologies, such as Figure 1 The display panel shown includes a passivation layer, a first electrode 303, a connecting electrode 304 (i.e., a second electrode), a first support 301, and a second support 302. The passivation layer has an opening, a portion of the first electrode 303 is located within the opening, and another portion of the first electrode 303 is located on the passivation layer. The first support 301 is located within the opening and on the first electrode 303. The second support 302 is located on the first support 301. The connecting electrode 304 is located on the second support 302 and the other portion of the first electrode 303. It is understood that in order to achieve a good electrical connection between the two electrodes, the overlapping area between them needs to be set to be large to increase the contact area. However, the overlapping area between the first electrode 303 and the connecting electrode 304 will affect the light emission of the display panel, thereby resulting in a deterioration in the final optical quality.

[0032] Embodiments of the present invention provide a display panel to solve the technical problem in the related art where the large overlap area between two electrodes reduces the light output of the overlap portion, resulting in a deterioration in optical quality.

[0033] The display panel includes a first substrate 200 and a second substrate 100, which are disposed opposite to each other, and liquid crystal is disposed between the first substrate 200 and the second substrate 100. A spacer 202 is also disposed between the first substrate 200 and the second substrate 100, and the spacer 202 is used to support the first substrate 200 and the second substrate 100.

[0034] The display panel can be used in a display device, which can be a device for displaying video or still images. It can be a fixed terminal such as a television, desktop computer, monitor, or billboard, or a mobile terminal such as a mobile phone, tablet computer, mobile communication terminal, electronic notebook, e-book, multimedia player, navigator, or laptop computer. It can also be a wearable electronic device such as a smartwatch, smart glasses, virtual reality device, or augmented reality device.

[0035] like Figure 2 As shown, the second substrate 100 includes a substrate 101, a driving circuit layer, a passivation layer, a first electrode, a conductive portion 120, and a second electrode 121.

[0036] The driving circuit layer is located on the substrate 101, and the driving circuit layer includes a first transistor. A passivation layer is disposed on the driving circuit layer, and the passivation layer has a first opening that exposes either the drain or source of the first transistor. The first electrode includes a first portion 1192 and a second portion 1191. The first portion 1192 is located within the first opening and is electrically connected to either the drain or source of the first transistor. The second portion 1191 is located on the passivation layer. A conductive portion 120 is disposed on the second portion 1191 of the first electrode. The orthographic projection of the conductive portion 120 onto the passivation layer lies within the orthographic projection range of the spacer 202 onto the passivation layer. The conductive portion 120 and the spacer 202 together support the first substrate 200. A second electrode 121 is disposed on the passivation layer, and a portion of the second electrode 121 covers the second portion 1191 and the conductive portion 120. The conductive portion 120 is electrically connected to both the second portion 1191 of the first electrode and the second electrode 121.

[0037] Understandably, since the conductive portion 120 is located on the second portion 1191 of the first electrode, and the second electrode 121 partially covers the second portion 1191 and the conductive portion 120, the second electrode 121 can be connected to the first electrode through the conductive portion 120. Compared with the case in the related art where the second support cannot provide a conductive connection between the first electrode and the second electrode 121, the contact area of ​​the first electrode and the second electrode 121 in this invention is increased, thereby reducing the overlapping portion of the first electrode and the second electrode 121, and further reducing the area affecting the light emission of the second substrate 100, thus ensuring optical quality.

[0038] In this embodiment, by providing a conductive portion 120 on the second part 1191 of the first electrode and covering the first opening with the conductive portion 120, the first electrode and the second electrode 121 can be electrically connected through the conductive portion 120, thereby increasing the contact area between the first electrode and the second electrode 121. As a result, the overlapping portion of the first electrode and the second electrode 121 can be reduced, thereby reducing the area affecting the light emission of the second substrate 100, ensuring optical quality, and improving the technical problem in related technologies where the overlapping area between the two electrodes is large, thereby reducing the light emission of the overlapping portion and causing a deterioration in optical quality.

[0039] For example, the conductive portion 120 may cover the first opening.

[0040] like Figure 2As shown, in one embodiment, the second substrate 100 includes a substrate 101, a first insulating layer, a driving circuit layer, a color resist layer 114, a planarization layer, a passivation layer, a first electrode, a second electrode 121, and a third electrode.

[0041] The substrate 101 may include a single-layer insulating material such as glass, quartz, and polymer resin, or a multilayer insulating material such as a double-layer polymer resin. The substrate 101 may be a rigid substrate 101 or a flexible substrate 101. The substrate 101 supports a film layer disposed thereon.

[0042] In one embodiment, the substrate 101 includes a display area and a non-display area. The display area may be a region for setting sub-pixels to display an image. The non-display area may be a region for providing driving signals to pixel driving circuits that are set as sub-pixels, such as gate driving circuits, and some lines connecting the driving units, such as power lines. No sub-pixels may be set in the non-display area. The non-display area may be located on at least one side of the display area. The non-display area may at least partially surround the display area.

[0043] The display area can have various shapes. For example, the display area can be provided in various shapes, such as a closed polygon including straight sides, a circle including curved sides, an ellipse, etc., and a semicircle including straight sides and curved sides, a semi-ellipse, etc. When the display area includes multiple areas, each area can also be provided in various shapes, such as a closed polygon including straight sides and a circle including curved sides, an ellipse, etc. In embodiments of this disclosure, as an example, the case where the display area is provided as an area having a quadrilateral shape including straight sides is described. A non-display area can be disposed on at least one side of the display area. The non-display area can at least partially surround the periphery of the display area.

[0044] In one embodiment, the driving circuit layer includes an active portion, a gate layer, a first gate insulating layer 104, a second gate insulating layer 105, a third gate insulating layer 107, a first source-drain layer, a second source-drain layer, a first interlayer insulating layer 109, a second interlayer insulating layer 111, a third interlayer insulating layer 113, and a first source 112.

[0045] The active part may include polycrystalline silicon or oxide semiconductor. The oxide semiconductor may include any one of oxides or composite oxides of titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In).

[0046] The active portion may include a semiconductor pattern. Each semiconductor pattern may include: a channel region overlapping the gate in the thickness direction; and source and drain regions located on one side and the other side of the channel region, respectively. The source and drain regions are conductive regions, which can have higher conductivity and lower resistance compared to the channel region. An oxide semiconductor layer is formed using physical vapor deposition, and the active layer is formed by patterning the oxide semiconductor layer.

[0047] In this embodiment, the active portion includes a first active portion 106 and a second active portion 103. The second active portion 103 is located on the substrate 101.

[0048] The first gate insulating layer 104 is located on the second active portion 103. The gate layer is located on the first gate insulating layer 104, and the gate layer includes a first gate 1052 and a second gate 1051. The second gate insulating layer 105 is located on the gate layer, the first active portion 106 is located on the second gate insulating layer 105, and the third gate insulating layer 107 is located on the first active portion 106. The second source-drain layer is located on the third gate insulating layer 107, and the second source-drain layer includes a second drain 1081, a second source 1082, and a second trace portion 1083. The second drain 1081 and the second source 1082 are electrically connected to the second active portion 103 through an opening.

[0049] The gate insulating layers (first gate insulating layer 104, second gate insulating layer 105, and third gate insulating layer 107) may include silicon compounds, metal oxides, etc. For example, the gate insulating layers may include silicon oxides, silicon nitrides, silicon nitrides, aluminum oxides, tantalum oxides, hafnium oxides, zirconium oxides, titanium oxides, etc. These materials may be used alone or in combination with each other.

[0050] The gates (first gate 1052 and second gate 1051) can be made of a low-resistivity material. The gates may include, but are not limited to, one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0051] The first interlayer insulating layer 109 is located on the second source-drain layer, and the first source-drain layer is located on the first interlayer insulating layer 109. The first source-drain layer includes a first drain 1112 and a first trace portion 1111. The first drain 1112 is electrically connected to the first active portion 106 through an opening. The orthographic projection of the first trace portion 1111 on the substrate 101 is within the orthographic projection range of the first active portion 106 on the substrate 101. The second interlayer insulating layer 111 is located on the first source-drain layer, and the first source 112 is located on the second interlayer insulating layer 111. The first source 112 is electrically connected to the first active portion 106 through a second opening. The second opening sequentially penetrates the second interlayer insulating layer 111, the first interlayer insulating layer 109, and the third gate insulating layer 107. The third interlayer insulating layer 113 is located on the first source electrode 112. It can be understood that part of the third interlayer insulating layer 113 fills the second opening and is located on the first source electrode 112.

[0052] like Figure 3 As shown, the second substrate 100 further includes a first data line Data1 and a second data line Data2. The first data line may be located in the first source-drain layer and electrically connected to the first drain 1113. The second data line may be located in the second source-drain layer and electrically connected to the second drain 1081.

[0053] The interlayer insulating layers (first interlayer insulating layer 109, second interlayer insulating layer, and third interlayer insulating layer 113) may include silicon compounds, metal oxides, etc. For example, the interlayer insulating layers may include silicon oxides, silicon nitrides, silicon nitrides, aluminum oxides, tantalum oxides, hafnium oxides, zirconium oxides, titanium oxides, etc. These substances may be used alone or in combination with each other.

[0054] The source / drain layers (first source / drain layer and second source / drain layer) may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The source / drain layers may be single-layer or multi-layer films. For example, the source / drain layers may be formed as a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0055] Understandably, the first gate 1052, the first active portion 106, the first drain 1112, and the first source 112 can constitute the first transistor, wherein the first source 112 can serve as the drain of the first transistor. The second gate 1051, the second active portion 103, the second drain 1081, and the second source 1082 can constitute the second transistor.

[0056] In some embodiments, the material of the first active portion 106 may be IGZO (indium gallium zinc oxide), and the material of the second active portion 103 may be polycrystalline silicon. It is understood that the first transistor and the second transistor may constitute an LTPO structure. The first transistor may serve as a driving transistor in a pixel, and the second transistor may serve as a control transistor in a pixel. In some embodiments, the first transistor may be located in the display area of ​​the second substrate 100, and the second transistor may be located in the non-display area of ​​the second substrate 100.

[0057] The color resist layer 114 is located on the third interlayer insulating layer 113. The color resist layer 114 includes a plurality of color resists spaced apart, including a first color resist 1141 (R), a second color resist 1142 (G), and a third color resist (B). In this embodiment, a portion of the second color resist 1142 fills the second opening.

[0058] The planarization layer includes a first planarization layer 115. The planarization layer is typically thick and provides a flat surface for the deposition of other film layers. The planarization layer may include inorganic insulating materials or organic insulating materials such as polyacrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). The planarization layer may also include, but is not limited to, photosensitive materials.

[0059] In this embodiment, the first planarization layer 115 is located on the color resist layer 114. The passivation layer includes a first passivation layer 116, a second passivation layer 118, and a third passivation layer 122, with the first passivation layer 116 located on the first planarization layer 115 and the second passivation layer 118 located on the first passivation layer 116.

[0060] The passivation layer may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide. The passivation layer may be formed in the display area, but not in at least a portion of the non-display area.

[0061] In one embodiment, the first opening is located between two adjacent color resistors, and the first opening sequentially penetrates the second passivation layer 118, the first passivation layer 116, the first planarization layer 115, and the third interlayer insulating layer 113. The first electrode includes a first portion 1192 and a second portion 1191. The first portion 1192 is located within the first opening and is electrically connected to the first source 112 of the first transistor, and the second portion 1191 is located on the second passivation layer 118.

[0062] In one embodiment, the second substrate 100 further includes a filling portion 203. The conductive portion 120 is disposed on the second portion 1191 of the first electrode and covers the first opening. The filling portion 203 is supported on the conductive portion 120. The second electrode 121 is disposed on the second passivation layer 118, and the third passivation layer 122 is located on the second electrode 121. A portion of the second electrode 121 covers the second portion 1191 of the first electrode and the conductive portion 120. The conductive portion 120 is electrically connected to both the second portion 1191 of the first electrode and the second electrode 121.

[0063] In one embodiment, the filling portion 203 is a black light-shielding material, including but not limited to Cr, Mo, W or WMo, MoOx, etc., and the thickness of the filling portion 203 can be 10-200 nm. By setting the filling portion 203 to black, the filling portion 203 can fill the first opening and improve the light efficiency, and at the same time, it can play a light-shielding role, improving the color shift and light leakage of the second substrate 100.

[0064] In one embodiment, the second substrate 100 further includes a light-shielding layer located between the first passivation layer 116 and the second passivation layer 118. The light-shielding layer includes a first light-shielding portion 1172 and a second light-shielding portion 1171. At least a portion of the orthographic projection of the first light-shielding portion 1172 on the driving circuit layer is located between the orthographic projections of two adjacent color resists on the driving circuit layer.

[0065] For example, the orthographic projection of the first drain 1112 on the substrate 101 at least partially overlaps with the orthographic projection of the first light-shielding portion 1172 on the substrate 101.

[0066] In one embodiment, the second substrate 100 further includes a third electrode located on the third passivation layer 122. The third electrode includes a first portion 1231 and a second portion 1232. The orthographic projection of the first portion 1231 of the third electrode onto the driving circuit layer is located within the orthographic projection range of the conductive portion 120 onto the driving circuit layer. The second portion 1232 of the third electrode passes through the passivation layer and is electrically connected to the second light-shielding portion 1171 and the first trace portion 1111.

[0067] A second light-shielding layer is disposed on the first substrate 200, and the second light-shielding layer is located on the side of the first substrate 200 facing the second substrate 100. The second light-shielding layer includes a third light-shielding portion 201, which is positioned directly opposite the conductive portion 120. A spacer 202 is disposed between the third light-shielding portion 201 and the first portion 1231 of the third electrode. The spacer 202 and the conductive portion 120 can support the first substrate 200. Exemplarily, the material of the first light-shielding layer includes a light-shielding metal, and the material of the second light-shielding layer includes at least one of a light-shielding metal and a light-shielding resin.

[0068] Secondly, embodiments of the present invention provide a display device, the display device being a display panel and a housing as described in any embodiment of the first aspect, wherein the display panel is mounted on the housing.

[0069] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A display panel, comprising a first substrate and a second substrate, wherein a liquid crystal layer and a spacer are disposed between the first substrate and the second substrate, characterized in that, The second substrate includes: Substrate; A driving circuit layer is disposed on the side of the substrate facing the first substrate, and includes at least one driving device; A passivation layer is disposed on the driving circuit layer, and the passivation layer has a first opening that exposes the electrode of the at least one driving device; The first electrode includes a first part and a second part, wherein the first part is located within the first opening and is electrically connected to the electrode of the driving device. A conductive portion is disposed on the second portion of the first electrode, and the orthogonal projection of the conductive portion on the passivation layer is located within the orthogonal projection range of the spacer on the passivation layer. The spacer is correspondingly disposed on the conductive portion to jointly support the first substrate. A second electrode is disposed on the passivation layer, and at least a portion of the second electrode covers the second part and the conductive part; The conductive portion is electrically connected to the second portion of the first electrode and the second electrode, respectively. The second substrate also includes a filling portion, which is disposed in the first opening and located on the first portion of the first electrode. The filling portion is supported by the conductive portion.

2. The display panel according to claim 1, characterized in that, The display panel includes a light-shielding portion, the first opening is located within the range of the light-shielding portion, and the second portion is located on the passivation layer and within the range of the light-shielding portion.

3. The display panel according to claim 2, characterized in that, The second substrate further includes a color resist layer and a first light-shielding layer. The color resist layer is disposed between the driving circuit layer and the passivation layer. The color resist layer includes a plurality of color resists spaced apart. The first light-shielding layer is disposed on one side of the color resist layer near the first substrate. The first light-shielding layer includes a first light-shielding portion. At least a portion of the orthographic projection of the first light-shielding portion on the driving circuit layer is located between the orthographic projections of two adjacent color resists on the driving circuit layer.

4. The display panel according to claim 3, characterized in that, The at least one driving device includes a first transistor, the first transistor including a first source and a first drain, the first source being electrically connected to the first electrode through the first opening, and the orthographic projection of the first drain on the substrate at least partially coinciding with the orthographic projection of the first light-shielding portion on the substrate.

5. The display panel according to claim 4, characterized in that, The driving circuit layer includes a first source-drain layer, which includes a first drain and a first trace portion. The first light-shielding layer also includes a second light-shielding portion. The second substrate also includes a third electrode, which is located on the second electrode. The third electrode also includes a second portion, which is electrically connected to the second light-shielding portion and the first trace portion.

6. The display panel according to claim 4, characterized in that, The second substrate includes a display area and a non-display area surrounding the display area, and the at least one driving device further includes a second transistor; The first transistor is an indium gallium zinc oxide transistor, and the second transistor is a polysilicon transistor. The first transistor is located in the non-display area, and the second transistor is located in the display area.

7. The display panel according to claim 3, characterized in that, The first substrate is provided with a second light-shielding layer, which is located within the range of the light-shielding portion and is located on the side of the first substrate facing the second substrate. The material of the first light-shielding layer includes metal, and the material of the second light-shielding layer includes at least one of light-shielding metal and light-shielding resin.

8. The display panel according to claim 1, characterized in that, The filling portion includes a black light-blocking material.

9. A display device, characterized in that, It includes a display panel as described in any one of claims 1-8 and a housing, wherein the display panel is mounted on the housing.

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