A weak signal protection diode array packaging method and its packaging structure

Abstract

A weak signal protection diode array packaging method and its packaging structure belong to the field of microelectronic device packaging technology. It includes a ceramic base body, a chip welding area, a wire bonding area, a wire bonding area ceramic surface, a wire bonding area metallization layer, a ring-shaped frame, a semicircular hollow recess, a semicircular hollow metallized recess, a chip welding area flat-bottomed pit ceramic surface, a chip welding area metallization layer, an outer pin back metallization layer, a sealing ring, and a shell cover. According to the height of the chip, the chip bonding area is designed to be lower than the bonding area, and a stepped bonding is implemented. The outer side of the pin is designed as a semicircular hollow metallized recess to increase the reliability of the pin welding. The problem of the existing diode chip array packaging shell size being too large and the single-plane pin welding reliability being poor, which cannot meet the requirements of miniaturization, lightweight, and high reliability, is solved. It is widely used in high-frequency signal, weak signal, and high anti-electromagnetic interference packaging technology fields.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device packaging technology, and more specifically to the field of semiconductor chip array packaging technology. In particular, it relates to a method and structure for packaging a weak signal protection diode array. Background Technology

[0002] With the development of chip processor design technology, high-speed signal transmission technology has become increasingly mature, leading to higher requirements for bandwidth and transmission rate, while simultaneously reducing the requirements for transmission power consumption. Ordinary electrostatic discharge (ESD) protection can negatively impact data transmission. A weak signal protection diode array is an array formed by integrating multiple diodes with independent protection functions across multiple channels. This array uses diodes with ultra-low leakage current and ultra-low capacitance, featuring ultra-low operating current and ultra-low standby power consumption, and is used for overvoltage protection of weak signals.

[0003] Traditional SOT (Surface Mount Technology) ceramic chip packages can only package a single chip and cannot meet the requirements of array-type multi-chip packaging. For array-type assembly of multiple diode chips—where multiple identical chips are assembled into the same package, with no interconnection or interference between them, and each chip can independently perform its function—currently only large-size package housings are used, far exceeding the SOT package size. This fails to meet the requirements of miniaturization, lightweight design, and high reliability, and the single-plane lead soldering results in poor reliability.

[0004] Traditional diodes using glass or metal encapsulation are bulky and heavy, failing to meet the growing demand for miniaturization and lightweight semiconductor devices. Plastic encapsulation suffers from drawbacks such as weak heat resistance, poor mechanical strength and electromagnetic interference resistance, and poor performance in high-frequency and weak signal applications.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The technical problem to be solved by this invention is to address the issues of excessively large package size and poor pin soldering reliability of existing diode chip arrays, which fail to meet the requirements of miniaturization, lightweighting, and high reliability.

[0007] Therefore, the present invention provides a method for packaging a weak signal protection diode array, such as... Figure 1-6 As shown. The encapsulation method is as follows:

[0008] Based on the circuit structure of the weak signal protection diode array, a multilayer ceramic substrate (ceramic base body) 1 is fabricated using LTCC multilayer ceramic fabrication technology. The top surface of the multilayer ceramic substrate is hollowed out to a predetermined depth, forming an annular frame 4 and multiple flat-bottomed recesses 2. A sealing ring 9 is welded onto the annular frame 4. A chip bonding area metallization layer 7 is fabricated on the bottom 6 of the flat-bottomed recesses 2. A wire bonding area metallization layer 302 is fabricated on the bottom surface 301 of the mesa area 3 where no recesses are formed. The depth of the flat-bottomed recesses is consistent with the thickness of the diode chip. The back of the ceramic base body 1 is then fabricated according to circuit requirements. A pin metal layer 8 is formed. A semi-circular hollow groove 5 is formed on the side of the ceramic base body 1, penetrating the ceramic base body 1. A semi-circular hollow metallized groove 501 is formed in the lower middle part of the semi-circular hollow groove 5. The lower end of the semi-circular hollow metallized groove 501 is connected to the pin metal layer 8 to increase the reliability of the pin soldering. The corresponding diode chips are assembled according to the circuit structure. According to the circuit requirements, the corresponding bonding connection is made using bonding wire to form a circuit integrity connection. The outer shell cover is placed on the sealing ring, and the airtight sealing is performed according to the set sealing process, thereby realizing the packaging of the diode array circuit.

[0009] The packaging structure of the weak signal protection diode array packaging method is as follows: Figure 2-6 As shown.

[0010] It includes a ceramic base body 1, a chip bonding area 2, a wire bonding area 3, a ceramic surface 301 of the wire bonding area, a metallization layer 302 of the wire bonding area, an annular frame 4, a semi-circular hollow groove 5, a semi-circular hollow metallization groove 501, a flat-bottomed recessed ceramic surface 6 of the chip bonding area, a metallization layer 7 of the chip bonding area, a metallization layer on the back of the outer pin 8, a sealing ring 9, and a housing cover plate.

[0011] The chip bonding area 2 and the wire bonding area 3 are located in the inner cavity of the ceramic base body 1. The chip bonding area 2 is a flat-bottomed recess, and a chip bonding area metallization layer 7 is placed on the ceramic surface 6 of the flat-bottomed recess. The wire bonding area 3 and the chip bonding area 2 form a stepped shape, and the height of the step is the depth of the flat-bottomed recess, which is the thickness of the diode chip. A wire bonding area metallization layer 302 is placed on the ceramic surface 301 of the wire bonding area.

[0012] The annular frame 4 is located around the ceramic base body 1 and is higher than the bottom plane of the ceramic base body 1; the sealing ring 9 is located above the annular frame 4, and the top of the sealing ring 9 is the outer shell cover plate. The enclosed space formed by the outer shell cover plate, the bottom plane of the ceramic base body 1, the annular frame 4, and the sealing ring 9 is a cavity.

[0013] The semi-circular hollow groove 5 is located on the side of the ceramic base body 1 and is perpendicular to the square bottom surface of the ceramic base body 1. At the lower middle end of the semi-circular hollow groove 5 is a semi-circular hollow metallized groove 501, which is electrically connected to the metallized layer 8 on the back of the outer pin.

[0014] The wire bonding regions 3 are distributed at both ends of the chip bonding region 2, forming a channel unit. Multiple channel units are arranged in parallel to form a diode array. The substrate of the diode chip is the positive electrode, and the surface of the diode chip is the negative electrode. There are two bonding regions. Bonding one region alone results in a single-phase diode, and bonding both regions separately results in a bidirectional diode.

[0015] The ceramic shell material is alumina ceramic or aluminum nitride ceramic.

[0016] The technical effects of this invention are as follows:

[0017] The internal cavity regions correspond to the pins on the back side and are connected to the same digital regions within the cavity via leads (conduction resistance R≤0.10Ω). To facilitate soldering, a semi-circular hollow metallized groove is designed on one side of the pins. After the diode chips are assembled and bonded, a single-channel diode path is formed, resulting in a multi-independent channel diode array.

[0018] Integrating multiple channels into one unit, it boasts high integration capabilities. While meeting the demands for increasingly lightweight and miniaturized semiconductor devices, it also features excellent insulation, rapid heat dissipation, high temperature resistance, corrosion resistance, strong electromagnetic shielding, high reliability, and broad product compatibility. It can be widely used in various products with high reliability requirements, such as semiconductor devices and hybrid integrated circuits.

[0019] It is prepared by using alumina or aluminum nitride ceramic materials and sintering them in multiple parallel layers under vacuum at 1300℃.

[0020] It resolves the contradiction between the redundant size, low integration, and poor salt spray, corrosion and oxidation resistance of metal and glass-encapsulated diode devices and the poor high temperature resistance, weak mechanical strength, poor electromagnetic interference resistance, and poor performance in high-frequency and weak signal applications of plastic-encapsulated parts.

[0021] It is widely used in the packaging technology of chips with high frequency signals, weak signals, and high requirements for electromagnetic interference resistance. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a diode array circuit.

[0023] Figure 2 This is a schematic diagram of a bidirectional diode circuit.

[0024] Figure 3 This is a schematic diagram of the front and cross-sectional structure of the ceramic base for the encapsulated housing.

[0025] Figure 4 This is a schematic diagram of the back structure of the ceramic base of the encapsulated shell.

[0026] Figure 5 This is a schematic diagram of the side structure of the ceramic base of the encapsulated shell.

[0027] Figure 6 This is a schematic diagram of the six-view structure of the ceramic base for the encapsulation shell.

[0028] Explanation of symbols in the attached diagram:

[0029] In the diagram: 1 is the ceramic base body, 2 is the chip bonding area, 3 is the wire bonding area, 301 is the ceramic surface of the wire bonding area, 302 is the metallization layer of the wire bonding area, 4 is the annular frame, 5 is the semi-circular hollow groove, 501 is the semi-circular hollow metallization groove, 6 is the flat-bottomed recessed ceramic surface of the chip bonding area, 7 is the metallization layer of the chip bonding area, 8 is the metallization layer on the back of the outer pin, and 9 is the sealing ring. Implementation

[0030] like Figure 1-4 As shown, the packaging method and structure for a weak signal protection diode array, taking the SOT23 package shape as an example, are implemented as follows:

[0031] The outer shell has external dimensions of 2.92mm × 2.82mm × 1mm, internal enclosed cavity dimensions of 1.92mm × 1.80mm, cavity height 1 of 0.3mm, and cavity height 2 of 0.2mm.

[0032] The chip bonding area is a Ni / Au metallized coating (Ni: 1.30~8.90μm, Au: 0.64~5.70μm). The length of the chip bonding area is 0.7mm~0.8mm, the width is 0.4mm~0.5mm, and the spacing between chip bonding areas is 0.2mm.

[0033] The chip soldering area has no electrical connection to the surrounding area.

[0034] The wire bonding region is a Ni / Au metallized coating (Ni: 1.30~8.90μm, Au: 0.64~5.70μm), with a length of 0.5mm and a width of 0.5mm. The spacing between the bonding regions is 0.21mm.

[0035] The sealing ring is a gold-tin sealing ring, and the cover plate is made of 4J42 with an AuSn20 solder ring, which together with the sealing ring form an airtight seal.

[0036] The metallization layers of the back pins are connected one-to-one with the designated areas inside the cavity, and are connected through internal leads.

[0037] To facilitate soldering of the finished product, a semi-circular hollow metallized groove with a radius of 0.1mm is designed on one side of the outer side of the pin.

[0038] In summary, the ceramic chip packaging of this invention provides a new technology for array packaging of chips with dimensions of less than 0.4mm*0.4mm in the field of microelectronic device packaging technology, which is lighter, more reliable, and meets the increasingly miniaturized and lightweight requirements of semiconductor devices.

[0039] The traditional SOT23 series ceramic surface mount package has dimensions of 2.92mm*2.80mm*1.00mm, which only meets the packaging function of a single chip with an area of ​​less than 0.4mm×0.4mm, and cannot meet the packaging requirements of arrays of multiple chips. For the array assembly of three diode chips with a size of less than 0.4mm×0.4mm×0.2mm, three identical chips are assembled into the same package, and the three chips are independent of each other and do not affect each other, and each chip can independently perform its function.

[0040] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This invention includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all possible implementations. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this invention are within the protection scope of this invention.

Claims

1. A method for packaging a weak signal protection diode array, characterized in that, The encapsulation method is as follows: Based on the circuit structure of the weak signal protection diode array, a ceramic base body is fabricated using LTCC multilayer ceramic manufacturing process. The top surface of the multilayer ceramic substrate is hollowed out to a set depth to form an annular frame and multiple flat-bottomed recesses. A sealing ring is welded onto the annular frame. A chip bonding area metallization layer is fabricated at the bottom of the flat-bottomed recesses. A wire bonding area metallization layer is fabricated on the bottom surface of the mesa area where no recesses are formed. The depth of the flat-bottomed recesses is consistent with the thickness of the diode chip. A pin metallization layer is fabricated on the back of the ceramic base body according to circuit requirements. A semi-circular hollow groove penetrating the ceramic base body is fabricated on the side of the ceramic base body. A semi-circular hollow metallization groove is fabricated in the lower middle part of the semi-circular hollow groove. The lower end of the semi-circular hollow metallization groove is connected to the pin metallization layer to increase pin reliability during soldering. The corresponding diode chips are assembled according to the circuit structure. Bonding wires are used to make corresponding bonding connections according to circuit requirements to form a complete circuit connection. The outer shell cover is placed on the sealing ring, and an airtight seal is performed according to the set sealing process, thereby realizing the encapsulation of the diode array circuit. The ceramic material is alumina ceramic or aluminum nitride ceramic; The packaging structure of the weak signal protection diode array packaging method includes: Ceramic base body, chip soldering area, wire bonding area, ceramic surface of wire bonding area, metallization layer of wire bonding area, annular frame, semi-circular hollow groove, semi-circular hollow metallization groove, flat-bottomed recessed ceramic surface of chip soldering area, metallization layer of chip soldering area, metallization layer on the back of outer pin, sealing ring, outer shell cover plate. The chip bonding area and the wire bonding area are located in the inner cavity of the ceramic base body. The chip bonding area is a flat-bottomed pit, and the chip bonding area metallization layer is located on the ceramic surface of the flat-bottomed pit. The wire bonding area and the chip bonding area form a stepped shape, and the height of the step is the depth of the flat-bottomed pit. The wire bonding area metallization layer is located on the ceramic surface of the wire bonding area. The annular frame is located around the ceramic base body and is higher than the bottom plane of the ceramic base body; the sealing ring is located above the annular frame, and the outer shell cover is above the sealing ring. The outer shell cover, the bottom plane of the ceramic base body, the annular frame, and the sealing ring form a cavity of closed space. The semi-circular hollow groove is located on the side of the ceramic base body and is perpendicular to the square bottom surface of the ceramic base body. At the lower middle end of the semi-circular hollow groove is a semi-circular hollow metallized groove, which is electrically connected to the metallized layer on the back of the outer pin. The wire bonding areas are distributed at both ends of the chip bonding area, forming a channel unit. Multiple channel units are arranged in parallel to form a diode array layout. The substrate of the diode chip is the positive electrode, and the surface of the diode chip is the negative electrode. There are two bonding areas. Bonding one area alone makes a single-phase diode, and bonding two areas separately makes a bidirectional diode.

2. The weak signal protection diode array packaging method as described in claim 1, characterized in that: The packaging structure has an SOT23 outer shape, with outer dimensions of 2.92mm × 2.82mm × 1mm, inner closed cavity dimensions of 1.92mm × 1.80mm, inner cavity height 1 of 0.3mm, and inner cavity height 2 of 0.2mm.

3. The packaging method for a weak signal protection diode array as described in claim 2, characterized in that: An array of three diode chips, each measuring less than 0.4mm × 0.4mm × 0.2mm, is soldered into the encapsulation cavity. The three chips are not interconnected.

4. The weak signal protection diode array packaging method as described in claim 2, characterized in that: The chip welding area is a Ni / Au metallized coating, with a length of 0.7mm~0.8mm and a width of 0.4mm~0.5mm, and the spacing between chip welding areas is 0.2mm.

5. The weak signal protection diode array packaging method as described in claim 2, characterized in that: The wire bonding area is a Ni / Au metallized coating, with a length of 0.5 mm, a width of 0.5 mm, and a spacing of 0.21 mm between bonding areas.

6. A method for packaging a weak signal protection diode array as described in claim 4 or 5, characterized in that: The thickness of Ni is 1.30 μm to 8.90 μm, and the thickness of Au is 0.64 μm to 5.70 μm.

7. The weak signal protection diode array packaging method as described in claim 1, characterized in that: The radius of the semi-circular hollow groove is 0.1 mm.

8. The weak signal protection diode array packaging method as described in claim 1, characterized in that: The sealing ring is a gold-tin sealing ring, and the cover plate is made of 4J42 with an AuSn20 solder ring, which is used for airtight sealing with the sealing ring.

9. The packaging method for a weak signal protection diode array as described in claim 1, characterized in that: The metallization layer on the back of the external pins is connected to a designated area inside the cavity, and the connection is made through the internal leads.

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