A low-delay detection method and circuit based on a wideband frequency conversion module SDLVA signal

Abstract

The application provides a low-delay detection method and circuit based on a broadband frequency conversion module SDLVA signal, which comprises the following steps: window filtering: processing N-channel AD chip acquisition data; a part of the data is directly outputted as the current moment instant; another part of the data is subjected to window filtering to obtain window-filtered AD chip acquisition data; selection: selecting the maximum value of the N-channel instant and the maximum value of the filtered value; double-threshold comparison: comparing the instant value and the filtered value by double threshold, and using the maximum value of the N-channel instant and the filtered value to obtain instant value detection switch and filtered value detection switch; decision selection: obtaining the switch state of each channel detection switch according to the instant value detection switch and the filtered value detection switch of each channel. The application uses FPGA to perform multi-stage algorithm and decision selection on AD chip acquisition data, meets the high real-time requirement, and solves the problem of large delay caused by data processing to system response.

Description

Technical Field

[0001] This invention relates to the field of control technology for broadband frequency conversion, and more specifically, to a low-delay detection method and circuit based on the SDLVA signal of a broadband frequency conversion module. Background Technology

[0002] Broadband frequency converter modules primarily convert radio frequency (RF) signals into intermediate frequency (IF) signals and are widely used in broadband electronic systems. To achieve rapid acquisition of broadband signals, the IF signal after broadband frequency conversion typically undergoes bandwidth filtering, logarithmic amplification, and video filtering before being processed by logarithmic video detection (SDLVA). Information extraction and output from the detected signal are then performed. This processing requires near real-time processing and must typically be completed within a few microseconds.

[0003] Traditional video signal detection and processing methods typically employ discrete components to form analog circuits, resulting in complex circuit designs, poor stability and reliability, and significant printed circuit board space consumption. With the development of large-scale integrated circuits, SDLVA processing has become increasingly complex, and digital signal processing technology has rapidly advanced, leading to the widespread use of combinations of analog converters (ADCs) and FPGAs. This method offers advantages such as increased circuit integration and great flexibility; however, constraints imposed by the ADC sampling frequency and FPGA clock cycle mean that data detection and processing time still cannot fully meet real-time application requirements. Furthermore, as the algorithm complexity increases, the required data processing time also increases, further impacting the real-time performance of signal detection and processing and reducing the signal interception probability. Summary of the Invention

[0004] The present invention aims to provide a low-delay detection method and circuit based on the SDLVA signal of a broadband frequency converter module, which addresses the high real-time requirements for signal detection and processing after broadband frequency conversion, while solving the problem of large delay in system response caused by data processing.

[0005] This invention provides a low-delay detection method based on the SDLVA signal of a broadband frequency converter module, comprising the following steps:

[0006] S1, sliding window filtering:

[0007] The data acquired by the N-channel AD chips is processed as follows: one part is directly output as the instantaneous current time; the other part is processed by sliding window filtering of the data acquired by the m AD chips according to the time sequence to obtain the AD chip acquired data after sliding window filtering.

[0008] S2, Select:

[0009] For N instantaneous values ​​{AD int0 AD int1 ,…,AD intN} and the filtered value {ADavg0 AD avg1 ,…,AD avgN The comparisons and sorting are performed to select the maximum value AD from the N instantaneous values. int_max and the maximum value of N-channel filter values ​​AD avg_max ;

[0010] S3, Dual Threshold Comparison:

[0011] Perform a dual-threshold comparison on the instantaneous values ​​and utilize the maximum value AD from the N instantaneous values. int_max The instantaneous value of the detector switch is obtained;

[0012] The filtered values ​​are compared using a dual-threshold method, and the maximum value (AD) of the N filtered values ​​is used. avg_max The filtered value is obtained from the detector switch;

[0013] S4, Decision Choice:

[0014] The switching state of each channel's detector switch is obtained based on the instantaneous value detector switch and the filter value detector switch of each channel.

[0015] Furthermore, in step S1, the correspondence between the instantaneous value and the data acquired by the AD chip is as follows:

[0016] {AD int0 AD int1 ,…,AD intN}={AD_Data0,AD_Data1,…,AD_Data N}

[0017] Where N is a natural number in the range (0, 1, ...), AD intN This is the instantaneous value of the Nth path.

[0018] Furthermore, in step S1, the Nth filter value AD avgN for:

[0019]

[0020] Where m is a positive integer (1,2,…).

[0021] Furthermore, in step S3, performing a dual-threshold comparison on the instantaneous values ​​includes:

[0022] Connect the N instantaneous values ​​to their corresponding instantaneous value thresholds {Thold} int0 Thold int1 ,…,Thold intN By comparing the values, the instantaneous values ​​of the N initial states of the detector switch SW are obtained. intN_Reg The Nth instantaneous value initial switch SW intN_Reg With ADintN Thold intN The following conditions should be met:

[0023]

[0024] Among them, SW intN_Reg =1 indicates that the Nth instantaneous value initial switch is on, otherwise it is off;

[0025] Nth instantaneous value detector switch SW intN The switching relationship is as follows:

[0026]

[0027] Among them, Thold diffint This is the instantaneous inter-channel threshold value.

[0028] Furthermore, in step S3, after performing a dual-threshold comparison on the filtered value, the Nth filter value detector switch SW... avgN The switching relationship is as follows:

[0029]

[0030] Among them, Thold avgN The threshold for the Nth filter value, Thold diffavg This is the threshold between filtering channels.

[0031] Furthermore, in step S4, the decision selection includes:

[0032] If any instantaneous value detector switch or filter value detector switch is set to 1, the actual detector switch output for that channel will be 1; based on this, the final detector switches {SW0, SW1, ..., SW1} for each channel are obtained. N The switch state of} is:

[0033] {SW0,SW1,…,SW N}={SW int0 ,SW int1 ,…,SW intN}or{SW avg0 ,SW avg1 ,…,SW avgN}

[0034] The present invention also provides a low-delay detection circuit based on the SDLVA signal of a broadband frequency converter module, which is used to implement the above-mentioned low-delay detection method based on the SDLVA signal of a broadband frequency converter module. The low-delay detection circuit is implemented using an FPGA and includes a sliding window filter circuit, a selection circuit, a dual-threshold comparison circuit and a decision selection circuit connected in sequence.

[0035] In summary, this invention utilizes an FPGA to perform multi-level algorithms and decision-making on the data acquired by the AD chip, realizing a low-delay detection method and circuit based on the SDLVA signal of a broadband frequency conversion module, which has the following characteristics:

[0036] 1. Utilizes sliding window filtering to remove burrs and improve noise immunity;

[0037] 2. It retains a large signal, resulting in high target detection accuracy;

[0038] 3. The logic is clear, the circuit composition is simple, and the implementation is highly feasible;

[0039] 4. The system has a fast response speed and high reliability;

[0040] 5. Suitable for broadband frequency conversion applications, with parallel processing of each frequency band without mutual interference: Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a low-delay detection method based on the SDLVA signal of a broadband frequency conversion module in an embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram of sliding window filtering in an embodiment of the present invention.

[0044] Figure 3 This is a schematic diagram of dual-threshold comparison in an embodiment of the present invention.

[0045] Figure 4 This is a schematic diagram illustrating the control timing in an embodiment of the present invention.

[0046] Figure 5 This is a simulation diagram of low-latency detection and processing as an application example in an embodiment of the present invention.

[0047] Figure 6 This is a simulation diagram of a conventional method for an application example in an embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0050] Example

[0051] like Figure 1 As shown, this embodiment proposes a low-delay detection method based on the SDLVA signal of a broadband frequency converter module, including the following steps:

[0052] S1, as Figure 2 As shown, sliding window filtering:

[0053] Data is acquired from N-channel AD chips {AD_Data0, AD_Data1, ..., AD_Data} N} to be processed:

[0054] One part directly outputs the instantaneous value at the current moment. The correspondence between the instantaneous value and the data collected by the AD chip is as follows:

[0055] {AD int0 AD int1 ,…,AD intN}={AD_Data0,AD_Data1,…,AD_Data N}

[0056] Where N is a natural number in the range (0, 1, ...), AD intN This is the instantaneous value of the Nth path;

[0057] The other part performs sliding window filtering on the data acquired by m AD chips according to the time sequence (from the current time to the previous m time steps), resulting in the filtered AD chip data. Therefore, the Nth filtered value AD... avgN for:

[0058]

[0059] Where m is a positive integer (1,2,…).

[0060] S2, Select:

[0061] For N instantaneous values ​​{AD int0 AD int1 ,…,AD intN} and the filtered value {AD avg0 AD avg1 ,…,AD avgN The comparisons and sorting are performed to select the maximum value AD from the N instantaneous values. int_max and the maximum value of N-channel filter values ​​AD avg_max .

[0062] S3, as Figure 3 As shown, dual threshold comparison:

[0063] First, perform a double threshold comparison on the instantaneous values; compare the N instantaneous values ​​with their corresponding instantaneous value thresholds {Thold}. int0 Thold int1 ,…,Thold intN By comparing with (threshold 1), the instantaneous values ​​of the N initial states of the detector switch SW are obtained. intN_Reg The instantaneous value threshold for each channel is obtained by multiplying the maximum instantaneous value over a period of time by a fixed coefficient. Based on this, the initial instantaneous value switch SW for the Nth channel is determined. intN_Reg With AD intN Thold intN The following conditions should be met:

[0064]

[0065] Among them, SW intN_Reg =1 indicates that the Nth instantaneous value initial switch is turned on, and vice versa.

[0066] Only when SW intN_Reg When T = 1, inter-channel comparison is performed on the Nth signal, where the instantaneous inter-channel threshold value is Thold. diffint (Threshold 2), otherwise the final output instantaneous value is detected by the detector switch SW. intN =SW intN_Reg =0. Nth instantaneous value detector switch SW intN The switching relationship is as follows:

[0067]

[0068] Secondly, a dual-threshold comparison is performed on the filtered value; similarly, the detector switch SW for the Nth filtered value can be obtained. avgN With the Nth filter value AD avgN The threshold Thold for the Nth filter value avgN Filtering channel threshold Thold diffavg The relationship is:

[0069]

[0070] The validity of each signal is determined by comparing the instantaneous values ​​and filtered values ​​of N channels with dual thresholds.

[0071] S4, Decision Choice:

[0072] If any instantaneous value detector switch or filter value detector switch is set to 1, the actual detector switch output for that channel will also be 1. Based on this, the final detector switches {SW0, SW1, ..., SW1} for each channel are obtained. N The switch state of} is:

[0073] {SW0,SW1,…,SW N}={SW int0 ,SW int1 ,…,SW intN}or{SW avg0 ,SW avg1 ,…,SW avgN}

[0074] This invention employs a combination of multiple AD chips and an FPGA in the detection circuit. The FPGA is used to implement multi-level algorithms and output selection, including a sliding window filter circuit, a selection circuit, a dual-threshold comparison circuit, and a decision selection circuit connected in sequence, ensuring low-latency processing of the SDLVA signal. The control timing schematic is shown below. Figure 4 As shown, after the SDLVA signal is quantized by AD_Data, it only needs one clock cycle (ns level) to complete the corresponding algorithm processing, thereby realizing the final detector switch output, which improves the system response speed and has wide applicability to broadband frequency conversion modules.

[0075] An application example:

[0076] In the development and research of a certain project, the low-latency detection method and circuit of this invention were adopted. The project used a Z7+AD9288 detection circuit to achieve 15-channel detection and independent control. Taking channel 0 as an example, ... Figure 5 As shown in the simulation results, the SDLVA signal is input via AD9288 data acquisition, and the filtered value AD is obtained through sliding window filtering. avg0 Choose the maximum instantaneous value AD. int_max and the maximum value of the filtered value AD avg_max The instantaneous value of the detector switch SW is obtained through dual threshold comparison. int0 and filter value detector switch SW avg0 Finally, output SW0 was selected, and it only took one clock cycle (10ns) from data input to obtaining a stable output result.

[0077] Under the same conditions, conventional processing methods require at least 8 clock cycles (80ns) to complete the corresponding algorithm processing, and this time increases with the number of channels. Figure 6 As shown in the figure. Through comparison, it can be seen that the present invention can significantly shorten data processing time while ensuring reliability, and has a wide range of applications, thus better meeting the needs of engineering applications.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-delay detection method based on the SDLVA signal of a broadband frequency converter module, characterized in that, Includes the following steps: S1, sliding window filtering: right N The AD chip collects and processes the data: one part directly outputs the current instant; the other part is processed according to the timing sequence. m The data collected by each AD chip is subjected to sliding window filtering to obtain the AD chip collected data after sliding window filtering. S2, Select: right N instantaneous value of the road { AD int0 , AD int1 ,…, AD intN } and filter value { AD avg0 , AD avg1 ,…, AD avgN } compare and sort to select N Maximum value of instantaneous road value AD int_max and N Maximum value of the filter path AD avg_max ; S3, Dual Threshold Comparison: Perform a dual-threshold comparison on the instantaneous values, and utilize... N Maximum value of instantaneous road value AD int_max The instantaneous value of the detector switch is obtained; Perform a dual-threshold comparison on the filtered values, and utilize... N Maximum value of the filter path AD avg_max The filtered value is obtained from the detector switch; S4, Decision Selection: The switching state of each channel detector switch is obtained based on the instantaneous value detector switch and the filter value detector switch of each channel; Step S3, performing a dual-threshold comparison on the instantaneous value, includes: Will N The instantaneous value of the path and its corresponding instantaneous value threshold { Thold int0 , Thold int1 ,…, Thold intN By comparison, we obtain N Instantaneous value detection switch of the initial state of the circuit SW intN_Reg ;No. N Road instantaneous value initial switch SW intN_Reg and AD intN , Thold intN The following conditions should be met: in, SW intN_Reg =1 indicates the first N The initial switch is turned on when the instantaneous value of the road is set to zero, and turned off when the instantaneous value is set to zero. No. N instantaneous value detector switch SW intN The switching relationships are as follows: in, Thold diffint This is an instantaneous inter-channel threshold value; In step S3, after performing a double-threshold comparison on the filtered value, the first... N Filter value detector switch SW avgN The switching relationship is as follows: in, Thold avgN For the first N Path filter threshold, Thold diffavg This is the threshold between filtering channels.

2. The low-delay detection method based on the SDLVA signal of a broadband frequency conversion module according to claim 1, characterized in that, In step S1, the correspondence between the instantaneous value and the data acquired by the AD chip is as follows: { AD int0 , AD int1 ,…, AD intN}={ AD_Data 0, AD_Data 1,…, AD_Data N} in, N For natural numbers in the range (0, 1, ...), AD intN For the first N Road instantaneous value.

3. The low-delay detection method based on the SDLVA signal of a broadband frequency conversion module according to claim 2, characterized in that, In step S1, the first N Filter value AD avgN for: in, m It is a positive integer in the range (1,2,...).

4. The low-delay detection method based on the SDLVA signal of a broadband frequency conversion module according to claim 3, characterized in that, In step S4, the decision-making process includes: If any instantaneous value detector switch or filter value detector switch is set to 1, the actual detector switch output for that channel will be 1; based on this, the final detector switch output for each channel is obtained. SW 0, SW 1,…, SW N The switch state of} is: { SW 0, SW 1,…, SW N}={ SW int0 , SW int1 ,…, SW intN}or{ SW avg0 , SW avg1 ,…, SW avgN}。 5. A low-delay detection circuit based on the SDLVA signal of a broadband frequency converter module, used to implement the low-delay detection method based on the SDLVA signal of a broadband frequency converter module as described in any one of claims 1-4, characterized in that, The low-latency detection circuit is implemented using an FPGA and includes a sliding window filter circuit, a selection circuit, a dual-threshold comparison circuit, and a decision selection circuit connected in sequence.

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