On-chip hardware semaphore array supporting multiple conditions

Abstract

Hardware semaphores are used to improve the speed of evaluating preconditions. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. A collection of hardware semaphores can be chained together to implement a chained semaphore that can support multiple conditions. Furthermore, hardware semaphores can not only have the ability to generate interrupts, but also commands, such as commands to other semaphores. A compiler can perform the implementation of a chained semaphore across multiple hardware semaphores at compile time or at runtime. An integrated circuit chip can include multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of a hardware semaphore array. A dedicated on-chip network can implement hardware semaphore communication.

Description

Background Technology

[0001] Just as physical semaphores provide an indication of whether a train can travel on a track, in computer science, semaphores refer to information indicating whether the execution of a process can continue if certain preconditions for its execution are met. For example, a consumer process might need data output by a producer process as input. The existence of this data—that is, the extent to which the producer process has completed execution up to the point of generating the output data—is a prerequisite for the consumer process to continue execution. If the consumer process attempts to continue execution before this prerequisite is established, it will fail because the necessary input data is not available. As another example, a consumer process might need a specific portion of memory to be available, and it might seek to store its output in that portion. In such an example, to avoid unintentional data overwriting, the consumer process should not continue execution and store its output in that portion of memory until a preceding process uses that portion of memory to store its own data.

[0002] Prerequisites can be defined as part of computer functionality programming using a human-readable computer programming language, or they can be created as part of program compilation. During the compilation of a program from a human-readable computer programming language into computer-executable instructions, software semaphores can be created and / or referenced to track prerequisites defined by the human-readable computer programming language or created by the compiler. These software semaphores themselves exist as computer-executable instructions, executed on processing units such as the ubiquitous Central Processing Unit (CPU).

[0003] However, in some cases, the execution of a software semaphore can add significant overhead to the execution of processes that presuppose it to be enumerated within the software semaphore. For example, a software semaphore might require one hundred clock cycles or more to execute. If the consuming process itself only requires one hundred clock cycles, the overhead of the software semaphore could potentially double the time required for the consuming process to perform its task. Summary of the Invention

[0004] Hardware semaphores are used to improve the speed of condition evaluation. Individually, each hardware semaphore can be implemented as a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement chained semaphores that can support multiple conditions. Furthermore, hardware semaphores can not only generate interrupts but also commands, such as commands for other semaphores. The compiler can execute the implementation of chained semaphores across multiple hardware semaphores at compile time or runtime. Integrated circuit chips can include multiple execution units, such as processing cores, and individual execution units within these units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. Dedicated on-chip networks enable hardware semaphore communication. A single block can include one or more execution units and one or more associated hardware semaphore arrays, and individual elements of the block can communicate with other elements within the same block. Multiple blocks can be aggregated on a single chip, using dedicated on-chip networks to enable hardware semaphores to communicate across blocks. Alternatively or additionally, multiple blocks can be aggregated into a superblock, using dedicated on-chip networks to enable hardware semaphores to communicate beyond the superblock to other parts of the chip.

[0005] This invention is intended to present, in a simplified form, some of the selected concepts further described below in the detailed embodiments. This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] Additional features and advantages will become apparent from the following detailed description with reference to the accompanying drawings. Attached Figure Description

[0007] The following detailed description may be best viewed in conjunction with the appendix. Figure 1 To understand, among which:

[0008] Figure 1 This is a block diagram of an example computing device;

[0009] Figure 2 This is a system diagram of an exemplary block circuit system that includes a hardware semaphore circuit system and an associated execution unit circuit system;

[0010] Figure 3a and Figure 3b It is a block diagram of an exemplary aggregation of multiple block circuit systems;

[0011] Figure 4a and Figure 4b This is an exemplary block diagram of a hardware semaphore circuit system for processing multiple conditions;

[0012] Figure 5 This is a block diagram of an exemplary semaphore chain implemented by a hardware semaphore circuit system to support multiple conditions; and

[0013] Figure 6 This is an exemplary flowchart for establishing a semaphore chain using a hardware semaphore circuit system. Detailed Implementation

[0014] The following description relates to improving the speed of evaluating prerequisites by utilizing hardware semaphores, whether used individually or in a sequence of multiple hardware semaphores. On an individual basis, each hardware semaphore can be implemented as a binary semaphore or a counting semaphore. Hardware semaphores are used to improve the speed of evaluating prerequisites. On an individual basis, each hardware semaphore can be implemented as a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement chained semaphores that can support multiple conditions. Furthermore, hardware semaphores can not only have the ability to generate interrupts but also commands, such as commands against other semaphores. The compiler can execute the implementation of chained semaphores across multiple hardware semaphores at compile time or runtime. An integrated circuit chip can include multiple execution units, such as processing cores, and individual execution units within an execution unit can be associated with multiple hardware semaphores, such as in the form of an array of hardware semaphores. A single block can include one or more execution units and one or more associated arrays of hardware semaphores, and individual elements of the block can communicate with other elements within the same block. Multiple blocks can be aggregated on a single chip, utilizing a dedicated on-chip network to enable hardware semaphores to communicate across blocks. Alternatively or additionally, multiple blocks can be aggregated into a superblock, using a dedicated on-chip network to enable hardware semaphores to communicate beyond the superblock to other parts of the chip.

[0015] Although not strictly required, the following description will be used in the general context of computer-executable instructions, such as program modules, executed by a computing device. More specifically, the description will refer to actions and symbolic representations of operations performed by one or more computing devices or peripheral devices, unless otherwise stated. Therefore, it should be understood that these actions and operations, sometimes referred to as computer-performed, include the manipulation of electrical signals of data represented in a structured form by a processing unit. Such manipulation transforms or maintains the data in a location in memory, which is reconfigured in a manner well known to those skilled in the art or otherwise alters the operation of the computing device or peripheral device. The data structure that maintains the data is a physical location having specific properties defined by the data format.

[0016] Typically, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. Furthermore, those skilled in the art will understand that computing devices are not limited to conventional personal computers, but include other computing configurations, including servers, handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframes, etc. Similarly, computing devices are not limited to standalone computing devices, as this mechanism can also be implemented in distributed computing environments, where tasks are performed by remote processing devices linked via communication networks. In distributed computing environments, program modules can reside on both local and remote storage devices.

[0017] Before proceeding with a detailed description of the implementation and utilization of the aforementioned hardware semaphores, please refer to... Figure 1 The exemplary computing device 100 shown is provided to offer a detailed description of the exemplary computing device, which provides context for the following description. The exemplary computing device 100 may include, but is not limited to, one or more central processing units (CPUs) 120, system memory 130, and a system bus 121 that couples various system components, including the system memory, to the processing unit 120. The system bus 121 may be any of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of various bus architectures. Depending on the specific physical implementation, one or more CPUs 120, system memory 130, and other components of the computing device 100 may be physically co-located, such as on a single chip. In this case, some or all of the system bus 121 may simply be silicon pathways within a single-chip structure, and its... Figure 1 The illustrations in the text may be merely symbols for illustrative purposes.

[0018] The computing device 100 typically also includes computer-readable media, which may include any available media accessible to the computing device 100, and includes volatile and non-volatile media as well as removable and non-removable media. By way of example, and not limitation, computer-readable media may include computer storage media and communication media. Computer storage media includes media implemented with any method or technique for storing content such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, cassette tape, magnetic tape, disk storage or other magnetic storage devices, or any other media that may be used to store desired content and is accessible to the computing device 100. However, computer storage media does not include communication media. Communication media typically embodies computer-readable instructions, data structures, program modules, or other data in the form of modulated data signals such as carrier waves or other transmission mechanisms, and includes any content delivery media. By way of example, and not limitation, communication media includes wired media such as wired networks or direct-line connections, and wireless media such as acoustic, RF, infrared, and other wireless media. Any combination of the above should also be included within the scope of computer-readable media.

[0019] System memory 130 includes computer storage media in the form of volatile and / or non-volatile memory, such as read-only memory (ROM) 131 and random access memory (RAM) 132. The basic input / output system 133 (BIOS) is typically stored in ROM 131, which contains basic routines that facilitate, for example, switching contents between elements within computing device 100 during startup. RAM 132 typically contains data and / or program modules that are readily accessible and / or currently in operation by processing unit 120. By way of example and not limitation, Figure 1 The operating system 134, other program modules 135, and program data 136 are shown.

[0020] The computing device 100 may also include other removable / non-removable, volatile / non-volatile computer storage media. This is merely an example. Figure 1 A hard disk drive 141 is shown that can be read from or written to from a non-removable, non-volatile magnetic medium. Other removable / non-removable, volatile / non-volatile computer storage media that can be used with the exemplary computing device include, but are not limited to, magnetic tape cassettes, flash memory cards, digital multifunction disks, digital videotapes, solid-state RAM, solid-state ROM, and other computer storage media as defined and described above. The hard disk drive 141 is typically connected to the system bus 121 via a non-volatile memory interface such as interface 140.

[0021] The above discussion and Figure 1 The drive and its associated computer storage medium shown provide storage for computer-readable instructions, data structures, program modules, and other data for computing device 100. For example, in Figure 1 In this diagram, hard disk drive 141 is shown storing operating system 144, other program modules 145, and program data 146. Note that these components may be the same as or different from operating system 134, other program modules 135, and program data 136. Operating system 144, other program modules 145, and program data 146 are given different numbers here to indicate that they are at least different copies.

[0022] Computing device 100 can operate in a networked environment using a logical connection to one or more remote computers. Computing device 100 is shown connected to a general network connection 151 (to network 190) via a network interface or adapter 150, which in turn connects to a system bus 121. In a networked environment, program modules or portions thereof, or peripheral devices depicted relative to computing device 100, may be stored in the memory of one or more other computing devices communicatively coupled to computing device 100 via a general network connection 161. It is understood that the network connection shown is exemplary, and other means of establishing communication links between computing devices may be used.

[0023] Although described as a single physical device, the exemplary computing device 100 can be a virtual computing device, in which case the functionality of the aforementioned physical components, such as CPU 120, system memory 130, network interface 160, and other similar components, can be provided by computer-executable instructions. These computer-executable instructions can execute on a single physical computing device or can be distributed across multiple physical computing devices, including dynamically across multiple physical computing devices, such that the specific physical computing device hosting the computer-executable instructions can dynamically change over time based on demand and availability. In the case where the exemplary computing device 100 is a virtualized device, the underlying physical computing device hosting such a virtualized computing device may itself include physical components similar to those described above and operate in a similar manner. Furthermore, virtual computing devices can be utilized in multiple layers, with one virtual computing device executing within the construction of another virtual computing device. Therefore, as used herein, the term "computing device" means either a physical computing device or a virtualized computing environment, including virtual computing devices, in which computer-executable instructions can be executed in a manner consistent with how they are executed by a physical computing device. Similarly, as used herein, the term referring to the physical components of a computing device means those physical components or their virtualizations that perform the same or equivalent functions.

[0024] Exemplary computing device 100 may include one or more hardware accelerator processing units, such as exemplary hardware accelerator processing unit 160. Exemplary hardware accelerator processing unit 160 may include multiple execution units, or processing "cores," to provide parallel execution of multiple threads and / or processes. Such execution units may implement specialized or custom instruction sets, or may be able to support the general instruction set of general-purpose central processing unit 120. Although shown as separate physical devices, central processing unit 120 and hardware accelerator processing unit 160 may be part of a single chip, such as... Figure 1 The dashed lines in the diagram represent this. For example, a specific part of a particular process or a single chip's circuitry can provide central processing unit capabilities, such as those represented by the exemplary central processing unit 120, while other parts of the chip can provide multi-core custom processing capabilities, such as those represented by the exemplary hardware accelerator processing unit 160.

[0025] Those skilled in the art will recognize that the design and fabrication of multiple integrated circuits, such as the central processing unit 120 and / or the hardware-accelerated processing unit 160, involves multiple layers of detailed concepts. In particular, at its most basic form, the circuitry of a processing unit includes etching or otherwise depositing and / or fabricating electrical pathways on a semiconductor substrate, such as a silicon substrate. Individual electrical pathways can interact to form processing building blocks, such as transistors. At higher levels, one or more transistors, combined with supporting circuitry (including resistors, capacitors, diodes, and other similar supporting circuitry), can implement basic electrical processing functions, such as OR gates and XOR gates. At even higher levels, multiple circuitry systems implementing such basic electrical processing functions are combined in known combinations to achieve further electrical processing functions. Therefore, the human design of multiple integrated circuits often occurs using known building blocks such as processing cores, communication pathways, on-chip memory storage functions, etc. While the following description is provided at a level commonly used by those skilled in the art, it will be further understood that what is ultimately described is a specific arrangement of the circuitry on silicon or other similar substrates. Therefore, the relevant components are referred to in a manner that includes the adjective "circuitry". Therefore, for example, the term "hardware semaphore circuit system" refers to a circuit system implemented using known building blocks that provides the hardware semaphore functionality described below. As another example, the term "execution unit circuit system" refers to a circuit system implemented using known building blocks that executes computer-executable instructions according to an instruction set supported by such execution unit circuit system. The terms "block circuit system" and "superblock circuit system" refer to circuit systems that include hardware semaphore circuit systems, execution unit circuit systems, communication paths, etc., to implement the communication and operation described below.

[0026] Turn Figure 2The system 200 shown illustrates an exemplary interaction between an execution unit circuit system (such as exemplary execution unit circuit system 220) and an array of hardware semaphore circuit systems (such as exemplary hardware semaphore circuit system array 210). This exemplary interaction is presented in the form of a block circuit system 250, which includes the hardware semaphore circuit systems of the execution unit circuit system 220 and the hardware semaphore array 210, combined with communication paths (such as exemplary communication connections 231, 232, and 241), and any other circuit systems necessary to support the implementation of the communication and operation described below. Although shown as a single execution unit circuit system 220, the exemplary block circuit system 250 may include multiple execution unit circuit systems coupled to the hardware semaphore array 210.

[0027] Each hardware semaphore circuit system, such as the exemplary hardware semaphore circuit system 211, may include circuit systems capable of implementing hardware semaphores representing dependencies on a consumer process. As described above, individual processes may require specific inputs to execute correctly and generate outputs, and / or may require specific memory available to store outputs prior to their generation. Where inputs are required, the required inputs are typically the outputs of preceding processes. As used herein, the term "consumer process" will be used to refer to the process that receives data (including data generated by preceding processes) as input, while the term "producer process" will be used to refer to the preceding process that generates the data. In other words, the producer process output is the data used as input to the consumer process. In a serial processing environment, the consumer process cannot execute until the producer process has finished executing, because only one thread may be executing at any given time. In contrast, in a parallel processing environment, there is the capability to execute both the producer and consumer processes simultaneously.

[0028] Therefore, hardware semaphores provide a hardware implementation of software semaphores, including signals that indicate when a specified precondition has been met, such as the data output by the producer process being a necessary input to the consumer process, or the release of memory used to store the output of the consumer process. In this way, the consumer process can avoid starting execution until the specified precondition has been met, thereby allowing the consumer process to access its required input data and / or its output data storage location. According to one aspect, hardware semaphores can be implemented using a circuit system that provides storage for one or more digital data bits, combined with a supporting circuit system that enables the reception of hardware semaphore commands, such as those described further below, and carries commands that include modifications to the digital data stored by the hardware semaphore. The digital data stored by the hardware semaphore can represent various states maintained by the hardware semaphore, which may correspond to the state of one or more outputs of the producer process, or other specified preconditions.

[0029] When the programmed prerequisites, as represented by binary data stored in the hardware semaphore, are met, the hardware semaphore circuitry can generate an interrupt or other similar notification, such as informing the consumer process that its prerequisites, as represented by the hardware semaphore circuitry, have been met. As a simple example, if the consumer process requires the producer process to generate output data, the hardware semaphore circuitry can include a single bit whose value can represent the state of output data generation by the producer process. For example, the binary value "zero" can indicate that the producer process has not yet generated output data. When the producer process generates output data, a semaphore command can be generated, including by the producer process itself, to increment the binary value stored in the hardware semaphore circuitry. The binary value of "one" can then indicate that output data has indeed been generated by the producer process. Furthermore, the hardware semaphore circuitry can include circuitry capable of detecting that the stored value ("one" in this simple example) satisfies the prerequisites represented by the hardware semaphore circuitry, and can therefore generate an interrupt or other similar notification indicating that the dependency represented by the hardware semaphore circuitry has been confirmed.

[0030] According to one aspect, an execution unit circuit system, such as the exemplary execution unit circuit system 220, may be the core of a circuit system or other similar collection capable of executing a defined instruction set. Such an execution unit circuit system 220 may be associated with one or more hardware semaphore circuit systems, such as the exemplary hardware semaphore circuit system array 210, wherein a combination of the execution unit circuit system 220 and the hardware semaphore circuit system array 210 is encapsulated within a block circuit system 250. According to one aspect, physical interconnections, such as the exemplary wiring 241, may communicatively couple the execution unit circuit system 220 to individual hardware semaphore circuit systems 211, 212, 213, 214, 215, 216, 217, and 218 of the hardware semaphore array 210. Wiring 241 enables any one or more of the individual hardware semaphore circuit systems (such as the exemplary hardware semaphore circuit system 211) to communicate with the memory of any one or more of the other individual hardware semaphore circuit systems and to read data from and / or write data to memory.

[0031] Alternatively or additionally, hardware semaphore circuitry systems can be communicatively coupled to other execution unit circuitry systems via a dedicated network on-chip (NOC). As used herein, the adjective "dedicated" means "excluding other uses," making a dedicated NOC a NOC used for transmitting semaphore commands and other hardware semaphore-related messages, excluding other types of communication. The NOC can be a packet-based network that can be implemented within a single integrated circuit. In such an implementation, individual circuitry systems can represent aspects of a traditional packet-based network, including endpoint transmit / receive functions and intermediate routing functions. Figure 2 The communication coupling between an individual semaphore circuit system 210 of the hardware semaphore circuit system array 210 and the exemplary dedicated NOC 230 of the system 200 is illustrated by wiring 231 or other similar hardware communication coupling. Similarly, to support communication with other hardware semaphore circuit systems, such as notifying other hardware semaphore circuit systems that a producer process executed on the execution unit circuit system 220 has completed execution and generated output, the execution unit circuit system 220 can also be communicatively coupled to the dedicated NOC 230, as illustrated by wiring 232 or other similar hardware communication coupling.

[0032] According to one aspect, semaphore commands can be sent to a semaphore from any source, including producer processes, and other semaphores as detailed below. In contrast, interrupts or other similar notifications generated by a semaphore can only be sent to the execution unit circuitry specifically associated with that semaphore, such as within a single block or superblock. For example, in... Figure 2Within the exemplary system 200 shown, the exemplary hardware semaphore circuit system 211 can receive semaphore messages from any source, but can only generate interrupts for processes executing on the execution unit circuit system 220.

[0033] Messages exchanged on the dedicated NOC 230 may include a destination address, and correspondingly, each individual hardware semaphore circuit system 211 may have a unique address assigned to it. Execution unit circuit systems (such as the exemplary execution unit circuit system 220) may also have a unique address assigned to them. Thus, a message to a hardware semaphore circuit system may include the destination address of such a message, as well as one or more commands to the destination hardware semaphore circuit system. Such semaphore commands include initialization commands for resetting the hardware semaphore circuit system, setup commands that can establish initial values ​​or other similar settings, and data access and modification commands (which may include commands for incrementing and / or decrementing values ​​currently stored by the hardware semaphore circuit system), and commands for reading current values ​​stored by the hardware semaphore circuit system.

[0034] According to one aspect, an individual hardware semaphore circuit system (such as a single hardware semaphore circuit system 211) can implement a binary semaphore or a counting semaphore. A binary semaphore can represent the presence or absence of a single premise, such as a single output from a single producer process. Therefore, a binary semaphore can have a value of zero (“off”) or one (“on”). In contrast, a counting semaphore can represent a number of premises, for example, including the number of output data units generated by a single producer process, the number of output data aggregated by individual producer processes, or combinations thereof. Therefore, a counting semaphore can maintain different states beyond just zero (“off”) or one (“on”). For example, such states can include an initialization state, as well as other states that can represent integers or other similar counting representations.

[0035] A single hardware semaphore array (such as the exemplary hardware semaphore array 210) may include multiple binary semaphores and multiple counting semaphores. For example, exemplary hardware semaphore circuit systems 211, 212, 213, and 214 may all be binary semaphores, while exemplary hardware semaphore circuit systems 215, 216, 217, and 218 may all be counting semaphores. Although the exemplary hardware semaphore array 210 is shown as including eight hardware semaphores, a hardware semaphore array may include two or more hardware semaphore circuit systems, and it is not necessary to include an even number of hardware semaphore circuit systems. Furthermore, the number of binary hardware semaphore circuit systems within the array does not necessarily equal the number of counting hardware semaphore circuit systems, and various numbers of binary and counting hardware semaphore circuit systems may be included in the hardware semaphore array.

[0036] Turn Figure 3a The exemplary system 301 shown illustrates an exemplary combination of multiple block circuit systems, such as the exemplary block circuit system 250, initially in Figure 2 As shown in the diagram and described in detail above. For example, multiple block circuit systems can be combined within a single integrated circuit (such as a computer chip) because the integrated circuit can include multiple execution unit circuit systems to provide parallel processing, and these execution unit circuit systems can be associated with a hardware semaphore array, as detailed above. In exemplary system 301, as... Figure 3a As shown, exemplary block circuit system 250 is integrated with another block circuit system 350, such as on a single substrate, a single integrated circuit, or other similar integration. Exemplary block circuit system 350, like exemplary block circuit system 250 detailed above, may include one or more execution unit circuit systems (such as exemplary execution unit circuit system 320) and associated hardware semaphore circuit systems (such as hardware semaphore circuit systems 311, 312, 313, 314, 315, 316, 317, and 318), which may include hardware semaphore array 310. Hardware semaphore array 310 and the hardware semaphore circuit systems of execution unit circuit system 320 may be communicatively coupled via wiring 341 or other similar communication paths, and may also include communication connections to dedicated NOC 230, such as exemplary communication connections 331 and 332.

[0037] According to one aspect, communication between block circuit system 250 and block circuit system 350 can be via dedicated NOC 230. For example, execution unit circuit system 320 can execute a producer process whose output is a prerequisite for executing a consumer process, such as, for example, on execution unit circuit system 220. In such an instance, execution unit circuit system 320 can communicate with one or more of the hardware semaphore circuit systems 210 of block circuit system 250, such as by sending hardware semaphore messages to, for example, hardware semaphore circuit system 211, representing events affecting the prerequisites for executing a consumer process on execution unit circuit system 220. For example, execution unit circuit system 320 can generate hardware semaphore messages addressed to hardware semaphore circuit system 211, which include hardware semaphore commands for incrementing hardware semaphore circuit system 211. For example, if the hardware semaphore circuit system 211 is implementing a binary semaphore, such a command can cause the hardware semaphore circuit system 211 to change from a "zero" state to a "one" state, instructing the producer process that its output is a prerequisite for the execution of the consumer process on the execution unit circuit system 220.

[0038] When addressing hardware semaphore messages to hardware semaphore circuitry 211, the processing executed on execution unit circuitry 320 can utilize an addressing scheme as implemented by dedicated NOC 230. For example, the addressing scheme can be based on standard Internet Protocol (IP) addressing. As another example, the addressing scheme can be based on other standardized network addressing schemes. In the addressing scheme used to implement dedicated NOC 230, each address in the block circuitry can include a single subnet. Therefore, in this exemplary addressing scheme, communication from execution unit circuitry 320 to hardware semaphore circuitry 211 can include inter-subnet communication, which can be routed by dedicated NOC 230, as shown by communication 361.

[0039] Turn Figure 3b The exemplary system 302 shown illustrates an alternative exemplary combination of multiple block circuit systems. More specifically, the exemplary system 302 illustrates an exemplary superblock circuit system, such as superblock circuit system 351. According to one aspect, a superblock may include multiple instances of block circuit systems interconnected by communication paths, such as exemplary communication path 241, which may communicatively couple execution unit circuit systems 220 and 320, and individual hardware semaphore circuit systems 211, 212, 213, 214, 215, 216, 217, 218, 311, 312, 313, 314, 315, 316, 317, and 318. A superblock (such as exemplary superblock circuit system 351) may include a higher level of hierarchy within a layered integrated circuit, chip, substrate, etc. For example, individual block circuit systems may be combined into a superblock circuit system, as shown. Multiple superblock circuit systems may then be combined on an integrated circuit chip, or they may be combined into a higher level of hierarchy and then combined on an integrated circuit chip.

[0040] One difference between the merging shown in exemplary system 301 and exemplary system 302 may be the utilization of hardware semaphore circuitry by processes executing on execution unit circuitry. For example, in exemplary system 301, individual hardware semaphore circuitry systems 211, 212, 213, 214, 215, 216, 217, and 218 may generate interrupts for processes executing on execution unit circuitry system 220, but not for processes executing on execution unit circuitry system 320. Similarly, individual hardware semaphore circuitry systems 311, 312, 313, 314, 315, 316, 317, and 318 may generate interrupts for processes executing on execution unit circuitry system 320, but not for processes executing on execution unit circuitry system 220. In contrast, in exemplary system 302, individual hardware semaphore circuit systems 211, 212, 213, 214, 215, 216, 217, and 218 can generate interrupts for processes executing on execution unit circuit system 220 or execution unit circuit system 320. Similarly, interrupts can also be generated for individual hardware semaphore circuit systems 311, 312, 313, 314, 315, 316, 317, and 318. Furthermore, as will be further detailed below, in a chain of hardware semaphore circuit systems, one hardware semaphore circuit system can directly modify a value held by another hardware semaphore circuit system. In exemplary system 301, such modifications can be performed in individual hardware semaphore circuit systems 211, 212, 213, 214, 215, 216, 217, and 218, excluding individual hardware semaphore circuit systems 311, 312, 313, 314, 315, 316, 317, and 318, and vice versa. In contrast, in exemplary system 302, such modifications can be performed in any of the individual hardware semaphore circuit systems 211, 212, 213, 214, 215, 216, 217, 218, 311, 312, 313, 314, 315, 316, 317, and 318. Therefore, for example, in exemplary system 301, a semaphore chain can be implemented across individual hardware semaphore circuit systems 211, 212, 213, 214, 215, 216, 217, and 218, excluding individual hardware semaphore circuit systems 311, 312, 313, 314, 315, 316, 317, and 318, while in exemplary system 302, a semaphore chain can be implemented across any one of individual hardware semaphore circuit systems 211, 212, 213, 214, 215, 216, 217, 218, 311, 312, 313, 314, 315, 316, 317, and 318.Therefore, a hardware semaphore circuit system such as exemplary hardware semaphore circuit system 218 can directly modify the value of another hardware semaphore circuit system (such as exemplary hardware semaphore circuit system 314) without communicating across dedicated NOC 230, but instead utilizes communication channel 241, as shown in communication 362.

[0041] Hardware semaphore chains allow hardware semaphores to support multiple conditions. First, go to... Figure 4a The exemplary system 401 shown illustrates exemplary operation of an individual hardware semaphore circuit system, such as in Figure 2 Within the context of system 200 shown and described in detail above. In exemplary system 401, hardware semaphore circuitry system 215 implements binary semaphores. Therefore, hardware semaphore circuitry system 215 can implement a state machine, such as exemplary state machine 450, having an off (or zero) state 451 and an on (or one) state 452. In contrast, exemplary hardware semaphore circuitry system 211 can implement a counting semaphore. Figure 4a Within the exemplary system 401 shown, the hardware semaphore circuitry system 211 may have been configured to count quantities up to three. For example, a dependency implemented by the hardware semaphore circuitry system 211 may be used for three outputs of a single producer process. As another example, a consumer process may have a premise implemented by the hardware semaphore circuitry system 211 that may require three separate data as inputs, and such input data may be generated by one or more producer processes. Thus, the hardware semaphore circuitry system 211 may implement a state machine (such as the exemplary state machine 440) having individual states that can represent quantities according to the premises defined by the hardware semaphore circuitry system 211. Such individual quantity states may include state 441 representing a quantity of zero, state 442 representing a quantity of one, state 443 representing a quantity of two, and state 444 representing a quantity of three.

[0042] The arrows shown in state machines 450 and 440 can indicate transitions between states. In exemplary state machine 450, for example, a notification indicating that a state has changed (such as, for example, a notification that an output has been generated) can cause state machine 450 to transition from state 451 to state 452. As another example, a reset of hardware semaphore circuitry 215 can cause state machine 450 to transition back to an initial state, such as state 451. Such notifications, resets, or other similar commands or information for hardware semaphore circuitry 215 can be delivered in the form of messages (such as those detailed above). Exemplary system 401 is shown as an example message 425 received via dedicated NOC 230. In a similar manner, for example, if exemplary state machine 440 receives a notification indicating that a state has changed (such as, for example, a notification that an output has been generated), such a message can cause state machine 440 to transition from the previous state to a subsequent state indicating an increment of 1. For example, such a transition can be from state 441 to state 442, from state 442 to state 443, or from state 443 to state 444. Similarly, a notification indicating that the state has changed in the opposite way (such as, for example, a notification that a previously generated output has been reset or otherwise deleted) can cause state machine 340 to transition from the previous state to the subsequent state indicating a decrement of 1. For example, such a transition can be from state 443 to state 442, or from state 442 to state 441. Additionally, a reset of the hardware semaphore circuitry system 211 can cause state machine 440 to transition from any of states 442, 443, or 444 to state 441, as... Figure 4a As shown by the arrow in the diagram. Again, notifications, resets, or other similar commands or information for the hardware semaphore circuitry system 211 can be delivered in the form of messages, such as the exemplary message 421 received from the dedicated NOC 230.

[0043] According to one aspect, the various mechanisms described herein can be implemented by a compiler during the generation of computer-executable instructions, such as custom or finite instruction sets executable by the execution unit circuitry of an integrated circuit chip, such as instruction sets designed according to the description provided herein. For example, human-readable programming instructions can specify prerequisites or dependencies for processes, threads, or other similar execution units. During compilation, the compiler can detect such specifications, and such a compiler can set one or more hardware semaphores, as detailed herein. This setting can also include the insertion of computer-executable instructions that can notify the associated hardware semaphore circuitry of changes in the state of the output of a preceding thread or process that provides input to a subsequent thread or process. Figure 4aIn the example, initialization action 411 illustrates setting the hardware semaphore circuit system 211 as a counting semaphore to maintain the exemplary state machine 440. Similarly, initialization action 415 illustrates setting the hardware semaphore circuit system 215 as a binary semaphore to maintain the exemplary state machine 450.

[0044] As detailed above, when a hardware semaphore circuit system reaches a state that indicates a predetermined condition, it can generate an interrupt according to the initialization settings of the hardware semaphore circuit system to trigger or modify the execution of a process, thread, or other similar computer-executable instruction on a processor core or other similar execution unit circuit system. Thus, for example, exemplary hardware semaphore circuit system 211 can generate an interrupt 431 for a process being executed by execution unit circuit system 220. More specifically, exemplary hardware semaphore circuit system 211 can cause interrupt 431 to be generated when transitioning from state 443 to state 444. As another example, exemplary hardware semaphore circuit system 215 can be configured to trigger an interrupt when it transitions to the enabled state 452.

[0045] According to one aspect, multiple conditional dependencies (such as multiple conditional dependencies 410) can be represented by two hardware semaphores, such as exemplary hardware semaphore circuit systems 211 and 215, which can generate corresponding interrupts, namely interrupts 431 and 432. For example, multiple conditional dependencies 410 can be in the form of "A and B", requiring conditions "A" and "B" to be satisfied, such as by execution unit circuit system 220, before thread execution. Conditions "A" and "B" can be conditions that can be represented by two binary hardware semaphore circuit systems, two counting hardware semaphore circuit systems, or one binary hardware semaphore circuit system and one counting hardware semaphore circuit system.

[0046] In cases of conditional dependencies referencing two or more states, receiving an interrupt (such as exemplary interrupt 331) can cause execution to continue waiting for a second interrupt (such as exemplary interrupt 335) before proceeding. However, implementing multiple conditional dependencies by a process executing on execution unit circuitry 220, even as simple as exemplary multiple conditional dependencies 410, can be expensive because it may require executing computer-executable instructions across many clock cycles, increasing the overhead of the process's own execution. Therefore, implementing multiple conditional dependencies within the process itself executing on execution unit circuitry 220 can be extremely slow and inefficient.

[0047] According to one aspect, in order to accommodate multiple condition dependencies in a faster, more efficient and less power-consuming manner, chained semaphores can be created, which can link or organize multiple hardware semaphore circuit systems in a sequential manner.

[0048] Turn Figure 4b Exemplary system 402 shows a source from Figure 4a The exemplary system 401 uses the same plurality of condition dependencies 410 as an exemplary implementation, except that it is now implemented using a semaphore chain implemented with multiple hardware semaphore circuit systems. More specifically, the initial hardware semaphore circuit system of the semaphore chain (such as the exemplary hardware semaphore circuit system 211) can be initialized as part of the semaphore chain, and more specifically, can be initialized as the first semaphore in the semaphore chain. Furthermore, the exemplary hardware semaphore circuit system 211 can be initialized as a counting semaphore, as it is in the exemplary system 401 described above. This initialization is illustrated by initialization action 461.

[0049] In contrast, the exemplary hardware semaphore circuit system 215 can be initialized as a subsequent semaphore in a semaphore chain. More specifically, the hardware semaphore circuit system 215 can be initialized such that its state machine considers not only the state of any process sending the semaphore command 425, but also whether a preceding semaphore in the semaphore chain (e.g., hardware semaphore circuit system 211) has reached a condition-satisfied state. For example, as in exemplary system 401, the exemplary hardware semaphore circuit system 215 can implement a binary semaphore. However, as shown in initialization action 465, by being set as a chained semaphore, and more specifically, as a subsequent semaphore in the chain, even if the exemplary hardware semaphore circuit system 215 is implementing a binary semaphore, its maintained state machine (such as, for example, exemplary state machine 480) can include more than [a certain number of processes]. Figure 4a The exemplary state machine 450 shown has two states.

[0050] As can be seen, for subsequent semaphores in the semaphore chain, the state machine can include twice the number of states because non-chained semaphores of the same type will be maintained, as each state of a non-chained semaphore is replicated in the chained semaphores (except for the first semaphore in the chain) to account for the possibility of satisfying or not satisfying a previous condition. Therefore, for example, an exemplary binary semaphore maintained by hardware semaphore circuitry 215 can be initialized to maintain four states, as shown in exemplary state machine 480. State 481 can represent a "closed" state of a premise implemented by another execution unit, whose message to hardware semaphore circuitry 215 is shown in message 425, and furthermore, state 481 can also represent a previous condition, such as condition "A" maintained by a previous semaphore in the semaphore chain (such as exemplary hardware semaphore circuitry 211), which has not yet been satisfied. In contrast, state 482 can represent a "closed" state of a premise being satisfied. Therefore, for example, if no semaphore command such as the exemplary semaphore command 425 is received, the hardware semaphore circuitry system 215 can maintain a state machine transitioning from state 481 to state 482, while receiving communication from the hardware semaphore circuitry system 211 to implement the previous semaphore in the semaphore chain, indicating that its condition has been met. Similarly, the exemplary state machine 480 may also include states 483 and 484, where state 483 represents the "on" state of a previous semaphore in the semaphore chain whose preceding condition has not yet been met, and state 484 represents the "on" state in the semaphore chain whose premise has been met. Therefore, for example, if the preceding condition in the semaphore chain is met, the exemplary state machine 480 can transition from state 482 to state 484 upon receiving the semaphore command 425.

[0051] According to one aspect, the condition fulfillment notification 471 from an exemplary hardware semaphore circuit system 211 implementing a semaphore in a semaphore chain to an exemplary hardware semaphore circuit system 215 implementing a subsequent semaphore in the semaphore chain can be in the form of a semaphore command. According to an alternative aspect, the condition fulfillment notification 471 can be a direct action by the hardware semaphore circuit system 211 on the hardware semaphore circuit system 215. For example, data stored in a memory area reserved for the hardware semaphore circuit system 215 can be directly modified by the hardware semaphore circuit system 211, such modification indicating a state change instructing the hardware semaphore circuit system 211 to satisfy its condition.

[0052] The hardware semaphore circuit system 215 can trigger interrupt 432 when state 484 is reached. However, from Figure 4bAs can be seen, state 484 can indicate that condition "B" (as indicated by the "Enable" portion of state 484 and conveyed by message 425) and condition "A" (as indicated by the "Satisfied" portion of state 484 and conveyed by notification 471) have been satisfied. In other words, a single interrupt 432 can indicate that multiple condition dependencies 410 have been satisfied. In this way, chained semaphores can support multiple conditions without burdening the execution unit circuitry 220, as in system 401, as previously described.

[0053] Turn Figure 5 The exemplary system 500 shown illustrates a multi-semaphore chain supporting exemplary multiple conditional dependencies 510, which may include four separate premises “A”, “B”, “C”, and “D”. In exemplary system 500 (as in exemplary system 402), exemplary hardware semaphore circuitry system 211 can be initialized to represent a first semaphore or initial semaphore in the semaphore chain and can maintain a state machine according to premise “A”. Similarly, exemplary hardware semaphore circuitry system 215 can be initialized to represent a subsequent semaphore in the semaphore chain and can maintain a state machine according to premise “B”, which also considers whether a preceding semaphore in the semaphore chain has indicated that its condition has been met. Thus, exemplary hardware semaphore circuitry system 215 can be configured as described above and... Figure 4b The same method as shown is used for initialization. Notification 471, which assumes the condition is met, can also be initialized as described above.

[0054] Then, as shown above, the output of the hardware semaphore circuitry 215 can represent multiple conditional dependencies “A” and “B”. However, since the exemplary multiple conditional dependencies 510 can be in the form of “A” and “B” and “C” and “D”, additional hardware semaphore circuitry can be initialized to implement additional semaphores in the semaphore chain. Just as the condition fulfillment notification 471 is not triggered until condition “A” is met, and just as the hardware semaphore circuitry 215 does not generate an interrupt until multiple prerequisites “A” and “B” are met, similarly, when implementing intermediate semaphores in the hardware semaphore chain, the hardware semaphore circuitry 215 can wait to generate the condition fulfillment notification 571 until its prerequisite “B” and one or more prerequisites of the preceding semaphores in the chain are met. In other words, the generation of the condition fulfillment notification 571 indicates that multiple conditional dependencies “A” and “B” are met.

[0055] Such a condition fulfillment notification 571 can be directed to a hardware semaphore circuitry system, such as the exemplary hardware semaphore circuitry system 312, which can be initialized to implement another subsequent semaphore in the semaphore chain, i.e., a semaphore that can be associated with the state of dependency "C". In a manner similar to that detailed above, upon receiving one or more semaphore commands (such as the exemplary semaphore command 522), it indicates that the state of prerequisite "C" satisfies the prerequisite, and further, upon receiving condition fulfillment notification 571, hardware semaphore circuitry system 312 can generate its own condition fulfillment notification 572. In a manner similar to that detailed above, the generation of condition fulfillment notification 572 can indicate that multiple condition dependencies "A" and "B" and "C" are satisfied.

[0056] Therefore, another hardware semaphore circuit system (such as the exemplary hardware semaphore circuit system 316) can be initialized to implement the last semaphore in the semaphore chain. Thus, when the exemplary hardware semaphore circuit system 316 receives one or more semaphore commands (such as the exemplary semaphore command 526), ​​it indicates that the state of prerequisite "D" is satisfied, and when the exemplary hardware semaphore circuit system 316 further receives a condition satisfaction notification 572 from the hardware semaphore circuit system 312, the hardware semaphore circuit system 316 can generate an interrupt 532, such as for a process executing on the exemplary execution unit circuit system 220. As described above, the generation of interrupt 532 can indicate the satisfaction of multiple conditional dependencies "A" and "B" and "C" and "D," i.e., the exemplary multiple conditional dependencies 510. In this way, Figure 5 The chain semaphore can support multiple condition dependencies 510 without burdening the execution unit circuitry 220.

[0057] Although described above only in the context of interrupts, according to one aspect, a hardware semaphore circuitry system (such as the exemplary hardware semaphore circuitry system 316) can output semaphore commands or other similar messages. For example, the exemplary hardware semaphore circuitry system 316 can generate an interrupt or other similar notification to a processing unit or other similar circuitry system that can be pre-programmed to deliver semaphore commands. Alternatively or additionally, the hardware semaphore circuitry system itself may include such a processing unit or other similar circuitry system and can select from pre-programmed semaphore commands and / or pre-programmed semaphore addressing to generate a command message with appropriate addressing.

[0058] As detailed above, the compiler can configure individual hardware semaphore circuitry systems to form a chain of semaphores. For example, the compiler can configure each of individual hardware semaphore circuitry systems 211, 215, 312, and 316 to perform the actions detailed above. Such configuration may include providing addressing or other similar identification information to enable condition fulfillment notifications to be delivered to the appropriate hardware semaphore circuitry system, or modifying data within an appropriate range of memory associated with the hardware semaphore circuitry system implementing the next semaphore in the semaphore chain.

[0059] Turn Figure 6 Referring to the exemplary flowchart 600 shown therein, an exemplary operation of a compiler creating a chain of semaphores using an individual hardware semaphore circuitry system is illustrated. Initially, in step 610, statements such as those in a programming language, or other similar instruction constructs consumed by the compiler, may be encountered that specify multiple conditional dependencies for a process, thread, function, or other similar set of computer-executable instructions. For ease of reference, such a process will be referred to herein as a "consumer process," where the multiple conditional dependencies enumerate logical interrelationships between multiple output states of multiple other processes, threads, functions, or other similar sets of computer-executable instructions, whose outputs may be used as input to the consumer process or may otherwise provide premises for the consumer process. For ease of reference, these other processes will be referred to herein as "producer processes."

[0060] In step 620, a conditional dependency can be selected from multiple conditional dependencies. In step 630, a hardware semaphore circuit system can be sent based on the selected conditional dependency. As part of the setup of this hardware semaphore circuit system, the address or other similar location identification information of the downlink hardware semaphore circuit system can be provided to the uplink hardware semaphore circuit system. Furthermore, the address or other similar location identification information of this uplink hardware semaphore circuit system can be provided to the producer process so that changes in its output state can be messaged to the hardware semaphore circuit system. In step 640, the provision of the address of this hardware semaphore circuit system is shown. In step 650, it can be determined whether there are any additional dependencies from multiple conditional dependencies that have not yet been accommodated by the chain hardware semaphore. In step 650, if it is determined that such additional dependencies are still not accommodated, the process can return to step 620; otherwise, the relevant processing can end in step 660.

[0061] The exemplary flowchart 600 is shown using a linear approach. However, recursive or backward operation methods are equally applicable. For example, and refer to Figure 6In the exemplary system 600, the compiler can generate chained semaphores by first setting up a final hardware semaphore circuitry (such as exemplary hardware semaphore circuitry 316). After setting up the final hardware semaphore circuitry, the compiler can work backwards, such as by setting up exemplary hardware semaphore circuitry 312, which includes providing the address of the already set final hardware semaphore circuitry 316. In this way, the compiler can recursively set up each hardware semaphore circuitry backwards as described below. In this way, multiple hardware semaphore circuitries can be linked to form chained semaphores to accommodate multiple conditional dependencies.

[0062] The above description includes, as a first example, a method using multiple hardware semaphore circuits as chain semaphores, the method comprising: receiving computer-executable instructions specifying multiple conditional dependencies for a first consumer process, the multiple conditional dependencies enumerating the states of outputs of multiple producer processes, the states of outputs of the multiple producer processes to be satisfied so that the first consumer process can execute correctly; configuring a first hardware semaphore circuit system as a first semaphore in the chain semaphores to: maintain a first state machine such that generation by outputs of the first producer process changes the first state machine, the first producer process being one of the multiple producer processes; and generating a first condition satisfied notification to a subsequent semaphore in the chain semaphores when the first state machine is in a state corresponding to a first condition specified by the multiple conditional dependencies; and configuring a second hardware semaphore circuit system as a subsequent semaphore in the chain semaphores to: maintain a second state machine such that generation by outputs of a second producer process changes the second state machine, the second producer process being another of the multiple producer processes; and generating a second condition satisfied notification when the second state machine is in a state corresponding to: (1) a second condition specified by the multiple conditional dependencies and (2) all preceding semaphores in the chain semaphores have generated condition satisfied notifications.

[0063] The second example is the method of the first example, wherein setting the second hardware semaphore circuitry as the subsequent semaphore in the chain includes setting the second hardware semaphore circuitry as the last semaphore in the chain; and wherein the second condition fulfillment notification is an interruption to the execution of the first consumer process.

[0064] The third example is the method of the first example, setting the second hardware semaphore circuitry as the subsequent semaphore in the chain includes setting the second hardware semaphore circuitry as the last semaphore in the chain; and wherein a second condition is satisfied to trigger a semaphore command on the third hardware semaphore circuitry.

[0065] The fourth example is the method of the first example, wherein the first producer process executes on a first execution unit circuit system communicatively coupled to a first hardware semaphore circuit system, the first execution unit circuit system and the first hardware semaphore circuit system being located on an integrated circuit chip.

[0066] The fifth example is the method of the fourth example, in which the first execution unit circuit system generates a command to the first hardware semaphore circuit system, which causes the state of the first hardware semaphore circuit system to change.

[0067] The sixth example is the method of the fourth example, in which the first hardware semaphore circuit system and the first execution unit circuit system are communicatively coupled by the fact that they are both part of a first circuit system on an integrated circuit chip.

[0068] The seventh example is a method of the second example, wherein the first execution unit circuit system is communicatively coupled to the first hardware semaphore circuit system via a dedicated on-chip network (NOC) circuit system.

[0069] The eighth example is the method of the seventh example, wherein the first execution unit circuit system is part of a dedicated NOC subnet that is different from the first hardware semaphore circuit system.

[0070] The ninth example is a method of the first example, wherein the generation of a first condition fulfillment notification by a first hardware semaphore circuit system includes the first hardware semaphore circuit system modifying one or more values ​​utilized by a second hardware semaphore circuit system to maintain a second state machine.

[0071] The tenth example is the method of the first example, where the second state machine includes four states: the first state represents that the second condition is not met and all preceding semaphores in the chain have not generated a condition met notification; the second state represents that the second condition is met and all preceding semaphores in the chain have not generated a condition met notification; the third state represents that the second condition is not met and all preceding semaphores in the chain have generated a condition met notification; and the fourth state represents that the second condition is met and all preceding semaphores in the chain have generated a condition met notification.

[0072] The eleventh example is an integrated circuit chip, comprising: a first execution unit circuit system; a second execution unit circuit system; a first hardware semaphore circuit system array associated with the first execution unit circuit system; a second hardware semaphore circuit system array associated with the second execution unit circuit system; the first hardware semaphore circuit system being configured as a first semaphore in a chain of semaphores, the first hardware semaphore circuit system: maintaining a first state machine such that generation output by a first producer process changes the first state machine; and generating a first condition fulfillment notification to subsequent semaphores in the chain of semaphores when the first state machine is in a state corresponding to a first condition with multiple condition dependencies; and the second hardware semaphore circuit system being configured as a subsequent semaphore in the chain of semaphores, the second hardware semaphore circuit system: maintaining a second state machine such that generation output by a second producer process changes the second state machine; and generating a second condition fulfillment notification when the second state machine is in a state corresponding to: (1) a second condition specified by multiple condition dependencies and (2) all preceding semaphores in the chain of semaphores have generated condition fulfillment notifications.

[0073] The twelfth example is an integrated circuit chip of the eleventh example, further comprising: a first circuit system including a first execution unit circuit system and a first hardware semaphore circuit system array; a second circuit system including a second execution unit circuit system and a second hardware semaphore circuit system array; and a dedicated network on-chip (NOC) circuit system communicatively coupling the first circuit system to the second circuit system; wherein the first hardware semaphore circuit system and the second hardware semaphore circuit system are part of the first hardware semaphore circuit system array; and wherein multiple conditional dependencies enumerate the states of the outputs of multiple producer processes, the states of the outputs of the multiple producer processes being satisfied so that a first consumer process executes correctly on the first execution unit.

[0074] The thirteenth example is the integrated circuit chip of the twelfth example, wherein a first manufacturing process is executed on a second execution unit circuit system and generates a command that changes the state of a first hardware semaphore, the command being transmitted from the second execution unit circuit system to the first hardware semaphore circuit system via a dedicated NOC.

[0075] The fourteenth example is an integrated circuit chip of the twelfth example, wherein the elements of the first circuit system are part of a first subnet of a dedicated NOC, and the elements of the second circuit system are part of a second subnet of a dedicated NOC.

[0076] The fifteenth example is an integrated circuit chip of the eleventh example, further comprising: a first superblock circuit system, the first superblock circuit system including a first execution unit circuit system, a first hardware semaphore circuit system array, a second execution unit circuit system, and a second hardware semaphore circuit system array; and a dedicated on-chip network (NOC) circuit system, the dedicated on-chip network (NOC) circuit system communicatively coupling the first superblock circuit system to other superblock circuit systems on the integrated circuit chip; wherein the first hardware semaphore circuit system is part of the first hardware semaphore circuit system array, and the second hardware semaphore circuit system is part of the second hardware semaphore circuit system array.

[0077] The sixteenth example is an integrated circuit chip of the eleventh example, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and wherein the second condition fulfillment notification is an interruption of the execution of the first consumer process, which has multiple condition dependencies as prerequisites for the execution.

[0078] The seventeenth example is the integrated circuit chip of the eleventh example, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and wherein a second condition is satisfied to trigger a semaphore command to the third hardware semaphore circuit system.

[0079] The eighteenth example is an integrated circuit chip comprising: a plurality of block circuit systems, each block circuit system including: an execution unit circuit system; and an array of two or more hardware semaphore circuit systems; and a dedicated on-chip network (NOC) circuit system communicatively coupled to the plurality of block circuit systems; wherein at least one of the plurality of block circuit systems includes: a first hardware semaphore circuit system configured as a first semaphore in a chain of semaphores, the first hardware semaphore circuit system: maintaining a first state machine such that generation output by a first producer process changes the first state machine; and generating a first condition fulfillment notification to a subsequent semaphore in the chain of semaphores when the first state machine is in a state corresponding to a first condition with multiple condition dependencies; and a second hardware semaphore circuit system configured as a subsequent semaphore in the chain of semaphores, the second hardware semaphore circuit system: maintaining a second state machine such that generation output by a second producer process changes the second state machine; and generating a second condition fulfillment notification when the second state machine is in a state corresponding to: (1) a second condition specified by multiple condition dependencies and (2) all preceding semaphores in the chain of semaphores have generated condition fulfillment notifications.

[0080] The 19th example is the integrated circuit chip of the 18th example, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and wherein the second condition fulfillment notification is an interruption of the execution of the first consumer process, which has multiple condition dependencies as prerequisites for the execution.

[0081] The twentieth example is the integrated circuit chip of the eighteenth example, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and wherein a second condition is met to trigger a semaphore command to the third hardware semaphore circuit system.

[0082] As can be seen from the above description, a mechanism has been proposed to support multiple conditions using semaphore chains implemented by a hardware semaphore circuit system. Given the many possible variations of the subject matter described herein, we claim protection as our invention for all such embodiments that may fall within the scope of the appended claims and their equivalents.

Claims

1. A method for using multiple hardware semaphore circuit systems as chain semaphores, the method comprising: Receive computer-executable instructions specifying multiple conditional dependencies for a first consumer process, the multiple conditional dependencies enumerating the states of the outputs of multiple producer processes, the states of the outputs of the multiple producer processes to be satisfied so that the first consumer process can execute correctly. The first hardware semaphore circuit system is configured as the first semaphore in the chain of semaphores: Maintain a first state machine such that the generation of the output of a first producer process changes the first state machine, where the first producer process is one of the plurality of producer processes; and When the first state machine is in a state corresponding to a first condition specified by the plurality of condition dependencies, a first condition fulfillment notification is generated for the subsequent semaphores in the chain semaphores; as well as Configure the second hardware semaphore circuit system as the subsequent semaphore in the chain of semaphores: Maintain a second state machine such that the generation of the output of a second producer process changes the second state machine, where the second producer process is another producer process among the plurality of producer processes; and A second condition satisfaction notification is generated when the second state machine is in a state corresponding to the following: (1) a second condition specified by the plurality of condition dependencies and (2) a condition satisfaction notification has been generated by all preceding semaphores in the chain semaphores.

2. The method of claim 1, wherein setting the second hardware semaphore circuitry as the subsequent semaphore in the chain comprises setting the second hardware semaphore circuitry as the last semaphore in the chain; and The notification that the second condition is met is an interruption of the execution of the first consumer process.

3. The method of claim 1, wherein setting the second hardware semaphore circuitry as the subsequent semaphore in the chain comprises setting the second hardware semaphore circuitry as the last semaphore in the chain; and The second condition being met triggers a semaphore command to the third hardware semaphore circuit system.

4. The method according to claim 1, wherein the first production process is executed on a first execution unit circuit system communicatively coupled to the first hardware semaphore circuit system, the first execution unit circuit system and the first hardware semaphore circuit system being located on an integrated circuit chip.

5. The method according to claim 4, wherein the first execution unit circuit system generates a command to the first hardware semaphore circuit system, the command causing the state of the first hardware semaphore circuit system to change.

6. The method of claim 4, wherein the first hardware semaphore circuit system and the first execution unit circuit system are communicatively coupled by means of both being part of a first circuit system on the integrated circuit chip.

7. The method of claim 4, wherein the first execution unit circuit system is communicatively coupled to the first hardware semaphore circuit system via a dedicated on-chip network (NOC) circuit system.

8. The method of claim 7, wherein the first execution unit circuit system is part of a different subnet of the dedicated NOC relative to the first hardware semaphore circuit system.

9. The method of claim 1, wherein generating the first condition fulfillment notification by the first hardware semaphore circuit system includes the first hardware semaphore circuit system modifying one or more values ​​used by the second hardware semaphore circuit system to maintain the second state machine.

10. The method of claim 1, wherein the second state machine comprises four states: The first state indicates that the second condition has not been met, and none of the preceding semaphores in the chain have generated a condition-met notification. The second state represents that the second condition is met, and none of the preceding semaphores in the chain semaphores have generated a condition met notification. The third state indicates that the second condition has not been met, and all preceding semaphores in the chain have generated a condition met notification. The fourth state indicates that the second condition has been met, and all preceding semaphores in the chain have generated a condition-metd notification.

11. An integrated circuit chip, comprising: First execution unit circuit system; Second execution unit circuit system; A first hardware semaphore circuit system array associated with the first execution unit circuit system; A second hardware semaphore circuit system array associated with the second execution unit circuit system; A first hardware semaphore circuit system, configured as the first semaphore in a chain of semaphores, wherein the first hardware semaphore circuit system: Maintain the first state machine such that the generation of the output of the first producer process changes the first state machine; and When the first state machine is in a state corresponding to a first condition that depends on multiple conditions, a first condition satisfaction notification is generated for the subsequent semaphores in the chain semaphores. as well as A second hardware semaphore circuit system, configured as the subsequent semaphore in the chain of semaphores, the second hardware semaphore circuit system: Maintain the second state machine such that the generation of the output by the second producer process changes the second state machine; and A second condition satisfaction notification is generated when the second state machine is in a state corresponding to the following: (1) a second condition specified by the plurality of condition dependencies and (2) a condition satisfaction notification has been generated by all preceding semaphores in the chain semaphores.

12. The integrated circuit chip according to claim 11, further comprising: The first circuit system includes the first execution unit circuit system and the first hardware semaphore circuit system array; The second circuit system includes the second execution unit circuit system and the second hardware semaphore circuit system array; as well as A dedicated on-chip network (NOC) circuit system, wherein the dedicated on-chip NOC circuit system communicatively couples the first circuit system to the second circuit system; The first hardware semaphore circuit system and the second hardware semaphore circuit system are part of the first hardware semaphore circuit system array; and The multiple conditions depend on enumerating the states of the outputs of multiple producer processes, and the states of the outputs of the multiple producer processes must be satisfied so that the first consumer process can execute correctly on the first execution unit.

13. The integrated circuit chip of claim 12, wherein the first manufacturing process is executed on the second execution unit circuit system and generates a command to change the state of the first hardware semaphore, the command being transmitted from the second execution unit circuit system to the first hardware semaphore circuit system via the dedicated NOC.

14. The integrated circuit chip of claim 12, wherein the elements of the first circuit system are part of a first subnet of the dedicated NOC, and the elements of the second circuit system are part of a second subnet of the dedicated NOC.

15. The integrated circuit chip according to claim 11, further comprising: The first superblock circuit system includes the first execution unit circuit system, the first hardware semaphore circuit system array, the second execution unit circuit system, and the second hardware semaphore circuit system array. as well as A dedicated on-chip network (NOC) circuit system, wherein the dedicated on-chip NOC circuit system communicatively couples the first superblock circuit system to other superblock circuit systems on the integrated circuit chip; The first hardware semaphore circuit system is part of the first hardware semaphore circuit system array, and the second hardware semaphore circuit system is part of the second hardware semaphore circuit system array.

16. The integrated circuit chip of claim 11, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and The notification that the second condition is met is an interruption of the execution of the first consumer process, which has the aforementioned multiple condition dependencies as prerequisites for execution.

17. The integrated circuit chip of claim 11, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and The second condition being met triggers a semaphore command to the third hardware semaphore circuit system.

18. An integrated circuit chip, comprising: Multiple block circuit systems, each block circuit system including: Execution unit circuit system; and Two or more hardware semaphore circuit system arrays; and A dedicated on-chip network (NOC) circuit system communicatively coupled to the plurality of block circuit systems; At least one of the plurality of block circuit systems includes: A first hardware semaphore circuit system, configured as the first semaphore in a chain of semaphores, wherein the first hardware semaphore circuit system: Maintain the first state machine such that the generation of the output of the first producer process changes the first state machine; and When the first state machine is in a state corresponding to a first condition that depends on multiple conditions, a first condition fulfillment notification is generated for a subsequent semaphore in the chain of semaphores; and A second hardware semaphore circuit system, configured as the subsequent semaphore in the chain of semaphores, the second hardware semaphore circuit system: Maintain the second state machine such that the generation of the output by the second producer process changes the second state machine; and A second condition satisfaction notification is generated when the second state machine is in a state corresponding to the following: (1) a second condition specified by the plurality of condition dependencies and (2) a condition satisfaction notification has been generated by all preceding semaphores in the chain semaphores.

19. The integrated circuit chip of claim 18, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and The notification that the second condition is met is an interruption of the execution of the first consumer process, which has the aforementioned multiple condition dependencies as prerequisites for execution.

20. The integrated circuit chip of claim 18, wherein the second hardware semaphore circuit system is the last semaphore in the chain of semaphores; and The second condition being met triggers a semaphore command to the third hardware semaphore circuit system.

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