Pixel circuit, driving method thereof, and display device

Abstract

Provided are a pixel circuit and a driving method thereof, and a display device, and belong to the technical field of display. In the pixel circuit, a data writing circuit is coupled with three gate signal terminals, and controls the potentials of a first node, a second node and a third node under the control of gate driving signals provided by the three gate signal terminals. A driving circuit can transmit a light emitting driving signal to the third node based on the potentials of the first node and the second node. A light emitting control circuit can control the third node to be conductive with a light emitting element, so that the light emitting driving signal is further transmitted to the light emitting element, thereby lighting the light emitting element. Moreover, there are parasitic capacitances respectively formed between two gate signal terminals and the second node. In this way, the gate driving signals provided by the two gate signal terminals can be flexibly adjusted, so that the potential of the second node remains stable. Furthermore, the brightness of the light emitting element can be the same when the pixel circuit drives the light emitting element in different frames, and the display effect of the display device is better.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display device. Background Technology

[0002] Display devices typically include multiple pixels, each pixel including a pixel circuit and a light-emitting element that are coupled to each other. The pixel circuit can transmit a light-emitting driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0003] Currently, pixel circuits generally include a data writing circuit and a driving circuit. The data writing circuit is coupled to two gate signal terminals, a data signal terminal, and the input, control, and output terminals of the driving circuit. The output terminal of the driving circuit is also coupled to the light-emitting element. The data writing circuit can respond to the gate driving signal provided by each gate signal terminal, writing the data signal from the data signal terminal to the input and control terminals of the driving circuit. The driving circuit can transmit a light-emitting driving signal to the light-emitting element through its output terminal based on the potential of its control terminal and the potential of its input terminal. Furthermore, a parasitic capacitance is formed between one of the two gate signal terminals and the control terminal of the driving circuit.

[0004] However, due to the coupling effect of parasitic capacitance, the potential at the control terminal of the driving circuit will shift with the potential jump of the gate driving signal. As a result, the brightness of the light-emitting element varies when the light-emitting element is driven in different frames, leading to poor display effect of the display device. Summary of the Invention

[0005] This disclosure provides a pixel circuit and its driving method, as well as a display device, which can solve the problem of poor display effect in related technologies. The technical solution is as follows:

[0006] On one hand, a pixel circuit is provided, the pixel circuit comprising:

[0007] A data writing circuit is coupled to a first gate signal terminal, a second gate signal terminal, a third gate signal terminal, a data signal terminal, a first node, a second node, and a third node, respectively. The data writing circuit is used to control the connection and disconnection between the data signal terminal and the first node, and to control the connection and disconnection between the second node and the third node, in response to a first gate drive signal provided by the first gate signal terminal, a second gate drive signal provided by the second gate signal terminal, and a third gate drive signal provided by the third gate signal terminal. A first parasitic capacitance is formed between the second gate signal terminal and the second node, and a second parasitic capacitance is formed between the third gate signal terminal and the second node.

[0008] A light-emitting control circuit is coupled to a light-emitting control terminal, a first power supply terminal, a first node, a third node, and a light-emitting element, respectively. The light-emitting control circuit is used to control the on / off state of the first power supply terminal and the first node in response to the light-emitting control signal provided by the light-emitting control terminal, and to control the on / off state of the third node and the light-emitting element.

[0009] A driving circuit, wherein the input terminal, control terminal and output terminal of the driving circuit are respectively coupled to the first node, the second node and the third node, and the driving circuit is used to transmit a light-emitting driving signal to the third node based on the potential of the first node and the potential of the second node.

[0010] Optionally, the data writing circuit includes: a data writing sub-circuit and a compensation sub-circuit;

[0011] The data writing sub-circuit is coupled to the first gate signal terminal, the second gate signal terminal, the data signal terminal and the first node respectively. The data writing sub-circuit is used to control the connection and disconnection of the data signal terminal and the first node in response to the first gate drive signal and the second gate drive signal.

[0012] The compensation sub-circuit is coupled to the third gate signal terminal, the second node and the third node respectively. The compensation sub-circuit is used to control the on / off state of the second node and the third node in response to the third gate drive signal.

[0013] Optionally, the data writing sub-circuit includes: a first data writing unit and a second data writing unit;

[0014] The first data writing unit is coupled to the first gate signal terminal, the data signal terminal and the first node respectively. The first data writing unit is used to control the connection and disconnection between the data signal terminal and the first node in response to the first gate drive signal.

[0015] The second data writing unit is coupled to the second gate signal terminal, the data signal terminal and the first node respectively. The second data writing unit is used to control the connection and disconnection of the data signal terminal and the first node in response to the second gate drive signal.

[0016] Optionally, the first data writing unit includes a first data writing transistor; the second data writing unit includes a second data writing transistor.

[0017] The gate of the first data writing transistor is coupled to the first gate signal terminal, the first electrode of the first data writing transistor is coupled to the data signal terminal, and the second electrode of the first data writing transistor is coupled to the first node.

[0018] The gate of the second data writing transistor is coupled to the second gate signal terminal, the first terminal of the second data writing transistor is coupled to the data signal terminal, and the second terminal of the second data writing transistor is coupled to the first node.

[0019] Optionally, both the first data write transistor and the second data write transistor are P-type transistors.

[0020] Optionally, the compensation sub-circuit includes: a compensation transistor;

[0021] The gate of the compensation transistor is coupled to the third gate signal terminal, the first terminal of the compensation transistor is coupled to the third node, and the second terminal of the compensation transistor is coupled to the second node.

[0022] Optionally, the compensation transistor is an N-type transistor.

[0023] Optionally, the driving circuit includes a driving transistor, and the driving transistor is a P-type transistor;

[0024] The gate of the driving transistor is coupled to the second node, the first electrode of the driving transistor is coupled to the first node, and the second electrode of the driving transistor is coupled to the third node.

[0025] Optionally, the light-emitting control circuit includes: a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and an adjustment sub-circuit;

[0026] The first light-emitting control sub-circuit is coupled to the light-emitting control terminal, the first power supply terminal, and the first node respectively. The first light-emitting control sub-circuit is used to control the on / off state of the first power supply terminal and the first node in response to the light-emitting control signal.

[0027] The second light-emitting control sub-circuit is coupled to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively. The second electrode of the light-emitting element is coupled to the second power supply terminal. The second light-emitting control sub-circuit is used to control the on / off state of the third node and the first electrode of the light-emitting element in response to the light-emitting control signal.

[0028] The regulating sub-circuit is coupled to the second node and the first power supply terminal respectively, and the regulating sub-circuit is used to adjust the potential of the second node based on the first power supply signal.

[0029] Optionally, the first light-emitting control sub-circuit includes a first light-emitting control transistor; the second light-emitting control sub-circuit includes a second light-emitting control transistor; and both the first light-emitting control transistor and the second light-emitting control transistor are N-type transistors; the adjustment sub-circuit includes a storage capacitor;

[0030] The gate of the first light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the first light-emitting control transistor is coupled to the first power supply terminal, and the second electrode of the first light-emitting control transistor is coupled to the first node.

[0031] The gate of the second light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the second light-emitting control transistor is coupled to the third node, and the second electrode of the second light-emitting control transistor is coupled to the first electrode of the light-emitting element;

[0032] One end of the storage capacitor is coupled to the first power supply terminal, and the other end of the storage capacitor is coupled to the second node.

[0033] Optionally, the pixel circuit further includes: a first reset circuit and a second reset circuit;

[0034] The first reset circuit is coupled to the reset signal terminal, the first reset power supply terminal and the second node respectively. The first reset circuit is used to control the on / off state of the first reset power supply terminal and the second node in response to the reset signal provided by the reset signal terminal.

[0035] The second reset circuit is coupled to the first gate signal terminal, the second reset power supply terminal and the light-emitting element respectively. The second reset circuit is used to control the on / off state of the second reset power supply terminal and the light-emitting element in response to the first gate drive signal.

[0036] Optionally, the first reset circuit includes a first reset transistor; the second reset circuit includes a second reset transistor; and the first reset transistor is an N-type transistor, and the second reset transistor is a P-type transistor.

[0037] The gate of the first reset transistor is coupled to the reset signal terminal, the first terminal of the first reset transistor is coupled to the first reset power supply terminal, and the second terminal of the first reset transistor is coupled to the second node.

[0038] The gate of the second reset transistor is coupled to the first gate signal terminal, the first terminal of the second reset transistor is coupled to the second reset power supply terminal, and the second terminal of the second reset transistor is coupled to the light-emitting element.

[0039] On the other hand, a method for driving a pixel circuit is provided for driving the pixel circuit as described above, the method comprising: a first stage and a second stage executed sequentially in refresh frames during multi-frame scanning, and a third stage and the second stage executed sequentially in hold frames during multi-frame scanning;

[0040] In the first stage, the potential of the light emission control signal provided by the light emission control terminal, the potential of the second gate drive signal provided by the second gate signal terminal, and the potential of the third gate drive signal provided by the third gate signal terminal are all the first potential, and the potential of the first gate drive signal provided by the first gate signal terminal is the second potential. The data writing circuit responds to the first gate drive signal, controls the data signal terminal to be connected with the first node, and responds to the third gate drive signal, controls the second node to be connected with the third node.

[0041] In the second stage, the potentials of the first gate driving signal and the second gate driving signal are both first potentials, and the potentials of the light emission control signal and the third gate driving signal are both second potentials. The light emission control circuit responds to the light emission control signal by controlling the first power supply terminal to be connected to the first node and controlling the third node to be connected to the light emission element. The driving circuit transmits the light emission driving signal to the third node based on the potentials of the first node and the second node.

[0042] In the third stage, the potential of the light emission control signal and the potential of the first gate drive signal are both the first potential, and the potential of the second gate drive signal and the potential of the third gate drive signal are both the second potential. The data writing circuit responds to the second gate drive signal and controls the data signal terminal to be connected to the first node.

[0043] Optionally, the method further includes: a fourth phase executed before the first phase in the refresh frame;

[0044] In the fourth stage, the potential of the reset signal provided by the reset signal terminal, the potential of the light emission control signal, the potential of the first gate drive signal and the potential of the second gate drive signal are all the first potential, the potential of the third gate drive signal is the second potential, and the first reset circuit responds to the reset signal to control the first reset power supply terminal to be connected to the second node.

[0045] Furthermore, in the first stage, the second reset circuit responds to the first gate drive signal and controls the second reset power supply terminal to be connected to the light-emitting element.

[0046] In another aspect, a display device is provided, the display device comprising: a display panel, a display driving circuit, and a plurality of pixels located on the display panel, the pixels comprising: a light-emitting element, and a pixel circuit as described above;

[0047] The display driving circuit is coupled to each signal terminal of the pixel circuit, and the display driving circuit is used to provide signals to each signal terminal.

[0048] The pixel circuit is coupled to the light-emitting element, and the pixel circuit is used to transmit a light-emitting driving signal to the light-emitting element, and the light-emitting element is used to emit light based on the light-emitting driving signal.

[0049] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can at least include:

[0050] A pixel circuit and its driving method, as well as a display device, are provided. In this pixel circuit, a data writing circuit is coupled to three gate signal terminals and controls the potentials of a first node, a second node, and a third node under the control of gate driving signals provided by these three gate signal terminals. The driving circuit can transmit a light-emitting driving signal to the third node based on the potentials of the first and second nodes. The light-emitting control circuit can control the third node to conduct with the light-emitting element, so that the light-emitting driving signal is further transmitted to the light-emitting element, thereby illuminating the light-emitting element. Furthermore, parasitic capacitances are formed between the two gate signal terminals and the second node. Thus, the potential of the second node can be kept stable by flexibly adjusting the gate driving signals provided by the two gate signal terminals. Consequently, the brightness of the light-emitting element is the same when the pixel circuit drives the light-emitting element in different frames, resulting in a better display effect of the display device. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0053] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure;

[0054] Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0055] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0056] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0057] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0058] Figure 7 This is a flowchart of a pixel circuit driving method provided in an embodiment of this disclosure;

[0059] Figure 8 This is a flowchart of another pixel circuit driving method provided in an embodiment of this disclosure;

[0060] Figure 9 This is a timing diagram of the signal terminals coupled to a pixel circuit according to an embodiment of the present disclosure;

[0061] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0063] All transistors used in the embodiments of this disclosure can be field-effect transistors or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the source is referred to as the first terminal and the drain as the second terminal, or vice versa. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include either P-type or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high, while an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. Additionally, multiple signals in the various embodiments of this disclosure correspond to valid and invalid potentials. Valid and invalid potentials only represent that the signal has two potential states and do not represent that the valid or invalid potentials have specific values ​​throughout the text.

[0064] Currently, the process of driving a pixel circuit to emit light from a light-emitting element can be divided into at least two stages: a data writing stage and a light-emitting stage. In the data writing stage, the gate signal terminal can provide a gate drive signal with an effective potential, causing the data writing circuit to respond to this effective gate drive signal and write the data signal provided by the data signal terminal to the input and control terminals of the driving circuit. In the light-emitting stage, the potential of the gate drive signal jumps from an effective potential to an ineffective potential. At this time, the driving circuit can transmit a light-emitting drive signal to the light-emitting element based on the potentials of its input and control terminals to drive the light-emitting element to emit light.

[0065] However, due to the coupling effect of the parasitic capacitance formed between the gate signal terminal and the control terminal of the driving circuit, the potential of the control terminal of the driving circuit will shift with the potential jump of the gate drive signal. For example, assuming the effective potential is high and the ineffective potential is low, after the data signal is written, when the gate drive signal jumps from high to low, the potential of the control terminal of the driving circuit will be pulled down by the coupling effect of the parasitic capacitance, resulting in a negative bias. This negative bias will affect the brightness of the light-emitting elements driven by the pixel circuit during two adjacent frames of scanning, resulting in a poor display effect of the display device.

[0066] Based on this, the poor display uniformity problem described in the above embodiments can currently be improved by adjusting the potential of the data signal. For example, if the potential of the control terminal of the driving circuit in the current frame is pulled low, the potential of the data signal can be increased in the next frame to compensate for the potential of the control terminal of the driving circuit, ensuring that the potential of the control terminal of the driving circuit can be relatively consistent in the two frames. However, increasing the potential of the data signal will undoubtedly cause a large difference in the potential of the data signal between the two frames, that is, the potential range of the data signal is too high. This will result in higher power consumption of the circuit that provides the data signal to the data signal terminal (e.g., the source driving circuit), and increase the operating power consumption of the display panel in the display device.

[0067] Furthermore, current display devices typically support high refresh rates for their panels, such as 120 Hz. While high refresh rates improve display quality, they also pose a significant challenge to the panel's power consumption. Moreover, in everyday panel use, a high refresh rate isn't always necessary; for example, a lower refresh rate can suffice when entering reading mode. Therefore, panel development should focus on minimizing power consumption through various means.

[0068] Based on this, the present disclosure provides a pixel circuit, and the display device using the pixel circuit not only has a better display effect, but also has lower power consumption.

[0069] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure. Figure 1 As shown, the pixel circuit includes: a data writing circuit 01, a light emission control circuit 02, and a driving circuit 03.

[0070] The data writing circuit 01 is coupled to the first gate signal terminal Gate_P, the second gate signal terminal Gate_P1, the third gate signal terminal Gate_N, the data signal terminal Data, the first node N1, the second node N2, and the third node N3, respectively. The data writing circuit 01 is used to control the on / off state of the data signal terminal Data and the first node N1, and to control the on / off state of the second node N2 and the third node N3, in response to the first gate drive signal provided by the first gate signal terminal Gate_P, the second gate drive signal provided by the second gate signal terminal Gate_P1, and the third gate drive signal provided by the third gate signal terminal Gate_N.

[0071] For example, the data writing circuit 01 can control the data signal terminal Data to be connected to the first node N1 when the potential of the first gate drive signal provided by the first gate signal terminal Gate_P is an effective potential, and / or when the potential of the second gate drive signal provided by the second gate signal terminal Gate_P1 is an effective potential. At this time, the data signal provided by the data signal terminal Data can be transmitted to the first node N1. The data writing circuit 01 can also control the data signal terminal Data to be disconnected from the first node N1 when the potential of the first gate drive signal is an invalid potential, and when the potential of the second gate drive signal is an invalid potential.

[0072] Similarly, the data writing circuit 01 can control the second node N2 and the third node N3 to conduct when the potential of the third gate drive signal provided by the third gate signal terminal Gate_N is an effective potential. At this time, the potentials of the second node N2 and the third node N3 can influence each other. Furthermore, the data writing circuit 01 can control the second node N2 and the third node N3 to disconnect when the potential of the third gate drive signal is an invalid potential.

[0073] Optionally, the data writing circuit 01 may include three transistors coupled to the first gate signal terminal Gate_P, the second gate signal terminal Gate_P1, and the third gate signal terminal Gate_N, respectively. Of these three transistors, the transistor coupled to the first gate signal terminal Gate_P and the transistor coupled to the second gate signal terminal Gate_P1 can both be P-type transistors, and the transistor coupled to the third gate signal terminal Gate_N can be an N-type transistor. Based on this, the invalid potential of the first gate drive signal and the invalid potential of the second gate drive signal can be high potentials, and the valid potentials of the first gate drive signal and the valid potentials of the second gate drive signal can be low potentials. The invalid potential of the third gate drive signal can be low potentials, and the valid potential of the third gate drive signal can be high potentials. In the following embodiments of this disclosure, the high potential can be referred to as the first potential, and the low potential can be referred to as the second potential.

[0074] refer to Figure 1As can be seen, after adding the second gate signal terminal Gate_P1 in this embodiment, not only will a second parasitic capacitance C2 be formed between the third gate signal terminal Gate_N and the second node N2, but a first parasitic capacitance C1 will also be formed between the second gate signal terminal Gate_P1 and the second node N2. Thus, under the coupling effect of the second parasitic capacitance C2, the potential of the second node N2 will shift with the potential jump of the third gate drive signal. Furthermore, under the coupling effect of the first parasitic capacitance C1, the potential of the second node N2 will shift with the potential jump of the second gate drive signal. Based on this, by flexibly adjusting the potentials of the second and third gate drive signals, the potential of the second node N2 can undergo positive shifts (i.e., potential increase) and negative shifts (i.e., potential decrease) at different stages, ensuring that the potential of the second node N2 ultimately remains at a stable potential, thereby solving the display non-uniformity problem described in the above embodiments. Furthermore, with the potential of the second node N2 remaining stable, the potential range of the data signal required by the data signal terminal Data between the two frames can remain relatively consistent, thus reducing the data range. Consequently, compared to related technologies, this effectively reduces the power consumption of the source drive circuit that provides the data signal to the data signal terminal Data, and also reduces the operating power consumption of the panel.

[0075] For example, in this embodiment of the present disclosure, when the panel adopts a low-frequency refresh mode, multi-frame scanning can be divided into refresh frames and hold frames. Refresh scanning is performed in the refresh frames, while no refresh scanning is performed in the hold frames; only display is considered. In the refresh frame, the potential of the first gate drive signal can be controlled to be low, and the potential of the third gate drive signal can be controlled to be high, to write data signals to the first node N1 and the second node N2. After the data signal is written, the potential of the first gate drive signal can be controlled to jump to high, and the potential of the third gate drive signal can be controlled to jump to low. At this time, under the coupling effect of the second parasitic capacitance C2, the potential of the second node N2 is pulled low. In the hold frame, the potential of the second gate drive signal can be controlled to be low, to write data signals to the first node N1. After the data signal is written, the potential of the second gate drive signal can be controlled to jump to high. At this time, under the coupling effect of the first parasitic capacitance C1, the potential of the second node N2 is pulled high. Thus, the potential of the second node N2 is ensured to remain stable. This ensures a good display effect and achieves the goal of reducing power consumption of the panel during the frame-holding phase in low refresh rate mode.

[0076] The light-emitting control circuit 02 is coupled to the light-emitting control terminal EM, the first power supply terminal VDD, the first node N1, the third node N3, and the light-emitting element L1. The light-emitting control circuit 02 is used to control the on / off state of the first power supply terminal VDD and the first node N1 in response to the light-emitting control signal provided by the light-emitting control terminal EM, and to control the on / off state of the third node N3 and the light-emitting element L1.

[0077] For example, when the potential of the light-emitting control signal is a first potential, the light-emitting control circuit 02 can control the first power supply terminal VDD to conduct with the first node N1, and control the third node N3 to conduct with the light-emitting element L1. At this time, the first power signal provided by the first power supply terminal VDD can be transmitted to the first node N1, and the potential of the third node N3 can be transmitted to the light-emitting element L1. Furthermore, when the potential of the light-emitting control signal is a second potential, the light-emitting control circuit 02 can control the first power supply terminal VDD to decouple from the first node N1, and control the third node N3 to decouple from the light-emitting element L1.

[0078] Optionally, the light-emitting control circuit 02 can be coupled to the first terminal of the light-emitting element L1, and the second terminal of the light-emitting element L1 can be coupled to the second power supply terminal VSS. Furthermore, as... Figure 1 As shown, the first electrode of the light-emitting element L1 can be an anode, and the second electrode of the light-emitting element L1 can be a cathode. Of course, in some other embodiments, the first electrode of the light-emitting element L1 can be a cathode, and correspondingly, the second electrode of the light-emitting element L1 can be an anode.

[0079] The input, control, and output terminals of the driving circuit 03 are coupled to the first node N1, the second node N2, and the third node N3, respectively. That is, the input terminal of the driving circuit 03 can be coupled to the first node N1, the control terminal of the driving circuit 03 can be coupled to the second node N2, and the output terminal of the driving circuit 03 can be coupled to the third node N3. The driving circuit 03 is used to transmit a light-emitting driving signal (e.g., driving current) to the third node N3 based on the potential of the first node N1 and the potential of the second node N2.

[0080] After the light-emitting control circuit 02 controls the third node N3 to conduct to the anode of the light-emitting element L1, the light-emitting drive signal can be transmitted to the anode of the light-emitting element L1 via the light-emitting control circuit 02. The light-emitting element L1 can emit light under the voltage difference between the light-emitting drive signal and the second power supply signal provided by the second power supply terminal VSS coupled to its cathode. It should be noted that since the light-emitting drive signal is transmitted to the anode of the light-emitting element L1 via the light-emitting control circuit 02, the potential of the light-emitting drive signal finally transmitted to the anode of the light-emitting element L1 may be different from the potential of the light-emitting drive signal generated by the drive circuit 03 based on the potential of the first node N1 and the potential of the second node N2.

[0081] In summary, this disclosure provides a pixel circuit. In this pixel circuit, a data writing circuit is coupled to three gate signal terminals and, under the control of the gate drive signals provided by these three gate signal terminals, controls the potentials of the first node, the second node, and the third node. The driving circuit can transmit a light-emitting driving signal to the third node based on the potentials of the first and second nodes. The light-emitting control circuit can control the third node to conduct with the light-emitting element, so that the light-emitting driving signal is further transmitted to the light-emitting element, thereby illuminating the light-emitting element. Furthermore, parasitic capacitances are formed between the two gate signal terminals and the second node. Thus, the potential of the second node can be kept stable by flexibly adjusting the gate drive signals provided by these two gate signal terminals. Consequently, the brightness of the light-emitting element is the same when the pixel circuit drives the light-emitting element in different frames, resulting in a better display effect for the display device.

[0082] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. For example... Figure 2 As shown, the data writing circuit 01 in the pixel circuit may include: a data writing sub-circuit 011 and a compensation sub-circuit 012.

[0083] The data writing sub-circuit 011 can be coupled to the first gate signal terminal Gate_P, the second gate signal terminal Gate_P1, the data signal terminal Data, and the first node N1, respectively. The data writing sub-circuit 011 is used to control the on / off state of the data signal terminal Data and the first node N1 in response to the first gate drive signal and the second gate drive signal.

[0084] For example, the data writing sub-circuit 011 can control the data signal terminal Data to be turned on with the first node N1 when the potential of the first gate drive signal is an effective potential and / or the potential of the second gate drive signal is an effective potential, so that the data signal is transmitted to the first node N1. Conversely, the data writing sub-circuit 011 can control the data signal terminal Data to be disconnected from the first node N1 when the potential of the first gate drive signal is an invalid potential and the potential of the second gate drive signal is an invalid potential.

[0085] The compensation sub-circuit 012 is coupled to the third gate signal terminal Gate_N, the second node N2, and the third node N3, respectively. The compensation sub-circuit 012 is used to control the on / off state of the second node N2 and the third node N3 in response to the third gate drive signal.

[0086] For example, the compensation sub-circuit 012 can control the second node N2 and the third node N3 to conduct when the potential of the third gate drive signal is an effective potential, so as to compensate the potential of the second node N2 based on the potential of the third node N3. Furthermore, the compensation sub-circuit 012 can control the second node N2 and the third node N3 to disconnect when the potential of the third gate drive signal is an invalid potential.

[0087] Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of this disclosure. For example... Figure 3 As shown, the data writing sub-circuit 011 in the data writing circuit 01 may include: a first data writing unit 0111 and a second data writing unit 0112.

[0088] The first data writing unit 0111 can be coupled to the first gate signal terminal Gate_P, the data signal terminal Data, and the first node N1, respectively. The first data writing unit 0111 can be used to control the on / off state of the data signal terminal Data and the first node N1 in response to the first gate drive signal.

[0089] For example, the first data writing unit 0111 can control the data signal terminal Data to be turned on with the first node N1 when the potential of the first gate drive signal is an effective potential. Also, the first data writing unit 0111 can control the data signal terminal Data to be disconnected from the first node N1 when the potential of the first gate drive signal is an invalid potential.

[0090] The second data writing unit 0112 can be coupled to the second gate signal terminal Gate_P1, the data signal terminal Data, and the first node N1, respectively. The second data writing unit 0112 can be used to control the on / off state of the data signal terminal Data and the first node N1 in response to the second gate drive signal.

[0091] For example, the second data writing unit 0112 can control the data signal terminal Data to be turned on with the first node N1 when the potential of the second gate drive signal is an effective potential. Also, the second data writing unit 0112 can control the data signal terminal Data to be disconnected from the first node N1 when the potential of the second gate drive signal is an invalid potential.

[0092] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. For example... Figure 4 As shown, the light emission control circuit 02 may include: a first light emission control sub-circuit 021, a second light emission control sub-circuit 022, and an adjustment sub-circuit 023.

[0093] The first light-emitting control sub-circuit 021 can be coupled to the light-emitting control terminal EM, the first power supply terminal VDD, and the first node N1, respectively. The first light-emitting control sub-circuit 021 can be used to control the on / off state of the first power supply terminal VDD and the first node N1 in response to the light-emitting control signal.

[0094] For example, the first light-emitting control sub-circuit 021 can control the first power supply terminal VDD to conduct with the first node N1 when the potential of the light-emitting control signal is an effective potential, so that the first power supply signal provided by the first power supply terminal VDD can be transmitted to the first node N1. Furthermore, the first light-emitting control sub-circuit 021 can control the first power supply terminal VDD to disconnect from the first node N1 when the potential of the light-emitting control signal is an invalid potential.

[0095] The second light-emitting control sub-circuit 022 can be coupled to the light-emitting control terminal EM, the third node N3, and the first electrode of the light-emitting element L1, respectively. The second electrode of the light-emitting element L1 is coupled to the second power supply terminal VSS. The second light-emitting control sub-circuit 022 can be used to control the on / off state of the third node N3 and the first electrode of the light-emitting element L1 in response to the light-emitting control signal. As described in the above embodiment, the first electrode of the light-emitting element L1 can be an anode, and the second electrode of the light-emitting element L1 can be a cathode.

[0096] For example, the second light-emitting control sub-circuit 022 can control the third node N3 to conduct with the first electrode of the light-emitting element L1 when the potential of the light-emitting control signal is an effective potential, so that the potential of the third node N3 is transmitted to the first electrode of the light-emitting element L1, driving the light-emitting element L1 to emit light. Furthermore, the second light-emitting control sub-circuit 022 can control the third node N3 to disconnect from the first electrode of the light-emitting element L1 when the potential of the light-emitting control signal is an invalid potential.

[0097] Optionally, in this embodiment of the disclosure, the potential of the first power signal can be a high potential, and the potential of the second power signal can be a low potential.

[0098] The regulating sub-circuit 023 can be coupled to the second node N2 and the first power supply terminal VDD, respectively. The regulating sub-circuit 023 can be used to regulate the potential of the second node N2 based on the first power supply signal.

[0099] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. For example... Figure 5 As shown, the pixel circuit may also include: a first reset circuit 04 and a second reset circuit 05.

[0100] The first reset circuit 04 can be coupled to the reset signal terminal Rst, the first reset power supply terminal Vinit1, and the second node N2, respectively. The first reset circuit 04 can be used to control the on / off state of the first reset power supply terminal Vinit1 and the second node N2 in response to the reset signal provided by the reset signal terminal Rst.

[0101] For example, the first reset circuit 04 can control the first reset power supply terminal Vinit1 to conduct with the second node N2 when the reset signal potential is an effective potential. At this time, the first reset power signal provided by the first reset power supply terminal Vinit1 can be transmitted to the second node N2 to reset the second node N2. Conversely, the first reset circuit 04 can also control the first reset power supply terminal Vinit1 to disconnect from the second node N2 when the reset signal potential is an invalid potential.

[0102] The second reset circuit 05 can be coupled to the first gate signal terminal Gate_P, the second reset power supply terminal Vinit2, and the light-emitting element L1, respectively. The second reset circuit 05 can be used to control the on / off state of the second reset power supply terminal Vinit2 and the light-emitting element L1 in response to the first gate drive signal.

[0103] For example, the second reset circuit 05 can be coupled to the anode of the light-emitting element L1. When the potential of the first gate drive signal is an effective potential, the second reset circuit 05 can control the second reset power supply terminal Vinit2 to conduct to the anode of the light-emitting element L1. At this time, the second reset power supply signal provided by the second reset power supply terminal Vinit2 can be transmitted to the anode of the light-emitting element L1 to reset the anode of the light-emitting element L1. Conversely, when the potential of the first gate drive signal is an ineffective potential, the second reset circuit 05 can control the second reset power supply terminal Vinit2 to disconnect from the anode of the light-emitting element L1.

[0104] Optionally, in this embodiment of the disclosure, the potential of the first reset power signal and the potential of the second reset power signal can both be low potentials. Furthermore, the potential of the first reset power signal can be less than or equal to the potential of the second reset power signal. Of course, in some other embodiments, the potential of the first reset power signal can also be greater than the potential of the second reset power signal.

[0105] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. For example... Figure 6As shown, the first data writing unit 0111 may include a first data writing transistor T1. The second data writing unit 0112 may include a second data writing transistor T2. The compensation sub-circuit 012 may include a compensation transistor T3. The driving circuit 03 may include a driving transistor T4. The first light-emitting control sub-circuit 021 may include a first light-emitting control transistor T5, the second light-emitting control sub-circuit 022 may include a second light-emitting control transistor T6, and the adjustment sub-circuit 023 may include a storage capacitor Cst. The first reset circuit 04 may include a first reset transistor T7. The second reset circuit 05 may include a second reset transistor T8.

[0106] Specifically, the gate of the first data writing transistor T1 can be coupled to the first gate signal terminal Gate_P, the first terminal of the first data writing transistor T1 can be coupled to the data signal terminal Data, and the second terminal of the first data writing transistor T1 can be coupled to the first node N1.

[0107] The gate of the second data writing transistor T2 can be coupled to the second gate signal terminal Gate_P1, the first terminal of the second data writing transistor T2 can be coupled to the data signal terminal Data, and the second terminal of the second data writing transistor T2 can be coupled to the first node N1.

[0108] Based on this, and in conjunction with the above embodiments, during frame refresh, the potential of the first gate drive signal can be controlled to be low, and the potential of the second gate drive signal can be controlled to be high, so that the first data write transistor T1 is turned on and the second data write transistor T2 is turned off. At this time, the data signal can be transmitted to the first node N1 via the turned-on first data write transistor T1, realizing data signal writing. During frame hold, the potential of the first gate drive signal can be controlled to be high, and the potential of the second gate drive signal can be controlled to be low, so that the first data write transistor T1 is turned off and the second data write transistor T2 is turned on. At this time, the data signal can be transmitted to the first node N1 via the turned-on second data write transistor T2, realizing data signal writing. In other words, at this time, the data signal terminal Data can be switched to the second data write transistor T2 to be connected to the first node N1. Subsequently, after the data writing is completed, the potential of the second gate drive signal can be controlled to be high, thereby pulling the potential of the second node N2 high under the coupling effect of the first parasitic capacitor C1, so as to cancel out the pull-down of the potential of the second node N2 under the potential jump of the third gate drive signal, thus ensuring the potential stability of the second node N2.

[0109] The gate of the compensation transistor T3 can be coupled to the third gate signal terminal Gate_N, the first terminal of the compensation transistor T3 can be coupled to the third node N3, and the second terminal of the compensation transistor T3 can be coupled to the second node N2.

[0110] The gate of the driving transistor T4 can be coupled to the second node N2, the first terminal of the driving transistor T4 can be coupled to the first node N1, and the second terminal of the driving transistor T4 can be coupled to the third node N3.

[0111] That is, the gate of the driving transistor T4 can be the control terminal of the driving circuit 03, the first terminal of the driving transistor T4 can be the input terminal of the driving circuit 03, and the second terminal of the driving transistor T4 can be the output terminal of the driving circuit 03.

[0112] The gate of the first light-emitting control transistor T5 is coupled to the light-emitting control terminal EM, the first terminal of the first light-emitting control transistor T5 is coupled to the first power supply terminal VDD, and the second terminal of the first light-emitting control transistor T5 is coupled to the first node N1.

[0113] The gate of the second light-emitting control transistor T6 is coupled to the light-emitting control terminal EM, the first terminal of the second light-emitting control transistor T6 is coupled to the third node N3, and the second terminal of the second light-emitting control transistor T6 is coupled to the first terminal of the light-emitting element L1.

[0114] One end of the storage capacitor Cst is coupled to the first power supply terminal VDD, and the other end of the storage capacitor Cst is coupled to the second node N2.

[0115] The gate of the first reset transistor T7 is coupled to the reset signal terminal Rst, the first terminal T7 of the first reset transistor is coupled to the first reset power supply terminal Vinit1, and the second terminal of the first reset transistor T7 is coupled to the second node N2.

[0116] The gate of the second reset transistor T8 is coupled to the first gate signal terminal Gate_P, the first terminal of the second reset transistor T8 is coupled to the second reset power supply terminal Vinit2, and the second terminal of the second reset transistor T8 is coupled to the light-emitting element L1.

[0117] Furthermore, as described in the above embodiments, both the first data writing transistor T1 and the second data writing transistor T2 can be P-type transistors. The compensation transistor T3 can be an N-type transistor. Also, in this embodiment, both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be N-type transistors. The driving transistor T4 can be a P-type transistor. The first reset transistor T7 can be an N-type transistor, and the second reset transistor T8 is a P-type transistor. Based on this, the effective potential of the light-emitting control signal and the effective potential of the reset signal can both be high potentials, and the ineffective potential of the light-emitting control signal and the ineffective potential of the reset signal can both be low potentials.

[0118] Optionally, in this embodiment of the disclosure, the P-type transistors included in the pixel circuit can all be transistors made of low-temperature poly-silicon (LTPS) material, and the N-type transistors can all be transistors made of oxide material. Correspondingly, the pixel circuit can be a low-temperature poly-silicon oxide (LTPO) pixel circuit. The oxide material can include indium gallium zinc oxide (IGZO) material. Here, the transistor material refers to the material of the active layer included in the transistor.

[0119] It should be noted that, provided the potential of the second node N2 can be stabilized, the pixel circuit described in this embodiment can, in addition to being able to... Figure 6 Besides the 8T1C structure shown (i.e., including 8 transistors and 1 capacitor), structures including other numbers of transistors are also possible. For example, a 6T1C structure. This disclosure does not limit this.

[0120] It should also be noted that the types of transistors included in the pixel circuit can be as described in the above embodiments. Of course, in some other embodiments, the types of transistors included in the pixel circuit can also satisfy other choices. For example, the first reset transistor T7 can be a P-type transistor. However, regardless of the choice, for P-type transistors, the effective potential is low relative to the ineffective potential; for N-type transistors, the effective potential is high relative to the ineffective potential.

[0121] In summary, this disclosure provides a pixel circuit. In this pixel circuit, a data writing circuit is coupled to three gate signal terminals and, under the control of the gate drive signals provided by these three gate signal terminals, controls the potentials of the first node, the second node, and the third node. The driving circuit can transmit a light-emitting driving signal to the third node based on the potentials of the first and second nodes. The light-emitting control circuit can control the third node to conduct with the light-emitting element, so that the light-emitting driving signal is further transmitted to the light-emitting element, thereby illuminating the light-emitting element. Furthermore, parasitic capacitances are formed between the two gate signal terminals and the second node. Thus, the potential of the second node can be kept stable by flexibly adjusting the gate drive signals provided by these two gate signal terminals. Consequently, the brightness of the light-emitting element is the same when the pixel circuit drives the light-emitting element in different frames, resulting in a better display effect for the display device.

[0122] Figure 7 This is a flowchart of a pixel circuit driving method provided in an embodiment of this disclosure. This method can be used to drive such... Figures 1 to 6 Any pixel circuit shown. (e.g.) Figure 7 As shown, the method includes: a first stage and a second stage executed sequentially for refresh frames in a multi-frame scan, and a third stage and a second stage executed sequentially for hold frames in a multi-frame scan. For example, assuming a total of 60 frames, 30 frames can be divided into refresh frames and 30 frames into hold frames.

[0123] Step 701: In the first stage, the potential of the light emission control signal provided by the light emission control terminal, the potential of the second gate drive signal provided by the second gate signal terminal, and the potential of the third gate drive signal provided by the third gate signal terminal are all first potentials, and the potential of the first gate drive signal provided by the first gate signal terminal is the second potential. The data writing circuit responds to the first gate drive signal, controls the data signal terminal to be connected with the first node, and responds to the third gate drive signal, controls the second node to be connected with the third node.

[0124] Step 702: In the second stage, the potential of the first gate driving signal and the potential of the second gate driving signal are both the first potential, and the potential of the light emission control signal and the potential of the third gate driving signal are both the second potential. The light emission control circuit responds to the light emission control signal, controls the first power supply terminal to be connected to the first node, and controls the third node to be connected to the light emission element. The driving circuit transmits the light emission driving signal to the third node based on the potential of the first node and the potential of the second node.

[0125] Step 703: In the third stage, the potential of the light emission control signal and the potential of the first gate drive signal are both the first potential, and the potentials of the second gate drive signal and the third gate drive signal are both the second potential. The data writing circuit responds to the second gate drive signal and controls the data signal terminal to be connected to the first node.

[0126] Optionally, as described in the above embodiments, in the method, the first potential may refer to a high potential and the second potential may refer to a low potential.

[0127] In summary, this disclosure provides a driving method for a pixel circuit. In this method, during the first and second stages of the refresh frame, the potential of the third gate driving signal provided by the third gate signal terminal jumps from a first potential to a second potential. Consequently, under the parasitic capacitance coupling between the third gate signal terminal and the second node, the potential of the second node is driven to undergo a first shift. During the third and second stages of the hold frame, the potential of the second gate driving signal provided by the second gate signal terminal jumps from a second potential to a first potential. Consequently, under the parasitic capacitance coupling between the second gate signal terminal and the second node, the potential of the second node is driven to undergo a first shift. Since the first shift occurs when the first potential jumps to the second potential, and the second shift occurs when the second potential jumps to the first potential, the potential of the second node can be kept stable. Furthermore, this ensures that the brightness of the light-emitting element is the same when the pixel circuit drives the light-emitting element in different frames, resulting in a better display effect for the display device.

[0128] Figure 8 This is a flowchart of another pixel circuit driving method provided in an embodiment of this disclosure. Figure 8 As shown, the method may further include a fourth stage executed before the first stage in the refresh frame, namely, step 704 below.

[0129] Step 704: In the fourth stage, the potential of the reset signal, the potential of the light emission control signal, the potential of the first gate drive signal and the potential of the second gate drive signal provided by the reset signal terminal are all the first potential, and the potential of the third gate drive signal is the second potential. The first reset circuit responds to the reset signal and controls the first reset power supply terminal to be connected to the second node.

[0130] In addition, in the first stage (i.e., in step 701), the second reset circuit responds to the first gate drive signal and controls the second reset power supply terminal to be turned on with the light-emitting element.

[0131] by Figure 6 Taking the pixel circuit shown, with the first potential being high and the second potential being low as an example, the driving principle of the pixel circuit described in the embodiments of this disclosure will be explained as follows. Figure 9 A timing diagram of the signal terminals coupled to a pixel circuit according to an embodiment of this disclosure is shown. (Reference) Figure 9It can be seen that after the refresh frame, a hold frame can be entered, and the refresh frame includes the fourth stage t4, the first stage t1, and the second stage t2 executed in sequence; the hold frame includes the third stage t3 and the second stage t2 executed in sequence.

[0132] In the fourth stage t4, the potentials of the light-emitting control signal provided by the light-emitting control terminal EM, the reset signal provided by the reset signal terminal Rst, the first gate drive signal provided by the first gate signal terminal Gate_P, and the second gate drive signal provided by the second gate signal terminal Gate_P1 are all high (i.e., the first potential), while only the potential of the third gate drive signal provided by the third gate signal terminal Gate_N is low (i.e., the second potential). Correspondingly, only the first reset transistor T7 is turned on, while the first data write transistor T1, the second data write transistor T2, the compensation transistor T3, the first light-emitting control transistor T5, the sixth light-emitting control transistor T6, and the second reset transistor T8 are all turned off. Based on this, the low-potential first reset power signal provided by the first reset power supply terminal Vinit1 can be transmitted to the second node N2 via the turned-on first reset transistor T7 to reset the second node N2, thereby driving transistor T4 to turn on. This fourth stage t4 can also be called the reset stage for resetting the second node N2.

[0133] In the first stage t1, the potentials of the light-emitting control signal, the second gate drive signal, and the third gate drive signal are all high, while the potentials of the reset signal and the first gate drive signal are low. Correspondingly, the first data write transistor T1, the second reset transistor T8, and the compensation transistor T3 are all turned on, while the second data write transistor T2, the first light-emitting control transistor T5, the sixth light-emitting control transistor T6, and the first reset transistor T are all turned off. Furthermore, due to the storage effect of the storage capacitor Cst, the potential of the second node N2 is initially maintained at the low potential of the previous stage t4, and the drive transistor T4 remains on. Based on this, the low-potential second reset power supply signal provided by the second reset power supply terminal Vinit can be transmitted to the anode of the light-emitting element L1 via the turned-on second reset transistor T8, thereby resetting the anode of the light-emitting element L1. Furthermore, the data signal provided by the data signal terminal Data can be transmitted to the first node N1 via the activated first data writing transistor T1. The potential of the first node N1 can then be transmitted to the third node N3 via the activated driving transistor T4. The potential of the third node N3 can then be transmitted to the second node N2 via the activated compensation transistor T3. Thus, the purpose of writing the data signal to the second node N2 is achieved. This first stage t1 can also be called the data writing stage, and the reset stage for resetting the light-emitting element L1.

[0134] In the second stage t2, the potentials of the first gate drive signal and the second gate drive signal are both high, while the potentials of the light emission control signal, the reset signal, and the third gate drive signal are all low. Correspondingly, the first light emission control transistor T5 and the second light emission control transistor T6 are both turned on, and the first data write transistor T1, the second data write transistor T2, the compensation transistor T3, the first reset transistor T7, and the second reset transistor T8 are all turned off. Furthermore, due to the storage effect of the storage capacitor Cst, the potential of the second node N2 is initially maintained at the low potential of the previous stage t4, and the driving transistor T4 remains on. Based on this, the high-potential first power supply signal provided by the first power supply terminal VDD can be transmitted to the first node N1 via the turned-on first light emission control transistor T5, and the anode of the third node N3 is connected to the light-emitting element L1, forming a path between the first power supply terminal VDD and the second power supply terminal VSS. The driving transistor T4 can transmit the light emission drive signal to the third node N3 based on the potentials of the first node N1 and the second node N2. The light-emitting drive signal is then transmitted to the anode of the light-emitting element L1 via the activated second light-emitting control transistor T6, causing the light-emitting element L1 to emit light. This second stage t2 can also be referred to as the light-emitting stage.

[0135] In the third stage t3, the potentials of the light emission control signal and the first gate drive signal are both high, while the potentials of the reset signal, the second gate drive signal, and the third gate drive signal are all low. Correspondingly, the second data write transistor T2 is turned on, and the first data write transistor T1, the compensation transistor T3, the first light emission control transistor T5, the second light emission control transistor T6, the first reset transistor T7, and the second reset transistor T8 are all turned off. Furthermore, under the storage effect of the storage capacitor Cst, the drive transistor T4 remains on. The data signal provided by the data signal terminal Data can be transmitted to the first node N1 via the turned-on second data write transistor T2. This third stage t3 can also be referred to as the data write stage in the holding frame. And, the second stage t2 is executed after the third stage t3.

[0136] Referring to the above descriptions of each stage, it can be further determined that in the refresh frame, the data signal terminal Data is connected to the first node N1 via the first data write transistor T1 coupled to the first gate signal terminal Gate_P, and data signals are transmitted to the first node N1 through the first data write transistor T1. In the hold frame, the data signal terminal Data switches to being connected to the first node N1 via the second data write transistor T2 coupled to the second gate signal terminal Gate_P1, and data signals are transmitted to the first node N1 through the second data write transistor T2. Furthermore, in the first stage t1 to the second stage t2 of the refresh frame, the potential of the third gate drive signal jumps from a high potential to a low potential, and thus, under the coupling effect of the second parasitic capacitance C2, the potential of the second node N2 is pulled low. In the third stage t3 to the second stage t2 of the hold frame, the potential of the second gate drive signal jumps from a low potential to a high potential, and thus, under the coupling effect of the first parasitic capacitance C1, the potential of the second node N2 is pulled high. Therefore, the potential of the second node N2 remains stable. The embodiments disclosed herein utilize a low refresh rate mode to refresh frames to hold frames and switch different data signal input transistors (i.e., switch different data write transistors) to reduce the data range and save power consumption.

[0137] It should be noted that, from Figure 9 It can also be seen that in the first stage t1, the duration of the third gate drive signal being at a high potential (i.e., the effective potential) is longer than the duration of the first gate drive signal being at a low potential (i.e., the effective potential). The duration of the third gate drive signal being at the effective potential determines the refresh rate; the longer the duration, the higher the refresh rate.

[0138] In summary, this disclosure provides a driving method for a pixel circuit. In this method, during the first and second stages of the refresh frame, the potential of the third gate driving signal provided by the third gate signal terminal jumps from a first potential to a second potential. Consequently, under the parasitic capacitance coupling between the third gate signal terminal and the second node, the potential of the second node is driven to undergo a first shift. During the third and second stages of the hold frame, the potential of the second gate driving signal provided by the second gate signal terminal jumps from a second potential to a first potential. Consequently, under the parasitic capacitance coupling between the second gate signal terminal and the second node, the potential of the second node is driven to undergo a first shift. Since the first shift occurs when the first potential jumps to the second potential, and the second shift occurs when the second potential jumps to the first potential, the potential of the second node can be kept stable. Furthermore, this ensures that the brightness of the light-emitting element is the same when the pixel circuit drives the light-emitting element in different frames, resulting in a better display effect for the display device.

[0139] Figure 10This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 10 As shown, the display device includes: a display panel 10, a display driving circuit 20, and a plurality of pixels P1 located on the display panel 10, wherein each pixel P1 may include: a light-emitting element L1, and as shown in the figure. Figures 1 to 6 Any of the pixel circuits shown is 00.

[0140] The display driving circuit 20 can be coupled to each signal terminal of the pixel circuit 00. The display driving circuit 20 is used to provide signals to each signal terminal.

[0141] The pixel circuit 00 can be coupled to the light-emitting element L1. The pixel circuit 00 can be used to transmit a light-emitting drive signal to the light-emitting element L1, and the light-emitting element L1 can emit light based on the light-emitting drive signal.

[0142] Optionally, the display driving circuit 20 may include a gate driving circuit and a source driving circuit. The gate driving circuit may be coupled to the gate signal terminal and used to provide a gate driving signal to the gate signal terminal. The source driving circuit may be coupled to the data signal terminal and used to provide a data signal to the data signal terminal.

[0143] Optionally, the display device can be any product or component with display function, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, or a monitor.

[0144] The terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0145] For example, the terms “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0146] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0147] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0148] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0149] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0150] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the gate drive circuit, shift register unit, various circuits and sub-circuits described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here.

[0151] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A pixel circuit, the pixel circuit comprising: A data writing circuit is coupled to a first gate signal terminal, a second gate signal terminal, a third gate signal terminal, a data signal terminal, a first node, a second node, and a third node, respectively. The data writing circuit is used to control the on / off state of the data signal terminal and the first node, and to control the on / off state of the second node and the third node, in response to a first gate drive signal provided by the first gate signal terminal, a second gate drive signal provided by the second gate signal terminal, and a third gate drive signal provided by the third gate signal terminal. A first parasitic capacitance is formed between the second gate signal terminal and the second node to control the potential of the second node to shift with the potential jump of the second gate drive signal. A second parasitic capacitance is formed between the third gate signal terminal and the second node to control the potential of the second node to shift with the potential jump of the third gate drive signal. A light-emitting control circuit is coupled to a light-emitting control terminal, a first power supply terminal, a first node, a third node, and a light-emitting element, respectively. The light-emitting control circuit is used to control the on / off state of the first power supply terminal and the first node in response to the light-emitting control signal provided by the light-emitting control terminal, and to control the on / off state of the third node and the light-emitting element. A driving circuit, wherein the input terminal, control terminal and output terminal of the driving circuit are respectively coupled to the first node, the second node and the third node, and the driving circuit is used to transmit a light-emitting driving signal to the third node based on the potential of the first node and the potential of the second node; The transistor coupled to the second gate signal terminal and the transistor coupled to the third gate signal terminal are different types of transistors; Furthermore, in the refresh frame, the potential of the third gate drive signal undergoes a jump from a first potential to a second potential, and in the hold frame, the potential of the second gate drive signal undergoes a jump from a second potential to a first potential, so as to control the potential of the second node to shift in opposite directions in the refresh frame and the hold frame through the first parasitic capacitance and the second parasitic capacitance.

2. The pixel circuit according to claim 1, wherein, The data writing circuit includes: a data writing sub-circuit and a compensation sub-circuit; The data writing sub-circuit is coupled to the first gate signal terminal, the second gate signal terminal, the data signal terminal and the first node respectively. The data writing sub-circuit is used to control the connection and disconnection of the data signal terminal and the first node in response to the first gate drive signal and the second gate drive signal. The compensation sub-circuit is coupled to the third gate signal terminal, the second node and the third node respectively. The compensation sub-circuit is used to control the on / off state of the second node and the third node in response to the third gate drive signal.

3. The pixel circuit according to claim 2, wherein, The data writing sub-circuit includes: a first data writing unit and a second data writing unit; The first data writing unit is coupled to the first gate signal terminal, the data signal terminal and the first node respectively. The first data writing unit is used to control the connection and disconnection between the data signal terminal and the first node in response to the first gate drive signal. The second data writing unit is coupled to the second gate signal terminal, the data signal terminal and the first node respectively. The second data writing unit is used to control the connection and disconnection of the data signal terminal and the first node in response to the second gate drive signal.

4. The pixel circuit according to claim 3, wherein, The first data writing unit includes a first data writing transistor; the second data writing unit includes a second data writing transistor. The gate of the first data writing transistor is coupled to the first gate signal terminal, the first electrode of the first data writing transistor is coupled to the data signal terminal, and the second electrode of the first data writing transistor is coupled to the first node. The gate of the second data writing transistor is coupled to the second gate signal terminal, the first terminal of the second data writing transistor is coupled to the data signal terminal, and the second terminal of the second data writing transistor is coupled to the first node.

5. The pixel circuit according to claim 4, wherein, Both the first data write transistor and the second data write transistor are P-type transistors.

6. The pixel circuit according to any one of claims 2 to 5, wherein, The compensation sub-circuit includes: a compensation transistor; The gate of the compensation transistor is coupled to the third gate signal terminal, the first terminal of the compensation transistor is coupled to the third node, and the second terminal of the compensation transistor is coupled to the second node.

7. The pixel circuit according to claim 6, wherein, The compensation transistor is an N-type transistor.

8. The pixel circuit according to any one of claims 1 to 5, wherein, The driving circuit includes a driving transistor, and the driving transistor is a P-type transistor; The gate of the driving transistor is coupled to the second node, the first electrode of the driving transistor is coupled to the first node, and the second electrode of the driving transistor is coupled to the third node.

9. The pixel circuit according to any one of claims 1 to 5, wherein, The light-emitting control circuit includes: a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and an adjustment sub-circuit; The first light-emitting control sub-circuit is coupled to the light-emitting control terminal, the first power supply terminal, and the first node respectively. The first light-emitting control sub-circuit is used to control the on / off state of the first power supply terminal and the first node in response to the light-emitting control signal. The second light-emitting control sub-circuit is coupled to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively. The second electrode of the light-emitting element is coupled to the second power supply terminal. The second light-emitting control sub-circuit is used to control the on / off state of the third node and the first electrode of the light-emitting element in response to the light-emitting control signal. The regulating sub-circuit is coupled to the second node and the first power supply terminal respectively, and the regulating sub-circuit is used to adjust the potential of the second node based on the first power supply signal provided by the first power supply terminal.

10. The pixel circuit according to claim 9, wherein, The first light-emitting control sub-circuit includes: a first light-emitting control transistor; the second light-emitting control sub-circuit includes: a second light-emitting control transistor; and both the first light-emitting control transistor and the second light-emitting control transistor are N-type transistors; the adjustment sub-circuit includes: a storage capacitor; The gate of the first light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the first light-emitting control transistor is coupled to the first power supply terminal, and the second electrode of the first light-emitting control transistor is coupled to the first node. The gate of the second light-emitting control transistor is coupled to the light-emitting control terminal, the first electrode of the second light-emitting control transistor is coupled to the third node, and the second electrode of the second light-emitting control transistor is coupled to the first electrode of the light-emitting element; One end of the storage capacitor is coupled to the first power supply terminal, and the other end of the storage capacitor is coupled to the second node.

11. The pixel circuit according to any one of claims 1 to 5, wherein, The pixel circuit further includes: a first reset circuit and a second reset circuit; The first reset circuit is coupled to the reset signal terminal, the first reset power supply terminal and the second node respectively. The first reset circuit is used to control the on / off state of the first reset power supply terminal and the second node in response to the reset signal provided by the reset signal terminal. The second reset circuit is coupled to the first gate signal terminal, the second reset power supply terminal and the light-emitting element respectively. The second reset circuit is used to control the on / off state of the second reset power supply terminal and the light-emitting element in response to the first gate drive signal.

12. The pixel circuit according to claim 11, wherein, The first reset circuit includes a first reset transistor; the second reset circuit includes a second reset transistor; and the first reset transistor is an N-type transistor, and the second reset transistor is a P-type transistor. The gate of the first reset transistor is coupled to the reset signal terminal, the first terminal of the first reset transistor is coupled to the first reset power supply terminal, and the second terminal of the first reset transistor is coupled to the second node. The gate of the second reset transistor is coupled to the first gate signal terminal, the first terminal of the second reset transistor is coupled to the second reset power supply terminal, and the second terminal of the second reset transistor is coupled to the light-emitting element.

13. A method for driving a pixel circuit, used to drive the pixel circuit as described in any one of claims 1 to 12, the method comprising: The first and second phases are executed sequentially in the refresh frames during multi-frame scanning, and the third and second phases are executed sequentially in the hold frames during the multi-frame scanning; In the first stage, the potential of the light emission control signal provided by the light emission control terminal, the potential of the second gate drive signal provided by the second gate signal terminal, and the potential of the third gate drive signal provided by the third gate signal terminal are all the first potential, and the potential of the first gate drive signal provided by the first gate signal terminal is the second potential. The data writing circuit responds to the first gate drive signal, controls the data signal terminal to be connected with the first node, and responds to the third gate drive signal, controls the second node to be connected with the third node. In the second stage, the potentials of the first gate driving signal and the second gate driving signal are both first potentials, and the potentials of the light emission control signal and the third gate driving signal are both second potentials. The light emission control circuit responds to the light emission control signal by controlling the first power supply terminal to be connected to the first node and controlling the third node to be connected to the light emission element. The driving circuit transmits the light emission driving signal to the third node based on the potentials of the first node and the second node. In the third stage, the potential of the light emission control signal and the potential of the first gate drive signal are both the first potential, and the potential of the second gate drive signal and the potential of the third gate drive signal are both the second potential. The data writing circuit responds to the second gate drive signal and controls the data signal terminal to be connected to the first node.

14. The method according to claim 13, wherein, The method further includes: a fourth phase executed before the first phase in the refresh frame; In the fourth stage, the potential of the reset signal provided by the reset signal terminal, the potential of the light emission control signal, the potential of the first gate drive signal and the potential of the second gate drive signal are all the first potential, the potential of the third gate drive signal is the second potential, and the first reset circuit responds to the reset signal to control the first reset power supply terminal to be connected to the second node. Furthermore, in the first stage, the second reset circuit responds to the first gate drive signal and controls the second reset power supply terminal to be connected to the light-emitting element.

15. A display device, the display device comprising: A display panel, a display driving circuit, and a plurality of pixels located on the display panel, the pixels comprising: a light-emitting element, and a pixel circuit as described in any one of claims 1 to 12; The display driving circuit is coupled to each signal terminal of the pixel circuit, and the display driving circuit is used to provide signals to each signal terminal. The pixel circuit is coupled to the light-emitting element, and the pixel circuit is used to transmit a light-emitting driving signal to the light-emitting element, and the light-emitting element is used to emit light based on the light-emitting driving signal.

Images