Gate driving circuit, display panel and display device

Abstract

The application discloses a gate driving circuit, a display panel and a display device. The gate driving circuit comprises a plurality of shift registers connected in cascade, and the shift registers are electrically connected with a clock signal end. The shift register comprises: a first transistor, a first electrode of the first transistor being electrically connected with a first voltage source, and a second electrode of the first transistor being electrically connected with an output end; a second transistor, a first electrode of the second transistor being electrically connected with a first signal end, and a gate electrode of the second transistor and a second electrode of the second transistor being electrically connected with a gate electrode of the first transistor; wherein the absolute value of the voltage of the first signal end is less than the absolute value of the on level of the clock signal end. According to the embodiment of the application, the service life of the display product can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] Gate drive circuits can be used in display products, such as automotive displays.

[0003] Vehicle display products have high requirements for service life, and how to improve the service life of display products is an important technical problem faced by those skilled in the art. Summary of the Invention

[0004] This application provides a gate driving circuit, a display panel, and a display device, which helps to improve the service life of display products.

[0005] In a first aspect, embodiments of this application provide a gate driving circuit, including a plurality of cascaded shift registers, the shift registers being electrically connected to a clock signal terminal, and the shift registers including: a first transistor, the first electrode of the first transistor being electrically connected to a first voltage source, and the second electrode of the first transistor being electrically connected to an output terminal; a second transistor, the first electrode of the second transistor being electrically connected to a first signal terminal, and the gate of the second transistor and the second electrode of the second transistor being electrically connected to the gate of the first transistor; wherein, the absolute value of the voltage at the first signal terminal is less than the absolute value of the conduction level at the clock signal terminal.

[0006] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display panel including the gate driving circuit as described in the first aspect embodiment.

[0007] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display device, including a display panel as described in the second aspect embodiment.

[0008] According to the gate driving circuit, display panel, and display device provided in the embodiments of this application, by setting a second transistor, the first electrode of the second transistor is electrically connected to the first signal terminal, the gate of the second transistor and its second electrode are electrically connected to the gate of the first transistor, and the absolute value of the voltage at the first signal terminal is less than the absolute value of the conduction level at the clock signal terminal, the absolute value of the conduction level received by the gate of the first transistor is less than the absolute value of the voltage at the first signal terminal, and thus less than the absolute value of the conduction level at the clock signal terminal. This reduces the amplitude of the gate voltage of the first transistor, reduces the bias stress on the gate of the first transistor, and slows down the aging rate of the first transistor, thereby helping to extend the working life of the gate driving circuit. Attached Figure Description

[0009] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0010] Figure 1a This illustration shows a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0011] Figure 1b This illustration shows another structural schematic diagram of the gate driving circuit provided in an embodiment of this application;

[0012] Figure 2 This diagram illustrates a connection of some transistors in the shift register of the gate drive circuit provided in an embodiment of this application.

[0013] Figure 3 This illustration shows a schematic diagram of a shift register in a gate drive circuit provided in an embodiment of this application;

[0014] Figure 4 This illustration shows another structural diagram of the shift register in the gate drive circuit provided in an embodiment of this application;

[0015] Figure 5 This is a timing diagram showing a first signal terminal connected to the gate drive circuit provided in an embodiment of the present application.

[0016] Figure 6 This illustration shows another timing diagram of the first signal terminal connected to the gate drive circuit provided in an embodiment of this application;

[0017] Figure 7 This illustration shows yet another timing diagram of the first signal terminal connected to the gate drive circuit provided in the embodiments of this application;

[0018] Figure 8 Show Figure 3 A timing diagram of the circuit structure shown;

[0019] Figure 9 Show Figure 4 A timing diagram of the circuit structure shown;

[0020] Figure 10 This illustration shows another structural diagram of the shift register in the gate drive circuit provided in an embodiment of this application;

[0021] Figure 11 This illustration shows another structural diagram of the shift register in the gate drive circuit provided in an embodiment of this application;

[0022] Figure 12This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0023] Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0024] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0025] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0026] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0027] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0028] It should be noted that when a component is described as "connected" or "electrically connected" to another component, it can be directly connected to the other component, or there may be one or more intermediate components in between.

[0029] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0030] This application provides a gate driving circuit, a display panel, and a display device. The following will describe in detail the various embodiments of the gate driving circuit, display panel, and display device provided in this application with reference to the accompanying drawings.

[0031] As shown in Figure 1, the gate drive circuit 100 provided in this embodiment includes multiple cascaded shift registers 10. The shift registers 10 are connected to a clock signal terminal. The clock signal terminal provides alternating high and low levels, where the high level is a positive level and the low level is a negative level. One of the high and low levels serves as the on-state, and the other as the off-state. For example, for an N-type transistor, the high level is the on-state, and the low level is the off-state. As another example, for a P-type transistor, the low level is the on-state, and the high level is the off-state.

[0032] In some examples, such as Figure 1a As shown, the clock signal terminals may include a first clock signal terminal CKB and a second clock signal terminal CK, and the shift register 10 is connected to the first clock signal terminal CKB and the second clock signal terminal CK. In other examples, such as Figure 1b As shown, the clock signal terminal may only include the first clock signal terminal CKB, and the shift register 10 is only connected to the first clock signal terminal CKB.

[0033] For example, at the same time, the signals provided by the first clock signal terminal CKB and the second clock signal terminal CK can be inverse signals to each other.

[0034] like Figure 2 As shown, the shift register 10 may include a first transistor T1 and a second transistor T2.

[0035] The first terminal of the first transistor T1 is electrically connected to the first voltage source VGL, and the second terminal of the first transistor T1 is electrically connected to the output terminal OUT.

[0036] The first terminal of the second transistor T2 is electrically connected to the first signal terminal DC1, and the gate of the second transistor T2 and the second terminal of the second transistor T2 are electrically connected to the gate of the first transistor T1.

[0037] Among them, the absolute value of the voltage of the first signal terminal DC1 is less than the absolute value of the conduction level of the clock signal terminal.

[0038] The transistors in the shift register 10 may malfunction after prolonged operation. The inventors have discovered that the causes of malfunction include the fact that the gates of at least some of the transistors in the shift register are under the control of a high amplitude conduction level for a long time. The bias stress on the gate of the transistor is large, which causes the transistor to generate a large threshold voltage shift (Vthshift), thereby accelerating the aging speed of the transistor and affecting the working life of the gate drive circuit.

[0039] In this embodiment, by setting a second transistor T2, the first electrode of the second transistor T2 is electrically connected to the first signal terminal DC1, and the gate of the second transistor T2 and its second electrode are electrically connected to the gate of the first transistor T1. Furthermore, the absolute value of the voltage at the first signal terminal DC1 is less than the absolute value of the conduction level at the clock signal terminal. In this way, the absolute value of the conduction level received by the gate of the first transistor T1 is less than the absolute value of the voltage at the first signal terminal DC1, and thus less than the absolute value of the conduction level at the clock signal terminal. This reduces the amplitude of the gate voltage of the first transistor T1, reduces the bias stress on the gate of the first transistor T1, and slows down the aging rate of the first transistor T1, thereby extending the working life of the gate drive circuit.

[0040] Understandably, the first transistor T1 serves as an output transistor of the shift register 10. The state of the first transistor T1 affects the output signal of the shift register 10, therefore the first transistor T1 is a key transistor in the shift register.

[0041] In some embodiments, such as Figure 3 As shown, shift register 10 may also include a third transistor T3 and a fourth transistor T4.

[0042] The first electrode of the third transistor T3 is electrically connected to the first voltage source VGL, and the second electrode of the third transistor T3 is electrically connected to the output terminal OUT.

[0043] The first terminal of the fourth transistor T4 is electrically connected to the second signal terminal DC2, and the gate of the fourth transistor T4 and the second terminal of the fourth transistor T4 are electrically connected to the gate of the third transistor T3.

[0044] Among them, the absolute value of the voltage at the second signal terminal DC2 is less than the absolute value of the conduction level at the clock signal terminal.

[0045] Similarly, in this embodiment, by setting a fourth transistor T4, the first electrode of the fourth transistor T4 is electrically connected to the second signal terminal DC2, and the gate of the fourth transistor T4 and its second electrode are electrically connected to the gate of the third transistor T3, and the absolute value of the voltage at the second signal terminal DC2 is less than the absolute value of the conduction level at the clock signal terminal, the absolute value of the conduction level received by the gate of the third transistor T3 is less than the absolute value of the voltage at the second signal terminal DC2, and thus less than the absolute value of the conduction level at the clock signal terminal. This reduces the amplitude of the gate voltage of the third transistor T3, reduces the bias stress on the gate of the third transistor T3, and slows down the aging rate of the third transistor T3, thereby helping to extend the working life of the gate drive circuit.

[0046] Understandably, the third transistor T3 serves as an output transistor of shift register 10. The state of the third transistor T3 affects the output signal of shift register 10, thus making it a key transistor in the shift register.

[0047] For example, the first transistor T1 and the third transistor T3 are of the same type, and the signals of the first signal terminal DC1 and the second signal terminal DC2 can be the same. For example, the first signal terminal DC1 and the second signal terminal DC2 are the same signal terminal.

[0048] For example, the first transistor T1 and the third transistor T3 are N-type transistors, and the bias stress on the gates of the first transistor T1 and the third transistor T3 can be called positive bias stress (PBTS). The voltages of the first signal terminal DC1 and the second signal terminal DC2 are positive voltages.

[0049] In some embodiments, please refer to Figure 3 The shift register 10 may also include a first capacitor C1, the first terminal of the first capacitor C1 being electrically connected to the first clock signal terminal CKB, and the second terminal of the first capacitor C1 being electrically connected to the gate of the first transistor T1.

[0050] Understandably, the second terminal of the first capacitor C1 is also electrically connected to the gate of the second transistor T2 and the second terminal of the second transistor T2.

[0051] In this embodiment, the first capacitor C1 can be used as a protection device to couple the gate signal of the first transistor T1 and to ensure that the absolute value of the gate voltage of the first transistor T1 is reduced to less than the absolute value of the voltage of the first signal terminal DC1.

[0052] In some embodiments, please refer to Figure 3The shift register 10 may also include a second capacitor C2, the first terminal of which is electrically connected to the second clock signal terminal CK, and the second terminal of which is electrically connected to the gate of the third transistor T3.

[0053] Understandably, the second terminal of the second capacitor C2 is also electrically connected to the gate of the fourth transistor T4 and the second terminal of the fourth transistor T4.

[0054] Similarly, in this embodiment, the second capacitor C2 can be used as a protection device to couple the gate signal of the third transistor T3 and to ensure that the absolute value of the gate voltage of the third transistor T3 is reduced to less than the absolute value of the voltage of the second signal terminal DC2.

[0055] In other embodiments, such as Figure 4 As shown, the shift register 10 may further include a third transistor T3. The first electrode of the third transistor T3 is electrically connected to the first voltage source VGL, and the second electrode of the third transistor T3 is electrically connected to the output terminal OUT. The gate of the third transistor T3 in the nth stage shift register 10 is used to receive the signal Gn+1 output from the output terminal of the (n+1)th stage shift register 10.

[0056] For example, the gate of the third transistor T3 in the nth stage shift register 10 can be electrically connected to the output terminal of the (n+1)th stage shift register 10, or the gate of the third transistor T3 in the nth stage shift register 10 can be electrically connected to the cascade terminal of the (n+1)th stage shift register 10. The output terminal and the cascade terminal of the shift register 10 can be different ports, or the output terminal of the shift register 10 can be multiplexed as the cascade terminal.

[0057] In the gate drive circuit, multiple shift registers 10 are cascaded, and the first shift register 10 to the last shift register 10 outputs the conduction level sequentially. For example, the time period from the start of the first shift register 10 outputting the conduction level to the end of the last shift register 10 outputting the conduction level is called one scan cycle of the gate drive circuit. The duration of the conduction level output by each shift register 10 is relatively short compared to the duration of this scan cycle.

[0058] In this embodiment, the gate of the third transistor T3 of the nth stage receives the signal Gn+1 output from the output terminal of the shift register 10 of the (n+1)th stage. In this way, the bias voltage duration of the gate of the third transistor T3 can be greatly reduced, which can reduce the aging speed of the third transistor T3 and thus help to extend the working life of the gate drive circuit.

[0059] Understandably, Figure 4 and Figure 3The similarities include: a second transistor T2 is provided to limit the gate voltage of the first transistor T1, such that the absolute value of the gate voltage of the first transistor T1 does not exceed the absolute value of the voltage of the first signal terminal DC1.

[0060] Figure 4 and Figure 3 The differences include: Figure 3 A fourth transistor T4 is provided to limit the gate voltage of the third transistor T3, ensuring that the absolute value of the gate voltage of the third transistor T3 does not exceed the absolute value of the voltage at the second signal terminal DC2. In other words, Figure 3 The illustrated embodiment extends the lifespan by reducing the magnitude of the voltage applied to the gate of the third transistor T3. Figure 4 The gate of the third transistor T3 of the nth stage receives the signal Gn+1 output from the output terminal of the shift register 10 of the n+1th stage, thereby extending its lifespan by reducing the bias voltage duration on the gate of the third transistor T3.

[0061] The inventors discovered that if the shift register 10 includes transistors of different types, these transistors can complement each other, and the threshold voltage offset problem will not be too significant. However, if the shift register 10 contains only one type of transistor, the threshold voltage offset will be more severe.

[0062] In some embodiments, the transistors in shift register 10 may be of the same type. For example, all transistors in shift register 10 may be N-type transistors. Alternatively, all transistors in shift register 10 may be P-type transistors.

[0063] However, although the shift register 10 can include different types of transistors to complement each other and thus alleviate the threshold voltage offset problem of the output transistor, in actual production, it would require more and more complex manufacturing steps to manufacture different types of transistors. Therefore, in order to obtain a higher yield and reduce production costs, the same type of transistor is usually used to manufacture the shift register.

[0064] In some embodiments, such as Figures 5 to 7 As shown in any of the accompanying figures, the operating period of the shift register includes a first period, during which the absolute value of the voltage at the first signal terminal DC1 increases over time. For example, this increasing trend may include a step-like increase, a linear increase, a curve-like increase, etc.

[0065] In the above embodiments, the transistor's lifespan is extended by reducing the bias stress on the transistor's gate or reducing the gate offset time. However, this cannot completely eliminate the threshold voltage drift of the transistor. As time increases, the transistor's threshold voltage continues to drift, and the drift becomes increasingly larger. In this embodiment, by increasing the absolute value of the voltage at the first signal terminal DC1 over time, the first transistor T1 is ensured to remain conducting under the control of the second transistor T2 and the first signal terminal DC1, thus maintaining normal operation of the first transistor T1 over time.

[0066] In some embodiments, such as Figures 5 to 7 As shown in any of the attached figures, during the first time period, the voltage of the second signal terminal DC2 may also show an increasing trend as time increases.

[0067] For example, the voltage change trends of the second signal terminal DC2 and the first signal terminal DC1 can be the same.

[0068] As an example, the output signal of the shift register has a refresh frequency of F1, and the first time period includes multiple first refresh frames f1, the duration of which is equal to 1 / F1.

[0069] like Figure 5 As shown, the minimum absolute value of the voltage of the first signal terminal DC1 in the i-th first refresh frame f1(i) is less than or equal to the maximum absolute value of the voltage of the first signal terminal DC1 in the j-th first refresh frame f1(j), where i is less than j.

[0070] For example, such as Figure 5 As shown, the i-th first refresh frame f1(i) is adjacent to the j-th first refresh frame f1(j). That is to say, with each subsequent first refresh frame, the absolute value of the voltage of the first signal terminal DC1 increases.

[0071] Or, such as Figure 6 As shown, the i-th first refresh frame f1(i) and the j-th first refresh frame f1(j) are not adjacent, thus there is at least one first refresh frame between the i-th first refresh frame f1(i) and the j-th first refresh frame f1(j). For example, as Figure 6 The voltage of the first signal terminal DC1 within the first refresh frame between the i-th first refresh frame f1(i) and the j-th first refresh frame f1(j) can be the same as the voltage of the first signal terminal DC1 within the i-th first refresh frame f1(i). Alternatively, the voltage of the first signal terminal DC1 within the first refresh frame between the i-th first refresh frame and the j-th first refresh frame can be the same as the voltage of the first signal terminal DC1 within the j-th first refresh frame.

[0072] For example, within the same first refresh frame f1, the voltage of the first signal terminal DC1 remains unchanged. Typically, the refresh rate of the refresh frame is relatively fast, meaning the duration of the first refresh frame is relatively short. Within the same first refresh frame f1, it is relatively easy to control the voltage of the first signal terminal DC1 to remain constant.

[0073] Understandably, Figure 5 , Figure 6 The example shown illustrates that the absolute value of the voltage at the first signal terminal DC1 increases in a stepwise manner.

[0074] It should be noted that, Figure 5 In this context, f1(i-1) represents the (i-1)th first refresh frame, and f1(n) represents the nth first refresh frame. Figure 6 In this context, f1(i+1) represents the (i+1)th first refresh frame, and f1(n) represents the nth first refresh frame.

[0075] As an example, the output signal of the shift register has a refresh frequency of F2, and the first time period includes a second refresh frame f2, the duration of which is equal to 1 / F2.

[0076] like Figure 7 As shown, the minimum absolute value of the voltage of the first signal terminal DC1 is the same in different first time periods, and / or the maximum absolute value of the voltage of the first signal terminal DC1 is the same in different first time periods.

[0077] In other words, within the same second refresh frame f2, the absolute value of the voltage at the first signal terminal DC1 can show an increasing trend.

[0078] In some application scenarios, the threshold voltage of the first transistor T1 may drift significantly in a short period of time, or the duration of the second refresh frame may be relatively long. Therefore, within the same second refresh frame f2, the absolute value of the voltage of the first signal terminal DC1 may increase, which can more flexibly reduce the change in the threshold voltage of the first transistor T1 within a refresh frame.

[0079] In some embodiments, the absolute value of the voltage at the first signal terminal DC1 is greater than 0, and the voltage at the first signal terminal DC1 is less than the difference between Vgh and Vth0, wherein Vgh is the absolute value of the conduction level at the clock signal terminal, and Vth0 is the maximum value of the absolute value of the corresponding threshold voltage among the plurality of transistors in the shift register, the plurality of transistors including the first transistor T1 and the transistor electrically connected to the gate of the first transistor T1.

[0080] In this embodiment, the voltage of the first signal terminal DC1 is less than the difference between Vgh and Vth0, which ensures that there is a voltage difference between the gate voltage and the source voltage of the first transistor T1, thereby ensuring that the first transistor T1 can be turned off normally when it needs to be turned off.

[0081] For example, such as Figure 3 or Figure 4 As shown, the transistors electrically connected to the gate of the first transistor T1 include the seventh transistor T7, the eighth transistor T8, and the second transistor T2, and Vth0 is the maximum absolute value of the corresponding threshold voltage among the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the second transistor T2.

[0082] In some embodiments, such as Figure 3 or Figure 4 As shown, the shift register 10 may also include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0083] The gate of the fifth transistor T5 is used to receive the trigger signal Gn-1, the first terminal of the fifth transistor T5 is used to receive the first scan direction signal DIR1, and the second terminal of the fifth transistor T5 is electrically connected to the bootstrap node PU. Except for the last stage shift register, the signal output from the output terminal of the previous stage shift register serves as the trigger signal for the next stage shift register. For example, the signal output from the output terminal of the (n-1)th stage shift register serves as the trigger signal Gn-1 for the nth stage shift register.

[0084] The gate of the sixth transistor T6 in the nth stage shift register is used to receive the signal Gn+1 output from the output terminal of the (n+1)th stage shift register. The first terminal of the sixth transistor T6 is used to receive the second scan direction signal DIR2. The second terminal of the sixth transistor T6 is electrically connected to the bootstrap node PU.

[0085] For example, the first scan direction signal DIR1 and the second scan direction signal DIR2 can be used to indicate different scan sequences. For instance, the first scan direction signal DIR1 is used to indicate a forward scan sequence, and the second scan direction signal DIR2 is used to indicate a reverse scan sequence. During the operation of the gate drive circuit, one of the first scan direction signal DIR1 and the second scan direction signal DIR2 is at an on level, and the other is at an off level.

[0086] The gate of the seventh transistor T7 is electrically connected to the first node PD, the first electrode of the seventh transistor T7 is electrically connected to the first voltage source VGL, and the second electrode of the seventh transistor T7 is electrically connected to the bootstrap node PU. The first node PD is electrically connected to the gate of the first transistor T1.

[0087] The gate of the eighth transistor T8 is electrically connected to the bootstrap node PU, the first electrode of the eighth transistor T8 is electrically connected to the first voltage source VGL, and the second electrode of the eighth transistor T8 is electrically connected to the first node PD.

[0088] The gate of the ninth transistor T9 is electrically connected to the bootstrap node PU, the first terminal of the ninth transistor T9 is electrically connected to the first clock signal terminal CKB, and the second terminal of the ninth transistor T9 is electrically connected to the output terminal OUT.

[0089] In some embodiments, such as Figure 3 or Figure 4 As shown, the shift register 10 may also include a third capacitor C3, the first terminal of the third capacitor C3 is electrically connected to the output terminal OUT, and the second terminal of the third capacitor C3 is electrically connected to the bootstrap node PU.

[0090] Figure 8 for Figure 3 A timing diagram of the circuit structure shown. Figure 9 for Figure 4 A timing diagram of the circuit structure shown.

[0091] The following is based on Figure 3 and Figure 4 Taking the example of N-type transistors in the circuit structure shown, the working process of the shift register is introduced.

[0092] Reference Figure 3 and Figure 8 The operation of the shift register can include stages t11 to t15.

[0093] The states of each transistor from stage t11 to stage t15 are shown in Table 1. In Table 1, “√” indicates that the transistor is turned on and “×” indicates that the transistor is turned off.

[0094] Table 1

[0095]

[0096] The shift register repeats stages t14 and t15 after stage t15.

[0097] like Figure 3 As shown, the shift register 10 includes a second transistor T2. The first electrode of the second transistor T2 is electrically connected to the first signal terminal DC1, and the gate of the second transistor T2 and its second electrode are electrically connected to the gate of the first transistor T1. Figure 8 In the circuit structure shown, all transistors are N-type transistors. The voltage of the first signal terminal DC1 is a positive voltage. The second transistor T2 can limit the gate voltage of the first transistor T1 to be less than the voltage of the first signal terminal DC1. The conduction level of the clock signal terminals (CKB, CK) is high (Vgh). The voltage of the first signal terminal DC1 is less than the high level. The gate voltage of the first transistor T1 does not exceed the voltage of the first signal terminal DC1, and the gate voltage of the first transistor T1 is less than the high level (Vgh).

[0098] Similarly, shift register 10 includes a fourth transistor T4. The first electrode of the fourth transistor T4 is electrically connected to the second signal terminal DC2, and the gate of the fourth transistor T4 and its second electrode are electrically connected to the gate of the third transistor T3. Figure 8 In the circuit structure shown, all transistors are N-type transistors. The voltage of the second signal terminal DC2 is a positive voltage. The fourth transistor T4 can limit the gate voltage of the third transistor T3 to be less than the voltage of the second signal terminal DC2. The conduction level of the clock signal terminals (CKB, CK) is high (Vgh). The voltage of the second signal terminal DC2 is less than the high level. The gate voltage of the third transistor T3 does not exceed the voltage of the second signal terminal DC2, and the gate voltage of the third transistor T3 is less than the high level (Vgh).

[0099] Reference Figure 4 and Figure 9 The operation of the shift register can include stages t21 to t25.

[0100] The states of each transistor from stage t21 to stage t25 are shown in Table 2. In Table 2, “√” indicates that the transistor is turned on and “×” indicates that the transistor is turned off.

[0101] Table 2

[0102]

[0103] The shift register repeats stages t24 and t25 after stage t25.

[0104] like Figure 4 As shown, the shift register 10 includes a second transistor T2. The first electrode of the second transistor T2 is electrically connected to the first signal terminal DC1, and the gate of the second transistor T2 and its second electrode are electrically connected to the gate of the first transistor T1. Figure 8 In the circuit structure shown, all transistors are N-type transistors. The voltage of the first signal terminal DC1 is a positive voltage. The second transistor T2 can limit the gate voltage of the first transistor T1 to be less than the voltage of the first signal terminal DC1. The conduction level of the clock signal terminals (CKB, CK) is high (Vgh). The voltage of the first signal terminal DC1 is less than the high level. The gate voltage of the first transistor T1 does not exceed the voltage of the first signal terminal DC1, and the gate voltage of the first transistor T1 is less than the high level (Vgh).

[0105] Figure 4 and Figure 3 The differences in the structure shown include that the gate of the third transistor T3 in the nth stage shift register receives the signal Gn+1 output from the output of the (n+1)th stage shift register. Figure 9 and Figure 8The difference includes the timing of the gate signal of the third transistor T3. Within one scan cycle, the gate of the third transistor T3 is high at stage t23 and low at other stages. This reduces the bias time of the third transistor and extends its lifespan.

[0106] In some embodiments, such as Figure 10 or Figure 11 As shown, shift register 10 may also include a tenth transistor T10 and an eleventh transistor T11.

[0107] The gate of the tenth transistor T10 is used to receive the reset signal Reset. The first terminal of the tenth transistor T10 is electrically connected to the first voltage source VGL, and the second terminal of the tenth transistor T10 is electrically connected to the output terminal OUT.

[0108] The gate of the eleventh transistor T11 is used to receive the reset signal Reset. The first terminal of the eleventh transistor T11 is electrically connected to the first voltage source VGL, and the second terminal of the eleventh transistor T11 is electrically connected to the bootstrap node PU.

[0109] In this embodiment, by configuring the tenth transistor T10 and the eleventh transistor T11, a reset of the gate drive circuit can be initiated according to reset requirements. For example, if the gate drive circuit is applied to a display panel, at the start of a frame on the display panel, the reset signal Reset can be used to control the conduction of the tenth transistor T10 and the eleventh transistor T11 to reset the gate drive circuit. Specifically, after the tenth transistor T10 and the eleventh transistor T11 are turned on, the bootstrap node PU and the output terminal OUT can be reset.

[0110] For example, when all transistors in the gate drive circuit are N-type transistors, the signal at the first power supply terminal VGL can be low.

[0111] It should be noted that for N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa; no distinction is made here. Additionally, the on-level and off-level in this embodiment are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0112] Based on the same inventive concept, embodiments of this application also provide a display panel. For example... Figure 12 As shown, the display panel 200 may include the gate driving circuit 100 provided in any of the above embodiments.

[0113] For example, the display panel 200 includes a display area AA and a non-display area NA, and the gate driving circuit 100 may be disposed in the non-display area NA. Of course, in other examples, the display panel 200 may be a frameless display panel, and the gate driving circuit may be disposed in the display area of ​​the display panel.

[0114] For example, it could be a liquid crystal display panel or an organic light-emitting diode (OLED) display panel.

[0115] Those skilled in the art should understand that in other implementations of this application, the display panel may also be a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0116] The display panel provided in this application embodiment has the beneficial effects of the gate driving circuit provided in this application embodiment. For details, please refer to the specific description of the gate driving circuit in the above embodiments. This embodiment will not repeat the description here.

[0117] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 13 , Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 13 The provided display device 1000 includes the display panel 200 provided in any of the above embodiments of this application. Figure 13This embodiment uses an in-vehicle display device as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and mobile phones; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0118] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A gate drive circuit characterized by comprising: The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise: a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; wherein, an absolute value of a voltage of the first signal end is less than an absolute value of a conduction level of the clock signal end; the shift register further comprises: a third transistor, a first electrode of the third transistor is electrically connected with the first voltage source, and a second electrode of the third transistor is electrically connected with the output end; a fourth transistor, a first electrode of the fourth transistor is electrically connected with a second signal end, a gate electrode of the fourth transistor and a second electrode of the fourth transistor are electrically connected with a gate electrode of the third transistor; wherein, an absolute value of a voltage of the second signal end is less than an absolute value of the conduction level of the clock signal end.

2. A gate drive circuit characterized by comprising: The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise: a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; wherein, an absolute value of a voltage of the first signal end is less than an absolute value of a conduction level of the clock signal end; the shift register further comprises:

3. The gate drive circuit according to claim 1 or 2, characterized in that, a third transistor, a first electrode of the third transistor is electrically connected with the first voltage source, and a second electrode of the third transistor is electrically connected with the output end; a fourth transistor, a first electrode of the fourth transistor is electrically connected with a second signal end, a gate electrode of the fourth transistor and a second electrode of the fourth transistor are electrically connected with a gate electrode of the third transistor; 4. The gate drive circuit according to claim 1, characterized by wherein, an absolute value of a voltage of the second signal end is less than an absolute value of the conduction level of the clock signal end. The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise:

5. The gate drive circuit according to claim 1 or 2, characterized by a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; 6. The gate drive circuit according to claim 1 or 2, characterized by a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; 7. The gate drive circuit according to claim 6, characterized in that wherein, an absolute value of a voltage of the first signal end is less than an absolute value of a conduction level of the clock signal end; the shift register further comprises:

8. The gate drive circuit according to claim 7, characterized by a third transistor, a first electrode of the third transistor is electrically connected with the first voltage source, and a second electrode of the third transistor is electrically connected with the output end; a fourth transistor, a first electrode of the fourth transistor is electrically connected with a second signal end, a gate electrode of the fourth transistor and a second electrode of the fourth transistor are electrically connected with a gate electrode of the third transistor; wherein, an absolute value of a voltage of the second signal end is less than an absolute value of the conduction level of the clock signal end. The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise: a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; wherein, an absolute value of a voltage of the first signal end is less than an absolute value of a conduction level of the clock signal end; the shift register further comprises: a third transistor, a first electrode of the third transistor is electrically connected with the first voltage source, and a second electrode of the third transistor is electrically connected with the output end; a fourth transistor, a first electrode of the fourth transistor is electrically connected with a second signal end, a gate electrode of the fourth transistor and a second electrode of the fourth transistor are electrically connected with a gate electrode of the third transistor; wherein, an absolute value of a voltage of the second signal end is less than an absolute value of the conduction level of the clock signal end. The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise: a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; wherein, an absolute value of a voltage of the first signal end is less than an absolute value of a conduction level of the clock signal end; the shift register further comprises: a third transistor, a first electrode of the third transistor is electrically connected with the first voltage source, and a second electrode of the third transistor is electrically connected with the output end; a fourth transistor, a first electrode of the fourth transistor is electrically connected with a second signal end, a gate electrode of the fourth transistor and a second electrode of the fourth transistor are electrically connected with a gate electrode of the third transistor; wherein, an absolute value of a voltage of the second signal end is less than an absolute value of the conduction level of the clock signal end. The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise: a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; wherein, an absolute value of a voltage of the first signal end is less than an absolute value of a conduction level of the clock signal end; the shift register further comprises: a third transistor, a first electrode of the third transistor is electrically connected with the first voltage source, and a second electrode of the third transistor is electrically connected with the output end; a fourth transistor, a first electrode of the fourth transistor is electrically connected with a second signal end, a gate electrode of the fourth transistor and a second electrode of the fourth transistor are electrically connected with a gate electrode of the third transistor; wherein, an absolute value of a voltage of the second signal end is less than an absolute value of the conduction level of the clock signal end. The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise: a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; wherein, an absolute value of a voltage of the first signal end is less than an absolute value of a conduction level of the clock signal end; the shift register further comprises: a third transistor, a first electrode of the third transistor is electrically connected with the first voltage source, and a second electrode of the third transistor is electrically connected with the output end; a fourth transistor, a first electrode of the fourth transistor is electrically connected with a second signal end, a gate electrode of the fourth transistor and a second electrode of the fourth transistor are electrically connected with a gate electrode of the third transistor; wherein, an absolute value of a voltage of the second signal end is less than an absolute value of the conduction level of the clock signal end. The shift register comprises a plurality of shift registers connected in cascade, the shift registers are electrically connected with a clock signal end, and the shift registers comprise: a first transistor, a first electrode of the first transistor is electrically connected with a first voltage source, and a second electrode of the first transistor is electrically connected with an output end; a second transistor, a first electrode of the second transistor is electrically connected with a first signal end, a gate electrode of the second transistor and a second electrode of the second transistor are electrically connected with a gate electrode of the first transistor; wherein, an absolute value of a voltage of the 9. The gate drive circuit according to claim 6, characterized by The signal outputted by the output terminal of the shift register has a refresh frequency of F2, and the first time period comprises a second refresh frame, and a time length of the second refresh frame is equal to 1 / F2. The minimum absolute value of the voltage of the first signal terminal in different first time periods is the same, and / or the maximum absolute value of the voltage of the first signal terminal in different first time periods is the same.

10. The gate drive circuit according to claim 1 or 2, characterized by The absolute value of the voltage of the first signal terminal is greater than 0, and the voltage of the first signal terminal is less than a difference between Vgh and Vth0, wherein Vgh is an absolute value of a turn-on level of the clock signal terminal, and Vth0 is a maximum value of absolute values of threshold voltages of a plurality of transistors in the shift register, and the plurality of transistors comprise the first transistor and a transistor electrically connected to the gate of the first transistor.

11. The gate drive circuit according to claim 1 or 2, characterized by The shift register further comprises: a fifth transistor, a gate of the fifth transistor is configured to receive a trigger signal, a first pole of the fifth transistor is configured to receive a first scanning direction signal, and a second pole of the fifth transistor is electrically connected to a bootstrap node; a sixth transistor, a gate of the sixth transistor in the n-th stage of the shift register is configured to receive a signal outputted by an output terminal of an (n+1)-th stage of the shift register, a first pole of the sixth transistor is configured to receive a second scanning direction signal, and a second pole of the sixth transistor is electrically connected to the bootstrap node; a seventh transistor, a gate of the seventh transistor is electrically connected to a first node, a first pole of the seventh transistor is electrically connected to the first voltage source, and a second pole of the seventh transistor is electrically connected to the bootstrap node, wherein the first node is electrically connected to the gate of the first transistor; an eighth transistor, a gate of the eighth transistor is electrically connected to the bootstrap node, a first pole of the eighth transistor is electrically connected to the first voltage source, and a second pole of the eighth transistor is electrically connected to the first node; a ninth transistor, a gate of the ninth transistor is electrically connected to the bootstrap node, a first pole of the ninth transistor is electrically connected to a first clock signal terminal, and a second pole of the ninth transistor is electrically connected to the output terminal; a third capacitor, a first pole of the third capacitor is electrically connected to the output terminal, and a second pole of the third capacitor is electrically connected to the bootstrap node.

12. The gate drive circuit according to claim 11, characterized by The shift register further comprises: a tenth transistor, a gate of the tenth transistor is configured to receive a reset signal, a first pole of the tenth transistor is electrically connected to the first voltage source, and a second pole of the tenth transistor is electrically connected to the output terminal; an eleventh transistor, a gate of the eleventh transistor is configured to receive the reset signal, a first pole of the eleventh transistor is electrically connected to the first voltage source, and a second pole of the eleventh transistor is electrically connected to the bootstrap node.

13. A display panel, characterized by The gate driving circuit according to any one of claims 1 to 12.

14. A display device comprising: The display panel according to claim 13.

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