A fast load response dc-dc boost converter and power management system

Abstract

This invention discloses a fast load-response DC-DC boost converter and a power management system. The DC-DC boost converter includes a DC input voltage source V. IN Switches S1 through S5, inductor L, output capacitor C O Output current source I O and flying capacitor C F The invention includes a control subsystem, a drive subsystem, and the DC-DC boost converter. The control subsystem includes voltage divider resistors, a Type-II compensation network based on an error amplifier, a clock and ramp generation circuit, a comparator, an RS latch, dead time, and drive logic circuitry. The drive subsystem includes a switch driver. This invention features fast load response, a wide voltage conversion ratio, and high efficiency.

Description

Technical Field

[0001] This invention relates to DC-DC boost converters, and more particularly to a DC-DC boost converter with fast load response and a power management system. Background Technology

[0002] In the design of power management chips for mobile devices (such as IoT, LED drivers, and PA envelope tracking), the industry has placed higher demands on the performance of DC-DC boost converters. In particular, in applications requiring rapid load response, when the output load current changes rapidly, the boost converter needs to minimize its response time to allow the output voltage to quickly return to a steady state. Secondly, high efficiency is a fundamental requirement for a power management chip; improved efficiency means longer chip lifespan and higher energy conversion efficiency. The voltage conversion ratio determines the applicability of the boost converter; if the theoretical limit of a boost converter's voltage conversion ratio is too low, its application range is limited. In the current market, boost converters using lithium batteries as input voltage (2.7-4.2V) often have output voltages higher than 5-6V, thus requiring a boost converter that can provide a relatively wide range of voltage conversion ratios.

[0003] Conventional boost converter topologies, such as Figure 1 As shown, the boost voltage is achieved by switching between two operating modes (Φ1 and Φ2). The main drawback of this topology is that, from a time-domain perspective, when a transient load response occurs, i.e., the load current I... O The sudden increase in current consumes the output capacitor C. O The charge on it, therefore the output voltage V O This will generate a transient voltage drop. Because the inductor needs to be charged, causing the inductor current to rise, for the boost converter to return to steady state, conventional converters require more time to remain at Φ1, while the output capacitor C... O Providing current to the output load separately at Φ1 will cause the output voltage V to... O It decreases further, and then as the inductor current gradually recovers to its steady-state value, V O It gradually returns to a steady state. Therefore, the transient response of a traditional boost converter is very slow, and the resulting voltage drop is also large. From the frequency domain perspective, in the traditional small-signal model, there exists a right-half-plane zero, such as... Figure 1As shown, this causes the gain to increase at a rate of 20 dB / Dec while the phase decreases at a rate of -45 degrees / Dec. This property significantly limits the system's bandwidth and poses challenges to the design of frequency compensation networks.

[0004] Figure 2 A topology called a dual-path step-up converter (DPUC) is demonstrated. It can shift the right-half-plane zero to a higher frequency to achieve higher bandwidth and reduce the average inductor current to lower conduction losses. However, DPUC only increases bandwidth by shifting the right-half-plane zero to a higher frequency; it does not completely eliminate the negative impact, because the expansion of system bandwidth is still limited as long as the right zero exists. Another drawback of DPUC is that it reduces the voltage conversion ratio. If the duty cycle corresponding to Φ1 is D and the duty cycle corresponding to Φ2 is 1-D, then the voltage conversion ratio of DPUC is... The voltage conversion ratio is always less than that of traditional types. In addition, the DPUC topology requires two voltage withstand terminals with voltage ratings of V. O and (2V) O -V IN ) high pressure pipe ( Figure 2 The high-voltage transistor has larger parasitic capacitance and on-resistance (S2 and S1), which reduces efficiency. Therefore, DPUC shows a disadvantage in terms of switching voltage withstand capability.

[0005] like Figure 2 The 1-Plus-D boost converter shown can also eliminate right-half-plane zeros. However, a drawback of the 1-Plus-D structure is that its theoretical maximum voltage conversion ratio cannot exceed 2. Considering actual capacitor hard-charging losses, its voltage boost capability is further reduced. Therefore, although the 1-Plus-D offers better dynamic performance than traditional converters and DPUCs, its application range is very limited.

[0006] In addition, there are other topologies that can move or even eliminate the zeros in the right half-plane, but these require more than one inductor and flying capacitor, as well as more switching transistors. This would significantly increase costs, increase system size (especially since inductors would greatly increase the size of off-chip systems), and reduce efficiency, making them unsuitable for chip designs in mobile devices. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a fast load response DC-DC boost converter and power management system with a single inductor and a single flying capacitor, while also featuring a wide range of voltage conversion ratios and high efficiency.

[0008] The objective of this invention is achieved through the following technical solution: a DC-DC boost converter with fast load response, characterized in that it includes a DC input voltage source V. IN Switches S1 through S5, inductor L, output capacitor C O Output current source I O and flying capacitor C F ;

[0009] The DC input voltage source V IN The positive terminals are connected to the first terminals of the first switch S1 and the third switch S3, respectively, and the DC input voltage source V IN The negative terminal is grounded; the second terminal of the first switch S1 is connected to the flying capacitor C. F The second terminal of the third switch S3 is connected to the first terminal of the inductor L, and the second terminal of the inductor L is connected to the load current source I. O The first terminal, load current source I O The second terminal is connected to the DC input voltage source V IN The negative terminal of the first switch is connected; the first terminal of the second switch S2 is connected to the first terminal of the inductor L, and the second terminal of the second switch S2 is connected to the flying capacitor C. F The first end;

[0010] The first terminal of the fourth switch S4 is connected to the load current source I. O The first terminal and the second terminal of the fourth switch S4 are connected to the flying capacitor C. F The first terminal of the fifth switch S5 is connected to the flying capacitor C. F The second terminal of the fifth switch S5 is grounded, and the output capacitor C O One end is connected to the load current source I O The first end is connected, and the other end is connected to the load current source I. O The second end is connected; the load current source I O The voltage between the first and second terminals is used as the output voltage V of the boost converter. O .

[0011] In the power stage of the boost converter of this invention, the inductor L and the flying capacitor C are... F and output capacitor C O These are off-chip devices; switches S1 to S5 are implemented using on-chip insulated-gate field-effect transistors (MOSFETs). Switches S1 to S2 are implemented using P-type MOSFETs, while switches S3 to S5 are implemented using N-type MOSFETs.

[0012] The power management system of the present invention includes a control subsystem, a drive subsystem, and the DC-DC boost converter;

[0013] The control subsystem includes voltage divider resistors, a type-II compensation network based on an error amplifier, a clock and ramp generation circuit, a comparator, an RS latch, a dead-time protection module, and a drive logic circuit module; the drive subsystem includes a switch driver module.

[0014] Considering that the control system needs to be connected to V DD The operating voltage is such that the drive subsystem also includes a level converter module. This level converter module uses a traditional level converter to convert the controller's voltage range from 0 to V. DD Transfer to the power stage voltage domain 0-V IN Between these points, the controller's power supply voltage is V. DD This is used to power the error amplifier, comparator, and logic circuitry inside the controller. Because V DD Generally, no current needs to be supplied to high-power devices; it only powers the controller, whose average current is less than 2mA. Therefore, a reference potential can be directly obtained from the power management system. In testing, this chip selected V... DD =5V, provided by an off-chip voltage source. The control and drive subsystems of the boost converter of this invention are also implemented entirely on-chip.

[0015] The first feedback voltage divider resistor R F1 One end is connected to the output current source I O The first terminal is connected to the first feedback voltage divider resistor R. F1 The other end is connected to the second feedback voltage divider resistor R. F2 Grounded; the inverting input of the error amplifier is connected to the first feedback voltage divider resistor R. F1 Second feedback voltage divider resistor R F2 Between; the non-inverting input of the error amplifier is used to input the reference voltage V. REF The equivalent output resistance of the error amplifier is r. O ,r O This is equivalent to connecting a resistor, with a value in the hundreds of kiloohms range, to ground at the output of the error amplifier. And the output V of the error amplifier... EA With R C and C C The series branches are connected to form a type-II compensation network. V EA After being compared with the RAMP signal generated by the ramp generation circuit, a square wave signal V is formed. C V CThe clock signal (CLK) input to the Reset terminal (R port) of the RS latch is transmitted to the Set port (S port) of the RS latch module. The non-inverting output terminal (Q port) of the RS latch module is used to output a square wave signal Q with a duty cycle of D and transmit it to the dead time and drive logic circuit. The inverting output port (Q' port) of the RS latch module is left floating.

[0016] After signal processing, the square wave signal carries the drive level information and dead time protection information of each switch transistor into the control switch driver module. In the embodiments of this application, the dead time protection module generates a dead time of sufficient duration. Considering that the actual turn-on and turn-off of the MOSFET power switch requires a certain response time, a sufficiently long dead time period is set to ensure that at the instant of switching between two operating modes, the power switch group of the previous mode is completely turned off before the power switch group of the next mode is turned on, avoiding the generation of short-circuit current. This invention uses a digital logic delay unit to set the dead time to ensure sufficient switching delay.

[0017] The driving logic circuit module, placed before the level converter and switch driver module, is used to set the correspondence between the square wave signal Q with a duty cycle of D and the power switch groups of two operating modes: when Q=1, the switch driver module is controlled to turn on the first mode switch group; when Q=0, the switch driver module is controlled to turn on the second mode switch group. The driving logic circuit module of this invention is implemented using a digital logic unit integrated inside the chip, or it can be implemented using an FPGA or other logic circuits.

[0018] The switch driver module is used to control the closing or closing of the switches, thereby achieving a steady-state switching between two operating modes. In the switch driver module, switches S1 and S5 use classic inverter chain drivers, while S3 and S4 use classic voltage bootstrap drivers. The gate of switch S2 can be directly connected to V... O Automatic opening and closing can be achieved without the need for special drivers, thus reducing the complexity of the drive circuit.

[0019] The control subsystem of the power management system is implemented using voltage-mode PWM control. Before the start of each cycle, CLK sets the Set pin of the RS latch to 1 for a period of time (approximately 10-20 ns), which causes Q to be set to 1 and RAMP to drop back to V. RAMP The lowest point, after RAMP rebounded to above V EA Previously, V CIf the value remains 0 and the Reset terminal remains inactive, Q will remain in the 1 state. After processing by the gating and drive logic, switches S1 and S2 will be turned on while switches S3, S4, and S5 will be turned off, and the power stage will enter the Φ1 state. Then, when RAMP rises back to a value higher than V... EA After that, V C The value becomes 1, making the Reset signal valid, thus forcing Q to 0. Switches S1 and S2 are open while switches S3, S4, and S5 are closed, and the power stage enters the Φ2 state; when the positive signal V of the error amplifier... REF When rising, V EA This will also increase, which will make the proportion of Q=1 within a cycle larger, thus resulting in a higher output voltage V. O .

[0020] The beneficial effects of this invention are: compared to CBC, this invention has the same theoretical voltage conversion ratio but can achieve fast load response; compared to DPUC and 1-Plus-D type boost converters, the boost converter proposed in this invention has a wider voltage conversion ratio range and a faster response speed; this invention has only one switch with a withstand voltage of V. O The withstand voltage of other switching transistors will not exceed V. IN This allows the boost converter described in this invention to use fewer high-voltage transistors. Typically, switching MOSFETs with a voltage rating exceeding 6V require high-voltage transistors, and the switching and conduction losses of high-voltage transistors are several times higher than those of low-voltage transistors (generally referring to switching MOSFETs with a voltage rating below 5V). The lower voltage rating of the switching MOSFETs allows for a high-efficiency design in this invention. Attached Figure Description

[0021] Figure 1 A schematic diagram of the principle of a boost converter with a traditional topology and a right half-plane zero;

[0022] Figure 2 Schematic diagrams of DPUC and 1-Plus-D boost converters;

[0023] Figure 3 This is a schematic diagram of the circuit structure of the present invention;

[0024] Figure 4 This is a schematic diagram of two operating modes of the boost converter of the present invention;

[0025] Figure 5 This is a schematic diagram of the overall circuit structure of the system of the present invention;

[0026] Figure 6 This is a schematic diagram of the small-signal model of the present invention;

[0027] Figure 7This is the chip test result diagram of the boost converter of the present invention operating in a steady state;

[0028] Figure 8 This is the chip test result diagram of the boost converter of the present invention experiencing load transient response;

[0029] <00> Figure 9 This is the efficiency test result curve of the boost converter chip of the present invention under different loads and voltage conversion ratios.

[0030] Figure 10 This is the micrograph of the boost converter chip of the present invention. Detailed implementation manners

[0031] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0032] The novel boost converter power management chip proposed by the present invention consists of two parts. The first part is the power stage circuit, and the second part is the controller circuit. Figure 3 The schematic diagram of the power stage structure of the boost converter of the present invention is shown. As described above, the power stage circuit of the boost converter of the present invention includes five on-chip switches S 1-5 and its driving circuit, an off-chip capacitor C F and an off-chip inductor L. Figure 4 The two operating modes Φ1 and Φ2 corresponding to the power stage are shown. Figure 5 This is the schematic diagram of the overall circuit structure of the system of the present invention. In Φ1, switches S1 and S2 are closed, and switches S3, S4, and S5 are open. The boost capacitor C F is discharged, and the inductor L is charged. The energy in the circuit is gradually concentrated and stored in the inductor L; in Φ2, switches S1 and S2 are open, and switches S3, S4, and S5 are closed. The boost capacitor C <00000 / F is charged, and the inductor L is discharged. The energy of the circuit is gradually concentrated and stored in the boost capacitor C F . Further, let the steady-state period be T, and let the average DC voltage between the positive and negative poles of the boost capacitor C F be V F , and set the duty cycle corresponding to Φ1 as D, then the duty cycle corresponding to Φ2 is 1 - D, where 0 < D < 1. According to the inductor volt-second balance principle, it can be known that for the inductor L, there is

[0033] DT(V IN + V F - V O ) + (1 - D)T(V IN - V O ) = 0. (1)

[0034] For the flying capacitor CF have

[0035] V F =V O (2)

[0036] Within the range of values ​​for D, the voltage conversion ratio achieved by this invention is M, and has

[0037]

[0038] Furthermore, based on the ideal power conservation principle, the average inductor current I of this invention can be obtained. L for:

[0039]

[0040] Therefore, under the same duty cycle, the voltage conversion ratio M and average inductor current of the present invention are the same as those of conventional boost converters, inheriting the advantage of wide-range conversion ratio, and can be applied to a wider range of applications.

[0041] In practical engineering applications, a boost converter with a flying capacitor often needs to consider its parasitic parameters. In fact, in the power stage circuit shown in this invention, C... F When a component is being charged, the parasitic resistance along the charging path of its RC branch will affect the charging current. When the RC charging time constant τ is much larger than a period T, the RC charging current can be approximated as a direct current. Let C... F The parasitic resistance on the charging path is r F ,r F This includes the on-resistance of S4 and S5, as well as the parasitic resistance of the chip package and PCB traces. In this tape-out design, r F The estimated value is approximately between 130mΩ and 150mΩ. F If the value is 20μF, then τ=r F ×C F ≈3μs>T=0.5μs, therefore C F The charging current can be simplified as (V O -V F / r F ).

[0042] Based on the above analysis, write out the three energy storage devices L, C in Φ1. F and C O The transient current or voltage equations are as follows:

[0043]

[0044]

[0045]

[0046] Similarly, in Φ2, we have

[0047]

[0048]

[0049]

[0050] Based on the volt-second balance principle of inductors and the ampere-second balance principle of capacitors, we can conclude that:

[0051]

[0052]

[0053]

[0054] Equations (11) to (13) show that r F The influence of the existence of the DC point can be ignored when D is very small, thus approximating the ideal situation. Applying the small-signal perturbation and linearization theory to equations (5) to (10), the first-order small-signal components are expressed as such as The form can be obtained within a complete cycle.

[0055]

[0056]

[0057]

[0058] By performing a Laplace transform on equations (14) to (16) and modeling the circuit, we can obtain... Figure 6 The small-signal model shown; after simplifying equations (14) to (16), the simplified form of the transfer function T(s) of the power stage circuit of the present invention is:

[0059]

[0060] Based on the transfer function, it can be concluded that the boost converter of this invention has one zero and a pair of conjugate complex poles:

[0061]

[0062]

[0063] By making the denominator of equation (18) greater than zero, the zero point can be placed in the left half-plane. In this invention, the minimum value of R is approximately 6Ω, and the value of L is 3.3μH.F The minimum value is approximately 130 mΩ, C F The value is 20μF, therefore this zero point is always in the left half-plane. By eliminating the constraint of the right half-plane zero, the boost converter of this invention can apply a classic and simple Type-II compensation scheme, thereby achieving a loop bandwidth of approximately 200kHz, equivalent to that of a traditional buck converter, while its phase margin can be designed to be around 45°-50°. The switching frequency of this invention is 2.2MHz, and the bandwidth is approximately one-tenth of the switching frequency. After the bandwidth is widened, the transient response of the system will be significantly accelerated. In contrast, because CBC and DPUC have a low-frequency right half-plane zero, their bandwidth cannot be set at one-tenth of the switching frequency.

[0064] Besides the bandwidth extension in the frequency domain, the foreseeable technical effects of this invention can be intuitively demonstrated in the time domain: when the load current I... O When it suddenly increases, the inductor current I L The increase cannot be matched instantaneously, therefore C O The charge on the inductor will rapidly dissipate, resulting in a downward overshoot voltage. At this point, the boost converter controller will allocate a larger D(Φ1) to charge the inductor, gradually increasing the inductor current I. L This increases the current to restore a steady state. For the boost converter of this invention, when its inductor is charged, the inductor current flows directly into C. O This can immediately affect C. O The lost charge is replenished, thereby reducing the downward overshoot voltage and shortening the recovery time. For boost converters like CBC and DPUC with right-half-plane zeros, the inductor charging period C... O It cannot directly obtain replenishment from the inductor current; the longer the inductor charging time, the lower C becomes. O The more charge is lost, the greater the overshoot voltage, and the slower the response speed.

[0065] Although the 1-Plus-D boost converter has similar operating characteristics to this invention, its inductor charging slope is only (2V). IN -V O ) / L, while in this invention it is V IN / L, therefore its response speed is slower than the boost converter proposed in this invention. Conversely, when the load current I O When the current suddenly decreases, the inductor current I L The instantaneous reduction is not possible, therefore C O Excess charge accumulation can occur, resulting in an upward overshoot voltage. In this case, the boost converter controller will allocate a larger 1-D (Φ2) to discharge the inductor. For the boost converter of this invention, the flying capacitor C... F At Φ2 and C OIt is a parallel relationship, therefore C F It will absorb C O The excess charge on the converter reduces the upward overshoot voltage and shortens the recovery time. Other boost converters do not possess these characteristics when dealing with transient load current drops.

[0066] exist Figure 7 The steady-state waveform of the boost converter proposed in this invention is shown. It can be seen that at V... IN When = 2.7V, V can be achieved O =6V, at which point the voltage conversion ratio is approximately 2.22. (This is in contrast to the classic battery voltage V.) IN =3.7V, V O At 6V, this invention can support I O =600mA, corresponding to a power of 3.6W. Figure 8 The instantaneous load response of the boost converter of the present invention is demonstrated. When V IN =4.2V,V O At 6V, when the load current changes rapidly from 50mA to 500mA within 150ns, the required recovery time is only 2.8μs, and the resulting downward overshoot voltage is only 115mV. Correspondingly, when the load current drops rapidly from 500mA to 50mA within 160ns, the required recovery time is only 2.7μs, and the resulting upward overshoot voltage is only 82mV. Compared with other international chip designs for eliminating right-half-plane zeros in boost converters, the technical effect achieved by this invention represents a significant improvement and is currently at a clearly leading level. Figure 9 The chip efficiency test curve is shown, with a peak efficiency of 95.1% and a maximum output power of approximately 4.8W. Figure 10 The image shows a microscopic photograph of the chip, which is approximately 2500 μm by 1500 μm in size. Key components of the chip are labeled in the image.

[0067] Compared to CBC, this invention has the same theoretical voltage conversion ratio but can achieve fast load response; compared to DPUC and 1-Plus-D type boost converter, the boost converter proposed in this invention has a wider voltage conversion ratio range and a faster response speed; for example, empirically, the optimal voltage conversion ratio of 1-Plus-D type boost converter is between 1.1 and 1.6; the optimal conversion ratio of DPUC is between 1.1 and 1.9; while the boost converter of this invention is between 1.1 and 2.2.

[0068] This invention has one and only one switching transistor with a withstand voltage of V. O The withstand voltage of other switching transistors will not exceed V. INThis allows the boost converter described in this invention to use fewer high-voltage transistors. Typically, switching MOSFETs with a voltage rating exceeding 6V require high-voltage transistors, and the switching and conduction losses of high-voltage transistors are approximately 2-4 times higher than those of low-voltage transistors (generally referring to switching MOSFETs with a voltage rating below 5V). The lower voltage rating of the switching MOSFETs allows for a high-efficiency design in this invention. For example, if the design specification is V... IN =3.7V, V O =6-8V. Generally speaking, a CBC requires two 8V high-voltage transistors, while a DPUC requires one 8V high-voltage transistor and one 12V high-voltage transistor. However, a 1-Plus-D type boost converter cannot be used (due to insufficient voltage conversion ratio). In contrast, the boost converter proposed in this invention shows its unique advantage: it only requires one 8V high-voltage transistor, which is beneficial for high-efficiency designs.

[0069] The foregoing description illustrates and describes a preferred embodiment of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept described herein through the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A DC-DC boost converter with fast load response, characterized in that: Including DC input voltage source V IN Switches S1 through S5, inductor L, output capacitor C O Output current source I O and flying capacitor C F ; The DC input voltage source V IN The positive terminals are connected to the first terminals of the first switch S1 and the third switch S3, respectively, and the DC input voltage source V IN The negative terminal is grounded; the second terminal of the first switch S1 is connected to the flying capacitor C. F The second terminal of the third switch S3 is connected to the first terminal of the inductor L, and the second terminal of the inductor L is connected to the load current source I. O The first terminal, load current source I O The second terminal is connected to the DC input voltage source V IN The negative terminal of the first switch is connected; the first terminal of the second switch S2 is connected to the first terminal of the inductor L, and the second terminal of the second switch S2 is connected to the flying capacitor C. F The first end; The first terminal of the fourth switch S4 is connected to the load current source I. O The first terminal and the second terminal of the fourth switch S4 are connected to the flying capacitor C. F The first terminal of the fifth switch S5 is connected to the flying capacitor C. F The second terminal of the fifth switch S5 is grounded, and the output capacitor C O One end is connected to the load current source I O The first end is connected, and the other end is connected to the load current source I. O The second end is connected; the load current source I O The voltage between the first and second terminals is used as the output voltage V of the boost converter. O .

2. The DC-DC boost converter with fast load response according to claim 1, characterized in that: The first switch S1 to the fifth switch S5 all use MOSFETs.

3. A DC-DC boost converter with fast load response according to claim 1, characterized in that: The first switch S1 to the second switch S2 are P-type MOSFETs, forming the first mode switch group, and the third switch S3 to the fifth switch S5 are N-type MOSFETs, forming the second mode switch group.

4. A power management system, based on the DC-DC boost converter according to any one of claims 1 to 3, characterized in that: It includes a control subsystem, a drive subsystem, and the DC-DC boost converter; The control subsystem includes voltage divider resistors, a type-II compensation network based on an error amplifier, a clock and ramp generation circuit, a comparator, an RS latch, a dead-time protection module, and a drive logic circuit module; the drive subsystem includes a switch driver module.

5. A power management system according to claim 4, characterized in that: The voltage divider resistor includes a first feedback voltage divider resistor R. F1 Second feedback voltage divider resistor R F2 The type-II compensation network includes an error amplifier and a resistor R. C and capacitor C C ; First feedback voltage divider resistor R F1 One end is connected to the output current source I O The first terminal is connected to the first feedback voltage divider resistor R. F1 The other end is connected to the second feedback voltage divider resistor R. F2 Grounded; the inverting input of the error amplifier is connected to the first feedback voltage divider resistor R. F1 Second feedback voltage divider resistor R F2 Between; the non-inverting input of the error amplifier is used to input the reference voltage V. REF The resistor R C The first terminal is connected to the output terminal of the error amplifier, and the other terminal is connected via C. C Grounding; The output of the error amplifier is connected to the inverting input of the comparator. The clock and ramp generation circuit generates a ramp signal RAMP and a clock signal CLK. The ramp signal RAMP output by the clock and ramp generation circuit is transmitted to the non-inverting input of the comparator; the clock signal CLK output by the clock and ramp generation circuit is transmitted to the S port of the RS latch module; the output of the error amplifier is the signal V. EA After being compared with the RAMP signal generated by the ramp generation circuit in the comparator, a square wave signal V is formed. C and V C The input is given to the R port of the RS latch module. The Q port of the RS latch module is used to output a square wave signal Q with a duty cycle of D and transmit it to the dead time and drive logic circuit. The Q' port of the RS latch module is left floating.

6. A power management system according to claim 4, characterized in that: The input terminal of the dead time protection module is connected to the Q port of the RS latch module, and is used to receive the D square wave signal output by the Q port of the RS latch module. When the signal D switches, the signal D is delayed before being sent to the drive logic circuit module. The drive logic circuit module is used to control the switch driver module to turn on the first mode switch group and turn off the second mode switch group when the received Q=1, that is, when the square wave signal is in a high state; and to control the switch driver module to turn on the second mode switch group and turn off the first mode switch group when the received Q=0, that is, when the square wave signal is in a low state.

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