A PCIe-based data transmission method, device and system

Abstract

The application provides a PCIe-based data transmission method, device and system. The method is executed at a device end. A plurality of ports of the device end are identified by a driver of a host end to match corresponding data buffers. The method comprises: segmenting a data packet into data packets; generating a descriptor by a descriptor generator according to the data packets; polling a channel corresponding to each port by the descriptor to detect the descriptor; transmitting the detected descriptor to be processed to a DMA controller to generate control information and send the control information to a data grabber and a data transmitter; reading the data packets from the corresponding channel by the data grabber and transmitting the data packets to the data transmitter; and transmitting the data packets to the data buffers of the host end by the data transmitter to process the data by the driver. The application can simplify the transmission process and reduce the data transmission delay.

Description

Technical Field

[0001] The present invention relates to the field of computer communication technology, and in particular to a PCIe-based data transmission method, device, and system. Background Art

[0002] As the network latency requirements for industries such as finance, securities, data centers, and 5G continue to increase, traditional network cards can no longer meet the requirements of business processing. Therefore, network cards with special optimizations for network latency are needed to accelerate the processing of industry business.

[0003] DMA (Direct Memory Access) technology allows external devices to directly access the computer's memory without the intervention of the central processing unit (CPU). It can improve the efficiency of data transmission, reduce latency, and reduce the burden on the CPU, allowing it to perform other tasks and improve the overall efficiency of the computer system.

[0004] In traditional DMA, the host generates descriptor information based on data transmission requirements and notifies the device. The device grabs the descriptor information from the specified location in the host memory. The DMA controller moves data between the host memory and the device based on the destination address, source address, and length information provided by the descriptor information.

[0005] Compared to traditional DMA, low-latency DMA reduces data transmission latency primarily through two approaches: one is to simplify or optimize the steps in the DMA transfer process, such as the host directly placing descriptors in a specified location on the device via PIO; the other is to reduce the number of data copies in memory, such as through zero-copy technology. C2H DMA requires the host to pre-populate descriptors and instruct the device on how to organize and send data to a specified location in the host's memory. Furthermore, network packets received by multiple port channels must be placed in the corresponding memory locations in this manner, which undoubtedly increases packet latency and is prone to high jitter. When traffic is high, packet loss can occur due to the inability to process network packets in a timely manner. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a PCIe-based data transmission method, device, and system to eliminate or improve one or more defects in the prior art.

[0007] One aspect of the present invention provides a PCIe-based data transmission method, which is executed on a device side. Multiple ports on the device side are identified and enabled by a host-side driver, and each port matches a data buffer pre-applied by the host side. The method includes the following steps:

[0008] Segment the data packets to be sent from each port according to preset rules to obtain data packets, and call the descriptor generator to generate descriptors according to the data packets;

[0009] Calling the descriptor arbiter to poll the channel corresponding to each port to detect and obtain the descriptor, and transmitting the detected descriptor to the DMA controller;

[0010] Calling the DMA controller to send control information to the data grabber and the data transmitter, instructing the data grabber to read the data packet from the corresponding channel and forward it to the data transmitter;

[0011] The data transmitter is called to send the data packet to the host end, and is stored in the data buffer matching the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one.

[0012] In some embodiments of the present invention, further comprising:

[0013] The data transmitter sends feedback information to the DMA controller, and transmits the feedback information to the descriptor arbitrator;

[0014] The descriptor arbiter receives the feedback information and continues to poll each channel to obtain the next descriptor.

[0015] In some embodiments of the present invention, the data packet includes a data field and a tag field; the data field includes valid data information; the tag field includes a data packet ID, a timestamp, the length of the valid data, packet statistics and hardware status information.

[0016] In some embodiments of the present invention, calling the data transmitter to send the data packet to the host end and store it in the data buffer matching the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one, further comprising:

[0017] The data transmitter sends an interrupt message to the host end, and the driver reads and aggregates the data packets in the data buffer one by one according to the interrupt message.

[0018] In some embodiments of the present invention, the host side triggers an interrupt by using a default interrupt or an interrupt aggregation method.

[0019] In some embodiments of the present invention, calling the data transmitter to send the data packet to the host end and store it in the data buffer matching the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one, further comprising:

[0020] The driver polls the data buffer to obtain the data packets, and reads and aggregates the data packets in the data buffer one by one.

[0021] In some embodiments of the present invention, calling the data transmitter to send the data packet to the host end and store it in the data buffer matching the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one, further comprising:

[0022] The data transmitter places the data packets into consecutive basic units in the data buffer in a preset order;

[0023] When the driver processes the data packets in the data buffer, it takes them out one by one in sequence and performs offset processing.

[0024] Another aspect of the present invention provides a PCIe-based data transmission device, the device comprising: a plurality of ports, a descriptor generator, a descriptor arbiter, a DMA controller, a data grabber, and a data transmitter;

[0025] The descriptor generator is used to generate a descriptor according to the data packet;

[0026] The descriptor arbiter is used for the channel corresponding to each port to detect and obtain the descriptor, and transmit the detected descriptor to the DMA controller;

[0027] The DMA controller is used to send control information to the data grabber and the data transmitter, instructing the data grabber to read the data packet from the corresponding channel and forward it to the data transmitter;

[0028] The data grabber is used to read the data packet from the corresponding channel according to the control information and transmit the data packet to the data transmitter;

[0029] The data transmitter is used to send the data packets to the host end and store them in a data buffer matching the port corresponding to the data packets, so that the driver can read and aggregate the data packets in the data buffer one by one.

[0030] Another aspect of the present invention provides a PCIe-based data transmission system, comprising a processor and a memory, wherein the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps of any of the above methods.

[0031] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program implements the steps of any of the above methods when executed by a processor.

[0032] The beneficial effects of the present invention include at least:

[0033] The present invention provides a PCIe-based data transmission method, device, and system. The method is executed on the device side. Multiple ports on the device side are identified by a host-side driver to match corresponding data buffers. On the device side, data packets are segmented into data packets. A descriptor generator is called to generate descriptors based on the data packets. A descriptor arbitration is called to poll the channels corresponding to each port to detect descriptors. The descriptors are then passed to a DMA controller to generate control information, which is then sent to a data grabber and a data transmitter. The data grabber reads the data packets from the corresponding channels and passes them to the data transmitter. The data transmitter sends the data packets to the host-side data buffer for the driver to process the data. The method of the present invention does not require the host side to generate descriptors, thus reducing the number of host-side operational steps in the DMA process, simplifying the transmission process, reducing DMA latency, and improving the overall efficiency of the system. A fair polling mechanism combining data packets and descriptors prevents large data packets or high-priority channel data from monopolizing PCIe. The operation of segmenting the entire data packet into small data packets allows the entire data packet to be transmitted in units of small data packets before it is completely received on the device side. This can achieve pipeline transmission and avoid data backlog, thereby reducing the load pressure of the PCIe bus and the entire processor system at a certain point in time and improving the utilization of the PCIe bus.

[0034] Additional advantages, objects, and features of the present invention will be set forth in part in the following description and will become apparent to those skilled in the art upon examination of the following or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained by the structures particularly pointed out in the description and drawings.

[0035] Those skilled in the art will understand that the purposes and advantages that can be achieved by the present invention are not limited to the above specific descriptions, and the above and other purposes that can be achieved by the present invention will be more clearly understood based on the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention. In the drawings:

[0037] Figure 1 The figure is a flow chart of a data transmission method based on PCIe according to an embodiment of the present invention.

[0038] Figure 2 This is a schematic structural diagram of a PCIe-based data transmission system according to another embodiment of the present invention.

[0039] Figure 3 This is a flowchart of the initialization configuration of the PCIe-based data transmission method according to another embodiment of the present invention.

[0040] Figure 4 This is a default execution flow chart of a PCIe-based data transmission method according to another embodiment of the present invention.

[0041] Figure 5 This is a flowchart of executing the PCIe-based data transmission method described in another embodiment of the present invention in an actual scenario.

[0042] Figure 6 (a) (b) are schematic diagrams of the data packet format according to another embodiment of the present invention.

[0043] Figure 7 This is an example diagram of the relationship between large data packets and small data packets according to another embodiment of the present invention.

[0044] Figure 8 This is an example diagram of a descriptor according to another embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0046] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, the accompanying drawings only show structures and / or processing steps closely related to the solutions according to the present invention, while other details that are not closely related to the present invention are omitted.

[0047] It should be emphasized that the term "include / comprises" when used herein refers to the existence of features, elements, steps or components, but does not exclude the existence or addition of one or more other features, elements, steps or components.

[0048] It should also be noted that, unless otherwise specified, the term "connection" herein may refer not only to a direct connection but also to an indirect connection involving an intermediate.

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0050] PCIe (Peripheral Component Interconnect Express) is a computer bus standard used to connect various hardware devices, such as graphics cards, network adapters, and storage devices, to a computer motherboard. PCIe offers higher data transfer rates than the traditional PCI (Peripheral Component Interconnect) bus. PCIe uses a point-to-point connection architecture, where each device connects directly to a PCIe slot on the motherboard rather than sharing a bus, which helps improve data transfer efficiency.

[0051] Direct Memory Access (DMA) is a data transfer technique in computer systems that allows external devices to directly access system memory without direct intervention from the central processing unit (CPU). The primary purpose of DMA is to increase data transfer rates and reduce the CPU's workload, freeing it to perform other tasks. In practical applications, DMA is typically managed by a dedicated hardware controller.

[0052] An aspect of an embodiment of the present invention provides a PCIe-based data transmission method, which is executed on a device side. Multiple ports on the device side are identified and enabled by a driver on the host side. Each port matches a data buffer pre-applied by the host side. The method includes the following steps S101 to S104:

[0053] Step S101: Segment the data packets to be sent from each port according to preset rules to obtain data packets, and call a descriptor generator to generate a descriptor according to the data packets.

[0054] Among them, data packets are segmented into small data packets, which can prevent large data packets from monopolizing the PCIe bus for a long time during data transmission, thereby achieving the purpose of efficient transmission.

[0055] A descriptor is an abstract data structure used to describe data attributes, location, and other information. A data packet is a logical unit of transmitted data, and a descriptor is a means of managing and controlling this data. A descriptor can contain a pointer to a data packet or metadata about the data packet. In this embodiment, the descriptor specifies the location, size, and other related information of a data packet.

[0056] Step S102: calling the descriptor arbiter to poll the channel corresponding to each port to detect and obtain descriptors, and transmitting the detected descriptors to the DMA controller.

[0057] Polling is a technique used to obtain or check information. In this embodiment, descriptors are sent to the descriptor arbiter via their respective descriptor channels as requests. The descriptor arbiter then polls each channel. If a descriptor exists on the currently polled channel, it retrieves it and performs a transfer operation. Other channels may have valid descriptors, but they cannot perform the corresponding transfer operation until the descriptor arbiter polls that channel.

[0058] Step S103: calling the DMA controller to send control information to the data grabber and the data transmitter, instructing the data grabber to read the data packet from the corresponding channel and forward it to the data transmitter.

[0059] Step S104: calling the data transmitter to send the data packet to the host end, and storing it in the data buffer matching the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one.

[0060] The host driver refers to the device driver in the computer system. It is responsible for communicating and coordinating with external devices, translating operating system requests into instructions that the hardware can understand and translating external device responses into data that the operating system can process. The driver provides an interface to the external device for the operating system, allowing applications to access device functions through standard system calls or APIs (application programming interfaces).

[0061] In some embodiments of the present invention, further comprising:

[0062] The data transmitter sends feedback information to the DMA controller, and transmits the feedback information to the descriptor arbitrator.

[0063] The descriptor arbiter receives the feedback information and continues to poll each channel to obtain the next descriptor.

[0064] In some embodiments of the present invention, a data packet includes a data field and a tag field. The data field (DATA field) includes valid data information, the actual length of which may be less than the length of the data field. The tag field (TAG field) includes the packet ID, timestamp, length of valid data, packet statistics, and hardware status information. The data field (DATA field) in a data packet is used to store the actual data content, while the tag field (TAG field) contains metadata about the data packet and other information used to implement more functions.

[0065] In some embodiments of the present invention, calling a data transmitter to send a data packet to a host end and storing the data packet in a data buffer that matches a port corresponding to the data packet, so that a driver can read and aggregate the data packets in the data buffer one by one, further comprising:

[0066] The data transmitter sends an interrupt message to the host, and the driver reads and aggregates the data packets in the data buffer one by one according to the interrupt message.

[0067] An interrupt is a hardware or software-generated signal that interrupts the normal flow of program execution, causing the processor to redirect execution to a specific interrupt service routine. Interrupts can be triggered by external devices, program errors, or other events that require the processor's attention. In this embodiment, interrupts are used by the device to communicate with the host, alerting the host to process data packets transmitted by the device.

[0068] In some embodiments of the present invention, the host side triggers an interrupt by using a default interrupt or an interrupt aggregation method.

[0069] The default interrupt refers to the interrupt triggering mode preset or default on the host side.

[0070] Interrupt aggregation combines or aggregates multiple interrupt events into a single interrupt event. Instead of processing each interrupt individually, the system can combine similar or related interrupts into one, thereby reducing interrupt frequency and processing overhead. This approach helps improve system efficiency, especially when facing a large number of interrupt events.

[0071] In some embodiments of the present invention, calling a data transmitter to send a data packet to a host end and storing the data packet in a data buffer that matches a port corresponding to the data packet, so that a driver can read and aggregate the data packets in the data buffer one by one, further comprising:

[0072] The driver polls the data buffer to obtain data packets, and reads and aggregates the data packets in the data buffer one by one.

[0073] In some embodiments of the present invention, calling a data transmitter to send a data packet to a host end and storing the data packet in a data buffer that matches a port corresponding to the data packet, so that a driver can read and aggregate the data packets in the data buffer one by one, further comprising:

[0074] The data transmitter places the data packets into consecutive basic units in the data buffer in a preset order.

[0075] When the driver processes the data packets in the data buffer, it takes them out one by one in sequence and performs offset processing.

[0076] The offset processing refers to adjusting the offset of a data packet. The offset refers to the offset of a specific portion of a data packet relative to the starting position of the entire data packet.

[0077] In some embodiments of the present invention, the length field of each data packet's corresponding descriptor is 64 bytes. The length of the valid data is recorded in the tag field (TAG field) and parsed by the driver. The source address and destination address corresponding to a descriptor and the offset of the source address and destination address corresponding to the adjacent descriptor, that is, the offset of the data packet, are all 64 bytes.

[0078] Another aspect of an embodiment of the present invention provides a PCIe-based data transmission device, which includes: multiple ports, a descriptor generator, a descriptor arbitrator, a DMA controller, a data grabber, and a data transmitter.

[0079] The descriptor generator is used to generate descriptors based on data packets.

[0080] The descriptor arbiter is used for the channel corresponding to each port to detect and obtain descriptors, and transmits the detected descriptors to the DMA controller.

[0081] The DMA controller is used to send control information to the data grabber and the data transmitter, instructing the data grabber to read data packets from the corresponding channel and forward them to the data transmitter.

[0082] The data grabber is used to read data packets from the corresponding channel according to the control information and transmit the data packets to the data transmitter.

[0083] The data transmitter is used to send data packets to the host end and store them in the data buffer that matches the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one.

[0084] Another aspect of an embodiment of the present invention provides a PCIe-based data transmission system, including a processor and a memory, wherein computer instructions are stored in the memory, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps of the method in any of the above embodiments.

[0085] Another aspect of an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0086] Another embodiment of the present invention provides a PCIe-based data transmission method, device, and system. The specific implementation scheme is as follows:

[0087] The overall structural diagram of this embodiment is as follows Figure 2As shown, the left side of the PCIe device is located within the device and includes the descriptor generator, descriptor arbiter, DMA controller, data fetcher, and transmitter. The descriptor generator is responsible for generating descriptors based on the data packets segmented from the large data packets and sending them to the descriptor arbiter. The descriptor arbiter polls each channel for descriptors and forwards them to the DMA controller. The DMA controller sends control information to the data fetcher and transmitter. The data fetcher fetches data from the corresponding channel based on the control information from the DMA controller. The transmitter sends the data packets returned by the data fetcher via PCIe to the corresponding address or queue position in the host memory based on the control information from the DMA controller.

[0088] The right side of the PCIe interface represents the host. Data buffers (queues or channels) in memory store data packets sent from the device. The correspondence between these buffers and channels within the device depends on the actual situation. Queues may correspond to specific user applications or virtual machines, and other objects may also be mapped according to specific rules. The driver is responsible for configuring the device during initialization and further processing the data packets in the buffer during actual operation based on interrupts or polling.

[0089] The implementation is divided into two major phases: the initial configuration phase and the actual execution phase.

[0090] The process of initialization phase is as follows Figure 3 As shown, the main behavior is that after the driver is loaded and the board is identified, the corresponding memory resources are allocated to the device according to the number of ports (physical or virtual) of the device.

[0091] For the actual execution phase, the default execution process after the initialization configuration is completed is as follows Figure 4 As shown in the figure, the arbiter continuously polls each channel. If it detects a descriptor to be processed, it sends the descriptor to the DMA controller. The DMA controller sends control information to the data grabber and data transmitter based on the descriptor. The data grabber reads data from the corresponding channel based on the control information and sends the returned data to the data transmitter. The data transmitter sends the data to the corresponding location in memory, then sends a completion response to the arbiter and notifies the interrupt sending logic to send an interrupt to the host. After receiving the response, the arbiter determines that the transfer is complete and checks whether there is another descriptor to be processed. After receiving the interrupt, the driver retrieves the data from the corresponding location in memory and performs further processing.

[0092] In actual application environments, the amount of data and the frequency of sending data packets are uncertain. For example, frequent interrupt processing under large amounts of data will occupy a large amount of CPU resources, thereby affecting the efficiency of data transmission. Therefore, in actual application environments, the driver can choose to configure relevant registers to inform the hardware whether to send interrupts or the frequency of sending interrupts (interrupt aggregation) according to actual needs. It can also choose pure software interrupt aggregation or polling mode on the host side to process data. The relevant execution relationship is as follows: Figure 5 As shown in the figure, the dotted paths can use default interrupt methods, interrupt aggregation, or pure software interrupt aggregation. Alternatively, the undashed paths can use driver-generated polling for data packets, or a combination of interrupts and polling. In actual applications, these methods can be combined or dynamically configured based on the specific scenario requirements.

[0093] like Figure 6 (a) shows the format of the data packet for each DMA transfer. The data packet is obtained by segmenting the complete network packet (data packet) received from Ethernet. The relationship is as follows: Figure 7 As shown in the figure. Each data packet has its own corresponding descriptor. The length field of the descriptor is 64B in size. The actual length of the valid data is recorded in the TAG and parsed by the driver. Figure 8 As shown, the source address and destination address corresponding to the descriptor and the offset of the source address and destination address corresponding to the adjacent descriptor, that is, the offset of the data packet are all 64B. The benefit of segmentation is to prevent large packets from monopolizing the PCIe bus for a long time, so that possible real-time data from other channels can be processed in a timely manner. Each frame of data packet consists of a data field (DATA field) and a tag field (TAG field), and the length of the data field (DATA field) and the tag field (TAG field) is fixed. Among them, the valid data length of the data field (DATA field) may be less than the length of the data field (DATA field). The information contained in the tag field (TAG field) includes the ID of the data packet, the length of the valid data, a flag indicating whether it is the last data packet, etc., and of course it can also carry information including but not limited to timestamps, packet statistics, hardware status, etc. As shown in FIG. Figure 6 As shown in (b), each DMAC2H sequentially places small data packets into the continuous queue unit of the data buffer using DMA. This process aggregates the small packets into large packets. The driver extracts the data packets from the buffer one by one, offsets the data within them, and then sends them as a large data packet to the corresponding application.

[0094] In the practical application of the DMAC2H solution described in the embodiments of the present invention, descriptors are generated by a descriptor generator logically adjacent to the DMAC2H within the device, reducing the latency of the descriptor stage in the DMA transfer process to single-digit nanoseconds. This, coupled with a segmented data processing approach, simplifies the logical complexity of the DMAC2H to a certain extent, thereby reducing latency throughout the entire transfer process. Furthermore, packet aggregation is achieved by sequentially placing data packets into the host buffer.

[0095] Corresponding to the above method, the present invention also provides a system, which includes a computer device, the computer device including a processor and a memory, the memory storing computer instructions, the processor being used to execute the computer instructions stored in the memory, and when the computer instructions are executed by the processor, the device / system implements the steps of the method described above.

[0096] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the aforementioned edge computing server deployment method. The computer-readable storage medium may be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the art.

[0097] In summary, the present invention provides a data transmission method, device, and system based on PCIe. The method is executed on the device side, and multiple ports on the device side are identified by a host-side driver to match corresponding data buffers. The method includes: segmenting a data packet into data packets, a descriptor generator generating descriptors based on the data packets, a descriptor arbitration polling the channel corresponding to each port to detect the descriptor, passing the descriptor to a DMA controller to generate control information and send it to a data grabber and a data transmitter, the data grabber reads the data packet from the corresponding channel and passes it to the data transmitter, and the data transmitter sends the data packet to the data buffer on the host side for the driver to process the data. The present invention can simplify the DMA transmission process and reduce data transmission latency. The operation of segmenting the entire data packet into data packets can achieve pipeline transmission, avoid data backlog, reduce the load pressure of the PCIe bus and the entire processor system, and improve the utilization rate of the PCIe bus.

[0098] It should be understood by those skilled in the art that the various exemplary components, systems and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software or a combination of the two. Whether it is specifically performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present invention are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link via a data signal carried in a carrier.

[0099] It should be understood that the present invention is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted. In the above embodiments, several specific steps are described and illustrated as examples. However, the method of the present invention is not limited to the specific steps described and illustrated. Those skilled in the art may make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present invention.

[0100] In the present invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or replace features of other embodiments.

[0101] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations to the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A data transmission method based on PCIe, characterized in that: The method is used to be executed on a device side, wherein multiple ports of the device side are identified and configured to be enabled by a driver on a host side, and each port is matched with a data buffer pre-applied by the host side. The method includes the following steps: Segment the data packets to be sent from each port according to preset rules to obtain data packets, and call a descriptor generator to generate a descriptor based on the data packets; the data packets include a data field and a tag field, the data field includes valid data information, and the tag field includes a data packet ID, a timestamp, the length of valid data, packet statistics, and hardware status information; Calling the descriptor arbiter to poll the channel corresponding to each port to detect and obtain the descriptor, and transmitting the detected descriptor to the DMA controller; Calling the DMA controller to send control information to the data grabber and the data transmitter, instructing the data grabber to read the data packet from the corresponding channel and forward it to the data transmitter; The data transmitter is called to send the data packet to the host end, and the data packet is stored in the data buffer matching the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one; the data transmitter sends feedback information to the DMA controller, and the DMA controller transmits the feedback information to the descriptor arbiter. After receiving the feedback information, the descriptor arbiter continues to poll each channel to obtain the next descriptor; the reading and aggregation method includes: The data transmitter sends an interrupt message to the host end, and the driver reads and aggregates the data packets in the data buffer one by one according to the interrupt message; Alternatively, the driver polls the data buffer to obtain the data packets, and reads and aggregates the data packets in the data buffer one by one; Alternatively, the data transmitter places the data packets into continuous basic units in the data buffer in a preset order; when the driver processes the data packets in the data buffer, it takes them out one by one in order and performs offset processing.

2. The PCIe-based data transmission method according to claim 1, wherein: The data transmitter sends interrupt information to the host end, and the host end triggers an interrupt by using a default interrupt or an interrupt aggregation method.

3. A data transmission device based on PCIe, characterized in that: The device includes: a plurality of ports, a descriptor generator, a descriptor arbitrator, a DMA controller, a data grabber and a data transmitter; The descriptor generator is used to generate a descriptor based on a data packet; the data packet includes a data field and a tag field, the data field includes valid data information, and the tag field includes a data packet ID, a timestamp, the length of valid data, packet statistics and hardware status information; The descriptor arbiter is used for the channel corresponding to each port to detect and obtain the descriptor, and transmit the detected descriptor to the DMA controller; The DMA controller is used to send control information to the data grabber and the data transmitter, instructing the data grabber to read the data packet from the corresponding channel and forward it to the data transmitter; The data grabber is used to read the data packet from the corresponding channel according to the control information and transmit the data packet to the data transmitter; The data transmitter is used to send the data packet to the host side and store it in a data buffer that matches the port corresponding to the data packet, so that the driver can read and aggregate the data packets in the data buffer one by one; the data transmitter sends feedback information to the DMA controller, and the DMA controller transmits the feedback information to the descriptor arbiter. After receiving the feedback information, the descriptor arbiter continues to poll each channel to obtain the next descriptor; the reading and aggregation method includes: the data transmitter sends an interrupt message to the host side, and the driver reads and aggregates the data packets in the data buffer one by one according to the interrupt message; or, the driver polls the data buffer to obtain the data packets, and reads and aggregates the data packets in the data buffer one by one; or, the data transmitter places the data packets in a preset order into consecutive basic units in the data buffer; when the driver processes the data packets in the data buffer, it takes them out one by one in sequence and performs offset processing.

4. A data transmission system based on PCIe, comprising a processor and a memory, characterized in that: The memory stores computer instructions, and the processor is configured to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps of the method according to any one of claims 1 to 2.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 2 are implemented.

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