Scanning circuit, display substrate and display device

Abstract

A scanning circuit having multiple stages is provided. Each stage of the scanning circuit includes a respective scanning unit configured to provide a control signal to at least one row of sub-pixels. Each scanning unit includes an input sub-circuit configured to receive a start signal or an output signal from a previous scanning unit, a first processing sub-circuit, a second processing sub-circuit, and an output sub-circuit. The output sub-circuit includes a first output transistor. The input sub-circuit includes a first input transistor and a second input transistor coupled in series between an input terminal and a first node. The first node is coupled to a gate of the first output transistor. The first processing sub-circuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a scanning circuit, a display substrate, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides a scanning circuit comprising multiple stages, wherein each stage of the scanning circuit includes a corresponding scanning unit configured to provide control signals to at least one row of sub-pixels; wherein each scanning unit includes an input sub-circuit, a first processing sub-circuit, a second processing sub-circuit, and an output sub-circuit configured to output a signal from an output terminal, the input sub-circuit being configured to receive a start signal or an output signal from a previous scanning unit of a previous stage from an input terminal; wherein the output sub-circuit includes a first output transistor; wherein the input sub-circuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node; and the first node is coupled to the gate of the first output transistor; wherein the first processing sub-circuit includes a first switching transistor and a second switching transistor coupled between the first node and a first reference terminal; and the first reference terminal is configured to receive a first reference signal.

[0004] Optionally, the gates of the first input transistor and the second input transistor are coupled to a first terminal and configured to receive a first clock signal from the first terminal; and the source of the first output transistor is coupled to a second terminal and configured to receive a second clock signal from the second terminal.

[0005] Optionally, the first processing sub-circuit further includes a first control transistor coupled between the second node and the first reference terminal; the gate of the first control transistor is coupled to the input terminal and configured to receive the start signal or the output signal from the previous scan unit of the previous stage; the source of the first control transistor is coupled to the first reference terminal and configured to receive the first reference signal; and the drain of the first control transistor is coupled to the second node, the second node being coupled to the gate of the first switching transistor and the gate of the second switching transistor.

[0006] Optionally, the second processing sub-circuit includes a second control transistor coupled between a second node and a second reference terminal; the second reference terminal is configured to receive a second reference signal; and the gate of the second control transistor is coupled to a third terminal and configured to receive a third clock signal from the third terminal.

[0007] Optionally, the first processing sub-circuit further includes a third control transistor coupled between the third node and the second reference terminal; the gate of the third control transistor is coupled to the first node; the source of the third control transistor is coupled to the second reference terminal and configured to receive a second reference signal from the second reference terminal; and the drain of the third control transistor is coupled to the drain of the first switching transistor and the source of the second switching transistor.

[0008] Optionally, the input sub-circuit further includes a fourth control transistor coupled between the fourth node and the second terminal; the second terminal is configured to receive a second clock signal; the fourth node is coupled to the drain of the first input transistor and the source of the second input transistor; the gate of the fourth control transistor is coupled to the output terminal and is configured to receive the output signal from the output terminal.

[0009] Optionally, the output sub-circuit further includes a second output transistor coupled between the first reference terminal and the output terminal; and the gate of the second output transistor is coupled to the gate of the first switching transistor and the gate of the second switching transistor.

[0010] In another aspect, this disclosure provides a display substrate including the scanning circuit, wherein a first output transistor and a second output transistor of the output sub-circuit are arranged in a first region; an input transistor, a switching transistor, and a control transistor of each scanning unit are arranged in a second region; a capacitor of each scanning unit is arranged in a third region; and the second region, the first region, and the third region are arranged sequentially.

[0011] Optionally, the display substrate further includes one or more clock signal lines arranged in the fourth region; wherein the fourth region, the second region, the first region, and the third region are arranged sequentially.

[0012] Optionally, in the second region, the first input transistor and the second input transistor are located on the side of the first switching transistor and the second switching transistor that is close to one or more clock signal lines; and the first switching transistor and the second switching transistor are located on the side of the first input transistor and the second input transistor that is close to the first output transistor and the second output transistor.

[0013] Optionally, the first input transistor, the second input transistor, the first switching transistor, and the second switching transistor are concentrated in the central region; each scanning unit further includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the first control transistor and the second control transistor are located on a first side of the central region; the third control transistor and the fourth control transistor are located on a second side of the central region; and the first side and the second side are opposite sides of the central region along the extension direction of one or more clock signal lines.

[0014] Optionally, the second control transistor is located on the side of the first control transistor close to the one or more clock signal lines, and the first control transistor is located on the side of the second control transistor close to the first output transistor and the second output transistor.

[0015] Optionally, the display substrate includes a semiconductor material layer; wherein the semiconductor material layer includes an active layer of one or more transistors of each scanning unit; the active layer of the first input transistor and the active layer of the second input transistor are part of a first integral structure in the semiconductor material layer; and at least a portion of the first integral structure has an L-shaped or I-shaped shape.

[0016] Optionally, the first overall structure also includes an active layer for the fourth control transistor.

[0017] Optionally, the display substrate includes a semiconductor material layer; wherein the semiconductor material layer includes an active layer of one or more transistors of each scanning unit; the active layer of the first switching transistor and the active layer of the second switching transistor are part of a second integral structure in the semiconductor material layer; and at least a portion of the second integral structure has an L-shaped or I-shaped shape.

[0018] Optionally, the second overall structure also includes the active layer of the first control transistor.

[0019] Optionally, the first output transistor has a first occupied area; the second output transistor has a second occupied area; the first occupied area is greater than the second occupied area; and the ratio of the first occupied area to the second occupied area is greater than or equal to 1.5:1.

[0020] Optionally, the active layer of the first output transistor has a first channel width; the active layer of the second output transistor has a second channel width; the first channel width is greater than the second channel width; and the ratio of the first channel width to the second channel width is greater than or equal to 1.5:1.

[0021] Optionally, the display substrate further includes a first reference signal line and a second reference signal line; the first reference signal line is located in the third region; the second reference signal line is located in the fourth region; and the transistors of each scanning unit are located between the first reference signal line and the second reference signal line.

[0022] In another aspect, this disclosure provides a display device including the display substrate and one or more integrated circuits connected to the display substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a schematic diagram illustrating a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0025] Figure 2 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0026] Figure 3 This is a timing diagram of each scanning unit in the operation scanning circuit according to some embodiments of the present disclosure.

[0027] Figure 4 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0028] Figure 5 This is a timing diagram of each scanning unit in the operation scanning circuit according to some embodiments of the present disclosure.

[0029] Figure 6 This is a schematic diagram illustrating the structure of a display substrate according to some embodiments of the present disclosure.

[0030] Figure 7 This is a circuit diagram of a display substrate according to some embodiments of the present disclosure.

[0031] Figure 8 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0032] Figure 9A Detailed structures in display areas of a display substrate according to some embodiments of the present disclosure are shown.

[0033] Figure 9B Detailed structures in display areas of a display substrate according to some embodiments of the present disclosure are shown.

[0034] Figure 10A The structure of the nth level scanning unit according to some embodiments of the present disclosure is shown.

[0035] Figure 10B It shows Figure 10A The structure of the semiconductor material layer in the nth level scanning unit is shown.

[0036] Figure 10C It shows Figure 10A The structure of the first conductive layer in the nth level scanning unit is shown.

[0037] Figure 10D It shows Figure 10A The structure of the second conductive layer in the nth level scanning unit shown.

[0038] Figure 10E It shows Figure 10A The structure of the interlayer dielectric layer in the nth level scanning unit is shown.

[0039] Figure 10F It shows Figure 10A The structure of the first signal line layer in the nth level scan unit shown.

[0040] Figure 11A The structure of the nth level scanning unit according to some embodiments of the present disclosure is shown.

[0041] Figure 11B It shows Figure 11A The structure of the semiconductor material layer in the nth level scanning unit is shown.

[0042] Figure 11C It shows Figure 11A The structure of the first conductive layer in the nth level scanning unit is shown.

[0043] Figure 11D It shows Figure 11A The structure of the second conductive layer in the nth level scanning unit shown.

[0044] Figure 11EIt shows Figure 11A The structure of the interlayer dielectric layer in the nth level scanning unit is shown.

[0045] Figure 11F It shows Figure 11A The structure of the first signal line layer in the nth level scan unit shown.

[0046] Figure 12A The structure of the nth level scanning unit according to some embodiments of the present disclosure is shown.

[0047] Figure 12B It shows Figure 12A The structure of the semiconductor material layer in the nth level scanning unit is shown.

[0048] Figure 12C It shows Figure 12A The structure of the first conductive layer in the nth level scanning unit is shown.

[0049] Figure 12D It shows Figure 12A The structure of the second conductive layer in the nth level scanning unit shown.

[0050] Figure 12E It shows Figure 12A The structure of the interlayer dielectric layer in the nth level scanning unit is shown.

[0051] Figure 12F It shows Figure 12A The structure of the first signal line layer in the nth level scan unit shown. Detailed Implementation

[0052] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0053] This disclosure provides, in particular, a scanning circuit, a display substrate, and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a scanning circuit comprising multiple stages. In some embodiments, each stage of the scanning circuit includes a corresponding scanning unit configured to provide control signals to at least one row of sub-pixels. Optionally, each scanning unit includes an input sub-circuit, a first processing sub-circuit, a second processing sub-circuit, and an output sub-circuit configured to output a signal from an output terminal, the input sub-circuit being configured to receive a start signal or an output signal from a previous scanning unit of the preceding stage. Optionally, the output sub-circuit includes a first output transistor. Optionally, the input sub-circuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node, and the first node is coupled to the gate of the first output transistor. Optionally, the first processing sub-circuit includes a first switching transistor and a second switching transistor coupled between the first node and a first reference terminal, and the first reference terminal is configured to receive a first reference signal.

[0054] Figure 1 This is a schematic diagram illustrating a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Reference Figure 1 In some embodiments, each scanning unit includes an input sub-circuit Isc, a first processing sub-circuit Psc1, a second processing sub-circuit Psc2, and an output sub-circuit Osc. The input sub-circuit Isc is configured to receive a start signal STV or an output signal G_(n-1) from the previous scanning unit in the preceding stage. Optionally, the input sub-circuit Isc is also configured to receive a first clock signal CLK1. Optionally, the input sub-circuit Isc is also configured to receive an output signal G_n. The input sub-circuit Isc is connected to the first processing sub-circuit Psc1.

[0055] In some embodiments, the first processing sub-circuit Psc1 is configured to receive a start signal STV or an output signal G_(n-1) from the previous scan unit of the previous stage. The first processing sub-circuit Psc1 is connected to the input sub-circuit Isc and to the second processing sub-circuit Psc2.

[0056] In some embodiments, the second processing sub-circuit Psc2 is configured to receive a second reference signal VREF2 (e.g., a constant low voltage signal). The second processing sub-circuit Psc2 is connected to the first processing sub-circuit Psc1 and to the output sub-circuit Osc.

[0057] In some embodiments, the output sub-circuit Osc is configured to receive a first reference signal VREF1 (e.g., a constant high voltage signal). The output sub-circuit Osc is connected to a second processing sub-circuit Psc2.

[0058] Figure 2 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Figure 2 A scanning unit is shown, where the transistors are p-type transistors. Various implementations of the scanning circuit can be achieved. In one example, the transistors in the scanning circuit can be p-type transistors, such as... Figure 2 As shown. In another example, the transistors in the scan circuit can be n-type transistors. In yet another example, the transistors in the scan circuit can include one or more p-type transistors and one or more n-type transistors.

[0059] refer to Figure 2 In some embodiments, the input sub-circuit Isc includes a first input transistor Ti1, a second input transistor Ti2, and a fourth control transistor Tc4. The first input transistor Ti1 is coupled between the input terminal TMi and the fourth node N4. The second input transistor Ti2 is coupled between the fourth node N4 and the first node N1. The fourth control transistor Tc4 is coupled between the fourth node N4 and the second terminal TM2. The first node N1 is coupled to the input sub-circuit Isc, the first processing sub-circuit Psc1, and the output sub-circuit Osc.

[0060] The gate of the first input transistor Ti1 is coupled to the first terminal TM1 and configured to receive the first clock signal CLK1 from the first terminal TM1. The source of the first input transistor Ti1 is coupled to the input terminal TMi and configured to receive the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage. The drain of the first input transistor Ti1 is coupled to the fourth node N4.

[0061] The gate of the second input transistor Ti2 is coupled to the first terminal TM1 and configured to receive the first clock signal CLK1 from the first terminal TM1. The source of the second input transistor Ti2 is coupled to the fourth node N4. The drain of the second input transistor Ti2 is coupled to the first node N1.

[0062] The gate of the fourth control transistor Tc4 is coupled to the output terminal TMo and configured to receive the output signal G_n from the current scan unit of the current stage. The source of the fourth control transistor Tc4 is coupled to the second terminal TM2 and configured to receive the second clock signal CLK2. The drain of the fourth control transistor Tc4 is coupled to the fourth node N4.

[0063] In some embodiments, the first processing sub-circuit Psc1 includes a first control transistor Tc1, a first switching transistor Ts1, a second switching transistor Ts2, and a third control transistor Tc3. The first control transistor Tc1 is coupled between the second node N2 and the first reference terminal TMR1. The first switching transistor Ts1 is coupled between the first reference terminal TMR1 and the third node N3. The second switching transistor Ts2 is coupled between the third node N3 and the first node N1. The third control transistor Tc3 is coupled between the third node N3 and the second reference terminal TMR2.

[0064] The gate of the first control transistor Tc1 is coupled to the input terminal TMi and is configured to receive a start signal STV or an output signal G_(n-1) from the previous scan unit of the previous stage. The source of the first control transistor Tc1 is coupled to the first reference terminal TMR1 and is configured to receive a first reference signal VREF1. The drain of the first control transistor Tc1 is coupled to the second node and is coupled to the gates of the first switching transistor Ts1 and the second switching transistor Ts2.

[0065] The gate of the first switching transistor Ts1 is coupled to the second node N2. The source of the first switching transistor Ts1 is coupled to the first reference terminal TMR1 and is configured to receive the first reference signal VREF1. The drain of the first switching transistor Ts1 is coupled to the third node N3.

[0066] The gate of the second switching transistor Ts2 is coupled to the second node N2. The source of the second switching transistor Ts2 is coupled to the third node N3. The drain of the second switching transistor Ts2 is coupled to the first node N1.

[0067] The gate of the third control transistor Tc3 is coupled to the first node N1. The source of the third control transistor Tc3 is coupled to the second reference terminal TMR2 and is configured to receive the second reference signal VREF2. The drain of the third control transistor Tc3 is coupled to the third node N3.

[0068] In some embodiments, the second processing sub-circuit Psc2 includes a second capacitor C2 and a second control transistor Tc2. The second capacitor C2 is coupled between the first reference terminal TMR1 and the second node N2. The second control transistor Tc2 is coupled between the second node N2 and the second reference terminal TMR2.

[0069] The first capacitor electrode of the second capacitor C2 is coupled to the first reference terminal TMR1 and is configured to receive the first reference signal VREF1. The second capacitor electrode of the second capacitor C2 is coupled to the second node N2.

[0070] The gate of the second control transistor Tc2 is coupled to the third terminal TM3 and configured to receive the third clock signal CLK3. The source of the second control transistor Tc2 is coupled to the second reference terminal TMR2 and configured to receive the second reference signal VREF2. The drain of the second control transistor Tc2 is coupled to the second node N2.

[0071] In some embodiments, the output sub-circuit OSc includes a first capacitor C1, a second output transistor To2, and a first output transistor To1. The first capacitor C1 is coupled between the output terminal TMo and the first node N1. The second output transistor To2 is coupled between the first reference terminal TMR1 and the output terminal TMo. The first output transistor To1 is coupled between the output terminal TMo and the second terminal TM2.

[0072] The first capacitor electrode of the first capacitor C1 is coupled to the output terminal TMo. The second capacitor electrode of the first capacitor C1 is coupled to the first node N1.

[0073] The gate of the second output transistor To2 is coupled to the second node N2. The source of the second output transistor To2 is coupled to the first reference terminal TMR1 and is configured to receive the first reference signal VREF1. The drain of the second output transistor To2 is coupled to the output terminal TMo.

[0074] The gate of the first output transistor To1 is coupled to the first node N1. The source of the first output transistor To1 is coupled to the second terminal TM2 and configured to receive the second clock signal CLK2. The drain of the first output transistor To1 is coupled to the output terminal TMo.

[0075] The gate of the first control transistor Tc1 is coupled to the source of the first input transistor Ti1. The drain of the first input transistor Ti1 is coupled to the source of the second input transistor Ti2 and also to the drain of the fourth control transistor Tc4. The source of the first control transistor Tc1 is coupled to the first capacitor electrode of the second capacitor C2 and also to the source of the second output transistor To2. The drain of the first control transistor Tc1 is coupled to the gate of the first switching transistor Ts1 and the gate of the second switching transistor Ts2.

[0076] The drain of the first switching transistor Ts1 is coupled to the source of the second switching transistor Ts2, and is also coupled to the drain of the third control transistor Tc3.

[0077] The gate of the first output transistor To1 is coupled to the second capacitor electrode of the first capacitor C1, coupled to the gate of the third control transistor Tc3, and coupled to the drain of the second switching transistor Ts2 and the drain of the second input transistor Ti2.

[0078] The source of the second control transistor Tc2 is coupled to the source of the third control transistor Tc3.

[0079] The drain of the second output transistor To2 is coupled to the drain of the first output transistor To1, and is also coupled to the first capacitor electrode of the first capacitor C1.

[0080] Figure 3 This is a timing diagram of each scanning unit in the operational scanning circuit according to some embodiments of this disclosure. (See reference...) Figure 3 In some embodiments, the individual scanning units in the image frame can be operated during the first time period P1 to the fourth time period P4.

[0081] Reference Figure 1 , Figure 2 and Figure 3 During the first time period P1, the effective voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal TMi; the effective voltage of the first clock signal CLK1 is provided to the first terminal TM1; the invalid voltage of the second clock signal CLK2 is provided to the second terminal TM2; and the invalid voltage of the third clock signal CLK3 is provided to the third terminal TM3. As used herein, the effective voltage refers to a low voltage in the case of a p-type transistor and a high voltage in the case of an n-type transistor; while the invalid voltage refers to a high voltage in the case of a p-type transistor and a low voltage in the case of an n-type transistor.

[0082] During the first time period P1, the first input transistor Ti1 and the second input transistor Ti2 are turned on by the effective voltage of the first clock signal CLK1; the first control transistor Tc1 is turned on by the effective voltage of the start signal STV from the input terminal TMi or the output signal G_(n-1) from the previous scan unit of the previous stage. When the first input transistor Ti1 and the second input transistor Ti2 are turned on, the first node N1 and the fourth node N4 are charged to the effective voltage level (e.g., low voltage level in the case of p-type transistors) by the effective voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage. The first output transistor To1 is turned on by the effective voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage, allowing the second clock signal CLK2 to be transmitted to the output terminal TMi. During the first time period P1, the second clock signal CLK2 is an invalid voltage signal (e.g., high voltage signal in the case of p-type transistors). Therefore, the output signal G_n is an invalid control signal.

[0083] During the first time period P1, the first control transistor Tc1 is turned on, thereby allowing the first reference signal VREF1 from the first reference terminal TMR1 to be transmitted to the second node N2. The first reference signal VREF1 is an invalid voltage signal (e.g., a high voltage signal in the case of a p-type transistor). Therefore, the second output transistor To2, the first switching transistor Ts1, and the second switching transistor Ts2 are turned off.

[0084] During the first time period P1, the second control transistor Tc2 is cut off by the invalid voltage of the third clock signal CLK3. The fourth control transistor Tc4 is cut off by the invalid voltage of the output signal G_n.

[0085] Reference Figure 1 , Figure 2 and Figure 3 During the second time period P2, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal TMi; the invalid voltage of the first clock signal CLK1 is provided to the first terminal TM1; the valid voltage of the second clock signal CLK2 is provided to the second terminal TM2; and the invalid voltage of the third clock signal CLK3 is provided to the third terminal TM3.

[0086] During the second time period P2, the first control transistor Tc1 is turned off by an invalid voltage from the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage. The first clock signal CLK1 is an invalid voltage signal (e.g., a high voltage signal in the case of a p-type transistor). The first input transistor Ti1 and the second input transistor Ti2 are turned off. The second control transistor Tc2 is turned off by an invalid voltage from the third clock signal CLK3. The voltage level at the second node N2 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor). The first switching transistor Ts1 and the second switching transistor Ts2 are turned off by the invalid voltage at the second node N2.

[0087] During the second time period P2, the second input transistor Ti2 and the second switching transistor Ts2 are off. The voltage level at the first node N1 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The first output transistor To1 is kept on by the effective voltage at the first node N1, thereby allowing the second clock signal CLK2 to be transmitted to the output terminal TMo. During the second time period P2, the second clock signal CLK2 is an effective voltage signal (e.g., a low voltage signal in the case of a p-type transistor). Therefore, the output signal G_n is an effective control signal.

[0088] During the second time period P2, the voltage level at the second node N2 remains at an invalid voltage level, and the second output transistor To2 remains off.

[0089] During the second time period P2, the second control transistor Tc2 is turned off by the invalid voltage of the third clock signal CLK3.

[0090] During the second time period P2, the fourth control transistor Tc4 is turned on by the effective voltage of the output signal G_n. The fourth node N4 is charged with the effective voltage of the second clock signal CLK2.

[0091] Reference Figure 1 , Figure 2 and Figure 3 During the third time period P3, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal TMi; the invalid voltage of the first clock signal CLK1 is provided to the first terminal TM1; the invalid voltage of the second clock signal CLK2 is provided to the second terminal TM2; and the valid voltage of the third clock signal CLK3 is provided to the third terminal TM3.

[0092] During the third time period P3, the first control transistor Tc1 is turned off by an invalid voltage from the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage. The first clock signal CLK1 is an invalid voltage. The first input transistor Ti1 and the second input transistor Ti2 are turned off by the invalid voltage of the first clock signal CLK1.

[0093] During the third time period P3, the third clock signal CLK3 is an effective voltage. The second control transistor Tc2 is turned on by the effective voltage of the third clock signal CLK3 provided at the third terminal TM3, thereby allowing the second reference signal VREF2 from the second reference terminal TMR2 to be transmitted to the second node N2. The second reference signal VREF2 is an effective voltage signal (e.g., a low voltage signal in the case of a p-type transistor). Therefore, the second output transistor To2, the first switching transistor Ts1, and the second switching transistor Ts2 are turned on.

[0094] During the third time period P3, the first switching transistor Ts1 and the second switching transistor Ts2 are turned on by the effective voltage at the second node N2, thereby allowing the first reference signal VREF1 from the first reference terminal TMR1 to be transmitted to the third node N3 and the first node N1. The first output transistor To1 and the third control transistor Tc3 are turned off by the ineffective voltage of the first reference signal VREF1.

[0095] During the third time period P3, the second output transistor To2 is turned on by the effective voltage at the second node N2, thereby allowing the first reference signal VREF1 from the first reference terminal TMR1 to be transmitted to the output terminal TMo. The first reference signal VREF1 is an invalid voltage signal (e.g., a high voltage signal in the case of a p-type transistor). Therefore, the output signal G_n is an invalid control signal.

[0096] During the third time period P3, the fourth control transistor Tc4 is cut off by the invalid voltage of the output signal G_n.

[0097] Reference Figure 1 , Figure 2 and Figure 3 During the fourth time period P4, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal TMi; and the invalid voltage of the third clock signal CLK3 is provided to the third terminal TM3.

[0098] In some embodiments, the fourth time period P4 includes a first stage P4-1 and a second stage P4-2. In the first stage P4-1, the effective voltage of the first clock signal CLK1 is provided to the first terminal TM1; the ineffective voltage of the second clock signal CLK2 is provided to the second terminal TM2. In the second stage P4-2, the ineffective voltage of the first clock signal CLK1 is provided to the first terminal TM1; the effective voltage of the second clock signal CLK2 is provided to the second terminal TM2.

[0099] In the first stage P4-1, the first input transistor Ti1 and the second input transistor TI2 are turned on by the effective voltage of the first clock signal CLK1, thereby allowing the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage to be transmitted to the first node N1 and the fourth node N4.

[0100] In the first stage P4-1, the first control transistor Tc1 is turned off by an invalid voltage from the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage. The second control transistor Tc2 is turned off by an invalid voltage from the third clock signal CLK3 provided to the third terminal TM3. The voltage level at the second node N2 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The second output transistor To2 is turned on by the effective voltage at the second node N2, thereby allowing an invalid voltage from the first reference signal VREF1 from the first reference terminal TMR1 to be transmitted to the output terminal TMo. The first reference signal VREF1 is an invalid voltage signal (e.g., a high voltage signal in the case of a p-type transistor). Therefore, the output signal G_n is an invalid control signal.

[0101] In the first stage P4-1, the first output transistor To1 is cut off by the invalid voltage at the first node N1.

[0102] In the first stage P4-1, the first switching transistor Ts1 and the second switching transistor Ts2 are turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 from the first reference terminal TMR1 to be transmitted to the first node N1.

[0103] In the first stage P4-1, the third control transistor Tc3 is cut off by the invalid voltage at the first node N1.

[0104] In the first stage P4-1, the fourth control transistor Tc4 is cut off by the invalid voltage of the output signal G_n.

[0105] In the second stage P4-2, the first input transistor Ti1 and the second input transistor Ti2 are cut off by the invalid voltage of the first clock signal CLK1; the first control transistor Tc1 is cut off by the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage; the second control transistor Tc2 is cut off by the invalid voltage of the third clock signal CLK3 provided to the third terminal TM3. The voltage level at the first node N1 remains an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor), while the voltage level at the second node N2 remains an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The second output transistor To2 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 from the first reference terminal TMR1 to be transmitted to the output terminal TMo. The first reference signal VREF1 is an invalid voltage signal (e.g., a high voltage signal in the case of a p-type transistor). Therefore, the output signal G_n is an invalid control signal.

[0106] In the second stage P4-2, the first output transistor To1 is cut off by the invalid voltage at the first node N1.

[0107] In the second stage P4-2, the first switching transistor Ts1 and the second switching transistor Ts2 are turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 from the first reference terminal TMR1 to be transmitted to the first node N1.

[0108] In the second stage P4-2, the third control transistor Tc3 is cut off by the invalid voltage at the first node N1.

[0109] In the second stage P4-2, the fourth control transistor Tc4 is cut off by the invalid voltage of the output signal G_n.

[0110] Figure 4This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of this disclosure. Besides... Figure 4 The transistors in each scanning unit described are all n-type transistors, while Figure 2 The transistors in each scan unit described herein are all p-type transistors. Figure 4 The scanning unit described in [the text] is otherwise similar to... Figure 2 The scanning unit described herein is the same. Except for the one used for operation... Figure 4 The effective voltage of each scanning unit depicted is a high voltage, while the voltage used for operation is... Figure 2 The effective voltage of each scanning unit depicted is a low voltage. Figure 4 The operation of each scanning unit described herein is otherwise similar to Figure 2 The operation of each scanning unit described herein is the same. Furthermore, the operation... Figure 4 The first reference signal for each scanning unit shown is a constant low voltage signal, while the signal used for operation... Figure 2 The first reference signal for each scanning unit shown is a constant high voltage signal; and the signal used for operation Figure 4 The second reference signal VREF2 of each scanning unit described herein is a constant high voltage signal, while the signal used for operation... Figure 2 The second reference signal VREF2 of each scanning unit described herein is a constant low voltage signal.

[0111] Figure 5 This is a timing diagram of each scanning unit in the operation scanning circuit according to some embodiments of the present disclosure. Figure 5 Some embodiments according to this disclosure are shown. Figure 4 The operation of each scanning unit is shown. Besides the functions used for operation... Figure 5 The effective voltage of each scanning unit shown is a high voltage, while the voltage used for operation is... Figure 3 The effective voltage of each scanning unit shown is a low voltage, in addition to the operation. Figure 5 Timing diagrams and operations of each scanning unit shown Figure 3 The timing diagrams for each scan unit shown are identical. Furthermore, the operation... Figure 5 The first reference signal for each scanning unit shown is a constant low voltage signal, while the signal used for operation... Figure 3 The first reference signal for each scanning unit shown is a constant high voltage signal; used for operation Figure 5 The second reference signal VREF2 of each scanning unit described herein is a constant high voltage signal, while the signal used for operation... Figure 3 The second reference signal VREF2 of each scanning unit described herein is a constant low voltage signal.

[0112] In this scanning circuit, each scanning unit includes multiple input transistors (e.g., a first input transistor Ti1 and a second input transistor Ti2) sequentially coupled between an input terminal TMi and a first node N1. The first node N1 is coupled to the gate of a first output transistor To1. Each scanning unit may also include multiple switching transistors (e.g., a first switching transistor Ts1 and a second switching transistor Ts2) coupled between the first node N1 and a first reference terminal TMR1. The first reference terminal TMR1 is configured to receive a first reference signal VREF1 (e.g., a constant high voltage signal in the case of a p-type transistor). By having multiple input transistors or multiple switching transistors, leakage current at node N1 (coupled to the gate of the first output transistor To1) can be prevented or significantly reduced, especially during the second time period P2 of the output active control signal G_n.

[0113] In another aspect, the present invention also provides a display substrate. Figure 6 This is a schematic diagram illustrating the structure of a display substrate according to some embodiments of the present disclosure. (Refer to...) Figure 6 In some embodiments, the display substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the display substrate in a display panel where the actual image is displayed. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas in two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the display substrate in a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display device, non-transparent or opaque components of the array device (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area instead of the display area.

[0114] Figure 7 This is a circuit diagram of a display substrate according to some embodiments of this disclosure. (Refer to...) Figure 7The display substrate includes an array of subpixels. Each subpixel includes electronic components, such as a light-emitting element. In some embodiments, the display substrate further includes multiple light-emitting elements driven by multiple pixel driving circuits. In one example, the light-emitting elements are driven by corresponding pixel driving circuits. The display substrate includes multiple gate lines GL, multiple data lines DL, and multiple power supply voltage lines Vdd. The emission of light from each subpixel Sp is driven by a corresponding pixel driving circuit PDC. In one example, a high-voltage signal is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding one of the multiple power supply voltage lines Vdd; a low-voltage signal (e.g., via a constant voltage supply line) is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0115] In some embodiments, the light-emitting substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. Optionally, each pixel of the display substrate includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The plurality of sub-pixels in the display substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, wherein S1 represents a first sub-pixel, S2 represents a second sub-pixel, S3 represents a third sub-pixel, and S4 represents a fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents a first sub-pixel of a first color, C2 represents a second sub-pixel of a second color, C3 represents a third sub-pixel of a third color, and C4 represents a fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the first sub-pixel of the first color, C2 represents the second sub-pixel of the second color, C3 represents the third sub-pixel of the third color, and C2' represents the fourth sub-pixel of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, each third sub-pixel is a blue sub-pixel, and each fourth sub-pixel is a green sub-pixel.

[0116] Various suitable pixel driving circuits can be used in this display substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. Various suitable light-emitting elements can be used in this display substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0117] Figure 8 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 8 In some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN in the current stage of a plurality of reset control signal lines, a source connected to a corresponding reset signal line Vint in the current stage of a plurality of first reset signal lines, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line in a plurality of gate lines GL, a source connected to a corresponding data line in a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first capacitor electrode Ce1 connected to the storage capacitor Cst, and the gate of the driving transistor Td. The source of the first transistor T1 and the drain of the second transistor T2 are connected to the source of the first transistor T1; the fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line in a plurality of light-emitting control signal lines em, a source connected to a corresponding voltage supply line in a plurality of voltage supply lines Vdd, and a drain connected to the source of the first transistor T1 and the drain of the second transistor T2; the fifth transistor T5 has a gate connected to a corresponding light-emitting control signal line, a source connected to the drain of the first transistor T1 and the drain of the second transistor T3, and a drain connected to the anode of the light-emitting element LE; and the sixth transistor T6 has a gate connected to a corresponding reset control signal line rst(N+1) in the next adjacent stage of a plurality of reset control signal lines, a source connected to a corresponding reset signal line Vint in the current stage of a plurality of second reset signal lines, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4.

[0118] In one example, the scanning circuit is a gate scan signal scanning circuit configured to provide light emission control signals to multiple gate lines. In another example, the scanning circuit is a light emission control signal scanning circuit configured to provide light emission control signals to multiple light emission control signal lines. In yet another example, the scanning circuit is a reset control signal scanning circuit configured to provide reset control signals to multiple reset control signal lines.

[0119] In some embodiments, the scanning circuitry is located in the peripheral area. In some embodiments, the light-emitting element and the pixel driving circuitry are located in the display area.

[0120] Various implementations of this display substrate can be practiced. Figure 9A Detailed structures in display areas of a display substrate according to some embodiments of the present disclosure are shown. (Refer to...) Figure 9AIn some embodiments, the display substrate includes a substrate BS (e.g., a flexible substrate) in the display area; an active layer ACT for a corresponding one of a plurality of thin-film transistors (TFTs) on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both part of a first conductive layer) located on the side of the gate insulating layer GI away from the substrate BS; an insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; and a second capacitor electrode Ce2 (a second conductive layer). The display substrate includes an insulating layer IN located on the side away from the gate insulating layer GI; an interlayer dielectric layer ILD located on the side away from the gate insulating layer GI; a first electrode S and a second electrode D (part of the first SD metal layer) located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a planarization layer PLN located on the side away from the interlayer dielectric layer ILD; a pixel defining layer PDL defining a sub-pixel opening and located on the side of the planarization layer PLN away from the substrate BS; and a light-emitting element LE in the sub-pixel opening. The light-emitting element LE includes an anode AD located on the side of the planarization layer PLN away from the interlayer dielectric layer ILD; a light-emitting layer EL located on the side of the anode AD away from the planarization layer PLN; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display substrate also includes an encapsulation layer EN in the display area, which encapsulates the light-emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display substrate further includes a buffer layer BUF located on the side of the encapsulation layer EN away from the substrate BS in the display area; a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF; and an outer coating OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.

[0121] Reference Figure 9AThe display substrate includes a semiconductor material layer SML, a first conductive layer Gate1, a second conductive layer Gate2, and a first signal line layer SLL1. The display substrate also includes an insulating layer IN between the first conductive layer Gate1 and the second conductive layer Gate2; and an interlayer dielectric layer ILD located between the second conductive layer Gate2 and the first signal line layer SLL1.

[0122] Figure 9B Detailed structures in display areas of a display substrate according to some embodiments of the present disclosure are shown. (Refer to...) Figure 9BIn some embodiments, the display substrate includes, in the display area, a substrate BS (e.g., a flexible substrate); an active layer ACT for a corresponding one of a plurality of thin-film transistors (TFTs) on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both part of a first conductive layer) located on the side of the gate insulating layer GI away from the substrate BS; an insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second conductive layer) located on the side of the insulating layer IN away from the gate insulating layer GI; and an interlayer dielectric layer ILD located on the side of the second capacitor electrode Ce2 away from the gate insulating layer GI. The system comprises: a first electrode S and a second electrode D (part of the first SD metal layer) located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a passivation layer PVX located on the side of the first electrode S and the second electrode D away from the interlayer dielectric layer ILD; a first planarization layer PLN1 located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; a relay electrode RE (part of the second SD metal layer) located on the side of the first planarization layer PLN1 away from the passivation layer PVX; a second planarization layer PLN2 located on the side of the relay electrode RE away from the first planarization layer PLN1; a pixel defining layer PDL defining a sub-pixel opening and located on the side of the second planarization layer PLN2 away from the substrate BS; and a light-emitting element LE in the sub-pixel opening. The light-emitting element LE includes an anode AD located on the side of the second planarization layer PLN2 away from the interlayer first planarization layer PLN1; a light-emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display substrate further includes an encapsulation layer EN in the display area, which encapsulates the light-emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display substrate also includes a buffer layer BUF located on the side of the encapsulation layer EN away from the substrate BS in the display area; a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF; and an outer coating OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.Optionally, the display substrate does not include a passivation layer PVX in the display area; for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0123] Reference Figure 9B The display substrate includes a semiconductor material layer SML, a first conductive layer Gate1, a second conductive layer Gate2, a first signal line layer SLL1, and a second signal line layer SLL2. The display substrate also includes: an insulating layer IN located between the first conductive layer Gate1 and the second conductive layer Gate2; an interlayer dielectric layer ILD located between the second conductive layer Gate2 and the first signal line layer SLL1; and at least a passivation layer PVX or a planarization layer PLN located between the first signal line layer SLL1 and the second signal line layer SLL2.

[0124] Figure 10A The structure of the nth level scanning unit according to some embodiments of the present disclosure is shown. Figure 10B It shows Figure 10A The structure of the semiconductor material layer in the nth level scanning unit is shown. Figure 10C It shows Figure 10A The structure of the first conductive layer in the nth level scanning unit is shown. Figure 10D It shows Figure 10A The structure of the second conductive layer in the nth level scanning unit shown. Figure 10E It shows Figure 10A The structure of the interlayer dielectric layer in the nth level scanning unit is shown. Figure 10F It shows Figure 10A The diagram shows the structure of the first signal line layer in the nth level scan unit. The transistors and capacitors in the nth level scan unit are located in... Figure 10A As shown in the image.

[0125] Figure 11A The structure of the nth level scanning unit according to some embodiments of the present disclosure is shown. Figure 11B It shows Figure 11A The structure of the semiconductor material layer in the nth level scanning unit is shown. Figure 11C It shows Figure 11A The structure of the first conductive layer in the nth level scanning unit is shown. Figure 11D It shows Figure 11A The structure of the second conductive layer in the nth level scanning unit shown. Figure 11E It shows Figure 11A The structure of the interlayer dielectric layer in the nth level scanning unit is shown. Figure 11F It shows Figure 11A The diagram shows the structure of the first signal line layer in the nth level scan unit. The transistors and capacitors in the nth level scan unit are located in... Figure 11A As shown in the image.

[0126] Figure 12A The structure of the nth level scanning unit according to some embodiments of the present disclosure is shown. Figure 12B It shows Figure 12A The structure of the semiconductor material layer in the nth level scanning unit is shown. Figure 12C It shows Figure 12A The structure of the first conductive layer in the nth level scanning unit is shown. Figure 12D It shows Figure 12A The structure of the second conductive layer in the nth level scanning unit shown. Figure 12E It shows Figure 12A The structure of the interlayer dielectric layer in the nth level scanning unit is shown. Figure 12F It shows Figure 12A The diagram shows the structure of the first signal line layer in the nth level scan unit. The transistors and capacitors in the nth level scan unit are located in... Figure 12A As shown in the image.

[0127] Reference Figure 10B , Figure 11B or Figure 12B Semiconductor material layer (e.g., corresponding to Figures 9A to 9B The SML in the nth scan cell includes the active layer of the transistor. The active layer of the transistor is in Figure 10B , Figure 11B or Figure 12B The annotation is in Chinese. (Refer to...) Figure 10A , Figure 11A , Figure 12A , Figure 10B , Figure 11B and Figure 12B In some embodiments, the active layer ACTi1 of the first input transistor Ti1, the active layer ACTi2 of the second input transistor Ti2, the active layer ACTc1 of the first control transistor Tc1, the active layer ACTc2 of the second control transistor Tc2, the active layer ACTc3 of the third control transistor Tc3, the active layer ACTs1 of the first switching transistor Ts1, the active layer ACTs2 of the second switching transistor Ts2, the active layer ACTo1 of the first output transistor To1, and the active layer ACTo2 of the second output transistor To2 are located on the same layer.

[0128] In one example, the first output transistor To1 is a multi-gate transistor, and the active layer ACTo1 of the first output transistor To1 comprises multiple portions spaced apart from each other, such as... Figure 10B , Figure 11B or Figure 12B As depicted in [the text]. In another example, the second output transistor To2 is a multi-gate transistor, and the active layer ACTo2 of the second output transistor To2 comprises multiple portions spaced apart from each other, as [examples would be inserted here]. Figure 10B , Figure 11B or Figure 12B As depicted in the text.

[0129] In one example, the active layers of the first input transistor Ti1 and the second input transistor Ti2 are part of the overall structure. In another example, the active layers of the first switching transistor Ts1 and the second switching transistor Ts2 are part of the overall structure. (See reference) Figure 10B In another example, the active layers of the first input transistor Ti1, the second input transistor Ti2, and the fourth control transistor Tc4 are part of the overall structure. See also Figure 11B In another example, the active layer of the first switching transistor Ts1, the active layer of the second switching transistor Ts2, and the active layer of the first control transistor Tc1 are part of the overall structure.

[0130] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, when the active layer of a transistor is formed due to one or more steps of the same patterning process performed in the same material layer, the active layer of the transistor is located in the same layer. In another example, an active layer can be formed in the same layer by simultaneously performing steps to form a first active layer and steps to form a second active layer. The term "same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view.

[0131] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer whose orthographic projection onto a substrate overlaps with the orthographic projection of a gate onto the substrate. As used herein, a first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer.

[0132] refer to Figure 10C , Figure 11C or Figure 12C In some embodiments, the first conductive layer (e.g., corresponding to) Figures 9A to 9B Gate1 in the nth scan unit includes the gate of the transistor. The gate of the transistor is... Figure 10C , Figure 11C or Figure 12C As shown in the image. (Refer to...) Figure 10A , Figure 11A , Figure 12A , Figure 10C , Figure 11C and Figure 12CIn some embodiments, the gate Gi1 of the first input transistor Ti1, the gate Gi2 of the second input transistor Ti2, the gate Gc1 of the first control transistor Tc1, the gate Gc2 of the second control transistor Tc2, the gate Gc3 of the third control transistor Tc3, the gate Gs1 of the first switching transistor Ts1, the gate Gs2 of the second switching transistor Ts2, the gate Go1 of the first output transistor To1, and the gate Go2 of the second output transistor To2 are located on the same layer.

[0133] In one example, the first output transistor To1 is a multi-gate transistor, and the gate Go1 of the first output transistor To1 includes multiple portions spaced apart from each other, such as... Figure 10C , Figure 11C or Figure 12C As depicted in [the text]. In another example, the second output transistor To2 is a multi-gate transistor, and the gate Go2 of the second output transistor To2 includes multiple portions spaced apart from each other, such as [examples would be inserted here]. Figure 10C , Figure 11C or Figure 12C As depicted in the text.

[0134] In one example, the gates of the first input transistor Ti1 and the second input transistor Ti2 are part of an integral structure. In another example, the gates of the first switching transistor Ts1 and the second switching transistor Ts2 are part of an integral structure. (See reference) Figure 10B In another example, the gates of the first input transistor Ti1, the second input transistor Ti2, and the fourth control transistor Tc4 are part of the overall structure. See also Figure 11B In another example, the gate of the first switching transistor Ts1, the gate of the second switching transistor Ts2, and the gate of the first control transistor Tc1 are part of the overall structure.

[0135] In some embodiments, the first conductive layer further includes a first capacitor electrode of the capacitor in the nth scanning unit. The first capacitor electrode of the capacitor is... Figure 10C , Figure 11C or Figure 12C The text is in Chinese and contains annotations. (See reference.) Figure 10A , Figure 11A , Figure 12A , Figure 10C , Figure 11C and Figure 12CIn some embodiments, the first capacitor electrode Ce1-1 of the first capacitor C1 and the first capacitor electrode Ce2-1 of the second capacitor C2 are in the same layer. Optionally, the first capacitor electrode Ce1-1 of the first capacitor C1 and the gate Go1 of the first output transistor To1 are part of an integral structure. Optionally, the first capacitor electrode Ce2-1 of the second capacitor C2 and the gate Go2 of the second output transistor To2 are part of an integral structure.

[0136] In some embodiments, the first conductive layer further includes an input signal line configured to receive a start signal STV or an output signal G_(n-1) from a previous scan unit of the previous stage as an input at an input terminal Tmi; and an output signal line configured to output an output signal G_n at an output terminal TMo.

[0137] Reference Figure 10D , Figure 11D or Figure 12D The second conductive layer (e.g., corresponding to) Figures 9A to 9B Gate2 in the diagram includes the second capacitor electrode of the capacitor in the nth scan unit. The second capacitor electrode of the capacitor is located in... Figure 10D , Figure 11D or Figure 12D The text is in Chinese and contains annotations. (See reference.) Figure 10A , Figure 11A , Figure 12A , Figure 10D , Figure 11D and Figure 12D In some embodiments, the second capacitor electrode Ce1-2 of the first capacitor C1 and the second capacitor electrode Ce2-2 of the second capacitor C2 are in the same layer.

[0138] Reference Figure 10F , Figure 11F or Figure 12F The first signal line layer (e.g., corresponding to) Figures 9A to 9B SLL1 in the diagram includes the source and drain of the transistor in the nth scan unit. (See reference...) Figure 10A , Figure 11A , Figure 12A , Figure 10F , Figure 11F and Figure 12FIn some embodiments, the source Si1 of the first input transistor Ti1, the source Si2 of the second input transistor Ti2, the source Sc1 of the first control transistor Tc1, the source Sc2 of the second control transistor Tc2, the source Sc3 of the third control transistor Tc3, the source Ss1 of the first switching transistor Ts1, the source Ss2 of the second switching transistor Ts2, the source So1 of the first output transistor To1, the source So2 of the second output transistor To2, the drain Di1 of the first input transistor Ti1, the drain Di2 of the second input transistor Ti2, the drain Dc1 of the first control transistor Tc1, the drain Dc2 of the second control transistor Tc2, the drain Dc3 of the third control transistor Tc3, the drain Ds1 of the first switching transistor Ts1, the drain Ds2 of the second switching transistor Ts2, the drain Do1 of the first output transistor To1, and the drain Do2 of the second output transistor To2 are located on the same layer.

[0139] In some embodiments, the first signal line layer further includes a first clock signal line LCLK1 configured to provide a first clock signal CLK1, a second clock signal line LCLK2 configured to provide a second clock signal CLK2, a third clock signal line LCLK3 configured to provide a third clock signal CLK3, a first reference signal line LVEEF1 configured to provide a first reference signal VREF1, and a second reference signal line LVEEF2 configured to provide a second reference signal VREF2.

[0140] refer to Figure 10A , Figure 11A and Figure 12A In some embodiments, the first output transistor To1 and the second output transistor To2 are disposed in the first region R1 between the second region R2 and the third region R3. Transistors other than the first output transistor To1 and the second output transistor To2 are disposed in the second region. The first capacitor C1 and the second capacitor C2 are disposed in the third region R3. Optionally, the first reference signal line LVREF1 is also disposed in the third region R3.

[0141] In some embodiments, at least clock signal lines (e.g., first clock signal line LCLK1, second clock signal line LCLK2, and third clock signal line LCLK3) are arranged in a fourth region R4. A second region R2 is located between the fourth region R4 and the first region R1. Optionally, the fourth region R4, the second region R2, the first region R1, and the third region R3 are arranged sequentially. Optionally, a second reference signal line LVREF2 is also provided in the fourth region R4.

[0142] The first reference signal line LVERF1 can be positioned in various suitable locations. In one example, the first reference signal line LVERF1 is in the third region R3. In another example, the orthographic projection of the first reference signal line LVERF1 onto the substrate at least partially overlaps with the orthographic projection of the first capacitor C1 or the second capacitor C2 onto the substrate. In another example, the first reference signal line LVERF1 is in the first region R1. In yet another example, the orthographic projection of the first reference signal line LVERF1 onto the substrate at least partially overlaps with the orthographic projection of the first output transistor To1 or the second output transistor To2 onto the substrate.

[0143] The second reference signal line LVEEF2 can be positioned in various suitable locations. In one example, the second reference signal line LVEEF2 is in the fourth region R4. In another example, the second reference signal line LVEEF2 is in the second region R2. In yet another example, the orthographic projection of the second reference signal line LVEEF2 onto the substrate at least partially overlaps with the orthographic projection of at least one transistor (e.g., a transistor other than an output transistor) onto the substrate.

[0144] In some embodiments, the transistors of each scan unit in the second region R2 are arranged such that the first input transistor Ti1 and the second input transistor Ti2 are located on the side of the first switching transistor Ts1 and the second switching transistor Ts2 closer to the clock signal line, and the first switching transistor Ts1 and the second switching transistor Ts2 are located on the side of the first input transistor Ti1 and the second input transistor Ti2 closer to the output transistor.

[0145] In some embodiments, the first input transistor Ti1, the second input transistor Ti2, the first switching transistor Ts1, and the second switching transistor Ts2 are concentrated in the central region, the first control transistor Tc1 and the second control transistor Tc2 are located on the first side of the central region, and the third control transistor Tc3 and the fourth control transistor Tc4 are located on the second side of the central region. The first side and the second side are opposite sides of the central region along the extension direction of the clock signal line or the reference signal line.

[0146] In some embodiments, the second control transistor Tc2 is located on the side of the first control transistor Tc1 closer to the clock signal line, and the first control transistor Tc1 is located on the side of the second control transistor Tc2 closer to the output transistor.

[0147] In some embodiments, at least a portion of the overall structure including the active layer ACTi1 of the first input transistor Ti1 and the active layer ACTi2 of the second input transistor Ti2 has an L-shape or an I-shape. In one example, the overall structure includes the active layer ACTi1 of the first input transistor Ti1, the active layer ACTi2 of the second input transistor Ti2, and the active layer ACTc4 of the fourth control transistor Tc4.

[0148] In some embodiments, at least a portion of the overall structure including the active layer ACTs1 of the first switching transistor Ts1 and the active layer ACTs2 of the second switching transistor Ts2 has an L-shape or an I-shape. In one example, the overall structure includes the active layer ACTs1 of the first switching transistor Ts1, the active layer ACTs2 of the second switching transistor Ts2, and the active layer ACTc1 of the first control transistor Tc1.

[0149] In some embodiments, the first output transistor To1 has a first occupied area, and the second output transistor To2 has a second occupied area, wherein the first occupied area is larger than the second occupied area. Optionally, the ratio of the first occupied area to the second occupied area is greater than or equal to 1.5:1, for example, greater than or equal to 1.6:1, greater than or equal to 1.7:1, greater than or equal to 1.8:1, greater than or equal to 1.9:1, or greater than or equal to 2.0:1.

[0150] In some embodiments, the active layer ACTo1 of the first output transistor To1 has a first channel width, and the active layer ACTo2 of the second output transistor To2 has a second channel width, wherein the first channel width is greater than the second channel width. As used herein, in the case of a multi-gate transistor, the active layer of the multi-gate transistor comprises a plurality of portions spaced apart from each other, such as Figure 10B , Figure 11B or Figure 12B As shown. The channel width of the active layer of a multi-gate transistor is the sum of the channel widths of its multiple sections.

[0151] Optionally, the ratio of the width of the first channel to the width of the second channel is greater than or equal to 1.5:1, for example, greater than or equal to 1.6:1, greater than or equal to 1.7:1, greater than or equal to 1.8:1, greater than or equal to 1.9:1, or greater than or equal to 2.0:1.

[0152] In another aspect, the present invention provides a display device comprising a scanning circuit or display substrate described herein or manufactured by the methods described herein, and one or more integrated circuits. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a quantum dot display device.

[0153] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A scanning circuit comprising multiple stages, wherein, Each stage of the scanning circuit includes a corresponding scanning unit configured to provide control signals to at least one row of sub-pixels; Each scanning unit includes an input sub-circuit, a first processing sub-circuit, a second processing sub-circuit, and an output sub-circuit configured to output a signal from an output terminal. The input sub-circuit is configured to receive a start signal or an output signal from the previous scanning unit of the previous stage from an input terminal. The output sub-circuit includes a first output transistor; The input sub-circuit includes a first input transistor and a second input transistor sequentially coupled between the input terminal and the first node; and The first node is coupled to the gate of the first output transistor; The first processing sub-circuit includes a first switching transistor and a second switching transistor coupled between the first node and the first reference terminal; The first processing sub-circuit further includes a first control transistor coupled between a second node and a first reference terminal; the gate of the first control transistor is coupled to the input terminal and configured to receive the start signal or the output signal from the previous scan unit of the previous stage; the source of the first control transistor is coupled to the first reference terminal and configured to receive a first reference signal; and the drain of the first control transistor is coupled to the second node, the second node being coupled to the gate of the first switching transistor and the gate of the second switching transistor; and The first reference terminal is configured to receive a first reference signal.

2. The scanning circuit according to claim 1, wherein, The gates of the first input transistor and the second input transistor are coupled to a first terminal and configured to receive a first clock signal from the first terminal; as well as The source of the first output transistor is coupled to the second terminal and is configured to receive a second clock signal from the second terminal.

3. The scanning circuit according to claim 1, wherein, The second processing sub-circuit includes a second control transistor coupled between the second node and the second reference terminal; The second reference terminal is configured to receive a second reference signal; as well as The gate of the second control transistor is coupled to a third terminal and is configured to receive a third clock signal from the third terminal.

4. The scanning circuit according to claim 1, wherein, The first processing sub-circuit also includes a third control transistor coupled between the third node and the second reference terminal; The gate of the third control transistor is coupled to the first node; The source of the third control transistor is coupled to the second reference terminal and is configured to receive a second reference signal from the second reference terminal; as well as The drain of the third control transistor is coupled to the drain of the first switching transistor and the source of the second switching transistor.

5. The scanning circuit according to claim 1, wherein, The input sub-circuit also includes a fourth control transistor coupled between the fourth node and the second terminal; The second terminal is configured to receive a second clock signal; The fourth node is coupled to the drain of the first input transistor and the source of the second input transistor; The gate of the fourth control transistor is coupled to the output terminal and is configured to receive the output signal from the output terminal.

6. The scanning circuit according to claim 1, wherein, The output sub-circuit further includes a second output transistor coupled between the first reference terminal and the output terminal; as well as The gate of the second output transistor is coupled to the gate of the first switching transistor and the gate of the second switching transistor.

7. A display substrate comprising a scanning circuit according to any one of claims 1 to 6, in, The first and second output transistors of the output sub-circuit are arranged in the first region; The input transistors, switching transistors, and control transistors of each scanning unit are arranged in the second region; The capacitors of each scanning unit are arranged in the third region; as well as The second region, the first region, and the third region are arranged sequentially.

8. The display substrate according to claim 7, further comprising one or more clock signal lines arranged in the fourth region; in, The fourth region, the second region, the first region, and the third region are arranged sequentially.

9. The display substrate according to claim 7, wherein, In the second region, the first input transistor and the second input transistor are located on the side of the first switching transistor and the second switching transistor that is close to one or more clock signal lines; as well as The first switching transistor and the second switching transistor are located on the side of the first input transistor and the second input transistor that are close to the first output transistor and the second output transistor.

10. The display substrate according to claim 7, wherein, The first input transistor, the second input transistor, the first switching transistor, and the second switching transistor are concentrated in the central region; Each scanning unit further includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; The first control transistor and the second control transistor are located on the first side of the central region; The third control transistor and the fourth control transistor are located on the second side of the central region; and The first side and the second side are two sides opposite to the central region along the extension direction of one or more clock signal lines.

11. The display substrate according to claim 10, wherein, The second control transistor is located on the side of the first control transistor closer to the one or more clock signal lines, and The first control transistor is located on the side of the second control transistor that is close to the first output transistor and the second output transistor.

12. The display substrate according to claim 7, comprising a semiconductor material layer; in, The semiconductor material layer includes the active layer of one or more transistors in each scanning unit; The active layer of the first input transistor and the active layer of the second input transistor are part of a first integral structure in the semiconductor material layer; as well as At least a portion of the first integral structure has an L-shaped or I-shaped form.

13. The display substrate according to claim 12, wherein, The first overall structure also includes an active layer for the fourth control transistor.

14. The display substrate according to claim 7, comprising a semiconductor material layer; in, The semiconductor material layer includes the active layer of one or more transistors in each scanning unit; The active layer of the first switching transistor and the active layer of the second switching transistor are part of the second integral structure in the semiconductor material layer; as well as At least a portion of the second integral structure has an L-shaped or I-shaped form.

15. The display substrate according to claim 14, wherein, The second overall structure also includes the active layer of the first control transistor.

16. The display substrate according to claim 7, wherein, The first output transistor has a first occupied area; The second output transistor has a second occupied area; The first occupied area is larger than the second occupied area; as well as The ratio of the first occupied area to the second occupied area is greater than or equal to 1.5:

1.

17. The display substrate according to claim 7, wherein, The active layer of the first output transistor has a first channel width; The active layer of the second output transistor has a second channel width; The width of the first channel is greater than the width of the second channel; and The ratio of the width of the first channel to the width of the second channel is greater than or equal to 1.5:

1.

18. The display substrate according to claim 8, further comprising a first reference signal line and a second reference signal line; The first reference signal line is located in the third region; The second reference signal line is located in the fourth region; The transistors of each scanning unit are located between the first reference signal line and the second reference signal line.

19. A display device comprising a display substrate according to any one of claims 7 to 18 and one or more integrated circuits connected to the display substrate.

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