Panel, motherboard and display device

Abstract

This disclosure provides a panel, a motherboard, and a display device. The panel includes an active area and an inactive area surrounding the active area. The panel includes: multiple sets of signal lines located within the active area; multiple sets of bonding pins distributed in the inactive areas on opposite sides of the active area, with different sets of bonding pins on the same side of the active area arranged side by side; and multiple sets of signal leads distributed in the inactive areas surrounding the active area. One end of each signal lead is electrically connected to a signal line, and the other end of each signal lead is electrically connected to a bonding pin. Both ends of the same signal line are respectively electrically connected to two signal leads.

Description

Technical Field

[0001] This disclosure relates to the field of active matrix organic light-emitting diode (OLED) panels, and more particularly to a panel, a motherboard, and a display device. Background Technology

[0002] In the field of active matrix organic light-emitting diode (AMOLED) panels, flexible multi-layer on cell (FMLOC) structures are typically used to achieve full-screen, borderless, and thin designs for AMOLED panels.

[0003] Currently, conventional FMLOC touch designs use a bottom-out wiring method, meaning that touch signals are fed through a flexible printed circuit (FPC) under the screen. However, for large-size FMLOCs, as the display panel bezels shrink, the routing space for peripheral signal lines (also known as trace signal lines) is compressed, and the linewidth of the trace signal lines is further compressed. This leads to an increase in the resistance of the trace signal lines, which in turn reduces the touch driving frequency of large-size FMLOCs, affecting sensitivity, SNR, and reporting rate. Summary of the Invention

[0004] This disclosure provides a panel, a motherboard, and a display device to solve the aforementioned technical problems in the prior art.

[0005] In a first aspect, to solve the above-mentioned technical problems, embodiments of this disclosure provide a panel, including an effective area and a non-effective area surrounding the effective area, the panel comprising:

[0006] Multiple signal lines are located within the effective area;

[0007] Multiple sets of bonding pins are distributed in the non-valid areas on opposite sides of the valid area, with different sets of bonding pins located on the same side of the valid area arranged side by side;

[0008] Multiple signal leads are distributed in the non-effective area surrounding the effective area. One end of each signal lead is electrically connected to the signal line, and the other end of each signal lead is electrically connected to the bonding pin. Both ends of the same signal line are respectively electrically connected to two signal leads.

[0009] One possible implementation includes the plurality of signal lines, comprising:

[0010] Two sets of first sub-signal lines extending along a first direction, the two sets of first sub-signal lines being symmetrically distributed about a first center line passing through the center of the effective region; wherein, the extension direction of the first center line is the first direction;

[0011] The multiple signal leads include:

[0012] Four sets of first sub-signal leads, with each pair of first sub-signal leads electrically connected to one set of first sub-signal lines. The two sets of first sub-signal leads connected to the same set of first sub-signal lines are symmetrical about a second center line passing through the center of the effective area. The two sets of first sub-signal leads connected to different sets of first sub-signal lines are symmetrical about the first center line. The extension direction of the second center line is a second direction, which intersects with the first direction.

[0013] One possible implementation includes the plurality of signal lines, comprising:

[0014] Two sets of second sub-signal lines extending along a second direction, the two sets of second sub-signal lines being symmetrically distributed about a second center line passing through the center of the effective region; wherein, the extension direction of the second center line is the second direction;

[0015] The multiple sets of signal leads include:

[0016] Four sets of second sub-signal leads, each pair of first sub-signal leads is electrically connected to one set of second sub-signal lines, and the two sets of second sub-signal leads connected to the same set of second sub-signal lines are symmetrical about a first center line passing through the center of the effective area, and the two sets of second sub-signal leads connected to different sets of second sub-signal lines are symmetrical about a second center line, and the extension direction of the first center line intersects with the second direction.

[0017] In one possible implementation, the panel has a bend area located between the bonding pin and the active area, and the other end of the signal lead passes through the bend area and is electrically connected to the corresponding bonding pin;

[0018] The panel also includes:

[0019] Multiple electrical test leads are electrically connected to the bonding pins one by one. The electrical test leads are used to electrically connect to the electrical test pins. The electrical test pins are used to perform flexible multilayer electrical testing (FMLOC ET) on the signal lines when the panel is in a non-modular configuration state. The non-modular configuration state refers to the state of the panel before it is bonded to a flexible circuit board with a driving circuit.

[0020] In one possible implementation, the electrical test lead is electrically connected to the end of the bonding pin away from the bend region.

[0021] In one possible implementation, the electrical test lead is electrically connected to the corresponding bonding pin via a corresponding signal lead.

[0022] In one possible implementation, the electrical test lead and the signal lead are electrically connected in the region between the bend and the bonding pin;

[0023] Alternatively, the electrical test lead and the signal lead are electrically connected in the region between the effective region and the bending region.

[0024] In one possible implementation, one end of the plurality of electrical test leads extends away from the bonding pin to the edge of the non-effective region and has a cross-section.

[0025] In one possible implementation, the panel further includes:

[0026] At least two sets of the electrical test pins are arranged side by side with the corresponding set of bonding pins;

[0027] Each of the electrical test pins is electrically connected to a bonding pin via an electrical test lead, with the electrical test pin being electrically connected to the electrical test lead at one end near the active region.

[0028] In one possible implementation, the electrical test lead includes a backplane metal wire.

[0029] In one possible implementation, the electrical test leads are double-layered.

[0030] In one possible implementation, when the panel is a display panel, the first sub-signal line is a scan line and the second sub-signal line is a data line;

[0031] Alternatively, the panel may be a touch panel, the first sub-signal line may be a touch sensing line, and the second sub-signal line may be a touch driving line.

[0032] Secondly, embodiments of this disclosure provide a motherboard, comprising:

[0033] Multiple panel units arranged in an array, wherein the panel units include the panel as described in the first aspect;

[0034] The panel unit has an effective area and a border area surrounding the effective area. The border area includes a wiring area surrounding the effective area and flexible structure areas extending from the wiring areas on opposite sides of the effective area. The wiring area and the flexible structure area together constitute the non-effective area of ​​the panel.

[0035] The outer boundary of the frame area has a first cutting line that cuts the panel unit.

[0036] The outer boundary of the non-effective area has a second cutting line that forms the panel, and the second cutting line is used after the panel unit has completed electrical testing.

[0037] In one possible implementation, the panel unit further includes:

[0038] At least two sets of electrical test pins are located on the side of the second cutting line away from the flexible structure area or within the flexible structure area, and are arranged side by side with the corresponding set of bonding pins in the panel. In the area between the outer boundary line of the frame area and the outer boundary line of the wiring area, each electrical test pin is electrically connected to a bonding pin through an electrical test lead, and the end of the electrical test pin near the effective area is electrically connected to the electrical test lead.

[0039] Thirdly, embodiments of this disclosure provide a display device, including:

[0040] The panel as described in the first aspect is at least one of a display panel and a touch panel. Attached Figure Description

[0041] Figure 1 This is a schematic diagram showing the arrangement of peripheral signal lines for a large-size touch panel in related technologies;

[0042] Figure 2 A schematic diagram of the structure of a panel provided in an embodiment of this disclosure;

[0043] Figure 3 This is a schematic diagram of another panel structure provided in an embodiment of the present disclosure;

[0044] Figure 4 and Figure 5 This is a schematic diagram of another panel structure provided in an embodiment of the present disclosure;

[0045] Figure 6 This is a schematic diagram of another panel structure provided in an embodiment of the present disclosure;

[0046] Figure 7 This is a schematic diagram of the panel arrangement in the motherboard provided in an embodiment of the present disclosure;

[0047] Figures 8-13 A schematic diagram of the electrical connection between the electrical test lead and the bonding pin provided in an embodiment of this disclosure;

[0048] Figure 14 This is a schematic diagram of the structure of a backplate provided in an embodiment of the present disclosure;

[0049] Figure 15 A top view of a touch panel provided in an embodiment of this disclosure;

[0050] Figure 16 A cross-sectional view of a touch panel provided in an embodiment of this disclosure;

[0051] Figure 17 This is a schematic diagram of the structure of the FMLOC film layer provided in the embodiments of this disclosure;

[0052] Figure 18 A schematic diagram of the structure of a display panel provided for embodiments of this disclosure;

[0053] Figure 19 A schematic diagram of another panel layout provided in an embodiment of this disclosure;

[0054] Figure 20 This is a schematic diagram of the structure of a motherboard provided in an embodiment of the present disclosure;

[0055] Figure 21 A schematic diagram of a panel unit provided in an embodiment of this disclosure;

[0056] Figure 22 and Figure 23 This is a schematic diagram showing the relative positions of the electrical test pins provided in an embodiment of this disclosure.

[0057] The system includes a bonding pin 1, a signal lead 2, a signal line 3, a first sub-signal line 31, a second sub-signal line 32, a first direction X, the center O of the effective area, a first center line OM1, a second direction Y, a first sub-signal lead 21, a second center line OM2, a second sub-signal lead 22, an electrical test lead 4, an electrical test pin 5, a first touch electrode 61, a second touch electrode 62, a touch sub-electrode 621, a bridging part 622, and multiple panel units 100. Detailed Implementation

[0058] This disclosure provides a panel, a motherboard, and a display device to solve the problem of high resistance in peripheral signal lines.

[0059] To make the above-described objects, features, and advantages of this disclosure more apparent and understandable, the disclosure will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction as described in this disclosure are illustrative of the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this disclosure. The accompanying drawings of this disclosure are for illustrative purposes only and do not represent actual scale.

[0060] It should be noted that specific details are set forth in the following description to provide a full understanding of this disclosure. However, this disclosure can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this disclosure. Therefore, this disclosure is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out this application; however, the description is for the purpose of illustrating the general principles of this application and is not intended to limit the scope of this application. The scope of protection of this application shall be determined by the appended claims.

[0061] Please see Figure 1 This is a schematic diagram showing the arrangement of peripheral signal lines for a large-size touch panel in related technologies.

[0062] Figure 1 The large-size touch panel shown uses dual-sided driving for its touch sensing lines (not shown) and touch driving lines (not shown). The peripheral signal lines leading out from these touch sensing lines and touch driving lines converge at the bottom of the touch area of ​​the large-size display panel and are electrically connected to the corresponding bonding pins (not shown).

[0063] from Figure 1 As can be seen, when the bezel of the touch panel is reduced, the routing space for the peripheral signal lines is compressed. To run as many peripheral signal lines as before, the line width of the peripheral signal lines needs to be reduced, which will increase the resistance of the peripheral signal lines and thus reduce the touch performance of large-size touch panels.

[0064] It should be understood that, for ease of explanation, Figure 1 A set of leader lines is represented by a thick solid line.

[0065] To address the above problems, this disclosure provides the following technical solution:

[0066] Please see Figure 2 , Figure 2 A schematic diagram of the structure of a panel provided in this embodiment includes an effective area and an ineffective area surrounding the effective area (i.e., the area between the outer boundary of the effective area and the dashed frame). The panel includes:

[0067] Multiple signal lines 3 (not shown) are located within the effective area;

[0068] Multiple sets of bonding pins 1 are distributed in the non-active areas on opposite sides of the active area, and different sets of bonding pins 1 located on the same side of the active area are arranged side by side. Figure 2 Instead of a single bonding pin 1, four groups of bonding pins 1 are shown, each group containing multiple bonding pins 1. Figure 2For example, two sets of binding pins 1 located on the upper side of the effective area are arranged side by side, and two sets of binding pins 1 located on the lower side of the effective area are arranged side by side.

[0069] Multiple signal leads 2 are distributed in the non-effective area around the effective area. One end of the signal lead 2 is electrically connected to the signal line 3, and the other end of the signal lead 2 is electrically connected to the bonding pin 1. The two ends of the same signal line 3 are respectively electrically connected to two signal leads 2.

[0070] If the panel is a touch panel, signal line 3 includes touch sensing line and touch driving line, and the effective area is the touch area of ​​the touch panel; if the panel is a display panel, signal line 3 includes data line and scan line, and the effective area is the display area of ​​the display panel.

[0071] In the embodiments provided in this disclosure, by distributing multiple sets of bonding pins 1 on opposite sides of the effective area and arranging different sets of bonding pins 1 on the same side of the effective area side by side, multiple sets of signal leads 2 distributed around the effective area can be grouped into the bonding pins 1 on opposite sides of the effective area, so that the signal leads 2 can be connected to the bonding pins 1 nearby, thereby reducing the length of the signal leads 2, which reduces the resistance of the signal leads 2, and also reduces the distance between the two sides of the non-effective area where bonding pins 1 are not laid and the corresponding two sides of the effective area, which is beneficial for the design of narrow bezel panels.

[0072] Please see Figure 3 This is a schematic diagram of another panel structure provided in an embodiment of the present disclosure. In this panel, multiple sets of signal lines 3 include:

[0073] Two sets of first sub-signal lines 31 extending along the first direction X are symmetrically distributed about the first center line OM1 passing through the center OO of the effective area; wherein, the extension direction of the first center line OM1 is the first direction X.

[0074] Multiple signal leads 2, including:

[0075] Four sets of first sub-signal leads 21, each pair of first sub-signal leads 21 being electrically connected to a set of first sub-signal lines 31. The two sets of first sub-signal leads 21 connected to the same set of first sub-signal lines 31 are symmetrical about the second center line OM2 passing through the center OO of the effective area. The two sets of first sub-signal leads 21 connected to different sets of first sub-signal lines 31 are symmetrical about the first center line OM1. The extension direction of the second center line OM2 is the second direction Y, which intersects with the first direction X.

[0076] For example, when the panel is a display panel, the first sub-signal line 31 is the scan line, and the first sub-signal lead 21 is the lead of the scan line. The scan lines of the display panel are divided into two groups, and each scan line is connected to a corresponding lead at both ends. The leads of the two groups of scan lines drawn from the same side of different groups of scan lines are respectively connected to two sets of bonding pins 1 on opposite sides of the effective area along the periphery of the effective area. Compared with related technologies (such as...), Figure 1 As shown, this reduces the number of first sub-signal lines 31 connected to the same group of bonded pins 1, reduces the routing length of some of the first sub-signal lines 31, and reduces the area occupied by the first sub-signal lines 31 in the non-effective area.

[0077] For example, when the panel is a touch panel, the first sub-signal line 31 is the touch sensing line, and the first sub-signal lead 21 is the lead of the touch sensing line. The touch sensing lines of the display panel are divided into two groups, and each touch sensing line is connected to a corresponding lead at both ends. The leads of the two groups of touch sensing lines drawn from the same side of different groups of touch sensing lines are respectively connected to the two sets of binding pins 1 on opposite sides of the effective area along the periphery of the effective area. This can also reduce the routing length of the first sub-signal line 31 and the area occupied by the first sub-signal line 31 in the non-effective area.

[0078] In the embodiments provided in this disclosure, by dividing the first sub-signal lead 21 extending along the first direction X into two groups and connecting them to different groups of binding pins 1 symmetrically arranged about the effective area, not only can the number of first sub-signal leads 21 extending from the same side of the first sub-signal line 31 connected to the same group of binding pins 1 be reduced, but the length of part of the first sub-signal line 31 is also reduced. This allows the first sub-signal lead 21 to occupy a smaller non-effective area space when laid out along the periphery of the effective area, so there is no need to reduce the width of the first sub-signal lead 21, and thus no increase in the resistance of the first sub-signal lead 21. Furthermore, since the length of part of the first sub-signal lead 21 is reduced, the resistance of part of the first sub-signal lead 21 can be reduced. Ultimately, this achieves the reduction of the non-effective area of ​​the panel while reducing the resistance of the first sub-signal lead 21. This enables both a narrow bezel design of the panel and an increase in the driving frequency, thereby improving sensitivity, signal-to-noise ratio, etc.

[0079] Please see Figure 4 and Figure 5 This is a schematic diagram of another panel structure provided in an embodiment of the present disclosure. In this panel, multiple sets of signal lines 3 include:

[0080] Two sets of second sub-signal lines 32 extending along the second direction Y are symmetrically distributed about the second center line OM2 passing through the center O of the effective area; wherein, the extension direction of the second center line OM2 is the second direction Y.

[0081] Multiple sets of signal leads 2, including:

[0082] Four sets of second sub-signal leads 22, each pair of first sub-signal leads 21 electrically connected to a set of second sub-signal lines 32, and the two sets of second sub-signal leads 22 connected to the same set of second sub-signal lines 32 are symmetrical about the first center line OM1 passing through the center O of the effective area, and the two sets of second sub-signal leads 22 connected to different sets of second sub-signal lines 32 are symmetrical about the second center line OM2, and the extension direction of the first center line OM1 intersects the second direction Y.

[0083] For example, when the panel is a display panel, the second sub-signal line 32 is the data line, and the second sub-signal lead 22 is the lead of the data line. The data lines of the display panel are divided into two groups, and each data line is connected to a corresponding lead at both ends. The leads of the two groups of data lines drawn from the same side of different groups of data lines are respectively connected to two sets of bonding pins 1 on opposite sides of the effective area along the periphery of the effective area. Compared with related technologies (such as...), Figure 1 As shown, this reduces the number of second sub-signal lines 32 connected to the same group of bonded pins 1, reduces the routing length of some of the second sub-signal lines 32, and reduces the area occupied by the second sub-signal lines 32 in the non-effective area.

[0084] For example, when the panel is a touch panel, the first sub-signal line 31 is the touch driving line, and the first sub-signal lead 21 is the lead of the touch driving line. The touch driving lines of the display panel are divided into two groups, and each touch driving line is connected to a corresponding lead at both ends. The leads of the two groups of touch driving lines drawn from the same side of different groups of touch driving lines are respectively connected to the two groups of binding pins 1 on opposite sides of the effective area along the periphery of the effective area. This can also reduce the routing length of the first sub-signal line 31 and the area occupied by the first sub-signal line 31 in the non-effective area.

[0085] like Figure 5 As shown, the first sub-signal line 31 can be divided into two groups and the second sub-signal line 32 can be divided into two groups at the same time. The arrangement of the corresponding first sub-signal lead 21 and second sub-signal lead 22 is similar to the above method, and will not be repeated here. In this way, the length of the signal lead 2 and the area occupied by the non-effective area in the larger panel can be reduced.

[0086] In the embodiments provided in this disclosure, by dividing the second sub-signal lead 22 extending along the second direction Y into two groups and connecting them to different groups of binding pins 1 symmetrically arranged about the effective area, not only can the number of second sub-signal leads 22 extending from the same side of the second sub-signal line 32 connected to the same group of binding pins 1 be reduced, but the length of part of the second sub-signal line 32 is also reduced. This allows the second sub-signal lead 22 to occupy a smaller space in the non-effective area when it is laid out along the periphery of the effective area. In this way, it is not necessary to reduce the width of the second sub-signal lead 22, and the resistance of the second signal lead 22 will not be increased. Furthermore, since the length of part of the second sub-signal lead 22 is reduced, the resistance of part of the second sub-signal lead 22 can be reduced. Ultimately, the non-effective area of ​​the panel is reduced while the resistance of the second sub-signal lead 22 is reduced. This achieves both a narrow bezel design of the panel and an increase in driving frequency, thereby improving sensitivity, signal-to-noise ratio, etc.

[0087] Please see Figure 6 This is a schematic diagram of another panel structure provided in an embodiment of the present disclosure. The panel has a bend area located between the bonding pin 1 and the active area, and the other end of the signal lead 2 passes through the bend area and is electrically connected to the corresponding bonding pin 1;

[0088] The panel also includes:

[0089] Multiple electrical test leads 4 are electrically connected to the bonding pins 1 one by one. The electrical test leads 4 are used to electrically connect to the electrical test pins 5. The electrical test pins 5 are used to perform electrical detection of the touch structure of the signal line 3 when the panel is in a non-modular configuration state. The non-modular configuration state is the state of the panel before it is bonded to a flexible circuit board with a driving circuit.

[0090] By setting an electrical test lead 4 in the panel that is electrically connected to each bonding pin 1, the electrical properties of the touch structure of the signal line 3 can be detected by using the electrical test pin 5 that is electrically connected to the electrical test lead 4 when the panel is in non-modular configuration.

[0091] like Figure 6 As shown, the electrical test lead 4 is electrically connected to the end of the bonding pin 1 away from the bending area. Figure 6 For ease of understanding, the electrical test pin 5 is shown together. In reality, when the panel is in module mode... Figure 6 The electrical test pin 5 has been removed, leaving only the electrical test lead 4 in the non-display area.

[0092] Please see Figure 7 This is a schematic diagram of the panel arrangement in the motherboard provided in an embodiment of this disclosure, as shown below. Figure 6 The panel shown uses dual-sided signal leads 2, which allows this type of panel to operate in non-modular mode. Figure 7 The motherboard shown requires more space. Figure 7(As shown in the black shaded area in the middle), this reduces the number of non-modular panels that can be arranged in the motherboard. In order to provide the amount of non-modular panels that can be arranged in the motherboard, the electrical test pin 5 is arranged side by side with the bonding pin 1.

[0093] The aforementioned electrical test pin 5 may or may not be retained after completing the electrical testing of the touch structure; please refer to [link / reference]. Figures 8-13 This is a schematic diagram illustrating the electrical connection between the electrical test lead and the bonding pin provided in an embodiment of this disclosure. When the telecommunications test pin is retained in the panel, the panel further includes:

[0094] At least two sets of electrical test pins 5 are arranged side by side with the corresponding set of bonding pins 1;

[0095] Each electrical test pin 5 is electrically connected to a bonding pin 1 via an electrical test lead 4, with the end of the electrical test pin 5 near the active area being electrically connected to the electrical test lead 4.

[0096] like Figure 8 and Figure 9 As shown, the electrical test lead 4 can be led out from the end of the bonding pin 1 away from the bending area. If the bonding test pin is not retained in the panel, the electrical test lead 4 extends along the periphery of the entire group of bonding pins 1 and the bending area to the edge of the ineffective area, where it has a cross-section (e.g., at the edge of the ineffective area). Figure 8 As shown), this cross-section is formed by cutting off the electrical test pin 5 after completing the electrical testing of the touch structure; if the bonding test pin is retained in the panel, the electrical test lead 4 extends along the periphery of the entire group of bonding pins 1 and the bending area to the end of the electrical test pin 5 near the bending area (e.g. Figure 9 (As shown).

[0097] like Figures 10-13 As shown, the electrical test lead 4 can also be electrically connected to the corresponding bonding pin 1 via the corresponding signal lead 2. The electrical test lead 4 can be led out from the signal lead 2 between the bonding pin 1 and the bending area (e.g., Figure 10 and Figure 11 Alternatively, it can be led out from signal lead 2 between the bending area and the effective area (e.g., Figure 12 and Figure 13 ).

[0098] like Figure 10 and Figure 11 As shown, after the electrical test lead 4 is led out from the bonding pin 1 and the signal lead 2 in the bending section, if the electrical test pin 5 is not retained in the panel, the electrical test lead 4 extends along the periphery of the bending area to the edge of the non-effective area and has a cross-section (such as...). Figure 10 (as shown); if the electrical test pin 5 is retained in the panel, the linear test lead extends along the periphery of the bending area to the end of the electrical test pin 5 near the bending area.

[0099] like Figure 12 and Figure 13 As shown, after the electrical test lead 4 is led out from the signal lead 2 in the bending area and the effective area, if the electrical test pin 5 is not retained in the panel, the electrical test lead 4 extends along the periphery of the effective area to the edge of the ineffective area and has a cross-section at the edge of the ineffective area; if the electrical test pin 5 is retained in the panel, the electrical test lead 4 extends along the periphery of the effective area and passes through the bending area to reach the electrical test pin 5.

[0100] Electrical test leads 4 include backplane metal wires, such as Gate (metal Mo), SD (Ti / Al / Ti), etc.

[0101] Please see Figure 14 This is a schematic diagram of a backplane structure provided in an embodiment of the present disclosure. The backplane includes a substrate, a buffer layer, an active layer (P-Si), a first gate insulating layer (GI1), a first gate metal layer (Gate1), a second gate insulating layer (GI2), a second gate metal layer (Gate2), an interlayer insulating layer (ILD), a first source / drain metal layer (SD1), a passivation layer (PVX), a first planarization layer (PLN1), a second source / drain metal layer (SD2), and a second planarization layer (PLN2). Electrical test leads 4 can be disposed on the same layer as the first gate metal layer (Gate1), the second gate metal layer (Gate2), the first source / drain metal layer (SD1), and the second source / drain metal layer (SD2) in the backplane, or at least two of these metal layers can be used to form the electrical test leads 4. When at least two different metal layers are used to form the electrical test leads 4, the different metal layers corresponding to the electrical test leads 4 are electrically connected by vias.

[0102] The electrical test pin 5 can be formed by stacking at least two of the following metal layers: a first gate metal layer (Gate1), a second gate metal layer (Gate2), a first source-drain metal layer (SD1), and a second source-drain metal layer (SD2). For example, a stacked structure can be formed in SD1 and SD2 to constitute an electrical test pin 5.

[0103] Please see Figure 15 This is a top view of a touch panel provided in an embodiment of the present disclosure. The touch panel includes a plurality of first touch electrodes 61 and a plurality of second touch electrodes 62, all located in the touch area (i.e., the effective area). The plurality of first touch electrodes 61 and the plurality of second touch electrodes 62 are staggered in the second direction Y and the first direction X and are arranged on the same layer. In some examples, the second direction Y is perpendicular to the first direction X.

[0104] In some embodiments, the second touch electrode 62 further includes a plurality of touch sub-electrodes 621 and a bridging portion 622, wherein two adjacent touch sub-electrodes 621 in the second direction X are electrically connected through the bridging portion 622. The plurality of first touch electrodes 61 and the plurality of touch sub-electrodes 621 are formed simultaneously using a patterning process (e.g., including exposure, development, etching, etc.), and are made of the same layer and material. Although the first touch electrodes 61 and the touch sub-electrodes 621 are disposed in the same layer, they are insulated from each other.

[0105] Please continue reading Figure 15 Multiple first touch electrodes 61 are divided into multiple columns along the second direction Y. Multiple first touch electrodes 61 located in the same column are coupled to each other, and the first touch electrodes 61 in adjacent columns are insulated from each other. For example, along the second direction Y, multiple first touch electrodes 61 in the same column are coupled to each other, while multiple first touch electrodes 61 in different columns are insulated from each other. Each column of first touch electrodes 61 can, for example, serve as a first channel, which is used for a first touch signal.

[0106] Multiple second touch electrodes 62 are divided into multiple rows along a first direction X. Multiple second touch electrodes 62 located in the same row are coupled to each other, and second touch electrodes 62 in adjacent rows are insulated from each other. For example, along the first direction X, multiple second touch electrodes 62 in the same row are coupled to each other, while multiple second touch electrodes 62 in different rows are insulated from each other. Each row of second touch electrodes 62 can, for example, serve as a second channel for transmitting a second touch signal.

[0107] In some embodiments, both the first touch electrode 61 and the second touch electrode 62 are grid-like structures.

[0108] The first touch electrode 61 can be Tx (Transmit, touch transmitting electrode), and the second touch electrode 62 can be Rx (Receive, touch receiving electrode), or the first touch electrode 61 can be Rx and the second touch electrode 62 can be Tx. The embodiments of this disclosure do not limit this.

[0109] by Figure 15 For example, in the effective area, the signal line of the first touch electrode 61 electrically connected to the same column is the second sub-signal line, and the signal line of the second touch electrode 62 electrically connected to the same row is the first sub-signal line. In the non-effective area, the first sub-signal line 31 electrically connected to the first sub-signal line 31 is the first sub-signal lead 21, and the second sub-signal line 32 electrically connected to the second sub-signal line 32 is the second sub-signal lead 22.

[0110] Please see Figure 16 This is a cross-sectional view of a touch panel provided in an embodiment of this disclosure. Figure 16 yes Figure 15 The cross-sectional view of section II' shows that touch panels are typically formed using FMLOC technology. The corresponding film layer of the touch panel can be called an FMLOC film layer. Please refer to [link / reference]. Figure 17 This is a schematic diagram of the structure of the FMLOC film layer provided in the embodiment of this disclosure. The FMLOC film layer includes a buffer layer, a first conductive layer (also known as TMA) corresponding to the metal layer of the bridging portion 622, an insulating layer (SiNx), a second conductive layer (Metal Mesh, also known as TMB) corresponding to the metal layer of the touch sub-electrode 621, and a protective layer (OC). The TMA is disposed on the same layer as the bridging portion 622, and the TMB is disposed on the same layer as the touch sub-electrode 621.

[0111] The electrical test lead 4 can be a double-layer trace. For example, an electrical test lead 4 can be formed by TMA (Ti / Al / Ti) and TMB (Ti / Al / Ti). The portions of this electrical test lead 4 in TMA and TMB are electrically connected by vias.

[0112] The electrical test pin 5 can also be formed by stacking TMA and TMB.

[0113] Please see Figure 18 A schematic diagram of the structure of a display panel provided for the implementation of this disclosure.

[0114] The display panel includes a backplane, an organic light-emitting diode (OLED) layer, and an encapsulation layer. The OLED layer includes an anode, a pixel boundary layer (PDL), a blocking pillar (PS), a light-emitting layer, and a cathode. The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The aforementioned FMLOC film layer is stacked on the encapsulation layer of the display panel.

[0115] By using the backplane metal wire as the electrical test lead 4, wiring can be saved. The electrical test lead 4 uses double-layer routing for flexible wiring and saves the space occupied by the electrical test lead 4.

[0116] Please see Figure 19 This is a schematic diagram of another panel arrangement provided in an embodiment of this disclosure. (The diagram shows the panel layout using...) Figures 8-13 In the panel shown, because the electrical test pin 5 and the bonding pin 1 are designed side by side, even if the panel uses two-sided wiring, each side only occupies the length of one bonding pin 1. However, in related technologies, when single-sided wiring is used, the bonding pin 1 and the electrical test pin 5 are arranged in the same column (e.g., Figure 6As shown, it occupies the length of 2 binding pins 1. Therefore, even if a double-sided line is used in this disclosure, since the electrical test pin 5 and the binding pin 1 are arranged side by side, it only occupies the length of 2 binding pins 1. It does not increase the area occupied by the panel in non-modular mode, so as to reduce the chip layout rate of the panel corresponding to the motherboard provided in the embodiments of this disclosure.

[0117] Based on the same inventive concept, this disclosure provides a motherboard, please refer to [link / reference]. Figure 20 This is a schematic diagram of the structure of a mother plate provided in an embodiment of the present disclosure. The mother plate includes:

[0118] A plurality of panel units 100 are arranged in an array, and each panel unit 100 includes a panel as described above.

[0119] Please see Figure 21 This is a schematic diagram of a panel unit provided in an embodiment of the present disclosure.

[0120] The panel unit 100 has an effective area and a border area surrounding the effective area. The border area includes a wiring area surrounding the effective area and flexible structure areas extending from the wiring areas on opposite sides of the effective area. The wiring area and the flexible structure area together constitute the non-effective area of ​​the panel.

[0121] The outer boundary of the border area has a first cutting line for cutting the panel unit (refer to the boundary line of the border area);

[0122] The outer boundary of the non-effective area has a second cutting line (Figure) for cutting to form the panel. The second cutting line is used after the panel unit completes electrical testing.

[0123] Please see Figure 22 and Figure 23 As shown in the schematic diagram of the relative positions of the electrical test pins provided in this embodiment, the panel unit 100 further includes:

[0124] At least two sets of electrical test pins are located on the side of the second cutting line away from the flexible structure area or within the flexible structure area, and are arranged side by side with the corresponding set of bonding pins in the panel. In the area between the outer boundary line of the frame area and the outer boundary line of the wiring area, each electrical test pin is electrically connected to a bonding pin via an electrical test lead. The end of the electrical test pin closest to the effective area is electrically connected to the electrical test lead (e.g., ...). Figure 9 , Figure 11 , Figure 13 (As shown).

[0125] When it is not necessary to retain electrical test pins on the panel, place the electrical test pins outside the flexible structure area (e.g., Figure 21 (As shown); When it is necessary to retain electrical test pins on the panel, place the electrical test pins within the flexible structure area (e.g., Figure 22(As shown).

[0126] Based on the same inventive concept, this disclosure provides a display device including the panel described above, and the details will not be repeated. The panel can be at least one of a display panel and a touch panel.

[0127] The display device can be a liquid crystal display, liquid crystal screen, liquid crystal television, or other display devices, or a mobile device such as a mobile phone, tablet computer, or laptop.

[0128] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0129] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0130] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A panel comprising an active area and a non-active area surrounding the active area, wherein, The panel includes: Multiple signal lines are located within the effective area; Multiple sets of bonding pins are distributed in the non-valid areas on opposite sides of the valid area, with different sets of bonding pins located on the same side of the valid area arranged side by side; Multiple sets of signal leads are distributed in the non-effective area surrounding the effective area. One end of each signal lead is electrically connected to the signal line, and the other end of each signal lead is electrically connected to the bonding pin. Furthermore, both ends of the same signal line are electrically connected to two signal leads respectively. The multiple sets of signal lines include: Two sets of first sub-signal lines extending along a first direction, the two sets of first sub-signal lines being symmetrically distributed about a first center line passing through the center of the effective region; wherein, the extension direction of the first center line is the first direction; The multiple sets of signal leads include: Four sets of first sub-signal leads, with each pair of first sub-signal leads electrically connected to one set of first sub-signal lines. The two sets of first sub-signal leads connected to the same set of first sub-signal lines are symmetrical about a second center line passing through the center of the effective area. The two sets of first sub-signal leads connected to different sets of first sub-signal lines are symmetrical about the first center line. The extension direction of the second center line is a second direction, which intersects with the first direction.

2. The panel of claim 1, wherein, The multiple sets of signal lines include: Two sets of second sub-signal lines extending along a second direction, the two sets of second sub-signal lines being symmetrically distributed about a second center line passing through the center of the effective region; wherein, the extension direction of the second center line is the second direction; The multiple sets of signal leads include: Four sets of second sub-signal leads, each pair of first sub-signal leads is electrically connected to one set of second sub-signal lines, and the two sets of second sub-signal leads connected to the same set of second sub-signal lines are symmetrical about a first center line passing through the center of the effective area, and the two sets of second sub-signal leads connected to different sets of second sub-signal lines are symmetrical about a second center line, and the extension direction of the first center line intersects with the second direction.

3. The panel of claim 1, wherein, The panel has a bend area located between the bonding pin and the active area, and the other end of the signal lead passes through the bend area and is electrically connected to the corresponding bonding pin. The panel also includes: Multiple electrical test leads are electrically connected to the bonding pins one by one. The electrical test leads are used to electrically connect to the electrical test pins. The electrical test pins are used to perform electrical detection of the touch structure on the signal lines when the panel is in a non-modular state. The non-modular state is the state of the panel before it is bonded to a flexible circuit board with a driving circuit.

4. The panel as claimed in claim 3, wherein, The electrical test lead is electrically connected to the end of the bonding pin away from the bend area.

5. The panel as claimed in claim 3, wherein, The electrical test leads are electrically connected to the corresponding bonding pins via corresponding signal leads.

6. The panel as claimed in claim 5, wherein, The electrical test lead and the signal lead are electrically connected in the region between the bend and the bonding pin; Alternatively, the electrical test lead and the signal lead are electrically connected in the region between the effective region and the bending region.

7. The panel as claimed in any one of claims 3-6, wherein, The plurality of electrical test leads extend from one end away from the bonding pin to the edge of the non-effective region and have a cross section.

8. The panel as claimed in any one of claims 3-6, wherein, The panel also includes: At least two sets of the electrical test pins are arranged side by side with the corresponding set of bonding pins; Each of the electrical test pins is electrically connected to a bonding pin via an electrical test lead, with the electrical test pin being electrically connected to the electrical test lead at one end near the active region.

9. The panel as claimed in any one of claims 3-6, wherein, The electrical test leads include backplane metal wires.

10. The panel as claimed in claim 9, wherein, The electrical test leads are routed in a double layer.

11. The panel as claimed in claim 2, wherein, When the panel is a display panel, the first sub-signal line is a scan line and the second sub-signal line is a data line; Alternatively, the panel may be a touch panel, the first sub-signal line may be a touch sensing line, and the second sub-signal line may be a touch driving line.

12. A motherboard, wherein, include: A plurality of panel units arranged in an array, wherein the panel units include a panel as described in any one of claims 1-11; The panel unit has an effective area and a border area surrounding the effective area. The border area includes a wiring area surrounding the effective area and flexible structure areas extending from the wiring areas on opposite sides of the effective area. The wiring area and the flexible structure area together constitute the non-effective area of ​​the panel. The outer boundary of the frame area has a first cutting line that cuts the panel unit. The outer boundary of the non-effective area has a second cutting line that forms the panel, and the second cutting line is used after the panel unit has completed electrical testing.

13. The mother plate as claimed in claim 12, wherein, The panel unit also includes: At least two sets of electrical test pins are located on the side of the second cutting line away from the flexible structure area or within the flexible structure area, and are arranged side by side with the corresponding set of bonding pins in the panel. In the area between the outer boundary line of the frame area and the outer boundary line of the wiring area, each electrical test pin is electrically connected to a bonding pin through an electrical test lead, and the end of the electrical test pin near the effective area is electrically connected to the electrical test lead.

14. A display device, wherein, include: The panel as described in any one of claims 1-11, wherein the panel is at least one of a display panel and a touch panel.

Images