Pixel circuits and their driving methods, display substrates, display devices

Abstract

A pixel circuit and its driving method, display substrate, and display device are disclosed. The pixel circuit includes a driving circuit and a light-emitting element. The driving circuit provides a driving current and controls the conduction duration of a current path between a first power supply terminal and a second power supply terminal. The light-emitting element receives the driving current in the current path and emits light. The driving circuit includes a current control sub-circuit and a duration control sub-circuit. The current control sub-circuit is configured to provide a driving current to a first node under the control of a first scan signal terminal, a first data signal terminal, and a first power supply terminal during both display and non-display phases. The duration control sub-circuit is configured to provide a signal of the first node to a second node under the control of a second scan signal terminal, a third scan signal terminal, a second data signal terminal, a first control signal terminal, a reset signal terminal, a first initial signal terminal, and a second initial signal terminal during the display phase.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a pixel circuit and its driving method, a display substrate, and a display device. Background Technology

[0002] Silicon-based light-emitting diode (LED) display devices are also known as silicon-based LED display devices. Silicon-based LED display devices are fabricated using mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology. They have advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate, and are widely used in various fields such as medicine, military, aerospace, and consumer electronics, especially in wearable devices, virtual reality (VR), or augmented reality (AR) near-eye displays. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a pixel circuit, comprising: a driving circuit and a light-emitting element, wherein the driving circuit and the light-emitting element are connected in series between a first power supply terminal and a second power supply terminal; the driving circuit is used to provide a driving current and control the conduction duration of the current path between the first power supply terminal and the second power supply terminal; the light-emitting element is used to receive the driving current in the current path and emit light; the driving circuit includes: a current control sub-circuit and a duration control sub-circuit.

[0005] The current control sub-circuit is electrically connected to the first scan signal terminal, the first data signal terminal, the first power supply terminal, and the first node, respectively, and is configured to provide drive current to the first node under the control of the first scan signal terminal, the first data signal terminal, and the first power supply terminal;

[0006] The duration control sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal and the second initial signal terminal, the first node and the second node, respectively, and is configured to provide the first node's signal to the second node under the control of the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal and the second initial signal terminal;

[0007] The light-emitting element is electrically connected to the second node and the second power supply terminal, respectively.

[0008] In some possible implementations, when the reset signal terminal is an active level signal, the signals of the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal are inactive level signals.

[0009] When the signal at the first scan signal terminal is a valid level signal, the signal at the second scan signal terminal is a valid level signal, and the signals at the reset signal terminal and the third scan signal terminal are invalid level signals;

[0010] When the signal at the third scan signal terminal is an active level signal, the signals at the reset signal terminal, the second scan signal terminal, and the third scan signal terminal are inactive level signals.

[0011] The signal at the first control signal terminal is a ramp signal;

[0012] The voltage values ​​of the signals at the first initial signal terminal and the second initial signal terminal are constant.

[0013] In some possible implementations, the current control sub-circuit is also electrically connected to the fourth scan signal terminal and is configured to provide drive current to the first node under the control of the first scan signal terminal, the fourth scan signal terminal, the first data signal terminal, and the first power supply terminal.

[0014] In some possible implementations, when the signal at the first scan signal terminal is a valid level signal, the signal at the fourth scan signal terminal is also a valid level signal.

[0015] In some possible implementations, the driving circuit further includes: a node control sub-circuit;

[0016] The node control sub-circuit is electrically connected to the fifth scan signal terminal, the second control signal terminal and the first node respectively, and is configured to provide the signal of the second control signal terminal to the first node under the control of the fifth scan signal terminal, or read the signal of the first node to the second control signal terminal;

[0017] During the display phase, the voltage value of the signal at the second control signal terminal remains constant.

[0018] In some possible implementations, when the signal at the first scan signal terminal is a valid level signal, the signal at the fifth scan signal terminal is also a valid level signal.

[0019] In some possible implementations, the current control subcircuit includes: a first write subcircuit, a first storage subcircuit, and a drive subcircuit;

[0020] The first write sub-circuit is electrically connected to the first scan signal terminal, the first data signal terminal, and the third node, respectively, and is configured to provide the signal from the first data signal terminal to the third node under the control of the first scan signal terminal;

[0021] The first storage sub-circuit is electrically connected to the third node and the third power supply terminal respectively, and is configured to store the voltage difference between the signals of the third node and the third power supply terminal; or, it is electrically connected to the first node and the third node respectively, and is configured to store the voltage difference between the signals of the first node and the third node.

[0022] The driving sub-circuit is electrically connected to the first power supply terminal, the first node, and the third node, respectively, and is configured to provide driving current to the first node under the control of the third node and the first power supply terminal.

[0023] In some possible implementations, the current control subcircuit includes: a first write subcircuit, a first storage subcircuit, and a drive subcircuit;

[0024] The first write sub-circuit is electrically connected to the first scan signal terminal, the fourth scan signal terminal, the first data signal terminal, and the third node, respectively, and is configured to provide the signal of the first data signal terminal to the third node under the control of the first scan signal terminal and the fourth scan signal terminal;

[0025] The first storage sub-circuit is electrically connected to the third node and the third power supply terminal respectively, and is configured to store the voltage difference between the signals of the third node and the third power supply terminal; or, it is electrically connected to the first node and the third node respectively, and is configured to store the voltage difference between the signals of the first node and the third node.

[0026] The driving sub-circuit is electrically connected to the first power supply terminal, the first node, and the third node, respectively, and is configured to provide driving current to the first node under the control of the third node and the first power supply terminal.

[0027] In some possible implementations, the first storage sub-circuit includes a first capacitor, and the driving sub-circuit includes a first transistor;

[0028] The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0029] One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node.

[0030] In some possible implementations, the first write sub-circuit includes: a second transistor;

[0031] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node.

[0032] In some possible implementations, the first write sub-circuit includes: a second transistor and a third transistor;

[0033] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node.

[0034] The control electrode of the third transistor is electrically connected to the fourth scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0035] The second transistor and the third transistor are of different transistor types.

[0036] In some possible implementations, the node control sub-circuit includes: a fourth transistor;

[0037] The control terminal of the fourth transistor is electrically connected to the fifth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the second control signal terminal, and the second terminal of the fourth transistor is connected to the first node.

[0038] In some possible implementations, the duration control subcircuit includes: a second write subcircuit, a second storage subcircuit, a reset subcircuit, and an output control subcircuit;

[0039] The second storage sub-circuit is electrically connected to the fourth node and the fifth node respectively, and is configured to store the voltage difference between the signals of the fourth node and the fifth node;

[0040] The second write sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, and the fifth node, respectively. It is configured to provide the second data signal terminal to the fifth node under the control of the second scan signal terminal, and to provide the first control signal terminal to the fifth node under the control of the third scan signal terminal.

[0041] The reset sub-circuit is electrically connected to the reset signal terminal, the first initial signal terminal, the second initial signal terminal, the fourth node, and the fifth node, respectively. Under the control of the reset signal terminal, it provides the signal from the first initial signal terminal to the fourth node and the signal from the second initial signal terminal to the fifth node.

[0042] The output control sub-circuit is electrically connected to the first node, the second node, and the fourth node, respectively, and is configured to provide the signal of the first node to the second node under the control of the fourth node.

[0043] In some possible implementations, the output control sub-circuit includes a fifth transistor, and the second storage sub-circuit includes a second capacitor;

[0044] The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node.

[0045] One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node.

[0046] In some possible implementations, the second write sub-circuit includes: a sixth transistor and a seventh transistor;

[0047] The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0048] The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node.

[0049] In some possible implementations, the reset sub-circuit includes: an eighth transistor and a ninth transistor;

[0050] The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0051] The control terminal of the ninth transistor is electrically connected to the reset signal terminal, the first terminal of the ninth transistor is electrically connected to the second initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the fifth node.

[0052] In some possible implementations, the current control subcircuit includes a first transistor, a second transistor, and a first capacitor, and the duration control subcircuit includes a fifth to a ninth transistor and a second capacitor;

[0053] The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0054] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node.

[0055] The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node.

[0056] The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0057] The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node.

[0058] The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0059] The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node.

[0060] One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node.

[0061] One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node.

[0062] The first transistor, the second transistor, and the fifth to ninth transistors are all of the same type and are all metal-oxide-semiconductor transistors.

[0063] In some possible implementations, the current control sub-circuit includes: a first transistor, a second transistor, a third transistor, and a first capacitor; the duration control sub-circuit includes: a fifth to a ninth transistor, and a second capacitor.

[0064] The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0065] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node.

[0066] The control electrode of the third transistor is electrically connected to the fourth scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0067] The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node.

[0068] The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0069] The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node.

[0070] The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0071] The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node.

[0072] One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node.

[0073] One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node.

[0074] The first transistor, the second transistor, and the fifth through ninth transistors are of the same type, and are the opposite type to the third transistor;

[0075] The transistors of the first transistor, the second transistor, the third transistor, and the fifth to ninth transistors are all metal-oxide-semiconductor transistors.

[0076] In some possible implementations, the driving circuit further includes: a node control sub-circuit, the current control sub-circuit including: a first transistor, a second transistor and a first capacitor, the node control sub-circuit including: a fourth transistor, and the duration control sub-circuit including: a fifth to a ninth transistor and a second capacitor;

[0077] The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0078] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node.

[0079] The control terminal of the fourth transistor is electrically connected to the fifth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the second control signal terminal, and the second terminal of the fourth transistor is connected to the first node.

[0080] The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node.

[0081] The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0082] The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node.

[0083] The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0084] The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node.

[0085] One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node.

[0086] One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node.

[0087] The first transistor, the second transistor, the fourth transistor, and the ninth transistor are all of the same type and are all metal-oxide-semiconductor transistors.

[0088] In some possible implementations, the driving circuit further includes: a node control sub-circuit, the current control sub-circuit including: a first transistor, a second transistor, a third transistor and a first capacitor, the node control sub-circuit including: a fourth transistor, and the duration control sub-circuit including: a fifth transistor to a ninth transistor and a second capacitor;

[0089] The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0090] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node.

[0091] The control electrode of the third transistor is electrically connected to the fourth scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0092] The control terminal of the fourth transistor is electrically connected to the fifth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the second control signal terminal, and the second terminal of the fourth transistor is connected to the first node.

[0093] The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node.

[0094] The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0095] The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node.

[0096] The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0097] The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node.

[0098] One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node.

[0099] One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node.

[0100] The first transistor, the second transistor, the fourth transistor through the ninth transistor are of the same type, and are the opposite type to the third transistor;

[0101] The transistors from the first to the ninth transistor are all metal-oxide-semiconductor transistors.

[0102] In some possible implementations, the light-emitting element includes a micro light-emitting diode or a mini light-emitting diode.

[0103] Secondly, this disclosure also provides a display substrate, including: a display area and a non-display area surrounding at least one side of the display area, wherein the display area is provided with a plurality of pixels, and the pixels are provided with pixel circuits as described above.

[0104] In some possible implementations, when the pixel circuit includes a node control sub-circuit, the display substrate further includes a first chip connected to a second control signal terminal and a second chip connected to a first data signal terminal.

[0105] The first chip is configured to provide a signal to the second control signal terminal during the display phase, and to read the signal through the second control signal terminal during the non-display phase. It is also configured to obtain the threshold voltage of the first transistor based on the signal from the second control signal terminal, generate a control signal based on the threshold voltage of the first transistor, and send the control signal to the second chip.

[0106] The second chip provides a signal to the first data signal terminal according to the control signal.

[0107] Thirdly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0108] Fourthly, this disclosure also provides a method for driving a pixel circuit, configured to drive the aforementioned pixel circuit, the pixel circuit being located in a display substrate, the display substrate comprising: a display stage and a non-display stage, the method comprising:

[0109] During the display and non-display phases, the current control sub-circuit provides drive current to the first node under the control of the first scan signal terminal, the first data signal terminal, and the first power supply terminal.

[0110] During the display phase, the duration control sub-circuit, under the control of the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal, and the second initial signal terminal, provides the first node's signal to the second node.

[0111] In some possible implementations, the pixel circuit further includes a node control sub-circuit, and the method further includes:

[0112] During the display phase, the node control sub-circuit, under the control of the fifth scan signal terminal, provides the signal from the second control signal terminal to the first node;

[0113] During the non-display phase, the node control sub-circuit, under the control of the fifth scan signal terminal, reads the signal of the first node to the second control signal terminal.

[0114] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0115] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0116] Figure 1 This is a schematic diagram of the pixel circuit provided in an embodiment of the present disclosure;

[0117] Figure 2 A schematic diagram of a pixel circuit provided for an exemplary embodiment;

[0118] Figure 3 A schematic diagram of a pixel circuit provided for another exemplary embodiment;

[0119] Figure 4 A schematic diagram of the pixel circuit provided as yet another exemplary embodiment;

[0120] Figure 5A A schematic diagram of the current control sub-circuit provided for an exemplary embodiment Figure 1 ;

[0121] Figure 5B A schematic diagram of the current control sub-circuit provided for an exemplary embodiment Figure 2 ;

[0122] Figure 6A Schematic diagram of the current control sub-circuit provided for another exemplary embodiment Figure 1 ;

[0123] Figure 6B Schematic diagram of the current control sub-circuit provided for another exemplary embodiment Figure 2 ;

[0124] Figure 7A Equivalent circuit of a current control sub-circuit provided for an exemplary embodiment Figure 1 ;

[0125] Figure 7B Equivalent circuit of a current control sub-circuit provided for an exemplary embodiment Figure 2 ;

[0126] Figure 8A Equivalent circuit of current control sub-circuit provided for another exemplary embodiment Figure 1 ;

[0127] Figure 8B Equivalent circuit of current control sub-circuit provided for another exemplary embodiment Figure 2 ;

[0128] Figure 9An equivalent circuit diagram of a node control sub-circuit provided for an exemplary embodiment;

[0129] Figure 10 A structural circuit diagram of a duration control sub-circuit provided as an exemplary embodiment;

[0130] Figure 11 An equivalent circuit diagram of a duration control sub-circuit provided for an exemplary embodiment;

[0131] Figure 12 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 1 ;

[0132] Figure 13 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 2 ;

[0133] Figure 14 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 3 ;

[0134] Figure 15 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 4 ;

[0135] Figure 16 for Figure 12 The provided timing diagram of the pixel circuit during the display stage;

[0136] Figure 17 for Figure 13 The provided timing diagram of the pixel circuit during the display stage;

[0137] Figure 18 for Figure 14 The provided timing diagram of the pixel circuit during the display stage;

[0138] Figure 19 for Figure 15 The provided timing diagram of the pixel circuit during the display stage;

[0139] Figure 20 for Figure 14 The provided timing diagram of the pixel circuit during the non-display stage;

[0140] Figure 21 for Figure 15 The provided timing diagram shows the operation of the pixel circuit during the non-display phase. Detailed Implementation

[0141] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0142] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0143] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0144] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0145] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0146] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0147] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0148] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0149] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0150] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0151] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0152] Due to the uneven manufacturing process of LED components, the turn-on voltage of different LED components is inconsistent. In addition, the electro-optical conversion characteristics of self-emissive components (including efficiency, uniformity, color coordinates, etc.) change with the current, resulting in uneven display in LED display products and reducing the display effect of the display products.

[0153] Figure 1 This is a schematic diagram of the pixel circuit provided in an embodiment of the present disclosure. Figure 1As shown, the pixel circuit provided in this embodiment includes: a driving circuit and a light-emitting element, the driving circuit and the light-emitting element being connected in series between a first power supply terminal VDD and a second power supply terminal VSS; the driving circuit is used to provide a driving current and control the conduction duration of the current path between the first power supply terminal VDD and the second power supply terminal Vcom; the light-emitting element is used to receive the driving current in the current path and emit light. Figure 1 As shown, the driving circuit may include a current control sub-circuit and a duration control sub-circuit.

[0154] like Figure 1 As shown, the current control sub-circuit is electrically connected to the first scan signal terminal G1, the first data signal terminal Data1, the first power supply terminal VDD, and the first node N1, respectively. It is configured to provide drive current to the first node N1 under the control of the first scan signal terminal G1, the first data signal terminal Data1, and the first power supply terminal VDD. The duration control sub-circuit is electrically connected to the second scan signal terminal G2, the third scan signal terminal G3, the second data signal terminal Data2, the first control signal terminal S1, the reset signal terminal Reset, the first initial signal terminal INIT1, the second initial signal terminal INIT2, the first node N1, and the second node N2, respectively. It is configured to provide the signal from the first node N1 to the second node N2 under the control of the second scan signal terminal G2, the third scan signal terminal G3, the second data signal terminal Data2, the first control signal terminal S1, the reset signal terminal Reset, the first initial signal terminal INIT1, and the second initial signal terminal INIT2.

[0155] like Figure 1 As shown, the light-emitting element is electrically connected to the second node N2 and the second power supply terminal Vcom, respectively.

[0156] In one exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal Vcom continuously provides a low-level signal.

[0157] In one exemplary embodiment, the voltage value of the signal at the second power supply terminal Vcom can be a negative voltage value.

[0158] In one exemplary embodiment, the light-emitting element includes a first electrode and a second electrode. Exemplarily, the first electrode of the light-emitting element is electrically connected to a second node N2, and the second electrode of the light-emitting element is electrically connected to a second power supply terminal Vcom.

[0159] In one exemplary embodiment, the light-emitting element may be a micro light-emitting diode or a mini light-emitting diode. The typical size (e.g., length) of a micro light-emitting diode may be less than 80 μm, for example, from 10 μm to 50 μm, and does not include a growth substrate (e.g., sapphire); the typical size (e.g., length) of a mini light-emitting diode may be from about 80 μm to 350 μm, for example, from 100 μm to 220 μm.

[0160] In one exemplary embodiment, the pixel circuit of this disclosure can be disposed on a silicon substrate. Disposing the pixel circuit on a silicon substrate improves its electrical stability. Because the pixel circuit disposed on a silicon substrate has better electrical stability, the driving circuit in the pixel circuit disposed on the silicon substrate does not need to include an internal compensation circuit, which reduces the area occupied by the driving circuit, increases the PPI of the display product containing the pixel circuit, avoids the "screen door effect," and improves the display effect of the display product containing the pixel circuit.

[0161] In one exemplary embodiment, when the reset signal terminal Reset is an active level signal, the signals of the first scan signal terminal G1, the second scan signal terminal G2, and the third scan signal terminal G3 are inactive level signals.

[0162] In one exemplary embodiment, when the signal of the first scan signal terminal G1 is an active level signal, the signal of the second scan signal terminal G2 is an active level signal, and the signals of the reset signal terminal Reset and the third scan signal terminal G3 are inactive level signals.

[0163] In one exemplary embodiment, when the signal of the third scan signal terminal G3 is an active level signal, the signals of the reset signal terminal Reset, the second scan signal terminal G2, and the third scan signal terminal G3 are inactive level signals.

[0164] In one exemplary embodiment, the signal at the first control signal terminal S1 is a ramp signal.

[0165] In one exemplary embodiment, the voltage value of the signal at the first initial signal terminal INIT1 is constant and is a DC signal; the voltage value of the signal at the first initial signal terminal INIT1 can be 3V.

[0166] In one exemplary embodiment, the voltage value of the signal at the second initial signal terminal INIT2 is constant and is a DC signal; the voltage value of the signal at the second initial signal terminal INIT2 can be 0V.

[0167] The pixel circuit provided in this embodiment includes: a driving circuit and a light-emitting element, which are connected in series between a first power supply terminal and a second power supply terminal; the driving circuit is used to provide a driving current and control the conduction duration of the current path between the first power supply terminal and the second power supply terminal; the light-emitting element is used to receive the driving current in the current path and emit light; the driving circuit includes: a current control sub-circuit and a duration control sub-circuit; the current control sub-circuit is electrically connected to a first scan signal terminal, a first data signal terminal, a first power supply terminal and a first node, respectively, and is configured to provide a driving current to the first node under the control of the first scan signal terminal, the first data signal terminal and the first power supply terminal; the duration control sub-circuit is electrically connected to a second scan signal terminal, a third scan signal terminal, a second data signal terminal, a first control signal terminal, a reset signal terminal, a first initial signal terminal and a second initial signal terminal, a first node and a second node, respectively, and is configured to provide a signal of the first node to the second node under the control of the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal and the second initial signal terminal; the light-emitting element is electrically connected to the second node and the second power supply terminal. This disclosure, by setting a current control sub-circuit and a duration control sub-circuit, can control the light emission time of the light-emitting element, ensuring the light emission stability of the light-emitting element at low gray levels and improving the display effect of the display product.

[0168] Figure 2 A schematic diagram of a pixel circuit provided for an exemplary embodiment. (See diagram below.) Figure 2 As shown, in one exemplary embodiment, the current control sub-circuit is also electrically connected to the fourth scan signal terminal G4 and is configured to provide drive current to the first node N1 under the control of the first scan signal terminal G1, the fourth scan signal terminal G4, the first data signal terminal Data1, and the first power supply terminal VDD.

[0169] In one exemplary embodiment, when the signal at the first scan signal terminal G1 is an active level signal, the signal at the fourth scan signal terminal G4 is also an active level signal.

[0170] Figure 3 A schematic diagram of the pixel circuit provided for another exemplary embodiment. Figure 4 A schematic diagram of a pixel circuit provided for yet another exemplary embodiment. (See diagram below.) Figure 3 and Figure 4 As shown, in one exemplary embodiment, the driving circuit may further include a node control sub-circuit. Figure 3 The following explanation uses the example of the current control sub-circuit being electrically connected to the first scan signal terminal G1. Figure 4 The following explanation is based on the example of the current control sub-circuit being electrically connected to the first scan signal terminal G1 and the fourth scan signal terminal G4.

[0171] like Figure 3 and Figure 4 As shown, the node control sub-circuit is electrically connected to the fifth scan signal terminal G5, the second control signal terminal S2, and the first node N1, respectively. It is configured to provide the signal of the second control signal terminal S2 to the first node N1 under the control of the fifth scan signal terminal G5, or to read the signal of the first node N1 to the second control signal terminal S2.

[0172] In one exemplary embodiment, the voltage value of the signal at the second control signal terminal S2 is constant.

[0173] This disclosure improves the display effect of the display product by setting a node control sub-circuit to perform external compensation on the signal of the first data signal terminal based on the signal of the first node N1.

[0174] In one exemplary embodiment, when the signal at the first scan signal terminal G1 is an active level signal, the signal at the fifth scan signal terminal G5 is also an active level signal.

[0175] In one exemplary embodiment, the current control sub-circuit can also be electrically connected to a third power supply terminal VSS.

[0176] In one exemplary embodiment, the third power supply terminal VSS continuously provides a low-level signal, and the voltage value of the signal at the third power supply terminal VSS can be 0V.

[0177] Figure 5A A schematic diagram of the current control sub-circuit provided for an exemplary embodiment Figure 1 , Figure 5B A schematic diagram of the current control sub-circuit provided for an exemplary embodiment Figure 2 .like Figure 5A and Figure 5B As shown, in one exemplary embodiment, the current control subcircuit may include: a first write subcircuit, a first storage subcircuit, and a drive subcircuit.

[0178] like Figure 5A and Figure 5BAs shown, the first write sub-circuit is electrically connected to the first scan signal terminal G1, the first data signal terminal Data1, and the third node N3, respectively, and is configured to provide the signal of the first data signal terminal Data1 to the third node N3 under the control of the first scan signal terminal G1; the first storage sub-circuit is electrically connected to the third node N3 and the third power supply terminal VSS, respectively, and is configured to store the voltage difference between the signals of the third node N3 and the third power supply terminal VSS, or is electrically connected to the first node N1 and the third node N3, respectively, and is configured to store the voltage difference between the signals of the first node N1 and the third node N3; the drive sub-circuit is electrically connected to the first power supply terminal VDD, the first node N1, and the third node N3, respectively, and is configured to provide drive current to the first node N1 under the control of the third node N3 and the first power supply terminal VDD. Figure 5A The following explanation uses the example of the first storage sub-circuit being electrically connected to the third node N3 and the third power supply terminal VSS. Figure 5B The following explanation is based on the example of the first storage sub-circuit being electrically connected to the first node N1 and the third node N3 respectively.

[0179] Figure 6A Schematic diagram of the current control sub-circuit provided for another exemplary embodiment Figure 1 , Figure 6B Schematic diagram of the current control sub-circuit provided for another exemplary embodiment Figure 2 .like Figure 6A and 6B As shown, in one exemplary embodiment, the current control subcircuit may include: a first write subcircuit, a first storage subcircuit, and a drive subcircuit.

[0180] like Figure 6A and 6B As shown, the first write sub-circuit is electrically connected to the first scan signal terminal G1, the fourth scan signal terminal G4, the first data signal terminal Data1, and the third node N3, respectively, and is configured to provide the signal of the first data signal terminal Data1 to the third node N3 under the control of the first scan signal terminal G1 and the fourth scan signal terminal; the first storage sub-circuit is electrically connected to the third node N3 and the third power supply terminal VSS, respectively, and is configured to store the voltage difference between the signals of the third node N3 and the third power supply terminal VSS, or is electrically connected to the first node N1 and the third node N3, respectively, and is configured to store the voltage difference between the signals of the first node N1 and the third node N3; the drive sub-circuit is electrically connected to the first power supply terminal VDD, the first node N1, and the third node N3, respectively, and is configured to provide drive current to the first node N1 under the control of the third node N3 and the first power supply terminal VDD. Figure 6A The following explanation uses the example of the first storage sub-circuit being electrically connected to the third node N3 and the third power supply terminal VSS. Figure 6BThe following explanation is based on the example of the first storage sub-circuit being electrically connected to the first node N1 and the third node N3 respectively.

[0181] Figure 7A Equivalent circuit of a current control sub-circuit provided for an exemplary embodiment Figure 1 , Figure 7B Equivalent circuit of a current control sub-circuit provided for an exemplary embodiment Figure 2 , Figure 8A Equivalent circuit of current control sub-circuit provided for another exemplary embodiment Figure 1 , Figure 8B Equivalent circuit of current control sub-circuit provided for another exemplary embodiment Figure 2 .like Figure 7A , Figure 7B , Figure 8A and Figure 8B As shown, in one exemplary embodiment, the first storage sub-circuit may include a first capacitor C1, and the driving sub-circuit may include a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the third node N3, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the first node N1. One plate of the first capacitor C1 is electrically connected to the third node N3, and the other plate of the first capacitor C1 is electrically connected to the third power supply terminal VSS or the first node N1. Figure 7A and Figure 8A This explanation uses the example of connecting the other plate of the first capacitor C1 to the third power supply terminal VSS. Figure 7B and Figure 8B This explanation is based on the example of the other plate of the first capacitor C1 being electrically connected to the first node N1.

[0182] Figure 7A , Figure 7B , Figure 8A and Figure 8B An exemplary structure of the first storage sub-circuit and the driving sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first storage sub-circuit and the driving sub-circuit is not limited thereto.

[0183] In one exemplary embodiment, such as Figure 7A and Figure 7B As shown, the first write sub-circuit may include a second transistor T2. The control terminal of the second transistor T2 is electrically connected to the first scan signal terminal G1, the first terminal of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second terminal of the second transistor T2 is electrically connected to the third node N3.

[0184] Figure 7A and Figure 7BAn exemplary structure of the first write sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first write sub-circuit is not limited to this.

[0185] In one exemplary embodiment, such as Figure 8A and Figure 8B As shown, the first write sub-circuit may include a second transistor T2 and a third transistor T3. The control electrode of the second transistor T2 is electrically connected to the first scan signal terminal G1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. Similarly, the control electrode of the third transistor T3 is electrically connected to the fourth scan signal terminal G4, the first electrode of the third transistor T3 is electrically connected to the first data signal terminal Data1, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0186] In this disclosure, the second transistor T2 and the third transistor T3 are equivalent to transmission gates, which can increase the writing range of the data signal at the first data signal terminal Data1 and improve the reliability of the pixel circuit.

[0187] Figure 8A and Figure 8B Another exemplary structure of the first write sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first write sub-circuit is not limited to this.

[0188] In one exemplary embodiment, the second transistor T2 and the third transistor T3 are of different transistor types.

[0189] Figure 9 An equivalent circuit diagram of a node control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 9 As shown, in one exemplary embodiment, the node control sub-circuit may include a fourth transistor T4. Figure 9 The following explanation uses the example of the current control sub-circuit being electrically connected to the first scanning signal terminal G1.

[0190] like Figure 9 As shown, the control terminal of the fourth transistor T4 is electrically connected to the fifth scan signal terminal G5, the first terminal of the fourth transistor T4 is electrically connected to the second control signal terminal S2, and the second terminal of the fourth transistor T4 is connected to the first node N1.

[0191] Figure 9 An exemplary structure of the node control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the node control sub-circuit is not limited to this.

[0192] Figure 10 A structural circuit diagram of a duration control sub-circuit provided for an exemplary embodiment. (See diagram below.) Figure 10As shown, in one exemplary embodiment, the duration control subcircuit may include: a second write subcircuit, a second storage subcircuit, a reset subcircuit, and an output control subcircuit.

[0193] like Figure 10 As shown, the second storage sub-circuit is electrically connected to the fourth node N4 and the fifth node N5, respectively, and is configured to store the voltage difference between the signals of the fourth node N4 and the fifth node N5; the second write sub-circuit is electrically connected to the second scan signal terminal G2, the third scan signal terminal G3, the second data signal terminal Data2, the first control signal terminal S1, and the fifth node N5, respectively, and is configured to provide the signal of the second data signal terminal Data2 to the fifth node N5 under the control of the second scan signal terminal G2, and provide the signal of the first control signal terminal S1 to the fifth node N5 under the control of the third scan signal terminal G3. The reset sub-circuit is electrically connected to the reset signal terminal Reset, the first initial signal terminal INIT1, the second initial signal terminal INIT2, the fourth node N4, and the fifth node N5, respectively. Under the control of the reset signal terminal Reset, it provides the signal of the first initial signal terminal INIT1 to the fourth node N4 and the signal of the second initial signal terminal INIT2 to the fifth node N5. The output control sub-circuit is electrically connected to the first node N1, the second node N2, and the fourth node N4, respectively. It is configured to provide the signal of the first node N1 to the second node N2 under the control of the fourth node N4.

[0194] Figure 11 An equivalent circuit diagram of a duration control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 11 As shown, in one exemplary embodiment, the output control sub-circuit may include a fifth transistor T5, and the second storage sub-circuit may include a second capacitor C2. The control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. One plate of the second capacitor C2 is electrically connected to the fourth node N4, and the other plate of the second capacitor C2 is electrically connected to the fifth node N5.

[0195] like Figure 11 As shown, in one exemplary embodiment, the second write sub-circuit may include a sixth transistor T6 and a seventh transistor T7. The control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal G2, the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal G3, the first electrode of the seventh transistor T7 is electrically connected to the first control signal terminal S1, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0196] like Figure 11 As shown, in one exemplary embodiment, the reset sub-circuit may include an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is electrically connected to the reset signal terminal Reset, the first electrode of the eighth transistor T8 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. Similarly, the control electrode of the ninth transistor T9 is electrically connected to the reset signal terminal Reset, the first electrode of the ninth transistor T9 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the ninth transistor T9 is electrically connected to the fifth node N5.

[0197] Figure 11 The diagram illustrates an exemplary structure of the second write sub-circuit, the second storage sub-circuit, the reset sub-circuit, and the output control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the second write sub-circuit, the second storage sub-circuit, the reset sub-circuit, and the output control sub-circuit is not limited thereto.

[0198] Figure 12 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 1 .like Figure 12 As shown, in one exemplary embodiment, the current control sub-circuit includes a first transistor T1, a second transistor T2, and a first capacitor C1, and the duration control sub-circuit includes a fifth transistor T5 to a ninth transistor T9 and a second capacitor C2.

[0199] like Figure 12As shown, the control electrode of the first transistor T1 is electrically connected to the third node N3, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal G1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal G2, the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal G1. Terminal G3 is electrically connected; the first terminal of the seventh transistor T7 is electrically connected to the first control signal terminal S1, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the reset signal terminal Reset, the first terminal of the eighth transistor T8 is electrically connected to the first initial signal terminal INIT1, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the control terminal of the ninth transistor T9 is electrically connected to the reset signal terminal Reset, the first terminal of the ninth transistor T9 is electrically connected to the second initial signal terminal INIT2, and the second terminal of the ninth transistor T9 is electrically connected to the fifth node N5; one plate of the first capacitor C1 is electrically connected to the third node N3, and the other plate of the first capacitor C1 is electrically connected to the third power supply terminal VSS or the first node N1; one plate of the second capacitor C2 is electrically connected to the fourth node N4, and the other plate of the second capacitor C2 is electrically connected to the fifth node N5. Figure 12 This explanation is based on the example of the other plate of the first capacitor C1 being electrically connected to the third power supply terminal VSS.

[0200] In one exemplary embodiment, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the ninth transistor T9 are of the same transistor type, which can simplify the manufacturing process.

[0201] In one exemplary embodiment, the first transistor T1, the second transistor T2, and the fifth transistors T5 through T9 are all metal-oxide-semiconductor (MODS) transistors. MODS transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0202] Figure 13 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 2 .like Figure 13As shown, in one exemplary embodiment, the current control sub-circuit includes: a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1, and the duration control sub-circuit includes: a fifth transistor T5 to a ninth transistor T9 and a second capacitor C2.

[0203] like Figure 13 As shown, the control electrode of the first transistor T1 is electrically connected to the third node N3, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal G1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the fourth scan signal terminal G4, the first electrode of the third transistor T3 is electrically connected to the first data signal terminal Data1, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal G2, and the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2. The second terminal of transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the third scan signal terminal G3, the first terminal of the seventh transistor T7 is electrically connected to the first control signal terminal S1, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the reset signal terminal Reset, the first terminal of the eighth transistor T8 is electrically connected to the first initial signal terminal INIT1, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the control terminal of the ninth transistor T9 is electrically connected to the reset signal terminal Reset, the first terminal of the ninth transistor T9 is electrically connected to the second initial signal terminal INIT2, and the second terminal of the ninth transistor T9 is electrically connected to the fifth node N5; one plate of the first capacitor C1 is electrically connected to the third node N3, and the other plate of the first capacitor C1 is electrically connected to the third power supply terminal VSS or the first node N1; one plate of the second capacitor C2 is electrically connected to the fourth node N4, and the other plate of the second capacitor C2 is electrically connected to the fifth node N5. Figure 13 This explanation is based on the example of the other plate of the first capacitor C1 being electrically connected to the third power supply terminal VSS.

[0204] In one exemplary embodiment, the first transistor T1, the second transistor T2, and the fifth transistors T5 through T9 are of the same transistor type, and are of the opposite type to the third transistor T3. For example, the first transistor T1, the second transistor T2, and the fifth transistors T5 through T9 are N-type transistors, and the third transistor T3 is a P-type transistor.

[0205] In one exemplary embodiment, the transistors of the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 through the ninth transistor T9 are all metal-oxide-semiconductor (MOS) transistors. MOS transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0206] Figure 14 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 3 .like Figure 14 As shown, in one exemplary embodiment, the driving circuit further includes: a node control sub-circuit; the current control sub-circuit includes: a first transistor T1, a second transistor T2 and a first capacitor C1; the node control sub-circuit includes: a fourth transistor T4; and the duration control sub-circuit includes: a fifth transistor T5 to a ninth transistor T9 and a second capacitor C2.

[0207] like Figure 14As shown, the control electrode of the first transistor T1 is electrically connected to the third node N3, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal G1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the fifth scan signal terminal G5, the first electrode of the fourth transistor T4 is electrically connected to the second control signal terminal S2, and the second electrode of the fourth transistor T4 is connected to the first node N1; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal G2, and the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2. The second terminal of transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the third scan signal terminal G3, the first terminal of the seventh transistor T7 is electrically connected to the first control signal terminal S1, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the reset signal terminal Reset, the first terminal of the eighth transistor T8 is electrically connected to the first initial signal terminal INIT1, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the control terminal of the ninth transistor T9 is electrically connected to the reset signal terminal Reset, the first terminal of the ninth transistor T9 is electrically connected to the second initial signal terminal INIT2, and the second terminal of the ninth transistor T9 is electrically connected to the fifth node N5; one plate of the first capacitor C1 is electrically connected to the third node N3, and the other plate of the first capacitor C1 is electrically connected to the third power supply terminal VSS or the first node N1; one plate of the second capacitor C2 is electrically connected to the fourth node N4, and the other plate of the second capacitor C2 is electrically connected to the fifth node N5. Figure 14 This explanation is based on the example of the other plate of the first capacitor C1 being electrically connected to the first node N1.

[0208] In one exemplary embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 to the ninth transistor T9 are of the same transistor type, which can simplify the manufacturing process.

[0209] In one exemplary embodiment, the first transistor T1, the second transistor T2, and the fourth transistors T4 through T9 are all metal-oxide-semiconductor (MODS) transistors. MODS transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0210] Figure 15 Equivalent circuit of pixel circuit provided for an exemplary embodiment Figure 4 .like Figure 15 As shown, in one exemplary embodiment, the driving circuit further includes a node control sub-circuit. The current control sub-circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1. The node control sub-circuit includes a fourth transistor T4. The duration control sub-circuit includes a fifth transistor T5 to a ninth transistor T9 and a second capacitor C2.

[0211] like Figure 15 As shown, the control electrode of the first transistor T1 is electrically connected to the third node N3, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal G1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the fourth scan signal terminal G4, the first electrode of the third transistor T3 is electrically connected to the first data signal terminal Data1, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the fifth scan signal terminal G5, the first electrode of the fourth transistor T4 is electrically connected to the second control signal terminal S2, and the second electrode of the fourth transistor T4 is connected to the first node N1; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal G1. 2. Electrical connections: The first terminal of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the third scan signal terminal G3, the first terminal of the seventh transistor T7 is electrically connected to the first control signal terminal S1, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the reset signal terminal Reset, the first terminal of the eighth transistor T8 is electrically connected to the first initial signal terminal INIT1, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the control terminal of the ninth transistor T9 is electrically connected to the reset signal terminal Reset, the first terminal of the ninth transistor T9 is electrically connected to the second initial signal terminal INIT2, and the second terminal of the ninth transistor T9 is electrically connected to the fifth node N5; one plate of the first capacitor C1 is electrically connected to the third node N3, and the other plate of the first capacitor C1 is electrically connected to the third power supply terminal VSS or the first node N1; one plate of the second capacitor C2 is electrically connected to the fourth node N4, and the other plate of the second capacitor C2 is electrically connected to the fifth node N5. Figure 15 This explanation is based on the example of the other plate of the first capacitor C1 being electrically connected to the first node N1.

[0212] In one exemplary embodiment, the first transistor T1, the second transistor T2, and the fourth transistors T4 through T9 are of the same transistor type, and are of the opposite type to the third transistor T3. For example, the first transistor T1, the second transistor T2, and the fourth transistors T4 through T9 can be N-type transistors, and the third transistor T3 can be a P-type transistor.

[0213] In one exemplary embodiment, the transistors of the first transistor T1 to the ninth transistor T9 can all be metal-oxide-semiconductor (MOS) transistors. MOS transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0214] In one exemplary embodiment, the first transistor T1 may be referred to as the driving transistor, and the first transistor T1 determines the driving current flowing between the first power supply terminal VDD and the first node N1 based on the potential difference between its control electrode and the first electrode.

[0215] In one exemplary embodiment, all transistors in this disclosure may be disposed on a silicon substrate and are metal-oxide-semiconductor transistors, wherein the aspect ratio of the active layer of the metal-oxide-semiconductor transistor is in the (sub)micron level, i.e., the size is small.

[0216] The aspect ratio of the active layer of a metal-oxide-semiconductor (MOS) transistor is in the sub-micron range, allowing the display substrate containing the pixel circuit to achieve a high PPI, typically above 2000-3000 PPI, thus avoiding the "screen door effect." The relatively stable electrical performance of MOS transistors further enhances the stability of the electrical performance of the driving circuit.

[0217] In one exemplary embodiment, pixel circuitry is disposed in a display substrate, the display substrate comprising a display phase and a non-display phase.

[0218] The following is through Figure 12 The operation of the example pixel circuit during the display stage illustrates an exemplary embodiment of this disclosure. Figure 12 This explanation uses N-type transistors, specifically transistors T1, T2, T5, T5, and T9, as an example. Figure 12The pixel circuit includes a first transistor T1, a second transistor T2, a fifth transistor T5 to a ninth transistor T9, two capacitors C (first capacitor C1 and second capacitor C2), and 11 signal terminals (first data signal terminal Data1, second data signal terminal Data2, first scan signal terminal G1, second scan signal terminal G2, third scan signal terminal G3, first control signal terminal S1, reset signal terminal Reset, first initial signal terminal INIT1, second initial signal terminal INIT2, first power supply terminal VDD, and third power supply terminal VSS). Figure 16 for Figure 12 The provided timing diagram shows the operation of the pixel circuit during the display stage.

[0219] Combination Figure 12 and Figure 16 The operation of the pixel circuit during the display stage can include:

[0220] In the first stage S1, the Reset signal is high, the eighth transistor T8 and the ninth transistor T9 are turned on. The signal of the first initial signal INIT1 is written to the fourth node N4 through the turned-on eighth transistor, and the signal of the second initial signal INIT2 is written to the fifth node N5 through the turned-on ninth transistor T9. The two plates of the second capacitor C2 are initialized (reset), the pre-stored voltage inside is cleared, and the initialization is completed. In this stage, the voltage value of the signal at the fourth node N4 is V1, and the voltage value of the signal at the fifth node N4 is V2. V1 is the voltage value of the signal at the first initial signal INIT1, and V2 is the voltage value of the signal at the second initial signal INIT2. The light-emitting element L does not emit light.

[0221] In the second stage S2, the signal at the first scan signal terminal G1 is a high-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 is turned on, and the signal at the first data signal terminal Data1 is written to the third node N3. The first transistor T1 is turned on, providing drive current to the first node N1. The signal at the second scan signal terminal G2 is a high-level signal, the second data signal terminal Data2 outputs a data voltage, the sixth transistor T6 is turned on, and the signal at the second data signal terminal Data2 is written to the fifth node N5. In this stage, the voltage value of the signal at the fifth node N5 is Vdata2, which is the voltage value of the signal at the second data signal terminal. Under the bootstrap effect of the second capacitor C2, the voltage value of the signal at the fourth node N4 is V1-V2+Vdata2, and the light-emitting element L does not emit light.

[0222] In the third stage S3, the first scan signal terminal G1 is a low-level signal, the second transistor T2 is cut off, the signal of the third node N3 remains the same as the signal of the previous node, the first transistor T1 is continuously turned on, providing driving current to the first node N1, the signal of the second scan signal terminal G2 is a low-level signal, the sixth transistor T6 is cut off, and the light-emitting element L does not emit light.

[0223] In the fourth stage (S4), the signal at the third scan signal terminal G3 is high, the seventh transistor T7 is turned on, and the signal at the first control signal terminal S1 is written to the fifth node N5. Under the bootstrap effect of the second capacitor C2, the voltage of the signal at the fourth node N4 is V1-V2+Vdata2+ΔV, where ΔV is the voltage value of the signal at the first control signal terminal S1. ΔV gradually increases, and the voltage value of the signal at the fourth node N4 is the voltage value of the control electrode of the fourth transistor. In this stage, ΔV is relatively small, so Vdata2 and ΔV do not meet the conduction condition of the fifth transistor T5, the fifth transistor T5 is turned off, and the light-emitting element L does not emit light. The conduction condition of the fifth transistor T5 is Vgs>Vth5 and Vds>Vgs-Vth5, where Vgs is the voltage difference between the control electrode and the first electrode of the fifth transistor T5, Vds is the voltage difference between the first electrode and the drain electrode of the fifth transistor T5, and Vth5 is the threshold voltage of the fifth transistor T5.

[0224] In the fifth stage S5, the signal at the third scan signal terminal G3 is a high-level signal, the seventh transistor T7 is turned on, and the signal at the first control signal terminal S1 is continuously written to the fifth node N5. Under the bootstrap effect of the second capacitor C2, the voltage of the signal at the fourth node N4 is V1-V2+Vdata2+ΔV. As ΔV increases, Vdata2 and ΔV satisfy the conduction condition of the fifth transistor T5, and the fifth transistor T5 is turned on. The signal at the first node N1 is written to the second node N2 through the turned-on fifth transistor T5, and the light-emitting element L emits light.

[0225] In one exemplary embodiment, the operation of the pixel circuit during the display phase may not include a third phase, but only includes a first phase, a second phase, a fourth phase, and a fifth phase. The operation of the pixel circuit during the display phase may depend on the duration of the display frame.

[0226] Figure 12 This explanation uses the example of the first capacitor C1 being electrically connected to the third node N3 and the third power supply terminal VSS. When the first capacitor C1 is electrically connected to the third node N2 and the first node N1, Figure 16 The same applies to the work sequence.

[0227] The following is through Figure 13 The operation of the example pixel circuit during the display stage illustrates an exemplary embodiment of this disclosure. Figure 13This explanation uses an example where the first transistor T1, the second transistor T2, the fifth transistor T5 through the ninth transistor T9 are N-type transistors, and the third transistor T3 is a P-type transistor. Figure 13 The pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fifth transistor T5 to a ninth transistor T9, two capacitors C (first capacitor C1 and second capacitor C2), and 12 signal terminals (first data signal terminal Data1, second data signal terminal Data2, first scan signal terminal G1, second scan signal terminal G2, third scan signal terminal G3, fourth scan signal terminal G4, first control signal terminal S1, reset signal terminal Reset, first initial signal terminal INIT1, second initial signal terminal INIT2, first power supply terminal VDD, and third power supply terminal VSS). Figure 17 for Figure 13 The provided timing diagram shows the operation of the pixel circuit during the display stage.

[0228] Combination Figure 13 and Figure 17 The operation of the pixel circuit during the display stage can include: the first stage S1 to the fifth stage S5.

[0229] Figure 13 The first stage S1, the third stage S3 to the fifth stage S5 in the operation of the pixel circuit are respectively related to Figure 12 The first stage S1, the third stage S3 to the fifth stage S5 in the operation process of the pixel circuit are the same, and will not be described again here. Figure 13 The second stage S2 in the operation of the pixel circuit Figure 12 The second stage S2 in the operation process of the pixel circuit is different.

[0230] In the second stage S2, the signal at the first scan signal terminal G1 is a high-level signal, the signal at the fourth scan signal terminal G4 is a low-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 and the third transistor T3 are turned on, the signal at the first data signal terminal Data1 is written to the third node N3, the first transistor T1 is turned on, providing drive current to the first node N1, the signal at the second scan signal terminal G2 is a high-level signal, the second data signal terminal Data2 outputs a data voltage, the sixth transistor T6 is turned on, the signal at the second data signal terminal Data2 is written to the fifth node N5. In this stage, the voltage value of the signal at the fifth node N5 is Vdata2, which is the voltage value of the signal at the second data signal terminal. Under the bootstrap effect of the second capacitor C2, the voltage value of the signal at the fourth node N4 is V1-V2+Vdata2, and the light-emitting element L does not emit light.

[0231] Figure 13This explanation uses the example of the first capacitor C1 being electrically connected to the third node N3 and the third power supply terminal VSS. When the first capacitor C1 is electrically connected to the third node N2 and the first node N1, Figure 17 The same applies to the work sequence.

[0232] The following is through Figure 14 The operation of the example pixel circuit during the display stage illustrates an exemplary embodiment of this disclosure. Figure 14 The following explanation uses N-type transistors as an example, specifically transistors T1, T2, T4, T5, T5, and T9. Figure 14 The pixel circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5 to a ninth transistor T9, two capacitors C (first capacitor C1 and second capacitor C2), and 11 signal terminals (first data signal terminal Data1, second data signal terminal Data2, first scan signal terminal G1, second scan signal terminal G2, third scan signal terminal G3, fifth scan signal terminal G5, first control signal terminal S1, reset signal terminal Reset, first initial signal terminal INIT1, second initial signal terminal INIT2, and first power supply terminal VDD). Figure 18 for Figure 14 The provided timing diagram shows the operation of the pixel circuit during the display stage.

[0233] Combination Figure 14 and Figure 18 The operation of the pixel circuit during the display stage can include: the first stage S1 to the fifth stage S5.

[0234] Figure 14 The first stage S1, the third stage S3 to the fifth stage S5 in the operation of the pixel circuit are respectively related to Figure 12 The first stage S1, the third stage S3 to the fifth stage S5 in the operation process of the pixel circuit are the same, and will not be described again here. Figure 14 The second stage S2 in the operation of the pixel circuit Figure 12 The second stage S2 in the operation process of the pixel circuit is different.

[0235] In the second stage S2, the signal at the first scan signal terminal G1 is high, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 is turned on, and the signal at the first data signal terminal Data1 is written to the third node N3. The signal at the fifth scan signal terminal G5 is high, the signal at the second control signal terminal S2 is written to the first node N1, the first transistor T1 is turned on, providing drive current to the first node N1, the signal at the second scan signal terminal G2 is high, the second data signal terminal Data2 outputs a data voltage, the sixth transistor T6 is turned on, and the signal at the second data signal terminal Data2 is written to the fifth node N5. In this stage, the voltage value of the signal at the fifth node N5 is Vdata2, which is the voltage value of the signal at the second data signal terminal. Under the bootstrap effect of the second capacitor C2, the voltage value of the signal at the fourth node N4 is V1-V2+Vdata2, and the light-emitting element L does not emit light.

[0236] Figure 14 This explanation uses the example of the first capacitor C1 being electrically connected to the third node N3 and the first node N1. When the first capacitor C1 is electrically connected to the third node N2 and the third power supply terminal VSS, Figure 18 The same applies to the work sequence.

[0237] The following is through Figure 15 The operation of the example pixel circuit during the display stage illustrates an exemplary embodiment of this disclosure. Figure 15 This explanation uses an example where transistors T1, T2, T4, T5 through T9 are N-type transistors, and transistor T3 is a P-type transistor. Figure 15 The pixel circuit includes transistors T1 to T9, two capacitors C (first capacitor C1 and second capacitor C2), and 12 signal terminals (first data signal terminal Data1, second data signal terminal Data2, first scan signal terminal G1, second scan signal terminal G2, third scan signal terminal G3, fourth scan signal terminal G4, fifth scan signal terminal G5, first control signal terminal S1, reset signal terminal Reset, first initial signal terminal INIT1, second initial signal terminal INIT2, and first power supply terminal VDD). Figure 19 for Figure 15 The provided timing diagram shows the operation of the pixel circuit during the display stage.

[0238] Combination Figure 15 and Figure 19 The operation of the pixel circuit during the display stage can include: the first stage S1 to the fifth stage S5.

[0239] Figure 15 The first stage S1, the third stage S3 to the fifth stage S5 in the operation of the pixel circuit are respectively related to Figure 12 The first stage S1, the third stage S3 to the fifth stage S5 in the operation process of the pixel circuit are the same, and will not be described again here. Figure 15 The second stage S2 in the operation of the pixel circuit Figure 12 The second stage S2 in the operation process of the pixel circuit is different.

[0240] In the second stage S2, the signal at the first scan signal terminal G1 is high, the signal at the fourth scan signal terminal G4 is low, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 is turned on, and the signal at the first data signal terminal Data1 is written to the third node N3. The signal at the fifth scan signal terminal G5 is high, the signal at the second control signal terminal S2 is written to the first node N1, the first transistor T1 is turned on, providing drive current to the first node N1, the signal at the second scan signal terminal G2 is high, the second data signal terminal Data2 outputs a data voltage, the sixth transistor T6 is turned on, and the signal at the second data signal terminal Data2 is written to the fifth node N5. In this stage, the voltage value of the signal at the fifth node N5 is Vdata2, which is the voltage value of the signal at the second data signal terminal. Under the bootstrap effect of the second capacitor C2, the voltage value of the signal at the fourth node N4 is V1-V2+Vdata2, and the light-emitting element L does not emit light.

[0241] Figure 15 This explanation uses the example of the first capacitor C1 being electrically connected to the third node N3 and the first node N1. When the first capacitor C1 is electrically connected to the third node N2 and the third power supply terminal VSS, Figure 19 The same applies to the work sequence.

[0242] The current control sub-circuit in this disclosure is configured to control the voltage amplitude of the control electrode of the first transistor, which can control the brightness amplitude of the light-emitting element L; the time control sub-circuit controls the duration for which the voltage of the control electrode of the first transistor is maintained at that amplitude, which can control the light-emitting time of the light-emitting element L.

[0243] In this disclosure, the first electrode of the light-emitting element and the control electrode of the first transistor are in a source-follower relationship.

[0244] This disclosure controls the turn-on time of the fifth transistor T5 based on the signal from the second data signal terminal Data2, thereby controlling the light-emitting time of the light-emitting element L.

[0245] The following is through Figure 14 The operation of the example pixel circuit during the non-display phase illustrates an exemplary embodiment of this disclosure. Figure 14 The following explanation uses N-type transistors as an example, specifically transistors T1, T2, T4, T5, T5, and T9. Figure 14 The pixel circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5 to a ninth transistor T9, two capacitors C (first capacitor C1 and second capacitor C2), and 11 signal terminals (first data signal terminal Data1, second data signal terminal Data2, first scan signal terminal G1, second scan signal terminal G2, third scan signal terminal G3, fifth scan signal terminal G5, first control signal terminal S1, reset signal terminal Reset, first initial signal terminal INIT1, second initial signal terminal INIT2, and first power supply terminal VDD). Figure 20 for Figure 14 The provided timing diagram shows the operation of the pixel circuit during the non-display phase.

[0246] Combination Figure 14 and Figure 20 The operation of the pixel circuit in the non-display stage can include: the signal of the first scan signal terminal G1 is a high-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 is turned on, the signal of the first data signal terminal Data1 is written to the third node N3 through the turned-on second transistor T2, the first transistor T1 is turned on, the signal of the first power supply terminal VDD is charged to the first node N1 through the turned-on first transistor T1 until the voltage value of the signal of the first node N1 is Vdata1-Vth1, where Vdata1 is the voltage value of the signal of the first data signal terminal Data, and Vth1 is the threshold voltage of the first transistor. At this time, the first transistor T1 is turned off, the signal of the fifth scan signal terminal G5 is a high-level signal, the fourth transistor T4 is turned on, and the signal of the first node N1 is read to the second control signal terminal S2.

[0247] This disclosure reads the signal of the first node N1 to the second control signal terminal S2, and obtains the threshold voltage Vth1 of the first transistor from the second control signal terminal S2. The data signal of the first data signal terminal Data1 in the display stage is externally compensated based on the threshold voltage Vth1 of the first transistor.

[0248] The following is through Figure 15 The operation of the example pixel circuit during the non-display phase illustrates an exemplary embodiment of this disclosure. Figure 15 This explanation uses an example where transistors T1, T2, T4, T5 through T9 are N-type transistors, and transistor T3 is a P-type transistor. Figure 15The pixel circuit includes transistors T1 to T9, two capacitors C (first capacitor C1 and second capacitor C2), and 12 signal terminals (first data signal terminal Data1, second data signal terminal Data2, first scan signal terminal G1, second scan signal terminal G2, third scan signal terminal G3, fourth scan signal terminal G4, fifth scan signal terminal G5, first control signal terminal S1, reset signal terminal Reset, first initial signal terminal INIT1, second initial signal terminal INIT2, and first power supply terminal VDD). Figure 21 for Figure 15 The provided timing diagram shows the operation of the pixel circuit during the non-display phase.

[0249] Combination Figure 15 and Figure 21 The operation of the pixel circuit in the non-display stage can include: the signal of the first scan signal terminal G1 is a high-level signal, the signal of the fourth scan signal terminal G2 is a low-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 is turned on, the signal of the first data signal terminal Data1 is written to the third node N3 through the turned-on second transistor T2, the first transistor T1 is turned on, the signal of the first power supply terminal VDD is charged to the first node N1 through the turned-on first transistor T1 until the voltage value of the signal of the first node N1 is Vdata1-Vth1, where Vdata1 is the voltage value of the signal of the first data signal terminal Data, and Vth1 is the threshold voltage of the first transistor. At this time, the first transistor T1 is turned off, the signal of the fifth scan signal terminal G5 is a high-level signal, the fourth transistor T4 is turned on, and the signal of the first node N1 is read to the second control signal terminal S2.

[0250] This disclosure reads the signal of the first node N1 to the second control signal terminal S2, and obtains the threshold voltage Vth1 of the first transistor from the second control signal terminal S2. The data signal of the first data signal terminal Data1 in the display stage is externally compensated based on the threshold voltage Vth1 of the first transistor.

[0251] This disclosure also provides a method for driving a pixel circuit, configured to drive the pixel circuit located in a display substrate, the display substrate including a display stage and a non-display stage. The method for driving the pixel circuit provided in this disclosure may include the following steps:

[0252] Step 100: During the display phase and the non-display phase, the current control sub-circuit, under the control of the first scan signal terminal, the first data signal terminal and the first power supply terminal, provides drive current to the first node.

[0253] Step 200: During the display phase, the duration control sub-circuit, under the control of the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal, and the second initial signal terminal, provides the first node's signal to the second node.

[0254] The pixel circuit is the same as the pixel circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0255] The pixel circuit may further include a node control sub-circuit. In one exemplary embodiment, the driving method for the pixel circuit may further include the following steps:

[0256] During the display phase, the node control sub-circuit, under the control of the fifth scan signal terminal, provides the signal from the second control signal terminal to the first node;

[0257] During the non-display phase, the node control sub-circuit, under the control of the fifth scan signal terminal, reads the signal of the first node to the second control signal terminal.

[0258] This disclosure also provides a display substrate, which includes a display area and a non-display area surrounding at least one side of the display area. The display area is provided with a plurality of pixels, and pixel circuits are provided within each pixel.

[0259] In one exemplary embodiment, the shape of the display area can be square, circular, or rounded rectangle, etc., and this disclosure does not limit it in any way.

[0260] The pixel circuit is the same as the pixel circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0261] The display substrate described in this embodiment can be used in display products of any resolution.

[0262] In one exemplary embodiment, when the pixel circuit includes a node control sub-circuit, the display substrate further includes a first chip connected to a second control signal terminal and a second chip connected to a first data signal terminal. The first chip is configured to provide a signal to the second control signal terminal during a display phase, and to read the signal passing through the second control signal terminal during a non-display phase. It is also configured to obtain a threshold voltage of a first transistor based on the signal from the second control signal terminal, generate a control signal based on the threshold voltage of the first transistor, and send the control signal to the second chip. The second chip provides a signal to the first data signal terminal based on the control signal.

[0263] This disclosure allows for external compensation of the first data signal terminal using the first chip, which can improve the lifespan of the display substrate and enhance its display performance.

[0264] This disclosure also provides a display device, including a display substrate.

[0265] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0266] In one exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0267] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0268] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0269] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel circuit, comprising: A driving circuit and a light-emitting element, wherein the driving circuit and the light-emitting element are connected in series between a first power supply terminal and a second power supply terminal; The driving circuit is used to provide driving current and control the conduction time of the current path between the first power supply terminal and the second power supply terminal. The light-emitting element is used to receive the driving current in the current path and emit light; The driving circuit includes: a current control sub-circuit and a duration control sub-circuit; The current control sub-circuit is electrically connected to the first scan signal terminal, the first data signal terminal, the first power supply terminal, and the first node, respectively, and is configured to provide drive current to the first node under the control of the first scan signal terminal, the first data signal terminal, and the first power supply terminal; The duration control sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal and the second initial signal terminal, the first node and the second node, respectively, and is configured to provide the first node's signal to the second node under the control of the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal and the second initial signal terminal; The light-emitting element is electrically connected to the second node and the second power supply terminal, respectively. When the reset signal terminal is an active level signal, the signals of the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal are invalid level signals. When the signal at the first scan signal terminal is a valid level signal, the signal at the second scan signal terminal is a valid level signal, and the signals at the reset signal terminal and the third scan signal terminal are invalid level signals; When the signal at the third scan signal terminal is a valid level signal, the signals at the reset signal terminal, the second scan signal terminal, and the first scan signal terminal are invalid level signals. The signal at the first control signal terminal is a ramp signal; The voltage values ​​of the signals at the first initial signal terminal and the second initial signal terminal are constant.

2. The pixel circuit according to claim 1, wherein, The current control sub-circuit is also electrically connected to the fourth scan signal terminal and is configured to provide drive current to the first node under the control of the first scan signal terminal, the fourth scan signal terminal, the first data signal terminal, and the first power supply terminal.

3. The pixel circuit according to claim 2, wherein, When the signal at the first scanning signal terminal is a valid level signal, the signal at the fourth scanning signal terminal is also a valid level signal.

4. The pixel circuit according to any one of claims 1 to 3, wherein, The driving circuit also includes: a node control sub-circuit; The node control sub-circuit is electrically connected to the fifth scan signal terminal, the second control signal terminal and the first node respectively, and is configured to provide the signal of the second control signal terminal to the first node under the control of the fifth scan signal terminal, or read the signal of the first node to the second control signal terminal; The voltage value of the signal at the second control signal terminal is constant.

5. The pixel circuit according to claim 4, wherein, When the signal at the first scanning signal terminal is a valid level signal, the signal at the fifth scanning signal terminal is also a valid level signal.

6. The pixel circuit according to claim 1, wherein, The current control sub-circuit includes: a first write sub-circuit, a first storage sub-circuit, and a drive sub-circuit; The first write sub-circuit is electrically connected to the first scan signal terminal, the first data signal terminal, and the third node, respectively, and is configured to provide the signal from the first data signal terminal to the third node under the control of the first scan signal terminal; The first storage sub-circuit is electrically connected to the third node and the third power supply terminal respectively, and is configured to store the voltage difference between the signals of the third node and the third power supply terminal; or, it is electrically connected to the first node and the third node respectively, and is configured to store the voltage difference between the signals of the first node and the third node. The driving sub-circuit is electrically connected to the first power supply terminal, the first node, and the third node, respectively, and is configured to provide driving current to the first node under the control of the third node and the first power supply terminal.

7. The pixel circuit according to claim 2, wherein, The current control sub-circuit includes: a first write sub-circuit, a first storage sub-circuit, and a drive sub-circuit; The first write sub-circuit is electrically connected to the first scan signal terminal, the fourth scan signal terminal, the first data signal terminal, and the third node, respectively, and is configured to provide the signal of the first data signal terminal to the third node under the control of the first scan signal terminal and the fourth scan signal terminal; The first storage sub-circuit is electrically connected to the third node and the third power supply terminal respectively, and is configured to store the voltage difference between the signals of the third node and the third power supply terminal; or, it is electrically connected to the first node and the third node respectively, and is configured to store the voltage difference between the signals of the first node and the third node. The driving sub-circuit is electrically connected to the first power supply terminal, the first node, and the third node, respectively, and is configured to provide driving current to the first node under the control of the third node and the first power supply terminal.

8. The pixel circuit according to claim 6 or 7, wherein, The first storage sub-circuit includes a first capacitor, and the driving sub-circuit includes a first transistor; The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node. One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node.

9. The pixel circuit according to claim 6, wherein, The first write sub-circuit includes: a second transistor; The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node.

10. The pixel circuit according to claim 7, wherein, The first write sub-circuit includes: a second transistor and a third transistor; The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the fourth scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the third node. The second transistor and the third transistor are of different transistor types.

11. The pixel circuit according to claim 4, wherein, The node control sub-circuit includes: a fourth transistor; The control terminal of the fourth transistor is electrically connected to the fifth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the second control signal terminal, and the second terminal of the fourth transistor is connected to the first node.

12. The pixel circuit according to claim 1, wherein, The duration control subcircuit includes: a second write subcircuit, a second storage subcircuit, a reset subcircuit, and an output control subcircuit; The second storage sub-circuit is electrically connected to the fourth node and the fifth node respectively, and is configured to store the voltage difference between the signals of the fourth node and the fifth node; The second write sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, and the fifth node, respectively. It is configured to provide the second data signal terminal to the fifth node under the control of the second scan signal terminal, and to provide the first control signal terminal to the fifth node under the control of the third scan signal terminal. The reset sub-circuit is electrically connected to the reset signal terminal, the first initial signal terminal, the second initial signal terminal, the fourth node, and the fifth node, respectively. Under the control of the reset signal terminal, it provides the signal from the first initial signal terminal to the fourth node and the signal from the second initial signal terminal to the fifth node. The output control sub-circuit is electrically connected to the first node, the second node, and the fourth node, respectively, and is configured to provide the signal of the first node to the second node under the control of the fourth node.

13. The pixel circuit according to claim 12, wherein, The output control sub-circuit includes a fifth transistor, and the second storage sub-circuit includes a second capacitor; The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node. One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node.

14. The pixel circuit according to claim 12, wherein, The second write sub-circuit includes: a sixth transistor and a seventh transistor; The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node.

15. The pixel circuit according to claim 12, wherein, The reset circuit includes: an eighth transistor and a ninth transistor; The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node. The control terminal of the ninth transistor is electrically connected to the reset signal terminal, the first terminal of the ninth transistor is electrically connected to the second initial signal terminal, and the second terminal of the ninth transistor is electrically connected to the fifth node.

16. The pixel circuit according to claim 1, wherein, The current control sub-circuit includes: a first transistor, a second transistor, and a first capacitor; the duration control sub-circuit includes: a fifth transistor to a ninth transistor and a second capacitor. The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node. The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node. One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node. One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node. The first transistor, the second transistor, and the fifth to ninth transistors are all of the same type and are all metal-oxide-semiconductor transistors.

17. The pixel circuit according to claim 2, wherein, The current control sub-circuit includes: a first transistor, a second transistor, a third transistor, and a first capacitor; the duration control sub-circuit includes: a fifth transistor to a ninth transistor and a second capacitor. The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the fourth scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node. The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node. One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node. One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node. The first transistor, the second transistor, and the fifth through ninth transistors are of the same type, and are the opposite type to the third transistor; The transistors of the first transistor, the second transistor, the third transistor, and the fifth to ninth transistors are all metal-oxide-semiconductor transistors.

18. The pixel circuit according to claim 4, wherein, The driving circuit further includes: a node control sub-circuit, the current control sub-circuit includes: a first transistor, a second transistor and a first capacitor, the node control sub-circuit includes: a fourth transistor, and the duration control sub-circuit includes: a fifth transistor to a ninth transistor and a second capacitor; The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node. The control terminal of the fourth transistor is electrically connected to the fifth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the second control signal terminal, and the second terminal of the fourth transistor is connected to the first node. The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node. The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node. One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node. One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node. The first transistor, the second transistor, the fourth transistor, and the ninth transistor are all of the same type and are all metal-oxide-semiconductor transistors.

19. The pixel circuit according to claim 4, wherein, The driving circuit further includes: a node control sub-circuit; the current control sub-circuit includes: a first transistor, a second transistor, a third transistor and a first capacitor; the node control sub-circuit includes: a fourth transistor; and the duration control sub-circuit includes: a fifth transistor to a ninth transistor and a second capacitor. The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the fourth scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the third node. The control terminal of the fourth transistor is electrically connected to the fifth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the second control signal terminal, and the second terminal of the fourth transistor is connected to the first node. The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node. The control terminal of the seventh transistor is electrically connected to the third scan signal terminal, the first terminal of the seventh transistor is electrically connected to the first control signal terminal, and the second terminal of the seventh transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the reset signal terminal, the first electrode of the eighth transistor is electrically connected to the first initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node. The control electrode of the ninth transistor is electrically connected to the reset signal terminal, the first electrode of the ninth transistor is electrically connected to the second initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node. One plate of the first capacitor is electrically connected to the third node, and the other plate of the first capacitor is electrically connected to the third power supply terminal or the first node. One plate of the second capacitor is electrically connected to the fourth node, and the other plate of the second capacitor is electrically connected to the fifth node. The first transistor, the second transistor, the fourth transistor through the ninth transistor are of the same type, and are the opposite type to the third transistor; The transistors from the first to the ninth transistor are all metal-oxide-semiconductor transistors.

20. The pixel circuit according to claim 1, wherein, The light-emitting element includes: a micro light-emitting diode or a mini light-emitting diode.

21. A display substrate, comprising: A display area and a non-display area surrounding at least one side of the display area, the display area having a plurality of pixels, and each pixel having a pixel circuit as described in any one of claims 1 to 20.

22. The display substrate according to claim 21, wherein, When the pixel circuit includes a node control sub-circuit, the display substrate further includes a first chip connected to the second control signal terminal and a second chip connected to the first data signal terminal. The first chip is configured to provide a signal to the second control signal terminal during the display phase, and to read the signal through the second control signal terminal during the non-display phase. It is also configured to obtain the threshold voltage of the first transistor based on the signal from the second control signal terminal, generate a control signal based on the threshold voltage of the first transistor, and send the control signal to the second chip. The second chip provides a signal to the first data signal terminal according to the control signal.

23. A display device, comprising: The display substrate as described in claim 21 or 22.

24. A method for driving a pixel circuit, configured to drive the pixel circuit as described in any one of claims 1 to 20, wherein the pixel circuit is located in a display substrate, the display substrate comprising: The method includes a display phase and a non-display phase: During the display and non-display phases, the current control sub-circuit provides drive current to the first node under the control of the first scan signal terminal, the first data signal terminal, and the first power supply terminal. During the display phase, the duration control sub-circuit, under the control of the second scan signal terminal, the third scan signal terminal, the second data signal terminal, the first control signal terminal, the reset signal terminal, the first initial signal terminal, and the second initial signal terminal, provides the first node's signal to the second node.

25. The method according to claim 24, wherein, The pixel circuit further includes a node control sub-circuit, and the method further includes: During the display phase, the node control sub-circuit, under the control of the fifth scan signal terminal, provides the signal from the second control signal terminal to the first node; During the non-display phase, the node control sub-circuit, under the control of the fifth scan signal terminal, reads the signal of the first node to the second control signal terminal.

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