Electrical load simulator for the inverter under test

Abstract

An electric load simulator ELE (1) for an inverter under test IUT (2), wherein an IUT output voltage VIUT at an IUT output terminal (10) is used to take a plurality of IUT voltage states, the plurality of IUT voltage states are separated by rising edges and falling edges, and an ELE output voltage at an ELE output terminal is used to take a plurality of ELE voltage states, the plurality of ELE voltage states are separated by rising edges and falling edges, and wherein each IUT voltage state corresponds to at least one ELE voltage state. The ELE (1) comprises a current sensor (3) for measuring an IUT output current IIUT, a coupling filter (4) for connecting the ELE (1) to the IUT (2), a voltage sensing unit (5) for measuring the IUT output voltage VIUT, and a control unit (6) for determining a reference current IREF corresponding to a simulated electric load according to the measured IUT output voltage VIUT, and comparing the reference current IREF with the measured IUT output current IIUT.

Description

Technical Field

[0001] The present disclosure relates to an electrical load emulator for an inverter under test. Background Art

[0002] Inverters are widely used to drive electrical loads such as motors or electrical power networks. There are usually two options for testing the inverter under test (IUT). The first option consists in using a test bench consisting of an electrical load. For example, in the case where the inverter is used to drive an electric motor, the test bench is a motor test bench comprising a matched motor and a load motor coupled to the matched motor. During the test, the inverter is connected to its matched motor. The matched motor is coupled to the load motor, which can provide the required torque load and absorb the mechanical power generated by the matched motor. This setup allows testing the inverter in almost real usage situations, but it is expensive, inflexible and time-consuming for testing different inverters and motors.

[0003] The second approach is to test the inverter using an electrical load emulator (ELE). For example, the ELE can be a motor simulator, which simulates the electrical behavior of a real motor. This testing approach falls into the category of power hardware-in-the-loop testing (PHiL). For example, some of the advantages of a motor simulator include:

[0004] -Flexibility: For motor test benches, each time before applying a new motor, the test setup should be changed and calibrated. This is a big problem, because one inverter manufacturer usually makes inverters for dozens of different motors. In contrast, a motor simulator can simulate almost all kinds of motors using the same hardware setup. To test a new motor, only a slight change in the motor simulator's software is required;

[0005] -Safety: Since the motor simulator does not have any mechanical parts, there is no kinetic energy or vibration during testing. Therefore, testing with a motor simulator is safer than with a motor test bench. At the same time, fault conditions can be tested non-destructively;

[0006] - Accelerate the design process: Motor simulators can greatly accelerate the design process of drive systems, especially in global collaboration. For example, if a European motor manufacturer plans to integrate an inverter into the drive system, it may be necessary to send test samples of the motor or inverter by the supplier to build a motor test bench. The motor should be fully designed and fully manufactured.

[0007] When using a motor simulator, the motor manufacturer only needs to send detailed motor data. A test bench using a motor simulator can be up and running within an hour and the test results can be sent back on the same day. Therefore, the drive system can be tested already during the design phase of the motor, which in turn helps design a dedicated motor for the drive system.

[0008] There are already power load simulator systems and they are available on the market. Document US2021 / 0036646A1 discloses an embodiment related to a motor simulator for an inverter under test (IUT), the motor simulator comprising: a voltage follower inverter for at least partially offsetting an output voltage of the IUT; and an output current control unit for controlling an output current of the IUT according to an estimated current of a simulated target motor.

[0009] Despite these advantages, most known ELEs involve complex control strategies, complex filter structures, or galvanically isolated power supplies. This results in more complex hardware topologies, higher cost and weight, and reduced portability of the ELE. An example of an ELE that is particularly suitable for simulating the dynamic operation of an electrical load is simulating power transients of the load at different time periods.

[0010] There is a need for an ELE suitable for dynamically emulating electrical loads while reducing complexity and cost. The present invention relates to a low-cost ELE that can be built using standard, low-volume components while being able to emulate load transients. Summary of the invention

[0011] The present invention provides an electrical load emulator (ELE) for an inverter under test (IUT), wherein an IUT output voltage V IUT The ELE output voltage at the ELE output terminal is used to adopt a plurality of IUT voltage states separated by the IUT rising edge and the falling edge, and each IUT voltage state corresponds to at least one ELE state. The ELE includes a circuit for measuring the IUT output current I IUT A current sensor, a coupling filter for connecting the ELE to the IUT, and a voltage sensor for sensing the output voltage V of the IUT IUT The ELE also includes a control unit for outputting a voltage V according to the sensed IUT. IUT To determine the reference current I corresponding to the simulated electrical load REF and compare the reference current with the measured IUT output current I IUT For comparison, the characteristics of ELE are:

[0012] -If I REF Basically equal to IIUT , the control unit is used to control the output voltage of the ELE to synchronously follow the output voltage of the IUT, so that each rising edge and / or falling edge of the IUT between two subsequent IUT voltage states is followed by a corresponding ELE rising edge and / or falling edge between two subsequent ELE voltage states;

[0013] -If I REF Higher than I IUT , the control unit is used to delay the subsequent ELE rising edge by a rising edge time relative to its corresponding IUT rising edge;

[0014] -If I REF Below I IUT , the control unit is used to delay the subsequent ELE falling edge by a falling edge time relative to its corresponding IUT falling edge.

[0015] Preferably, each phase coupling filter of the ELE of the present invention may include at least one series inductor L F , more preferably, only the series inductor L F .

[0016] Preferably, the ELE inverter of the present invention has a two-level topology or a multi-level topology.

[0017] Preferably, the ELE inverter of the present invention is adapted to be powered by a DC power source that is shared with the IUT.

[0018] Preferably, the control unit of the ELE of the present invention is used to:

[0019] According to the measured IUT output voltage V IUT , to determine the reference current I corresponding to the simulated electrical load REF ;

[0020] The reference current I REF The measured IUT output current I REF and compare with the IUT output voltage V IUT Asynchronously calculate the time delay of the rising or falling edge.

[0021] Preferably, the control unit is used to:

[0022] Based on the IUT output voltage V measured periodically at the second frequency F2 IUT , to determine the reference current I corresponding to the simulated electrical load REF. Preferably, the second frequency F2 is between one third of the switching frequency of the IUT and 300 MHz, more preferably between the switching frequency of the IUT and 100 MHz, more preferably between 2 and 50 MHz, and more preferably between 3 and 10 MHz;

[0023] The reference current I REF The measured IUT output current I IUT Compare and periodically calculate the time delay of the rising edge or the falling edge with the third frequency F3, wherein the third frequency F3 is preferably lower than or equal to the second frequency F2, more preferably between 100 Hz and 100 MHz, more preferably between 1 kHz and 20 MHz, more preferably between 10 kHz and 10 MHz, more preferably between 1 MHz and 5 MHz.

[0024] The present invention provides a method for controlling an electric load emulator (ELE) for testing an inverter under test (IUT), wherein an IUT output voltage V IUT For adopting a plurality of IUT voltage states separated by IUT rising and falling edges, the method comprising:

[0025] - Sense the IUT output voltage V at the IUT output IUT ;

[0026] - Based on the sensed IUT output voltage V IUT , determine the reference current I corresponding to the simulated electrical load REF ;

[0027] -Measure the IUT output current I IUT ;

[0028] - Set the reference current I REF The measured IUT output current I IUT Make a comparison.

[0029] -If I REF Basically equal to I IUT , then the output voltage of ELE is controlled to synchronously follow the output voltage of IUT V IUT Thus, each IUT rising edge and / or falling edge between two subsequent IUT voltage states corresponds to a rising edge and / or falling edge of the ELE between two subsequent ELE voltage states.

[0030] -If I REF Higher than I IUT , then relative to its corresponding IUT rising edge, the subsequent ELE rising edge is delayed by one rising edge time;

[0031] -If I REF Below I IUT , then the subsequent ELE falling edge will be delayed by one falling edge time relative to its corresponding IUT falling edge.

[0032] The present invention also provides a programmable hardware for controlling an electric load emulator (ELE), the electric load emulator (ELE) being used to test an inverter under test (IUT), the programmable hardware being used to make the ELE perform the method according to the present invention, wherein the programmable hardware is a programmable logic device, such as an FPGA, an EPROM or a microcontroller. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The features, aspects and advantages of the devices, systems and methods of the present invention will be better understood from the following description and accompanying drawings, in which:

[0034] Figure 1 Schematically represents a system consisting of an ELE and an IUT according to the present invention, wherein power connections are represented by continuous lines and control signal connections are represented by dashed lines;

[0035] Figure 2 It shows a three-phase ELE inverter connected to a three-phase IUT through a coupling filter;

[0036] Figure 3 Schematically showing a single-phase coupled filter connected to an IUT and an ELE, the single-phase coupled filter comprising only series-connected elements;

[0037] Figure 4 When I REF Basically equal to I IUT When the output variables of IUT and ELE and the reference current I REF Graphs of changes over time;

[0038] Figure 5 When I REF I REF Higher than I IUT When the output variables of IUT and ELE and the reference current I REF Graphs of changes over time;

[0039] Figure 6 When I REF Below I IUT When the output variables of IUT and ELE and the reference current I REF A graph showing changes over time.

[0040] The accompanying drawings are neither drawn to scale nor are they to proportion. Generally speaking, like parts are indicated by like reference numerals in the drawings. DETAILED DESCRIPTION

[0041] The terms used to describe specific embodiments are not meant to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates. The term "and / or" includes any and all combinations of one or more related listed items. It is understood that the terms "include" and / or "include" indicate the presence of the features, but do not exclude the presence or increase of one or more other features. It is further understood that when a particular step of a method is referred to as a follow-up to another step, it can directly follow the other step, or one or more intermediate steps can be performed before performing the particular step, unless otherwise specified. Similarly, it is understood that when describing the connection between structures or components, unless otherwise specified, such connection can be established directly or through intermediate structures or components.

[0042] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the present invention is not limited thereto. The drawings described are only schematic and non-limiting. In the drawings, for the purpose of illustration, the size of some elements may be exaggerated and not drawn to scale.

[0043] The term "comprising" used in this specification does not exclude other elements or steps.

[0044] In addition, the term first, second, third and similar terms in the specification are used to distinguish similar elements and are not necessarily used to describe order or time sequence. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, and the embodiments of the present invention described herein can be operated in other orders compared to the description or illustration herein.

[0045] The terms "approximately" and "approximately" are synonymous and are used to indicate that the value modified by the term has an understanding range associated with it, where the range can be +20%, +15%, +10%, +5% or +1%. The term "substantially" is used to indicate that a result (e.g., a measurement) is close to a target value, where close can mean, for example, that the result is within 80% of the value, within 90% of the value, within 95% of the value, or within 99% of the value. Substantially equal values ​​can be understood as values ​​that differ by at most 20%, or 10%, or 5% or 1%.

[0046] The present invention will be described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. In the accompanying drawings, the absolute and relative sizes of systems, components, layers and regions may be exaggerated for clarity. The embodiments may be described with reference to schematic and / or cross-sectional illustrations of possible idealized embodiments and intermediate structures of the invention. In the specification and drawings, like numbers refer to similar elements throughout. Relative terms and their derivatives should be understood to refer to the direction being described at the time or the direction shown in the figure being discussed. These relative terms are for convenience of description and do not require that the system be constructed or operated in a particular direction unless otherwise specified.

[0047] Electrical Load Emulator (ELE)

[0048] Figure 1 An example of an electrical load emulator (1) according to the present invention, here called ELE, is coupled to an inverter under test (2), here called IUT. The ELE (1) comprises an ELE inverter (7) and a coupling filter (4), the coupling filter (4) being used to connect the ELE inverter (7) to the IUT (2).

[0049] like Figure 1 As shown, a DC power source (8) is connected to the IUT (2) and provides power to it. Figure 1 In one example of the invention shown, the ELE (1) is used to share a DC power supply (8) with an IUT (2). In this case, the size of the DC power supply (8) can be reduced because it should only provide the combined losses of the ELE (1) and the IUT (2), which is usually much lower than the peak power of the IUT (1) and the ELE (2) considered separately. In another example, the ELE (1) of the invention can be used to connect to a DC power supply of the ELE, which is separate from the DC power supply (8) that powers the IUT.

[0050] Current Sensors

[0051] like Figure 1 As shown, the ELE of the present invention comprises a current sensor (3) for measuring the IUT output current I flowing from the IUT output terminal. IUT , and generates a current I representing the measured IUT output current IUT For example, the current sensor (3) can be installed at the output of the IUT or built into the ELE inverter (7).

[0052] Voltage sensing unit

[0053] The ELE comprises a voltage sensing unit (5) for sensing an IUT output voltage V at an IUT output terminal.IUT , and generates a voltage V representing the sensed IUT output IUT The voltage sensing unit outputs a signal.

[0054] For example, the voltage sensing unit (5) may include a voltage comparator coupled or connected to the IUT output terminal, and the voltage sensing unit output signal represents the IUT output voltage V IUT In this example, the ELE (1) is used to determine an estimated IUT output voltage based on at least the voltage sensing unit output signal from the voltage comparator. More preferably, the ELE (1) is used to determine an estimated IUT output voltage based on the voltage sensing unit output signal and a voltage representing the measured IUT output current I IUT This allows the ELE (1) to more accurately determine the IUT output voltage because the ELE can be used to determine the IUT output voltage V based on both the voltage drop across the conducting IUT IGBT (e.g., and based on the forward voltage of the anti-parallel diode of the IUT IGBT). IUT Preferably, the ELE (1) is configured to periodically determine the estimated IUT output voltage V IUT .

[0055] In another example, the voltage sensing unit (5) may include a voltage measurement sensor for measuring the IUT output voltage V IUT The output signal of the voltage sensing unit represents V IUT In another example, the voltage sensing unit (5) may include an edge detector (preferably an emulated edge detector) for continuously operating and detecting the IUT output voltage V IUT rising and falling edges.

[0056] The ELE (1) further comprises a control unit (6), which is connected to the ELE inverter (7) and the current sensor (3) and the voltage sensing unit (5). The control unit (6) is used to receive the output signal of the current sensor and the output signal of the voltage sensing unit, and output a current I according to the measured IUT. IUT and the induced IUT output voltage V IUT (i.e., according to the output signal of the voltage sensing unit and the output signal of the current sensor) to control the ELE inverter (7).

[0057] Inverter under test (IUT)

[0058] ELE (1) is used to simulate the load of the IUT, wherein the IUT output voltage V IUTis a switched output voltage (i.e., takes multiple IUT voltage states separated by IUT rising edges and IUT falling edges). The IUT falling and rising edges correspond to transients in the IUT output voltage caused by a change in state of the IUT switch (i.e., the IUT switch moves from an open position to a closed position, or vice versa).

[0059] Figure 4 shows the IUT output voltage V IUT An example of change over time. Figure 4 V IUT Can be Figure 2 A phase leg of the two-level inverter shown in FIG. Figure 4 In the example, there is a first IUT voltage state (2s) and a second IUT voltage state (2s), corresponding to the time interval when the IUT output voltage is approximately constant. The amplitude of the first IUT voltage state is null, while the amplitude of the second IUT voltage state is equal to the output voltage of the DC power supply (8) used to power the IUT (2). Generally speaking, the first IUT voltage state can be DC- or low potential, while the second IUT voltage state can be DC+ or high potential. The IUT voltage state (2s) is separated by the IUT rising edge (2r) and the IUT falling edge (2f). Of course, the skilled person should easily recognize that Figure 4 The voltage and current signals shown in are idealized signals and do not limit the scope of the present invention. IUT and V ELE These signals may contain noise, ripples, and the rising and falling edges of IUT and ELE have finite slopes. Figure 4 There is no indication in . Figure 4 Parasitic delays are not shown either. IUT More than two IUT voltage states may also be included, for example, if the IUT has a multi-level topology. For example, the IUT may have a neutral-point clamped topology where the IUT output voltage V IUT Switch between DC-potential, zero potential and DC+potential. Figure 2 As shown, the IUT may be a multi-phase IUT comprising a plurality of IUT inverter phase legs, each phase leg providing an IUT output voltage at a respective IUT output terminal (10) connected thereto.

[0060] The switching output voltage of the IUT may include modulation, PWM (such as variable switching frequency PWM), or direct torque control.

[0061] ELE Inverter(7)

[0062] The ELE (1) of the present invention comprises an ELE inverter (7). The ELE inverter (7) comprises at least one ELE inverter phase leg (71) having a plurality of switch units (7s). It may have one, two, three, four or more ELE inverter phase legs. Figure 2 The ELE inverter (7) of the present invention includes an example of three two-stage ELE inverter phase legs (71), wherein each phase leg includes two ELE switch units (7s), wherein the central nodes of the ELE inverter phase legs are connected to respective ELE output terminals (9). The ELE output terminals (9) are used to connect the ELE inverter (7) to the coupling filter (4). The ELE inverter (7) may also be one (for providing more than two ELE output voltages V ELE voltage level) multi-level inverter.

[0063] The ELE (1) is used to command the ELE switch unit (7s) to provide an ELE output voltage V at each ELE output terminal (9). ELE , it takes multiple ELE voltage states (1s) (i.e., ELE voltage levels) separated in time by ELE rising edges (1r) and ELE falling edges (1f). Therefore, the output voltage V ELE is a switched output voltage. The ELE falling edge and rising edge correspond to the ELE output voltage transient after the ELE inverter switching state changes, and the ELE voltage state corresponds to the specific state of the ELE switch unit (7s).

[0064] exist Figure 4 In the figure, an ELE output voltage V ELE Example of time variation. This is a two-level voltage at one terminal (9) of the ELE. As with the IUT (2), a skilled person should easily recognize that Figure 4 The ELE output voltage V ELE is an idealized signal and should not limit the scope of the present invention. ELE The noise, ripple and other parasitic signal components that may exist in the ELE are not shown. The rising edge (1r) and falling edge (1f) of the ELE have a finite slope, which Figure 4 It is not shown in the V ELE More than two ELE voltage states may also be included, for example if the ELE inverter (7) has a multi-level topology.

[0065] ELE and IUT voltage status

[0066] ELE(1) is used to provide ELE output voltage V ELE, wherein each IUT voltage state (2s) corresponds to a substantially equal ELE voltage state (1s), so that the voltage on the coupling filter (4) connecting the ELE output terminal (9) and the IUT output terminal (10) can be substantially offset. Preferably, the ELE (1) is used to provide the ELE output voltage V ELE , where the number of different ELE voltage states is the same as the number of different IUT voltage states.

[0067] The ELE (1) may include a multi-level ELE inverter adapted to provide a greater number of different ELE voltage states (1s) than a greater number of different IUT voltage states (2s). In this case, the ELE (1) may be used to command the switch unit (7s) to provide only a smaller number of ELE voltage states (1s), wherein each of the smaller number of ELE voltage states is substantially equal to one of the different IUT voltage states (2s).

[0068] Coupling Filters(4)

[0069] like Figure 2 and 3 As shown, the ELE (1) comprises a coupling filter (4) connected to the ELE output terminal (9) and the IUT output terminal (10). The coupling filter (4) of the ELE of the present invention may include one or more phases, preferably without cross coupling between the phases. Each phase of the coupling filter (4) comprises at least one inductor L connected in series. F , it is best to have only the inductor L in series F Preferably, each phase of the coupling filter (4) comprises only series-connected elements, such as Figure 3 As shown, the filter current I passing through the coupling filter F =IUT output current I flowing from the IUT output terminal (10) IUT and the ELE output current I entering the ELE output terminal (9) ELE .

[0070] Control Unit(6)

[0071] The control unit (6) of the ELE (1) is used to generate an output voltage V of the IUT according to the output voltage V IUT The voltage sensing unit outputs a signal to determine the reference current I corresponding to the simulated electrical load. REF For example, the simulated electrical load may be a motor or a power network. The ELE (1) may include a model of the simulated electrical load, for example, a motor model for determining the relationship between the phase current of the simulated motor and the phase voltage of the simulated motor. In this case, the phase current of the simulated motor is the calculated reference current I REF, and the phase voltage of the simulated motor is the measured IUT output voltage V IUT Preferably, the control unit (6) in the ELE (1) is configured to periodically determine the reference current I at a second frequency F2. REF Preferably, the second frequency F2 is equal to the first frequency F1. Further preferably, the second frequency F2 may be between one third of the switching frequency of the IUT and 300 MHz, further preferably between the switching frequency of the IUT and 100 MHz, further preferably between 2 and 50 MHz, further preferably between 3 and 10 MHz.

[0072] In an example of the ELE of the present invention, the control unit (6) includes a discrete time calculation circuit, which is used to receive the output signal of the voltage sensing unit and periodically determine the reference current I REF In the ELE of the present invention, this can be accomplished asynchronously with respect to changes in the IUT voltage state at the IUT output.

[0073] The paper IEEE TRANSACTIONS ON POWER ELECTRONICS, Vol. 33, No. 8, AUGUST 2018, pp. 6926-6935 (Digital Object Identifier 10.1109 / TPEL.2017.2759662) describes examples of voltage sensing techniques that can be used in the present invention to detect the IUT output voltage V IUT of sensing.

[0074] The control unit (6) in the ELE (1) is also used to compare the reference current IREF with the measured IUT output current I IUT Preferably, the control unit (6) is used to compare the reference current I REF The latest value of IUT output current I IUT The instantaneous value of the reference current I REF The latest value of is determined by the control unit (6); the IUT output current I IUT The instantaneous value of is measured by the current sensor (3). Preferably, the third frequency F3 is lower than or equal to the second frequency F2. Further preferably, the third frequency F3 is between 100 Hz and 100 MHz, further preferably between 1 kHz and 20 MHz, further preferably between 10 kHz and 10 MHz, further preferably between 1 MHz and 5 MHz. Further preferably, the third frequency F3 is higher than the switching frequency of the IUT, or higher than the frequency at which the IUT refreshes the IUT output current target.

[0075] I REF Basically equal to I IUT

[0076] If I REF Basically equal to I IUT , the control unit (6) can enter the voltage following mode, that is, control the ELE output voltage V ELE Synchronously follow the IUT output voltage V IUT , so that each IUT rising edge and / or falling edge between two subsequent IUT voltage states follows a corresponding ELE rising edge and / or falling edge between two subsequent ELE voltage states, respectively. Figure 4 An example of this mode of operation of the ELE is illustrated in FIG. 1. In this example, the current sensor (3) measures the output current I of the IUT IUT and with the control unit (6) at time instant T i1 、T i2 、T i3 、T i4 The calculated reference current I REF In this case, I REF Basically equal to I IUT , and the control unit (6) is used to command the ELE switch unit (7s) of the ELE inverter (7) to synchronously follow the IUT output voltage with the ELE output voltage, that is, the ELE (1) is used to set the ELE output voltage V ELE is set to be substantially equal to the ongoing IUT voltage state. In other words, the ELE is used to output the voltage V ELE Tracking IUT output voltage V IUT , by changing V ELE The synchronization is set at one of the ELE voltage states which is substantially equal to the ongoing IUT voltage state. Figure 4 It is described in, where, at the time instant T f1 , I IUT Switching from a high IUT voltage state to a low IUT voltage state is detected by a voltage sensing unit of the ELE, and the ELE is used to synchronously switch from a corresponding high ELE voltage state to a corresponding low ELE voltage state, respectively, wherein the high ELE voltage state and the low ELE voltage state are substantially equal to their corresponding high IUT voltage state and low IUT voltage state.

[0077] If I REF Basically equal to I IUT , the control unit (6) is used to control V ELE The voltage state adopted by the ELE synchronously follows V IUT In this case, each IUT voltage state and its synchronously following ELE voltage state are expressed as "corresponding".REF Basically equal to I IUT , the control unit (6) is used to control V ELE The rising and falling edges of ELE are taken synchronously with I IUT In this case, each IUT rising edge or falling edge and its synchronously following ELE rising edge or falling edge are indicated as "corresponding".

[0078] Figure 3 Indicates that a single phase of the coupling filter is connected to one phase of the IUT and one phase of the ELE. REF Basically equal to I IUT When V ELE The ELE voltage state taken synchronously follows that of V IUT The IUT voltage state is taken. This causes V IUT ≈V ELE , and the filter voltage (V F =V IUT -V ELE ) is canceled out at essentially all times, and the filter current I F In one example of the present invention, the coupling filter (4) comprises only one series inductor L F , where the inductor L F The parasitic resistance R P It is best to ignore it. In this case, V F =R P R P *I IUT +L F *dI IUT / dt≈L F *dI IUT / dt≈0, so dI IUT / dt=0.

[0079] Controls discrete and continuous operation of the unit

[0080] In order to minimize the delay of the parasitic time between the rising edge of the IUT and the ELE when the ELE is in the voltage following mode, the control unit (6) may include a continuous time logic unit, which is used to receive the output signal of the voltage sensing unit, wherein the output signal of the voltage sensing unit is a continuous edge detection signal representing the rising edge and the falling edge of the IUT, and the rising edge and the falling edge of the IUT are detected by the voltage sensing unit (5). For example, the continuous time logic unit can be used to control the ELE inverter and the ELE output voltage V according to the continuous edge detection signal. ELE To synchronously follow the IUT output voltage V IUTFor example, the continuous-time logic cell can be an emulation circuit that operates continuously in time, such as an EPROM or FPGA, while the output signal of the voltage sensing cell can be generated by a comparator in the sensing cell that also operates continuously in time. The use of continuous-time logic circuits in combination with comparators can minimize parasitic delays associated with sensing and control in the ELE compared to using (for example) discrete-time control circuits.

[0081] Generally speaking, edge detection is much faster than actual voltage amplitude determination or measurement, and controlling the ELE inverter (7) to replicate the IUT output signal based on the edge detection signal is much faster than based on the voltage amplitude measurement value.

[0082] For example, the ELE of the present invention may include a continuous-time logic circuit for tracking or rapidly replicating the IUT output signal, combined with a slower-reacting discrete-time control circuit for determining the reference current I REF .

[0083] I REF Higher than I IUT

[0084] If I REF Higher than I IUT ,like Figure 5 As shown, the control unit (6) is used to delay the subsequent ELE rising edge by a rising edge time relative to its corresponding IUT rising edge (2r). In the present case, the subsequent ELE rising edge is the ELE rising edge that occurs after the measured IUT output current is compared with the reference current, and the control unit (6) calculates the rising edge time delay to be applied. Preferably, the ELE (1) is used to delay the reference current I REF The measured IUT output current I IUT The comparison is performed and the time delay of the rising edge or the falling edge is periodically calculated at the third frequency F3. Figure 5 In the example, the control unit (6) sets I REF with I IUT Compare and calculate the application at time T i1 、T i2 、T i3 、T i4 Preferably, if Figure 5 As shown, the control unit (6) is used to delay the first ELE rising edge (1r) relative to its corresponding IUT rising edge (2r) so that the IUT output current is quickly adjusted to be close to the reference current. Of course, it should be easily recognized by the technicians that Figure 5 The voltage and current signals shown in are idealized signals and do not limit the scope of the present invention.IUT and V ELE These signals may include noise, ripples, and the rising and falling edges of IUT and ELE have finite slopes. Figure 5 Not shown in . Figure 5 No parasitic delays are shown either.

[0085] If I REF Higher than I IUT , then the control unit (6) is preferably used to control the ELE output voltage V ELE Synchronously follow the IUT output voltage V IUT , as in I REF =I IUT In the case of the ELE rising edge (1r), the ELE rising edge (1r) is delayed by the rising edge time relative to its corresponding IUT rising edge (2r). The delayed ELE rising edge (1r) is compared in the control unit (6) to produce the result I REF >I IUT The ELE rising edge (1r) that appears later, preferably the first ELE rising edge (1r) that appears after the comparison by the control unit (6). In this context, if the ELE is in voltage tracking mode, the corresponding ELE rising edge (1r) is the ELE rising edge that may appear synchronously with the IUT rising edge (2r).

[0086] During the rising edge time delay between the rising edges of ELE and IUT, the IUT output voltage therefore assumes an IUT voltage state that is higher than the ELE voltage state assumed by the ELE output voltage, and the filter voltage V F is positive, IUT output current I IUT In this case, and in the example of the invention, the coupling filter (4) comprises only one series inductor L F , and the inductance L F The parasitic resistance R P can be ignored, V F ≈L F *dI IUT / dt, and d I IUT / dt>0, because V F In this case, the control unit (6) is preferably configured to delay the subsequent ELE rising edge (1r) by a rising edge time Δt=L relative to its corresponding IUT rising edge (2r). F *│I REF -I IUT │ / │V ELE -V IUT │. Among them│I REF -I IUT │ is the absolute value of the difference between the reference current and the measured IUT current, where │VELE -V IUT │ is the absolute value of the difference between the ELE and IUT output voltages, i.e., during the time delay Δt between the following ELE rising edge (1r) and its corresponding IUT rising edge (2r), │V ELE -V IUT │ is the absolute value between the voltages related to the ELE and IUT voltage states.

[0087] I REF Lower than I IUT

[0088] If I REF Below I IUT , the control unit (6) is used to delay one of the subsequent ELE falling edges by a falling edge time relative to its corresponding IUT falling edge (2f), such as Figure 6 Preferably, ELE (1) is used to convert the reference current I REF The measured IUT output current I IUT The comparison is performed and a rising edge or falling edge time delay is calculated, which is periodically applied at a third frequency F3. In this context, the subsequent ELE falling edge is an ELE falling edge that occurs after the measured IUT output current is compared with the reference current, and the time delay of the falling edge to be applied is calculated by the control unit (6). Figure 6 In the example, the control unit (6) sets I REF with I IUT The comparison is performed and the time delay of the falling edge applied at the time Ti1, Ti2, Ti3, Ti4 is calculated. Preferably, the control unit (6) is used to delay the first displayed ELE falling edge (1f) relative to its corresponding IUT falling edge (2f), such as Figure 6 As shown, the IUT output current is quickly adjusted to be close to the reference current. Of course, the technician should easily recognize that Figure 6 The voltage and current signals shown in are idealized signals and do not limit the scope of the present invention. IUT and V ELE These signals may include noise, ripples, and the rising and falling edges of IUT and ELE have finite slopes. Figure 6 Not shown in . Figure 6 No parasitic delays are shown either.

[0089] If I REF Below I IUT The control unit (6) is preferably used to control the ELE output voltage V ELE , so that it is consistent with I REF =I IUTUnder the condition of IUT output voltage V IUT Synchronous, except that the falling edge (1f) of ELE is delayed by the falling edge time relative to its corresponding falling edge (2r) of IUT. The delayed falling edge (1f) of ELE is compared in the control unit (6) to produce the result I REF IUT What happens afterwards is that during this falling edge time delay between the ELE and IUT falling edges, the IUT output voltage therefore takes an IUT voltage state whose voltage is lower than the ELE voltage state taken by the ELE output voltage, and the filter voltage VF is negative, and the IUT output current I IUT In this case, and in the example of the invention, the coupling filter (4) comprises only one series inductor L F , and the inductance L F The parasitic resistance R P can be ignored, V F ≈L F *dI IUT / dt, and dI IUT / dt<0, because V F In this case, the control unit (6) is preferably configured to delay the subsequent ELE falling edge (1f) by a falling edge time Δt=L relative to its corresponding IUT falling edge (2f). F *│I REF -I IUT │ / │V ELE -V IUT │. Among them│I REF -I IUT │ is the absolute value of the difference between the reference current and the measured IUT current, where │V ELE -V IUT │ is the absolute value of the difference between the ELE and IUT output voltages, i.e., during the time delay Δt between the following ELE falling edge (1f) and its corresponding IUT falling edge (2f), │ V ELE -V IUT │ is the absolute value between the voltages related to the ELE and IUT voltage states.

[0090] Although the present invention is described below with reference to specific embodiments, this is intended to clarify rather than limit the present invention. It should be understood by those skilled in the art that various modifications and different combinations of the disclosed features are possible without departing from the scope of the present invention.

[0091] Reference numerals

[0092] 1 Electrical Load Emulator (ELE) 1r The rising edge of the ELE output voltage 1f The falling edge of the ELE output voltage 1s ELE voltage status of ELE output voltage 2 Inverter under test (IUT) 2r The rising edge of the IUT output voltage 2f The falling edge of the IUT output voltage 2s IUT voltage status of IUT output voltage 3 Current Sensors 4 Coupling filter 5 Voltage sensing unit 6 Control unit 7 ELE Inverter 7l Phase leg of ELE inverter 7s ELE switch unit 8 DC Power Supply 9 ELE output 10 IUT output ​

Claims

1. An electrical load emulator ELE (1) for an inverter under test IUT (2), wherein: IUT output voltage V at the IUT output IUT for assuming a plurality of IUT voltage states separated by a rising edge and a falling edge of the IUT, and an ELE output voltage at an ELE output terminal for assuming a plurality of ELE voltage states separated by a rising edge and a falling edge of the ELE, and wherein each IUT voltage state corresponds to at least one ELE voltage state, and wherein the ELE comprises: - Current sensor (3) for measuring the output current I of the IUT IUT ; - a coupling filter (4) for connecting the ELE and the IUT; - Voltage sensing unit (5), used to sense the output voltage V of the IUT IUT ; - A control unit (6) for: outputting a voltage V according to the sensed IUT IUT , to determine the reference current I corresponding to the simulated electrical load REF ; Compare with reference current I REF and the measured IUT output current I IUT ; It is characterized in that If I REF Basically equal to I IUT , the control unit (6) is used to control the ELE output voltage to synchronously follow the IUT output voltage, so that each IUT rising edge and / or falling edge between two subsequent IUT voltage states respectively follows the corresponding ELE rising edge and / or falling edge between two subsequent ELE voltage states; If I REF Higher than I IUT , the control unit (6) is used to delay the subsequent ELE rising edge by one rising edge time relative to its corresponding IUT rising edge; If I REF Below I IUT , the control unit (6) is used to delay the subsequent ELE falling edge by a falling edge time relative to its corresponding IUT falling edge.

2. The ELE according to claim 1, characterized in that Each phase of the coupling filter (4) comprises at least one series inductor LF.

3. The ELE according to claim 1, characterized in that The invention comprises an ELE inverter (7) which has a two-level topology structure or a multi-level topology structure.

4. The ELE according to claim 1, characterized in that: in, The ELE inverter (7) is used to be supplied by a DC power source (8) shared with the IUT (2).

5. The ELE according to claim 1, characterized in that: in, The control unit (6) is used to: - According to the measured IUT output voltage V IUT , determine the reference current I corresponding to the simulated electrical load REF ; - Set the reference current I REF The measured IUT output current I IUT Compare and calculate the IUT output voltage V IUT Asynchronous rising or falling edge time delay.

6. The ELE according to claim 1, characterized in that: in, The control unit (6) is used to: -According to the IUT output voltage V periodically measured at the second frequency F2 IUT , determine the reference current I corresponding to the simulated electrical load REF , wherein the second frequency F2 is between one third of the switching frequency of the IUT and 300 MHz; - Compare the reference current IREF with the measured IUT output current I IUT A comparison is performed, and a time delay of a rising edge or a falling edge is periodically calculated at a third frequency F3, wherein the third frequency F3 is lower than or equal to the second frequency F2, and wherein the third frequency F3 is between 100 Hz and 100 MHz.

7. A method for controlling an electric load simulator ELE (1) as claimed in any one of claims 1 to 6, for testing an inverter under test IUT (2), characterized in that: The IUT output voltage V IUT For assuming a plurality of IUT voltage states, the plurality of IUT voltage states being separated by IUT rising edges and falling edges, the method comprising: -Sensing the output voltage V of the IUT at the output terminal of the IUT IUT ; -According to the sensed IUT output voltage V IUT , determine the reference current I corresponding to the simulated electrical load REF ; -Measure the output current I of the IUT IUT ; - Set the reference current I REF The measured IUT output current I IUT Make comparisons; -If I REF Basically equal to I IUT , then the ELE output voltage is controlled to synchronously follow the IUT output voltage V IUT , so that each IUT rising edge and / or falling edge between two subsequent IUT voltage states follows a corresponding ELE rising edge and / or falling edge between two subsequent ELE voltage states; -If I REF Higher than I IUT , then relative to its corresponding IUT rising edge, the subsequent ELE rising edge is delayed by one rising edge time; -If I REF Below I IUT , then the subsequent ELE falling edge is delayed by one falling edge time relative to its corresponding IUT falling edge.

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